Super junction terminal structure and preparation method thereof

Abstract

The invention provides a super-junction terminal structure and a preparation method thereof. In the super-junction terminal structure, a second conduction type terminal region column is arranged on one side, far away from a second conduction type active region column, of a second conduction type transition region column; the distances between the second conductive type terminal region columns and the first conductive type substrate are reduced in sequence; a second conduction type heavily doped region is arranged on the second conduction type terminal region column; and the second conduction type ion implantation well and the second conduction type terminal main junction are respectively positioned on the second conduction type active region column and the second conduction type transition region column. The non-equal-depth super-junction terminal structure improves the terminal efficiency, reduces the electric field peak at the edge of the terminal and the electric field on the surface of the terminal, and improves the long-term reliability; in addition, the second conductive type junction termination extension layer is matched to reduce the electric field peak at the edge of the terminal and improve the efficiency and performance reliability of the terminal; and finally, through a second conductive type heavily doped region on the second conductive type terminal region column, the surface electric field concentration ratio of the terminal is reduced, and the efficiency and performance of the terminal are improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor integrated circuit manufacturing, and particularly relates to a super-junction terminal structure and a preparation method thereof. BACKGROUND

[0002] In a conventional power semiconductor device, there is a contradictory relationship between the withstand voltage and the on-resistance. With the increase of the withstand voltage of the device, in order to be able to withstand higher voltage, the drift region needs to be thicker, which will lead to the increase of the on-resistance of the drift region. The emergence of the super-junction device breaks this contradiction, by alternately arranging P-type and N-type columnar regions in the drift region, using the charge balance between the P-type and N-type regions, the resistance of the drift region can be greatly reduced under the same withstand voltage.

[0003] However, the edge electric field of the PN junction alternately arranged region in the super-junction device is relatively concentrated when high voltage is withstood, thereby leading to the decrease of the breakdown voltage of the device. In the prior art, a suitable terminal structure is generally designed to optimize the electric field distribution and improve the performance of the device. However, the terminal structure used in the prior art is low in efficiency, is easy to cause waste of chip area, and significantly increases the production cost; at the same time, the edge of the terminal structure is still easy to produce electric field peaks, leading to the decrease of the withstand voltage capacity of the device, and affecting the long-term reliability of the device; and the region of the surface of the terminal structure close to the oxide layer is easy to cause electric field concentration, which also threatens the long-term reliability of the device.

[0004] Therefore, there is an urgent need for a structure or method capable of improving the efficiency, withstand voltage capacity and reliability of the terminal structure of the super-junction device.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of clearly and completely describing the technical scheme of the present application, and for the convenience of understanding by those skilled in the art, and the above technical scheme cannot be considered as known to those skilled in the art only because it is described in the background section of the present application. SUMMARY

[0006] In view of the above shortcomings of the prior art, the purpose of the present application is to provide a super-junction terminal structure and a preparation method thereof, for solving the problem that the terminal structure efficiency of the super-junction device is low, and the withstand voltage capacity and reliability are difficult to improve in the prior art.

[0007] To achieve the above purpose, the present application provides a super-junction terminal structure, which comprises:

[0008] a first conductive type substrate, the first conductive type substrate comprising opposite first and second surfaces;

[0009] a first-conductivity-type epitaxial layer located at a first surface of the first-conductivity-type substrate;

[0010] a second-conductivity-type active region pillar located within the first-conductivity-type epitaxial layer away from the first-conductivity-type substrate;

[0011] a second-conductivity-type transition region pillar located within the first-conductivity-type epitaxial layer away from the first-conductivity-type substrate and adjacent to the second-conductivity-type active region pillar;

[0012] n second-conductivity-type terminal region pillars located within the first-conductivity-type epitaxial layer and located on a side of the second-conductivity-type transition region pillar away from the second-conductivity-type active region pillar; the minimum distance between the n second-conductivity-type terminal region pillars and the first-conductivity-type substrate decreases in turn from a position close to the second-conductivity-type transition region pillar to a position away from the second-conductivity-type transition region pillar; n is a positive integer greater than or equal to 2;

[0013] n second-conductivity-type heavily doped regions, each of which is located at an end of a corresponding one of the second-conductivity-type terminal region pillars away from the first-conductivity-type substrate;

[0014] a second-conductivity-type ion implantation well located at an end of the second-conductivity-type active region pillar away from the first-conductivity-type substrate;

[0015] a second-conductivity-type terminal main junction located at an end of the second-conductivity-type transition region pillar away from the first-conductivity-type substrate.

[0016] Optionally, the super junction terminal structure further comprises a second-conductivity-type junction terminal extension layer located within the first-conductivity-type epitaxial layer on a side of the second-conductivity-type terminal main junction away from the second-conductivity-type ion implantation well and connected to the second-conductivity-type terminal main junction, the second-conductivity-type junction terminal extension layer covering corresponding positions above the n second-conductivity-type terminal region pillars.

[0017] Optionally, the second-conductivity-type junction terminal extension layer is flush with a top surface of the second-conductivity-type ion implantation well.

[0018] Optionally, the super junction terminal structure further comprises:

[0019] a terminal dielectric layer on the first conductivity type epitaxial layer, the terminal dielectric layer completely covering the second conductivity type junction termination extension layer and covering an edge portion of the second conductivity type terminal main junction;

[0020] a terminal isolation dielectric on the second conductivity type terminal main junction;

[0021] a terminal region metal on the second conductivity type terminal main junction between the terminal dielectric layer and the terminal isolation dielectric and extending to cover a portion of a surface of the terminal dielectric layer proximate to the terminal isolation dielectric;

[0022] a gate structure including a gate dielectric on the first conductivity type epitaxial layer and over a location between the second conductivity type ion implantation well and the second conductivity type terminal main junction, a gate electrode on the gate dielectric, and a gate isolation dielectric wrapping surfaces exposed by the gate dielectric and the gate electrode;

[0023] a cell region source metal on the second conductivity type ion implantation well and the second conductivity type terminal main junction and wrapping surfaces exposed by the gate structure, the cell region source metal being insulated from the terminal region metal by the terminal isolation dielectric;

[0024] a drain metal on the second surface of the first conductivity type substrate.

[0025] Optionally, a top of the second conductivity type heavily doped region corresponding to the second conductivity type terminal region pillar proximate to the second conductivity type transition region pillar is flush with a top surface of the second conductivity type transition region pillar.

[0026] Optionally, n is a positive integer greater than or equal to 4.

[0027] Optionally, the first conductivity type is P-type and the second conductivity type is N-type, or the first conductivity type is N-type and the second conductivity type is P-type.

[0028] The present application also provides a method for manufacturing a super junction termination structure, the method being used for manufacturing any one of the super junction termination structures described above, the method comprising:

[0029] providing a first conductivity type substrate including opposite first and second surfaces;

[0030] initial value of i is 1, a first conductive type i-th epitaxial layer is disposed on a first surface of the first conductive type substrate, ion implantation is performed on the first conductive type i-th epitaxial layer, and i second conductive type ion implantation regions are formed as i-th ion implantation of a second conductive type n-th terminal column, (i-1)-th ion implantation of a second conductive type (n-1)-th terminal column, (i-2)-th ion implantation of a second conductive type (n-2)-th terminal column, and 1st ion implantation of a second conductive type 1st terminal column, and the step is repeated n times, and the value of i is increased by 1 each time;

[0031] initial value of m is 1, a first conductive type (n+m)-th epitaxial layer is disposed on the first conductive type n-th epitaxial layer, ion implantation is performed on the first conductive type (n+m)-th epitaxial layer, and (n-m+x) second conductive type ion implantation regions are formed as n-th ion implantation of a second conductive type (n-m)-th terminal column, (n-1)-th ion implantation of a second conductive type (n-m-1)-th terminal column, (n-2)-th ion implantation of a second conductive type (n-m-2)-th terminal column, (1+m)-th ion implantation of a second conductive type 1st terminal column, m-th ion implantation of a second conductive type transition region column, and m-th ion implantation of a second conductive type active region column, ion implantation is performed on the first conductive type (n+m)-th epitaxial layer at a position corresponding to a second conductive type (n-m+1)-th terminal column, a second conductive type heavily doped region of the second conductive type (n-m+1)-th terminal column is formed, the step is repeated n times, and the value of m is increased by 1 each time, and x is the total number of the second conductive type transition region column and the second conductive type active region column, and thus n second conductive type terminal region columns, a second conductive type transition region column, and a second conductive type active region column are obtained;

[0032] a first conductive type (2n+1)-th epitaxial layer is disposed on the first conductive type 2n-th epitaxial layer;

[0033] a second conductive type terminal main junction is disposed above the second conductive type transition region column on the first conductive type (2n+1)-th epitaxial layer, and a second conductive type ion implantation well is disposed above the second conductive type active region column on the first conductive type (2n+1)-th epitaxial layer.

[0034] Optionally, the preparation method further comprises: a second conductive type junction terminal extension layer is disposed on a side of the second conductive type terminal main junction away from the second conductive type ion implantation well in the first conductive type (2n+1)-th epitaxial layer, the second conductive type junction terminal extension layer is connected to the second conductive type terminal main junction and covers positions corresponding to the n second conductive type terminal region columns.

[0035] Optionally, the preparation method further comprises: forming a gate dielectric on the first conductive type (2n+1) epitaxial layer, the gate dielectric being above a position between the second conductive type ion implantation well and the second conductive type terminal main junction;

[0036] a gate electrode is arranged on the gate dielectric, a gate isolation dielectric is arranged on the gate electrode, the gate isolation dielectric wrapping the gate dielectric and the exposed surface of the gate electrode, a terminal isolation dielectric is arranged on the first conductive type (2n+1) epitaxial layer, the terminal isolation dielectric being on the second conductive type terminal main junction, a terminal dielectric layer is arranged on the first conductive type (2n+1) epitaxial layer, the terminal dielectric layer completely covering the second conductive type junction terminal extension layer and covering the edge portion of the second conductive type terminal main junction, a cell area source metal and a terminal area metal are formed on the first conductive type (2n+1) epitaxial layer, the cell area source metal being on the second conductive type ion implantation well and the second conductive type terminal main junction and wrapping the exposed surface of the gate structure, the terminal area metal being on the second conductive type terminal main junction at a position between the terminal dielectric layer and the terminal isolation dielectric and covering a part of the surface of the terminal dielectric layer close to the terminal isolation dielectric, the cell area source metal and the terminal area metal being insulated and separated by the terminal isolation dielectric, and a drain metal is arranged on the second surface of the first conductive type substrate.

[0037] As described above, the super junction terminal structure and the preparation method thereof have the following beneficial effects:

[0038] By adopting the non-equal-depth super junction terminal structure, the terminal efficiency can be improved, the electric field peak at the terminal edge can be reduced, the electric field concentration degree on the terminal surface can be reduced, and the long-term reliability can be improved.

[0039] The second conductive type junction terminal extension layer is further adopted to reduce the electric field peak at the terminal edge, improve the terminal efficiency and performance reliability.

[0040] By arranging the second conductive type heavily doped region on the second conductive type terminal area column, the terminal surface electric field is further reduced, and the terminal efficiency and reliability are improved. BRIEF DESCRIPTION OF DRAWINGS

[0041] Figure 1 A structural schematic diagram of a super junction terminal structure of the prior art is shown.

[0042] Figure 2 A structural schematic diagram of a super junction terminal structure of the present application is shown.

[0043] Figure 3The surface electric field distribution of the super junction termination structure of the present application is shown in comparison with the prior art super junction termination structure.

[0044] Figure 4 The structure schematic diagram of the first conductive type substrate provided in step 1 of the preparation method of the super junction termination structure of the present application is shown.

[0045] Figure 5 The structure schematic diagram of the first conductive type first epitaxial layer provided and ion implantation in step 2 of the preparation method of the super junction termination structure of the present application is shown.

[0046] Figure 6 The structure schematic diagram of the first conductive type second epitaxial layer provided and ion implantation in step 2 of the preparation method of the super junction termination structure of the present application is shown.

[0047] Figure 7 The structure schematic diagram of the epitaxial layer provided and ion implantation repeated 5 times in step 2 of the preparation method of the super junction termination structure of the present application is shown.

[0048] Figure 8 The structure schematic diagram of the first conductive type sixth epitaxial layer provided and ion implantation in step 3 of the preparation method of the super junction termination structure of the present application is shown.

[0049] Figure 9 The structure schematic diagram of the second conductive type heavily doped region provided in step 3 of the preparation method of the super junction termination structure of the present application is shown.

[0050] Figure 10 The structure schematic diagram of the epitaxial layer provided and ion implantation repeated 5 times in step 3 of the preparation method of the super junction termination structure of the present application is shown.

[0051] Figure 11 The structure schematic diagram of the first conductive type (2n+1) epitaxial layer provided in step 4 of the preparation method of the super junction termination structure of the present application is shown.

[0052] Figure 12 The structure schematic diagram of the second conductive type termination main junction and the second conductive type ion implantation well provided in step 5 of the preparation method of the super junction termination structure of the present application is shown.

[0053] Figure 13 The structure schematic diagram of the second conductive type termination extension layer provided in the preparation method of the super junction termination structure of the present application is shown.

[0054] Figure 14Fig. 1 shows a schematic diagram of a device structure according to an embodiment of the present application.

[0055] BRIEF DESCRIPTION OF DRAWINGS

[0056] 1, drain metal; 2, first conductivity type substrate; 3, first conductivity type epitaxial layer; 31, first conductivity type 1st epitaxial layer; 32, first conductivity type 2nd epitaxial layer; 33, first conductivity type 3rd epitaxial layer; 34, first conductivity type 4th epitaxial layer; 35, first conductivity type 5th epitaxial layer; 36, first conductivity type 6th epitaxial layer; 37, first conductivity type 7th epitaxial layer; 38, first conductivity type 8th epitaxial layer; 39, first conductivity type 9th epitaxial layer; 310, first conductivity type 10th epitaxial layer; 311, first conductivity type 11th epitaxial layer; 4, second conductivity type active region pillar; 5, second conductivity type transition region pillar; 6, second conductivity type termination region pillar; 61, second conductivity type ion implant region; 7, second conductivity type heavily doped region; 8, second conductivity type ion implant well; 9, second conductivity type termination main junction; 10, second conductivity type junction termination extension layer; 11, gate dielectric; 12, gate electrode; 13, gate isolation dielectric; 14, termination isolation dielectric; 15, termination dielectric layer; 16, termination region metal; 17, cell region source metal. DETAILED DESCRIPTION

[0057] Objects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description or can be learned by practice of the application. The application will be described with reference to specific

[0058] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. In the drawings:

[0059] To facilitate an understanding of this application, numerous specific details are set forth in the description below. However, it should be understood that the application is not limited to the specific details set forth and, in some instances, concepts can be practiced without those specific details. In other instances, multiple details known to those of ordinary skill in the art are not set forth in order to avoid obscuring the application.

[0060] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0061] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex. The quantity range given in the present invention includes the two boundary values ​​of the quantity range by default unless otherwise specified.

[0062] In the current technological field, such as Figure 1 As shown, the termination structure of existing superjunction devices is inefficient, leading to wasted chip area and significantly increased production costs. Furthermore, electric field spikes at the edge of the termination structure persist, reducing the device's breakdown voltage and negatively impacting its long-term reliability. In addition, electric field concentration near the oxide layer on the termination structure surface also poses a potential threat to the device's long-term reliability.

[0063] To address the above problems, this invention provides a superjunction termination structure, such as... Figure 2 As shown, the superjunction termination structure includes:

[0064] A first conductivity type substrate 2, the first conductivity type substrate 2 includes opposing first and second surfaces;

[0065] The first conductivity type epitaxial layer 3 is located on the first surface of the first conductivity type substrate 2;

[0066] The second conductivity type active region pillar 4 is located in the first conductivity type epitaxial layer 3 at a position away from the first conductivity type substrate 2.

[0067] The second conductivity type transition region pillar 5 is located in the first conductivity type epitaxial layer 3 at a position away from the first conductivity type substrate 2 and is adjacent to the second conductivity type active region pillar 4.

[0068] n second-conductivity-type terminal region pillars 6 located in the first-conductivity-type epitaxial layer 3 and on the side of the second-conductivity-type transition region pillar 5 away from the second-conductivity-type active region pillar 4; the minimum distances between the n second-conductivity-type terminal region pillars 6 and the first-conductivity-type substrate 2 decrease in turn from the position close to the second-conductivity-type transition region pillar 5 to the position away from the second-conductivity-type transition region pillar 5; n is a positive integer greater than or equal to 2;

[0069] n second-conductivity-type heavily doped regions 7, each of which is located at the end of a corresponding second-conductivity-type terminal region pillar 6 away from the first-conductivity-type substrate 2;

[0070] a second-conductivity-type ion implantation well 8 located at the end of the second-conductivity-type active region pillar 4 away from the first-conductivity-type substrate 2;

[0071] a second-conductivity-type terminal main junction 9 located at the end of the second-conductivity-type transition region pillar 5 away from the first-conductivity-type substrate 2.

[0072] The present application proposes a new terminal structure, which realizes a non-equal-depth super-junction terminal structure by designing second-conductivity-type terminal region pillars 6 with minimum distances to the first-conductivity-type substrate 2 decreasing in turn. Figure 3 As shown in the surface electric field distribution simulation diagram of the terminal structure in the prior art and the terminal structure in the present application, it can be seen that the surface electric field of the terminal structure in the prior art on the left has an electric field peak at the edge and poor uniformity of electric field intensity distribution, while the electric field peak of the surface electric field of the terminal structure in the present application on the right is eliminated, and the uniformity of electric field intensity distribution is significantly improved. Therefore, the design of the present application can not only significantly improve the uniformity of the terminal electric field, improve the terminal efficiency, and thus reduce the chip area and save costs, but also effectively reduce the electric field peak at the edge of the terminal and improve the withstand voltage capability. In this way, in combination with the arrangement of the second-conductivity-type heavily doped regions 7 on the second-conductivity-type terminal region pillars 6, the electric field intensity concentration of the terminal surface is effectively controlled and reduced, thereby greatly improving the long-term reliability of the entire device.

[0073] In one embodiment, as Figure 2As shown, the super junction termination structure further comprises a second-conductivity-type junction termination extension layer 10 (JTE, Junction Termination Extension) located in the first-conductivity-type epitaxial layer 3 on the side of the second-conductivity-type terminal main junction 9 away from the second-conductivity-type ion implantation well 8 and connected with the second-conductivity-type terminal main junction 9, the second-conductivity-type junction termination extension layer 10 covering the corresponding positions above the n second-conductivity-type terminal pillars 6.

[0074] The present application further reduces the electric field peak at the edge of the termination structure by setting the non-equal-depth super junction termination structure in cooperation with the second-conductivity-type junction termination extension layer 10, thereby reducing the electric field peak at the edge of the termination structure, reducing the risk of electric field concentration near the oxide layer on the surface of the termination structure, and improving the termination efficiency and performance reliability.

[0075] In one embodiment, as shown in FIG. 1, the second-conductivity-type junction termination extension layer 10 is flush with the top surface of the second-conductivity-type ion implantation well 8. Figure 2

[0076] The present application further reduces the electric field peak at the edge of the termination structure by setting the second-conductivity-type junction termination extension layer 10 flush with the top surface of the second-conductivity-type ion implantation well 8, thereby further reducing the electric field peak at the edge of the termination structure and reducing the electric field concentration near the oxide layer on the surface of the termination structure, and improving the reliability and working efficiency of the termination structure.

[0077] In one embodiment, as shown in FIG. 1, the super junction termination structure further comprises: Figure 2

[0078] a termination dielectric layer 15 located on the first-conductivity-type epitaxial layer 3, the termination dielectric layer 15 completely covering the second-conductivity-type junction termination extension layer 10 and covering the edge portion of the second-conductivity-type terminal main junction 9;

[0079] a termination isolation dielectric 14 located on the second-conductivity-type terminal main junction 9;

[0080] a termination region metal 16 located between the termination dielectric layer 15 and the termination isolation dielectric 14 on the second-conductivity-type terminal main junction 9 and extending to cover a portion of the surface of the termination dielectric layer 15 near the termination isolation dielectric 14;

[0081] ​​a gate structure, the gate structure comprising a gate dielectric 11, a gate electrode 12 and a gate isolation dielectric 13, the gate dielectric 11 being located on the first conductivity type epitaxial layer 3 and above a location between the second conductivity type ion implantation well 8 and the second conductivity type termination main junction 9, the gate electrode 12 being located on the gate dielectric 11, the gate isolation dielectric 13 wrapping exposed surfaces of the gate dielectric 11 and the gate electrode 12;

[0082] a cell region source metal 17, the cell region source metal 17 being located on the second conductivity type ion implantation well 8 and the second conductivity type termination main junction 9 and wrapping exposed surfaces of the gate structure, the cell region source metal 17 being insulated from the termination region metal 16 by the termination isolation dielectric 14;

[0083] a drain metal 1, the drain metal 1 being located on a second surface of the first conductivity type substrate 2.

[0084] The present application obtains a super-junction MOSFET device comprising a termination structure by continuing to set a device structure on an epitaxial layer where the termination structure is set. Specifically, the termination structure scheme of the present application can also be set with other device structures to be applied in other super-junction structure devices, all within the protection scope of the present application.

[0085] In one embodiment, as shown in Figure 2 The top of the second conductivity type heavily doped region 7 corresponding to the second conductivity type termination region column 6 closest to the second conductivity type transition region column 5 is flush with the top surface of the second conductivity type transition region column 5.

[0086] The present application can achieve better optimization effect on the electric field distribution of the termination structure by setting the height position relationship between the second conductivity type heavily doped region 7 and the second conductivity type transition region column 5, thereby further improving the performance and reliability of the super-junction device.

[0087] In one embodiment, n is a positive integer greater than or equal to 4.

[0088] The present application can further optimize the efficiency of the termination structure by setting the number of the second conductivity type termination region column 6, thereby reducing the electric field peak value while maximizing the production cost.

[0089] In one embodiment, as shown in Figure 2 n is 5.

[0090] In one embodiment, the first conductivity type is P-type, and the second conductivity type is N-type; or the first conductivity type is N-type, and the second conductivity type is P-type.

[0091] The application further provides a preparation method of the super-junction terminal structure, which is used for preparing the super-junction terminal structure and comprises the following steps:

[0092] Step 1: providing a first-conductivity-type substrate 2 comprising opposite first and second surfaces;

[0093] Step 2: initially setting i as 1, setting a first-conductivity-type i-th epitaxial layer on the first surface of the first-conductivity-type substrate 2, and performing ion implantation on the first-conductivity-type i-th epitaxial layer to form i second-conductivity-type ion implantation regions 61 as the i-th ion implantation of a second-conductivity-type n-th terminal column, the (i-1)-th ion implantation of a second-conductivity-type (n-1)-th terminal column, the (i-2)-th ion implantation of a second-conductivity-type (n-2)-th terminal column, and the 1st ion implantation of a second-conductivity-type 1st terminal column; repeating the step n times, and increasing the value of i to i+1 in each repetition;

[0094] Step 3: initially setting m as 1, setting a first-conductivity-type (n+m)-th epitaxial layer on the first-conductivity-type n-th epitaxial layer, performing ion implantation on the first-conductivity-type (n+m)-th epitaxial layer to form (n-m+x) second-conductivity-type ion implantation regions 61 as the n-th ion implantation of a second-conductivity-type (n-m)-th terminal column, the (n-1)-th ion implantation of a second-conductivity-type (n-m-1)-th terminal column, the (n-2)-th ion implantation of a second-conductivity-type (n-m-2)-th terminal column, and the (1+m)-th ion implantation of a second-conductivity-type 1st terminal column, as well as the m-th ion implantation of a second-conductivity-type transition region column 5 and a second-conductivity-type active region column 4; performing ion implantation on the first-conductivity-type (n+m)-th epitaxial layer at a position corresponding to a second-conductivity-type (n-m+1)-th terminal column to form a second-conductivity-type heavily doped region 7 of the second-conductivity-type (n-m+1)-th terminal column; repeating the step n times, and increasing the value of m to m+1 in each repetition; x is the total number of the second-conductivity-type transition region column 5 and the second-conductivity-type active region column 4; thus, n second-conductivity-type terminal region columns 6, the second-conductivity-type transition region column 5 and the second-conductivity-type active region column 4 are obtained;

[0095] Step 4: setting a first-conductivity-type (2n+1)-th epitaxial layer on the first-conductivity-type 2n-th epitaxial layer;

[0096] Step 5: A second conductivity type terminal main junction 9 is disposed above the transition region pillar 5 of the first conductivity type epitaxial layer (2n+1) corresponding to the second conductivity type, and a second conductivity type ion implantation trap 8 is disposed above the active region pillar 4 of the first conductivity type epitaxial layer (2n+1) corresponding to the second conductivity type.

[0097] The preparation method of the superjunction terminal structure of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the above order does not strictly represent the preparation order of the superjunction terminal structure protected by the present invention, and those skilled in the art can make changes according to the actual preparation steps.

[0098] First, proceed with step 1, as follows: Figure 4 As shown, a first conductivity type substrate 2 is provided, the first conductivity type substrate 2 including opposing first and second surfaces.

[0099] In one embodiment, the material of the first conductivity type substrate 2 is 4H-SiC material, the thickness of the first conductivity type substrate 2 is 90μm to 1500μm, and the doping concentration ranges from 5e. 18 cm -3 ~1e 19 cm -3 .

[0100] By setting the material of the substrate 2 of the first conductivity type, the present invention enables the obtained superjunction termination structure to be used on SiC devices. Combined with the high performance of SiC devices, better device performance can be achieved together.

[0101] Then, proceed to step 2, where the initial value of i is 1. A first conductivity type i-th epitaxial layer is formed on the first surface of the first conductivity type substrate 2. Ion implantation is performed on the first conductivity type i-th epitaxial layer to form i second conductivity type ion implantation regions 61, which are respectively used as the i-th ion implantation of the n-th terminal post of the second conductivity type, the (i-1)-th ion implantation of the (n-1)-th terminal post of the second conductivity type, the (i-2)-th ion implantation of the (n-2)-th terminal post of the second conductivity type, until the first ion implantation of the 1-th terminal post of the second conductivity type. This step is repeated n times, and the value of i increases to i+1 of the previous step each time it is repeated.

[0102] In one embodiment, n is 5, such as Figure 5 As shown, a first conductivity type first epitaxial layer 31 is formed on the first surface of the first conductivity type substrate 2. Ion implantation is performed on the first conductivity type first epitaxial layer 31 to form a second conductivity type ion implantation region 61, which serves as the first ion implantation of the second conductivity type fifth terminal post; as shown Figure 6As shown, a first conductive type second epitaxial layer 32 is disposed on the first surface of the first conductive type substrate 2, ion implantation is performed on the first conductive type second epitaxial layer 32, and two second conductive type ion implantation regions 61 are formed as the second time ion implantation of the second conductive type fifth terminal column and the first time ion implantation of the second conductive type fourth terminal column, respectively. After repeating five times, a structure as shown in FIG. 4 is obtained, and the first conductive type first epitaxial layer 31, the first conductive type second epitaxial layer 32, the first conductive type third epitaxial layer 33, the first conductive type fourth epitaxial layer 34, and the first conductive type fifth epitaxial layer 35 are obtained. The second conductive type first terminal column has been ion implanted once, the second conductive type second terminal column has been ion implanted twice, the second conductive type third terminal column has been ion implanted three times, the second conductive type fourth terminal column has been ion implanted four times, and the second conductive type fifth terminal column has been ion implanted five times. Figure 7 As shown in the structure, the first conductive type first epitaxial layer 31, the first conductive type second epitaxial layer 32, the first conductive type third epitaxial layer 33, the first conductive type fourth epitaxial layer 34, and the first conductive type fifth epitaxial layer 35 are obtained. The second conductive type first terminal column has been ion implanted once, the second conductive type second terminal column has been ion implanted twice, the second conductive type third terminal column has been ion implanted three times, the second conductive type fourth terminal column has been ion implanted four times, and the second conductive type fifth terminal column has been ion implanted five times.

[0103] In one embodiment, the thickness of the first conductive type first epitaxial layer 31 is 1.5 microns to 2.5 microns, and the doping concentration of each first conductive type sub-epitaxial layer is 1e 16 cm -3 to 3e 17 cm -3 .

[0104] In one embodiment, the thickness of each first conductive type i-th epitaxial layer disposed in step 2 except the first conductive type first epitaxial layer 31 is 0.6 microns to 1.2 microns, and the doping concentration is 1e 16 cm -3 to 3e 17 cm -3 .

[0105] Next, in step 3, the initial value of m is 1. A (n+m)th epitaxial layer of the first conductivity type is formed on the nth epitaxial layer of the first conductivity type. Ion implantation is performed on the (n+m)th epitaxial layer of the first conductivity type to form (n-m+x) spaced second conductivity type ion implantation regions 61, which are respectively used as the nth ion implantation of the (nm)th terminal post of the second conductivity type, the (n-1)th ion implantation of the (nm-1)th terminal post of the second conductivity type, the (n-2)th ion implantation of the (nm-2)th terminal post of the second conductivity type, until the (1+m)th ion implantation of the first terminal post of the second conductivity type. The m-th ion implantation is performed on the transition region pillar 5 and the active region pillar 4 of the second conductivity type; ion implantation is performed at the position of the terminal pillar of the second conductivity type corresponding to the (n-m+1)th epitaxial layer of the first conductivity type to form the second conductivity type heavily doped region 7 of the (n-m+1)th terminal pillar of the second conductivity type; this step is repeated n times, and the value of m is increased to m+1 of the previous step each time; x is the total number of the transition region pillar 5 and the active region pillar 4 of the second conductivity type; thus, n terminal region pillars 6, transition region pillars 5 and active region pillars 4 of the second conductivity type are obtained.

[0106] In one embodiment, n is 5 and x is 4, such as Figure 8 As shown, a first conductivity type sixth epitaxial layer 36 is formed on the first conductivity type fifth epitaxial layer 35. Ion implantation is performed on the first conductivity type sixth epitaxial layer 36 to form eight phase-separated second conductivity type ion implantation regions 61, which serve as the fifth ion implantation of the second conductivity type fourth terminal pillar, the fourth ion implantation of the second conductivity type third terminal pillar, the third ion implantation of the second conductivity type second terminal pillar, the second ion implantation of the second conductivity type first terminal pillar, and the first ion implantation of the second conductivity type transition region pillar 5 and the second conductivity type active region pillar 4; as Figure 9 As shown, ion implantation is performed at the position of the 6th epitaxial layer 36 of the first conductivity type corresponding to the 5th terminal pillar of the second conductivity type to form a heavily doped region 7 of the second conductivity type with the 5th terminal pillar; this process is repeated 5 times to obtain the following result. Figure 10 The structure shown yields a first conductivity type sixth epitaxial layer 36, a first conductivity type seventh epitaxial layer 37, a first conductivity type eighth epitaxial layer 38, a first conductivity type ninth epitaxial layer 39, a first conductivity type tenth epitaxial layer 310, five second conductivity type terminal region pillars 6, two second conductivity type transition region pillars 5, and two second conductivity type active region pillars 4.

[0107] In one embodiment, the thickness of each (n+m)th epitaxial layer of the first conductivity type set in step 3 is 0.6 micrometers to 1.2 micrometers, and the doping concentration of each (n+m)th epitaxial layer of the first conductivity type is 1e.16 cm -3 ~3e 17 cm -3 .

[0108] In one embodiment, the doping concentration of each second conductivity type heavily doped region 7 is 1e. 18 cm -3 ~1e 20 cm -3 .

[0109] Then, proceed to step 4, as follows: Figure 11 As shown, a first conductivity type (2n+1) epitaxial layer (first conductivity type 11 epitaxial layer 311) is provided on the first conductivity type 2n epitaxial layer (first conductivity type 10 epitaxial layer 310).

[0110] In one embodiment, the doping concentration of the (2n+1)th epitaxial layer of the first conductivity type is the same as that of each (n+m)th epitaxial layer of the first conductivity type, and the thickness of the (2n+1)th epitaxial layer of the first conductivity type is 0.8 micrometers to 1.5 micrometers.

[0111] Finally, proceed to step 5, as follows: Figure 12 As shown, a second conductivity type terminal main junction 9 is provided above the transition region pillar 5 of the first conductivity type (11th epitaxial layer 311 of the first conductivity type) corresponding to the second conductivity type, and a second conductivity type ion implantation trap 8 is provided above the active region pillar 4 of the first conductivity type (11th epitaxial layer 311 of the first conductivity type) corresponding to the second conductivity type.

[0112] In one embodiment, the junction depth of the second conductivity type ion implantation trap 8 and the second conductivity type terminal main junction 9 is 1 micrometer to 3 micrometers, and the doping concentration is 4e. 17 cm -3 ~5e 18 cm -3 .

[0113] In one embodiment, such as Figure 13 As shown, the preparation method further includes: setting a second conductivity type junction extension layer 10 on the side of the second conductivity type terminal main junction 9 away from the second conductivity type ion implantation trap 8 in the first conductivity type (2n+1) epitaxial layer (first conductivity type 11 epitaxial layer 311), the second conductivity type junction extension layer 10 is connected to the second conductivity type terminal main junction 9 and covers the corresponding positions above the n second conductivity type terminal pillars 6.

[0114] In one embodiment, the junction depth of the second conductivity type junction termination extension layer 10 is 0.5-1 microns, and the doping concentration is 1e 16 cm -3 -4e 16 cm -3 .

[0115] In one embodiment, as shown in FIG. 11, the manufacturing method further comprises: forming a gate dielectric 11 on the first conductivity type (2n+1) epitaxial layer (first conductivity type 11 epitaxial layer 311), the gate dielectric 11 being above the position between the second conductivity type ion implantation well 8 and the second conductivity type main junction 9; Figure 14

[0116] forming a gate electrode 12 on the gate dielectric 11; forming a gate isolation dielectric 13 on the gate electrode 12, the gate isolation dielectric 13 wrapping the exposed surfaces of the gate dielectric 11 and the gate electrode 12; forming a termination isolation dielectric 14 on the first conductivity type (2n+1) epitaxial layer (first conductivity type 11 epitaxial layer 311), the termination isolation dielectric 14 being on the second conductivity type main junction 9; forming a termination dielectric layer 15 on the first conductivity type (2n+1) epitaxial layer (first conductivity type 11 epitaxial layer 311), the termination dielectric layer 15 completely covering the second conductivity type junction termination extension layer 10 and covering the edge portion of the second conductivity type main junction 9; forming a cell region source metal 17 and a termination region metal 16 on the first conductivity type (2n+1) epitaxial layer (first conductivity type 11 epitaxial layer 311), the cell region source metal 17 being on the second conductivity type ion implantation well 8 and the second conductivity type main junction 9 and wrapping the exposed surfaces of the gate structure, the termination region metal 16 being on the second conductivity type main junction 9 at the position between the termination dielectric layer 15 and the termination isolation dielectric 14 and covering the portion of the surface of the termination dielectric layer 15 close to the termination isolation dielectric 14, the cell region source metal 17 and the termination region metal 16 being insulated by the termination isolation dielectric 14; forming a drain metal 1 on the second surface of the first conductivity type substrate 2.

[0117] In one embodiment, a SiO2 layer is formed on the first conductivity type (2n+1) epitaxial layer by thermal oxidation technology, as the gate dielectric 11 and the termination isolation dielectric 14, and the thickness is 50-200 nanometers.

[0118] In one embodiment, the material of the gate electrode 12 is doped polysilicon.

[0119] ​In one embodiment, the gate isolation medium 13 is formed by chemical vapor deposition, and has a thickness of 100-800 nm, and is made of one of SiO2 and Si3N4.

[0120] In one embodiment, the termination medium layer 15 is formed by chemical vapor deposition, and has a thickness of 100-800 nm, and is made of one of SiO2 and Si3N4.

[0121] In one embodiment, the termination region metal 16 and the cell region source metal 17 are formed by electron beam evaporation, and are made of one of Al / Ti stack and Ni-based metal.

[0122] In one embodiment, the drain metal 1 is formed by electron beam evaporation, and is made of one or more of Ni, Ti, Al, Pt, and the like.

[0123] In summary, the super-junction termination structure and the preparation method thereof can improve the termination efficiency, reduce the electric field peak at the termination edge, reduce the electric field concentration on the termination surface, and improve the long-term reliability by using the non-equal-depth super-junction termination structure. In addition, the second-conductivity-type junction termination extension layer can further reduce the electric field peak at the termination edge, improve the termination efficiency and performance reliability. Finally, the second-conductivity-type heavily doped region on the second-conductivity-type termination region column can further reduce the electric field on the termination surface, and improve the termination efficiency and reliability.

[0124] Therefore, the present application effectively overcomes the shortcomings of the prior art and has high industrial utilization value.

[0125] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. A super junction termination structure, characterized in that, The super junction termination structure comprises: a first-conductivity-type substrate comprising opposite first and second surfaces; a first-conductivity-type epitaxial layer on the first surface of the first-conductivity-type substrate; a second-conductivity-type active region column in the first-conductivity-type epitaxial layer away from the first-conductivity-type substrate; a second-conductivity-type transition region column in the first-conductivity-type epitaxial layer away from the first-conductivity-type substrate and adjacent to the second-conductivity-type active region column; n second-conductivity-type termination region columns in the first-conductivity-type epitaxial layer and on a side of the second-conductivity-type transition region column away from the second-conductivity-type active region column, the n second-conductivity-type termination region columns being arranged in order from a position close to the second-conductivity-type transition region column to a position away from the second-conductivity-type transition region column, and the minimum distance between the n second-conductivity-type termination region columns and the first-conductivity-type substrate decreasing in order; n is a positive integer greater than or equal to 2; n second-conductivity-type heavily doped regions, each of the n second-conductivity-type heavily doped regions being located at an end of a corresponding one of the n second-conductivity-type termination region columns away from the first-conductivity-type substrate; a second-conductivity-type ion implantation well at an end of the second-conductivity-type active region column away from the first-conductivity-type substrate; a second-conductivity-type termination main junction at an end of the second-conductivity-type transition region column away from the first-conductivity-type substrate.

2. The superjunction termination structure of claim 1, wherein, The super junction termination structure further comprises a second-conductivity-type junction termination extension layer in the first-conductivity-type epitaxial layer on a side of the second-conductivity-type termination main junction away from the second-conductivity-type ion implantation well and connected to the second-conductivity-type termination main junction, the second-conductivity-type junction termination extension layer covering corresponding positions above the n second-conductivity-type termination region columns.

3. The superjunction termination structure of claim 2, wherein, The second-conductivity-type junction termination extension layer is flush with a top surface of the second-conductivity-type ion implantation well.

4. The superjunction termination structure of claim 2, wherein, The super junction termination structure further comprises: a termination dielectric layer on the first-conductivity-type epitaxial layer, the termination dielectric layer completely covering the second-conductivity-type junction termination extension layer and covering an edge portion of the second-conductivity-type termination main junction; a termination isolation dielectric on the second-conductivity-type termination main junction; a termination region metal on the second-conductivity-type termination main junction at a position between the termination dielectric layer and the termination isolation dielectric and extending to cover a portion of a surface of the termination dielectric layer close to the termination isolation dielectric; a gate structure including a gate dielectric on the first conductivity type epitaxial layer and over a location disposed between the second conductivity type ion implant well and the second conductivity type termination main junction, a gate electrode on the gate dielectric, and a gate isolation dielectric wrapping exposed surfaces of the gate dielectric and the gate electrode; a cell region source metal on the second conductivity type ion implant well and the second conductivity type termination main junction and wrapping exposed surfaces of the gate structure, the cell region source metal being insulated from the termination region metal by the termination isolation dielectric; a drain metal on the second surface of the first conductivity type substrate.

5. The superjunction termination structure of claim 1, wherein, a top of the second conductivity type heavily doped region corresponding to the second conductivity type termination region pillar proximate to the second conductivity type transition region pillar is flush with a top surface of the second conductivity type transition region pillar.

6. The superjunction termination structure of claim 1, wherein, n is a positive integer greater than or equal to 4.

7. The superjunction termination structure of any of claims 1-6, wherein, the first conductivity type is P-type and the second conductivity type is N-type, or the first conductivity type is N-type and the second conductivity type is P-type.

8. A method for preparing a superjunction terminal structure, characterized in that, the method of making is for making the super junction termination structure of any one of claims 1-7, the method of making comprising: providing a first conductivity type substrate including opposing first and second surfaces; The initial value of i is 1, a first conductive type i-th epitaxial layer is arranged on a first surface of the first conductive type substrate, ion implantation is performed on the first conductive type i-th epitaxial layer, and i second conductive type ion implantation regions are formed as the i-th ion implantation of a second conductive type n-th terminal column, the (i-1)-th ion implantation of a second conductive type (n-1)-th terminal column, the (i-2)-th ion implantation of a second conductive type (n-2)-th terminal column, and the 1st ion implantation of a second conductive type 1st terminal column; the step is repeated n times, and the value of i is increased by 1 in each repetition; the initial value of m is 1, a first conductive type (n+m)-th epitaxial layer is arranged on the first conductive type n-th epitaxial layer, ion implantation is performed on the first conductive type (n+m)-th epitaxial layer, and (n-m+x) second conductive type ion implantation regions are formed as the n-th ion implantation of a second conductive type (n-m)-th terminal column, the (n-1)-th ion implantation of a second conductive type (n-m-1)-th terminal column, the (n-2)-th ion implantation of a second conductive type (n-m-2)-th terminal column, the (1+m)-th ion implantation of a second conductive type 1st terminal column, the m-th ion implantation of a second conductive type transition region column, and the m-th ion implantation of a second conductive type active region column; ion implantation is performed on the first conductive type (n+m)-th epitaxial layer at a position corresponding to a second conductive type (n-m+1)-th terminal column, and a second conductive type heavily doped region of the second conductive type (n-m+1)-th terminal column is formed; the step is repeated n times, and the value of m is increased by 1 in each repetition; x is the total number of the second conductive type transition region column and the second conductive type active region column; thus, n second conductive type terminal region columns, a second conductive type transition region column, and a second conductive type active region column are obtained; A first conductive type (2n+1)-th epitaxial layer is arranged on the first conductive type 2n-th epitaxial layer; A second conductive type terminal main junction is arranged above the second conductive type transition region column on the first conductive type (2n+1)-th epitaxial layer, and a second conductive type ion implantation well is arranged above the second conductive type active region column on the first conductive type (2n+1)-th epitaxial layer.

9. The method of claim 8, wherein the method further comprises: The preparation method further comprises: a second conductive type junction terminal extension layer is arranged on a side of the second conductive type terminal main junction away from the second conductive type ion implantation well in the first conductive type (2n+1)-th epitaxial layer, the second conductive type junction terminal extension layer is connected with the second conductive type terminal main junction and covers positions corresponding to the n second conductive type terminal region columns.

10. The method of claim 9, wherein the method further comprises: The preparation method further comprises: a gate dielectric is formed on the first conductive type (2n+1)-th epitaxial layer, and the gate dielectric is arranged above a position between the second conductive type ion implantation well and the second conductive type terminal main junction. forming a gate electrode on the gate dielectric; forming a gate isolation dielectric on the gate electrode, the gate isolation dielectric wrapping exposed surfaces of the gate dielectric and the gate electrode; forming a termination isolation dielectric on the first conductivity type (2n+1) epitaxial layer, the termination isolation dielectric being on the second conductivity type termination main junction; forming a termination dielectric layer on the first conductivity type (2n+1) epitaxial layer, the termination dielectric layer completely covering the second conductivity type junction termination extension layer and covering an edge portion of the second conductivity type termination main junction; forming a cell region source metal and a termination region metal on the first conductivity type (2n+1) epitaxial layer, the cell region source metal being on the second conductivity type ion implantation well and the second conductivity type termination main junction and wrapping exposed surfaces of the gate structure, the termination region metal being on the second conductivity type termination main junction between the termination dielectric layer and the termination isolation dielectric and covering a portion of a surface of the termination dielectric layer proximate to the termination isolation dielectric, the cell region source metal and the termination region metal being insulated from each other by the termination isolation dielectric; forming a drain metal on a second surface of the first conductivity type substrate.

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