Solar cell and preparation method thereof

Abstract

The invention relates to a solar cell and a preparation method thereof. The preparation method of the solar cell comprises the following steps: forming an intrinsic silicon layer on the surface of a substrate; first deposition and second deposition are sequentially carried out on at least one surface of the intrinsic silicon layer, so that an incubation layer and a doped microcrystalline silicon layer are sequentially formed on at least one surface of the intrinsic silicon layer, and the incubation layer is made of amorphous silicon; in the first deposition, the flow of the silane is 10 sccm to 30 sccm, the deposition time is 5 s to 10 s, and the starting power is 10000 W to 15000 W; in the second deposition, the flow rate of the silane is 100 sccm to 300 sccm, the deposition time is 150 s to 200 s, and the starting power is 6000 W to 8000 W. According to the preparation method of the solar cell, the thickness of the incubation layer in the solar cell can be thin, the overall crystallization rate of the doped silicon layer can be improved, and therefore the conversion efficiency of the solar cell is improved.

Description

Technical Field

[0001] This application relates to the field of photovoltaic technology, and in particular to a solar cell and its preparation method. Background Technology

[0002] In the fabrication of crystalline silicon solar cells, a doped silicon layer is typically required, which includes an incubation layer and a doped microcrystalline silicon layer. During the initial stage of microcrystalline silicon layer fabrication, an incubation layer is formed first, followed by the formation of the doped microcrystalline silicon layer. Traditional solar cell fabrication methods result in a relatively thick incubation layer, leading to a lower overall crystallinity of the doped silicon layer. The incubation layer increases parasitic light absorption, further reducing the overall crystallinity of the doped silicon layer and consequently lowering the solar cell's conversion efficiency. Summary of the Invention

[0003] Therefore, it is necessary to provide a solar cell and its fabrication method. The solar cell fabrication method of this application enables the solar cell to have a thinner incubation layer, thereby increasing the overall crystallinity of the doped silicon layer and thus improving the conversion efficiency of the solar cell.

[0004] In a first aspect, this application provides a method for fabricating a solar cell, comprising the following steps:

[0005] An intrinsic silicon layer is formed on the surface of the substrate;

[0006] A first deposition and a second deposition are sequentially performed on at least one surface of the intrinsic silicon layer to sequentially form an incubation layer and a doped microcrystalline silicon layer on at least one surface of the intrinsic silicon layer, wherein the material of the incubation layer is amorphous silicon; in the first deposition, the silane flow rate is 10 sccm to 30 sccm, the deposition time is 5 s to 10 s, and the ignition power is 10000 W to 15000 W; in the second deposition, the silane flow rate is 100 sccm to 300 sccm, the deposition time is 150 s to 200 s, and the ignition power is 6000 W to 8000 W.

[0007] In some embodiments, the deposition temperature of the first deposition is 15°C to 30°C lower than that of the second deposition.

[0008] In some embodiments, the flow rate ratio of silane, dopant gas, and hydrogen in the first deposition is 1:(0.5~5):(1000~3000).

[0009] In some embodiments, the gas pressure in the first deposition is 5 Torr to 7 Torr.

[0010] In some embodiments, the deposition temperature in the first deposition is 130°C to 180°C.

[0011] In some embodiments, the flow rate ratio of silane, dopant gas, and hydrogen in the second deposition is 1:(0.5~5):(100~300).

[0012] In some embodiments, the gas pressure in the second deposition is 3 Torr to 6 Torr.

[0013] In some embodiments, the deposition temperature in the second deposition is 150°C to 200°C.

[0014] In some embodiments, the thickness of the incubation layer is 2nm to 5nm.

[0015] In some embodiments, the thickness of the doped microcrystalline silicon layer is 15 nm to 40 nm.

[0016] In some embodiments, the incubation layer comprises the following elements in mass percentages: 1% to 1.5% carbon, 2% to 3% oxygen, 1% to 3% dopant elements, and the balance silicon.

[0017] In some embodiments, the doped microcrystalline silicon layer comprises the following elements in mass percentages: 1% to 1.5% carbon, 2% to 3% oxygen, 1% to 3% dopant elements, and the balance silicon.

[0018] In some embodiments, forming an intrinsic silicon layer on the surface of a substrate includes the following steps:

[0019] A first intrinsic amorphous silicon sublayer is prepared on the surface of a substrate using process gases including silane and carbon dioxide;

[0020] A second intrinsic amorphous silicon sublayer is prepared on the surface of the first intrinsic amorphous silicon sublayer using a process gas including silane;

[0021] A third intrinsic amorphous silicon sublayer is prepared on the surface of the second intrinsic amorphous silicon sublayer using process gases including silane and hydrogen.

[0022] In some embodiments, an intrinsic silicon layer is formed on the surface of a substrate; a first deposition and a second deposition are sequentially performed on at least one surface of the intrinsic silicon layer to sequentially form an incubation layer and a doped microcrystalline silicon layer on at least one surface of the intrinsic silicon layer, comprising the following steps:

[0023] A first intrinsic amorphous silicon layer is formed on the front side of the substrate, and a first incubation layer and a first doped microcrystalline silicon layer are formed sequentially on the surface of the first intrinsic amorphous silicon layer away from the substrate by the first deposition and the second deposition performed in sequence.

[0024] A second intrinsic amorphous silicon layer is formed on the back side of the substrate, and a second incubation layer and a second doped microcrystalline silicon layer are formed sequentially on the surface of the second intrinsic amorphous silicon layer away from the substrate by the first deposition and the second deposition performed in sequence.

[0025] The first doped microcrystalline silicon layer and the second doped microcrystalline silicon layer have opposite doping types.

[0026] Secondly, this application provides a solar cell prepared by any of the methods described above.

[0027] In some embodiments, the solar cell includes: a substrate, wherein a first intrinsic amorphous silicon layer, a first incubation layer, a first doped microcrystalline silicon layer, a first transparent conductive layer and a first electrode are sequentially stacked on the front side of the substrate, and the thickness of the first incubation layer is 2 nm to 5 nm; and a second intrinsic amorphous silicon layer, a second incubation layer, a second doped microcrystalline silicon layer, a second transparent conductive layer and a second electrode are sequentially stacked on the back side of the substrate, and the thickness of the second incubation layer is 2 nm to 5 nm.

[0028] In the aforementioned method for fabricating solar cells, an incubation layer and a doped microcrystalline silicon layer are sequentially formed on the surface of an intrinsic silicon layer through a first deposition and a second deposition. Compared to the second deposition, in the first deposition, the silane flow rate is 10 sccm to 30 sccm, the deposition time is 5 s to 10 s, and the ignition power is 10000 W to 15000 W. This means that by using a smaller silane flow rate, a shorter deposition time, and a higher ignition power, more microcrystals can be precipitated in the initial stage of the doped silicon layer fabrication process, thereby reducing the thickness of the incubation layer and improving the overall crystallinity of the doped silicon layer. Further, in the second deposition, the silane flow rate is 100 sccm to 300 sccm, the deposition time is 150 s to 200 s, and the ignition power is 6000 W to 8000 W. This higher silane flow rate, longer deposition time, and lower ignition power are used to prepare a higher quality doped microcrystalline silicon layer. In the first deposition, the higher ignition power and shorter deposition time aim for rapid film formation. If the second deposition also uses the same process as the first deposition, prolonged high-power deposition will damage the quality of the doped microcrystalline silicon layer, thus adversely affecting the electrical performance of the solar cell. In the solar cell fabrication method of this application, by coordinating the first deposition and its process parameters with the second deposition and its process parameters, the thickness of the incubation layer in the solar cell can be made thinner, which can improve the overall crystallinity of the doped silicon layer, thereby improving the conversion efficiency of the solar cell. Attached Figure Description

[0029] Figure 1 A schematic flowchart illustrating a solar cell fabrication method according to an embodiment of this application;

[0030] Figure 2 A schematic flowchart of a solar cell fabrication method provided in another embodiment of this application;

[0031] Figure 3 This is a schematic diagram of the structure of a solar cell provided in an embodiment of this application.

[0032] Explanation of reference numerals in the attached figures

[0033] 10. Substrate; 21. First intrinsic amorphous silicon layer; 22. Second intrinsic amorphous silicon layer; 31. First incubation layer; 32. Second incubation layer; 41. First doped microcrystalline silicon layer; 42. Second doped microcrystalline silicon layer; 51. First transparent conductive layer; 52. Second transparent conductive layer; 61. First electrode; 62. Second electrode. Detailed Implementation

[0034] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, a detailed description of specific embodiments of this application is provided below. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0036] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0037] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0038] Reference Figure 1 As shown, one embodiment of this application provides a method for fabricating a solar cell, comprising the following steps:

[0039] S10: An intrinsic silicon layer is formed on the surface of the substrate;

[0040] S11: A first deposition and a second deposition are sequentially performed on at least one surface of the intrinsic silicon layer to sequentially form an incubation layer and a doped microcrystalline silicon layer on at least one surface of the intrinsic silicon layer; in the first deposition, the silane flow rate is 10 sccm to 30 sccm, the deposition time is 5 s to 10 s, and the ignition power is 10000 W to 15000 W; in the second deposition, the silane flow rate is 100 sccm to 300 sccm, the deposition time is 150 s to 200 s, and the ignition power is 6000 W to 8000 W.

[0041] In the aforementioned method for fabricating solar cells, an incubation layer and a doped microcrystalline silicon layer are sequentially formed on the surface of an intrinsic silicon layer through a first deposition and a second deposition. Compared to the second deposition, in the first deposition, the silane flow rate is 10 sccm to 30 sccm, the deposition time is 5 s to 10 s, and the ignition power is 10000 W to 15000 W. This means that by using a smaller silane flow rate, a shorter deposition time, and a higher ignition power, more microcrystals can be precipitated in the initial stage of the doped silicon layer fabrication process, thereby reducing the thickness of the incubation layer and improving the overall crystallinity of the doped silicon layer. Further, in the second deposition, the silane flow rate is 100 sccm to 300 sccm, the deposition time is 150 s to 200 s, and the ignition power is 6000 W to 8000 W. This higher silane flow rate, longer deposition time, and lower ignition power are used to prepare a higher quality doped microcrystalline silicon layer. In the first deposition, the higher ignition power and shorter deposition time aim for rapid film formation. If the second deposition also uses the same process as the first deposition, prolonged high-power deposition will damage the quality of the doped microcrystalline silicon layer, thus adversely affecting the electrical performance of the solar cell. In the solar cell fabrication method of this application, by coordinating the first deposition and its process parameters with the second deposition and its process parameters, the thickness of the incubation layer in the solar cell can be made thinner, which can improve the overall crystallinity of the doped silicon layer, thereby improving the conversion efficiency of the solar cell.

[0042] Optionally, in the first deposition, the silane flow rate is 10 sccm, 12 sccm, 14 sccm, 16 sccm, 18 sccm, 20 sccm, 22 sccm, 24 sccm, 26 sccm, 28 sccm, or 30 sccm. Alternatively, in the first deposition, the silane flow rate may also be within any two of the above-mentioned flow rates.

[0043] Optionally, in the first deposition, the deposition time is 5s, 6s, 7s, 8s, 9s, or 10s. Alternatively, in the first deposition, the deposition time may also be within any two of the above-mentioned time ranges.

[0044] Optionally, in the first deposition, the ignition power is 10000W, 10500W, 11000W, 11500W, 12000W, 12500W, 13000W, 13500W, 14000W, or 15000W. Alternatively, in the first deposition, the ignition power may also be within the range of any two of the above power values.

[0045] Optionally, in the second deposition, the silane flow rate is 100 sccm, 120 sccm, 140 sccm, 160 sccm, 180 sccm, 200 sccm, 220 sccm, 240 sccm, 260 sccm, 280 sccm, or 300 sccm. Alternatively, in the second deposition, the silane flow rate can also be within any two of the above-mentioned flow rates.

[0046] Optionally, in the second deposition, the deposition time is 150s, 155s, 160s, 165s, 170s, 175s, 180s, 185s, 190s, 195s, or 200s. Alternatively, in the second deposition, the deposition time may also be within the range of any two of the above deposition times.

[0047] Optionally, in the second deposition, the ignition power is 6000W, 6200W, 6400W, 6600W, 6800W, 7000W, 7200W, 7400W, 7600W, 7800W, or 8000W. Alternatively, in the second deposition, the ignition power can also be within the range of any two of the above power values.

[0048] In some embodiments, the deposition temperature of the first deposition is 15°C to 30°C lower than that of the second deposition.

[0049] Optionally, the deposition temperature of the first deposition is 15°C, 18°C, 20°C, 22°C, 25°C, 28°C, or 30°C lower than the deposition temperature of the second deposition. Alternatively, the difference between the deposition temperatures of the first and second depositions can be within any of the two temperatures mentioned above.

[0050] In some embodiments, during the first deposition, the flow rate ratio of silane, dopant gas, and hydrogen is 1:(0.5~5):(1000~3000).

[0051] In some embodiments, the flow rate ratio of silane to dopant gas in the first deposition is 1:0.5, 1:1, 1:1.5, 1:2, 1:2.5, 1:3, 1:3.5, 1:4, 1:4.5, or 1:5. Alternatively, the flow rate ratio of silane to dopant gas in the first deposition may also be within the range of any two of the above flow rates.

[0052] In some embodiments, the flow rate ratio of silane to hydrogen in the first deposition is 1:1000, 1:1200, 1:1500, 1:1800, 1:2000, 1:2200, 1:2500, 1:2800, or 1:3000. Alternatively, the flow rate ratio of silane to hydrogen in the first deposition may also be within the range of any two of the above flow rate ratios.

[0053] In some of these embodiments, the process gas for the first deposition also includes carbon dioxide.

[0054] In some embodiments, the flow rate ratio of silane to hydrogen in the first deposition is less than that in the second deposition.

[0055] In some embodiments, the gas pressure in the first deposition is 5 Torr to 7 Torr.

[0056] Optionally, the gas pressure in the first deposition is 5 Torr, 5.5 Torr, 6 Torr, 6.5 Torr, or 7 Torr. Alternatively, the gas pressure in the first deposition can also be within the range of any two of the above pressures.

[0057] In some embodiments, the gas pressure in the first deposition is greater than the gas pressure in the second deposition.

[0058] In some embodiments, the deposition temperature in the first deposition is 130°C to 180°C.

[0059] Optionally, the deposition temperature in the first sedimentation is 130°C, 140°C, 150°C, 160°C, 170°C, or 180°C. Alternatively, the deposition temperature in the first sedimentation can also be within the range of any two of the above temperatures.

[0060] In some embodiments, the flow rate ratio of silane, dopant gas, and hydrogen in the second deposition is 1:(0.5~5):(100~300).

[0061] In some embodiments, the flow rate ratio of silane to dopant gas in the second deposition is 1:0.5, 1:1, 1:1.5, 1:2, 1:2.5, 1:3, 1:3.5, 1:4, 1:4.5, or 1:5. Alternatively, the flow rate ratio of silane to dopant gas in the second deposition may also be within the range of any two of the above flow rate ratios.

[0062] In some embodiments, the flow rate ratio of silane to hydrogen in the second deposition is 1:100, 1:120, 1:150, 1:180, 1:200, 1:220, 1:250, 1:280, or 1:300. Alternatively, the flow rate ratio of silane to hydrogen in the second deposition may also be within the range of any two of the above flow rate ratios.

[0063] In some of these embodiments, the process gas for the second deposition also includes carbon dioxide.

[0064] In some embodiments, the gas pressure in the second deposition is 3 Torr to 6 Torr.

[0065] Optionally, the gas pressure in the second deposition is 3 Torr, 3.5 Torr, 4 Torr, 4.5 Torr, 5 Torr, 5.5 Torr, or 6 Torr. Alternatively, the gas pressure in the second deposition can also be within the range of any two of the above pressures.

[0066] In some embodiments, the deposition temperature in the second deposition is 150°C to 200°C.

[0067] Optionally, the deposition temperature in the second deposition is 150°C, 160°C, 170°C, 180°C, 190°C, or 200°C. Alternatively, the deposition temperature in the second deposition may be within the range of any two of the above temperatures.

[0068] In some embodiments, the thickness of the incubation layer is 2nm to 5nm.

[0069] Optionally, the thickness of the incubation layer is 2nm, 2.5nm, 3nm, 3.5nm, 4nm, 4.5nm, or 5nm. Alternatively, the thickness of the incubation layer can be within any two of the above-mentioned thicknesses.

[0070] In some embodiments, the thickness of the doped microcrystalline silicon layer is 15 nm to 40 nm.

[0071] Optionally, the thickness of the doped microcrystalline silicon layer is 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, or 40 nm. Alternatively, the thickness of the doped microcrystalline silicon layer can also be within any two of the above-mentioned thicknesses.

[0072] In some embodiments, the incubation layer comprises the following elements in mass percentages: 1% to 1.5% carbon, 2% to 3% oxygen, 1% to 3% dopant elements, and the balance silicon.

[0073] In some embodiments, the doped microcrystalline silicon layer comprises the following elements in mass percentages: 1% to 1.5% carbon, 2% to 3% oxygen, 1% to 3% dopant elements, and the balance silicon.

[0074] It is understood that when preparing a P-type doped microcrystalline silicon layer, the doping gas can be B2H6 or other conventional P-type doping gases in the art, and when preparing an N-type doped microcrystalline silicon layer, the doping gas can be PH3 or other conventional N-type doping gases in the art.

[0075] In some embodiments, an intrinsic silicon layer is formed on the surface of a substrate; a first deposition and a second deposition are sequentially performed on at least one surface of the intrinsic silicon layer to sequentially form an incubation layer and a doped microcrystalline silicon layer on at least one surface of the intrinsic silicon layer, comprising the following steps:

[0076] A first intrinsic amorphous silicon layer is formed on the front side of the substrate, and a first incubation layer and a first doped microcrystalline silicon layer are formed sequentially on the surface of the first intrinsic amorphous silicon layer away from the substrate through a first deposition and a second deposition.

[0077] A second intrinsic amorphous silicon layer is formed on the back side of the substrate, and a second incubation layer and a second doped microcrystalline silicon layer are formed on the surface of the second intrinsic amorphous silicon layer away from the substrate by a first deposition and a second deposition performed sequentially.

[0078] The first doped microcrystalline silicon layer and the second doped microcrystalline silicon layer have opposite doping types.

[0079] Reference Figure 2 As shown, in some embodiments, the method for fabricating a solar cell includes the following steps S20-S28:

[0080] S20: Provides the texturized substrate.

[0081] In some embodiments, the substrate is a monocrystalline silicon substrate.

[0082] In some embodiments, a monocrystalline silicon wafer is subjected to texturing cleaning treatment using a texturing solution on a texturing cleaning machine to form a textured surface structure on the surface of the monocrystalline silicon wafer, thereby obtaining a texturized monocrystalline silicon substrate.

[0083] In some embodiments, the monocrystalline silicon substrate is an N-type monocrystalline silicon substrate.

[0084] It should be noted that this application does not specify the resistivity of the monocrystalline silicon substrate, the specific structure of the texturing and cleaning machine, or the process conditions for texturing and cleaning. Existing monocrystalline silicon substrates, texturing and cleaning machines, and conventional texturing and cleaning process conditions can be used.

[0085] S21: Deposit a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer on the front and back sides of the substrate, respectively.

[0086] In some embodiments, depositing a first intrinsic amorphous silicon layer and / or a second intrinsic amorphous silicon layer includes the following steps:

[0087] A first intrinsic amorphous silicon sublayer is prepared on the surface of a substrate using process gases including silane and carbon dioxide;

[0088] A second intrinsic amorphous silicon sublayer is prepared on the surface of the first intrinsic amorphous silicon sublayer using a process gas including silane;

[0089] A third intrinsic amorphous silicon sublayer is prepared on the surface of the second intrinsic amorphous silicon sublayer using process gases including silane and hydrogen.

[0090] In some embodiments, depositing a first intrinsic amorphous silicon layer includes the following steps:

[0091] Deposition of the first intrinsic amorphous silicon sublayer: The process gases are SiH4 and CO2, the process gas pressure is 0.5 Torr~0.57 Torr, the ignition power is 600W~800W, the SiH4 to CO2 flow ratio is 1:1~1.5, and the ignition time is 5s~8s;

[0092] Deposition of the second intrinsic amorphous silicon sublayer: The process gas is SiH4, the process gas pressure is 0.5 Torr~0.57 Torr, the ignition power is 600W~800W, and the ignition time is 8s~13s;

[0093] Deposition of the third intrinsic amorphous silicon layer: The process gases are SiH4 and H2, the process gas pressure is 0.5 Torr~0.57 Torr, the ignition power is 600W~800W, the SiH4 to H2 flow ratio is 1:1~1.5, and the ignition time is 3s~7s.

[0094] In some embodiments, depositing a second intrinsic amorphous silicon layer includes the following steps:

[0095] Deposition of the first intrinsic amorphous silicon sublayer: The process gases are SiH4 and CO2, the process gas pressure is 0.5 Torr~0.57 Torr, the ignition power is 600W~800W, the SiH4 to CO2 flow ratio is 1:1~1.5, and the ignition time is 5s~8s;

[0096] Deposition of the second intrinsic amorphous silicon sublayer: The process gas is SiH4, the process gas pressure is 0.5 Torr~0.57 Torr, the ignition power is 600W~800W, and the ignition time is 8s~13s;

[0097] Deposition of the third intrinsic amorphous silicon layer: The process gases are SiH4 and H2, the process gas pressure is 0.5 Torr~0.57 Torr, the ignition power is 600W~800W, the SiH4 to H2 flow ratio is 1:1~1.5, and the ignition time is 3s~7s.

[0098] In some embodiments, the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer are prepared by plasma-enhanced chemical vapor deposition.

[0099] S22: A first incubation layer and a first doped microcrystalline silicon layer are formed sequentially on the surface of the first intrinsic amorphous silicon layer by a first deposition and a second deposition; a second incubation layer and a second doped microcrystalline silicon layer are formed sequentially on the surface of the second intrinsic amorphous silicon layer by a first deposition and a second deposition; in the first deposition, the silane flow rate is 10 sccm~30 sccm, the deposition time is 5s~10s, and the ignition power is 10000W~15000W; in the second deposition, the silane flow rate is 100 sccm~300 sccm, the deposition time is 150s~200s, and the ignition power is 6000W~8000W.

[0100] In some embodiments, the first doped microcrystalline silicon layer is an N-type doped microcrystalline silicon layer, and the first incubation layer is an N-type incubation layer. The preparation method includes: in the first deposition, the silane flow rate is 10 sccm to 30 sccm, the deposition time is 5 s to 10 s, the ignition power is 12000 W to 15000 W, and the deposition temperature is 150 °C to 180 °C; in the second deposition, the silane flow rate is 100 sccm to 300 sccm, the deposition time is 150 s to 200 s, the ignition power is 6000 W to 8000 W, and the gas pressure is 3 Torr to 5 Torr.

[0101] In some embodiments, the second doped microcrystalline silicon layer is a P-type doped silicon layer, and the second incubation layer is a P-type incubation layer. The preparation method includes: in the first deposition, the silane flow rate is 10 sccm to 30 sccm, the deposition time is 5 s to 10 s, the ignition power is 10000 W to 13000 W, and the deposition temperature is 130℃ to 150℃; in the second deposition, the silane flow rate is 100 sccm to 300 sccm, the deposition time is 150 s to 200 s, the ignition power is 6000 W to 8000 W, and the gas pressure is 4 Torr to 6 Torr.

[0102] In some embodiments, the first incubation layer, the first doped microcrystalline silicon layer, the second incubation layer, and the second doped microcrystalline silicon layer are prepared by plasma-enhanced chemical vapor deposition.

[0103] S23: A first transparent conductive layer is prepared on the surface of the first doped microcrystalline silicon layer, and a second transparent conductive layer is prepared on the surface of the second doped microcrystalline silicon layer.

[0104] In some embodiments, the first transparent conductive layer and the second transparent conductive layer are prepared by physical vapor deposition.

[0105] It is understood that the present invention does not specifically limit the specific preparation method, process conditions, deposition thickness, or material type of the transparent conductive film.

[0106] S24: Prepare a first electrode on the surface of the first transparent conductive layer, and prepare a second electrode on the surface of the second transparent conductive layer.

[0107] In some embodiments, the first electrode and the second electrode are respectively prepared on the first transparent conductive layer and the second transparent conductive layer by methods such as screen printing or electroplating.

[0108] In some embodiments, the first electrode and the second electrode can be silver electrodes or copper electrodes. When the electrode is a silver electrode, it is generally prepared by screen printing; when the electrode is a copper electrode, it is generally prepared by electroplating.

[0109] Another embodiment of this application provides a solar cell prepared by any of the above-described methods.

[0110] Reference Figure 3 As shown, in some embodiments, the solar cell includes: a substrate 10, on the front side of which a first intrinsic amorphous silicon layer 21, a first incubation layer 31, a first doped microcrystalline silicon layer 41, a first transparent conductive layer 51 and a first electrode 61 are sequentially stacked, the thickness of the first incubation layer 31 being 2nm~5nm; and on the back side of the substrate 10 a second intrinsic amorphous silicon layer 22, a second incubation layer 32, a second doped microcrystalline silicon layer 42, a second transparent conductive layer 52 and a second electrode 62 are sequentially stacked, the thickness of the second incubation layer 32 being 2nm~5nm.

[0111] In some embodiments, the overall crystallinity of the first incubation layer 31 and the first doped microcrystalline silicon layer 41 is 40% to 60%.

[0112] Optionally, the overall crystallinity of the first incubation layer 31 and the first doped microcrystalline silicon layer 41 is 40%, 42%, 44%, 46%, 48%, 50%, 52%, 54%, 56%, 58%, or 60%. Alternatively, the overall crystallinity of the first incubation layer 31 and the first doped microcrystalline silicon layer 41 may also be within the range between any two of the above crystallinity rates.

[0113] In some embodiments, the overall crystallinity of the second incubation layer 32 and the second doped microcrystalline silicon layer 42 is 40% to 60%.

[0114] Optionally, the overall crystallinity of the second incubation layer 32 and the second doped microcrystalline silicon layer 42 is 40%, 42%, 44%, 46%, 48%, 50%, 52%, 54%, 56%, 58%, or 60%. Alternatively, the overall crystallinity of the second incubation layer 32 and the second doped microcrystalline silicon layer 42 may also be within the range between any two of the above crystallinity rates.

[0115] Compared to traditional solar cells, the solar cell in this application has a higher overall crystallinity of the doped silicon layer, improved open-circuit voltage and short-circuit current, and higher photoelectric conversion efficiency.

[0116] The following are specific embodiments.

[0117] Example 1

[0118] Methods for manufacturing solar cells:

[0119] (1) Fabrication of the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer:

[0120] A first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer were deposited on the front and back sides of a texturized N-type single-crystal silicon substrate using PECVD. The first intrinsic amorphous silicon layer consisted of three sequentially deposited intrinsic amorphous silicon sublayers. The process gases for depositing the first intrinsic amorphous silicon sublayer were SiH4 and CO2, with a process gas pressure of 0.57 Torr, an ignition power of 650 W, a SiH4 to CO2 flow ratio of 1:1, and an ignition time of 5 s. The process gases for depositing the second intrinsic amorphous silicon sublayer were SiH4, with a process gas pressure of 0.57 Torr, an ignition power of 650 W, and an ignition time of 8 s. The process gases for depositing the third intrinsic amorphous silicon sublayer were SiH4 and H2, with a process gas pressure of 0.57 Torr, an ignition power of 800 W, a SiH4 to H2 flow ratio of 1:1.5, and an ignition time of 7 s. The second intrinsic amorphous silicon layer also includes three intrinsic amorphous silicon sublayers deposited sequentially. The process conditions for each intrinsic amorphous silicon sublayer are the same as those for the corresponding intrinsic amorphous silicon sublayer when depositing the first intrinsic amorphous silicon layer.

[0121] (2) Preparation of N-type doped silicon layer:

[0122] First and second depositions were performed on a first intrinsic amorphous silicon layer using PECVD. The process gases for the first deposition were SiH4, PH3, H2, and CO2, with a pressure of 5 Torr, flow rates of 20 sccm, 20 sccm, 30000 sccm, and 20 sccm for SiH4, PH3, H2, and CO2, respectively. The ignition power was 13000 W, the ignition time was 8 s, and the deposition temperature was 160 °C. The process gases for the second deposition were also SiH4, PH3, H2, and CO2, with a pressure of 3 Torr, flow rates of 160 sccm, 160 sccm, 30000 sccm, and 160 sccm for SiH4, PH3, H2, and CO2, respectively. The ignition power was 7000 W, and the ignition time was 150 s. The resulting first incubation layer (N-type incubation layer) had a thickness of approximately 2.2 nm, and the N-type doped microcrystalline silicon layer (first doped microcrystalline silicon layer) had a thickness of approximately 40 nm. In the first incubation layer, the doping ratio of O element is 3%, the doping ratio of C element is 1.5%, and the doping ratio of P element is 1.5%.

[0123] (3) Preparation of P-type doped silicon layer:

[0124] First and second depositions were performed on a second intrinsic amorphous silicon layer using PECVD. The process gases for the first deposition were SiH4, B2H6, H2, and CO2, at a pressure of 5.5 Torr. The flow rates of SiH4, B2H6, H2, and CO2 were 20 sccm, 20 sccm, 30000 sccm, and 20 sccm, respectively. The ignition power was 12000 W, the ignition time was 8 s, and the deposition temperature was 140℃. The process gases for the second deposition were SiH4, B2H6, H2, and CO2, at a pressure of 3 Torr. The flow rates of SiH4, B2H6, H2, and CO2 were 160 sccm, 160 sccm, 30000 sccm, and 160 sccm, respectively. The ignition power was 6000 W, and the ignition time was 150 s. The thickness of the resulting second incubation layer, i.e., the P-type incubation layer, was approximately 2.6 nm. The thickness of the P-type doped microcrystalline silicon layer, i.e., the second doped microcrystalline silicon layer, was approximately 40 nm. In the second incubation layer, the doping ratio of oxygen is 3%, the doping ratio of carbon is 1.5%, and the doping ratio of boron is 3%.

[0125] (4) A first transparent conductive layer and a second transparent conductive layer are deposited on the N-type doped microcrystalline silicon layer and the P-type doped microcrystalline silicon layer, respectively. Then, a first electrode and a second electrode are prepared on the first transparent conductive layer and the second transparent conductive layer, respectively, to obtain a solar cell.

[0126] Raman spectroscopy analysis revealed that the overall crystallinity of each doped silicon layer in this embodiment was approximately 58%.

[0127] Example 2

[0128] Methods for manufacturing solar cells:

[0129] The solar cell fabrication method in this embodiment is basically the same as that in Embodiment 1, except that: in step (2), the flow rates of SiH4, PH3 and CO2 in the first deposition are 10 sccm, 10 sccm and 10 sccm respectively, and the ignition power is 14000W; in step (3), the flow rates of SiH4, B2H6 and CO2 in the first deposition are 10 sccm, 10 sccm and 10 sccm respectively, and the ignition power is 13000W. The thickness of the first incubation layer is about 2.5 nm, and the thickness of the second incubation layer is about 3.0 nm.

[0130] Raman spectroscopy analysis revealed that the overall crystallinity of each doped silicon layer in this embodiment was approximately 50%.

[0131] Example 3:

[0132] Methods for manufacturing solar cells:

[0133] The solar cell fabrication method in this embodiment is basically the same as that in Embodiment 1, except that: in step (2), the flow rates of SiH4, PH3 and CO2 in the first deposition are 30 sccm, 30 sccm and 30 sccm respectively, and the ignition power is 12000W; in step (3), the flow rates of SiH4, B2H6 and CO2 in the first deposition are 30 sccm, 30 sccm and 30 sccm respectively, and the ignition power is 10000W. The thickness of the first incubation layer is about 3.5 nm, and the thickness of the second incubation layer is about 4.2 nm.

[0134] Raman spectroscopy analysis revealed that the overall crystallinity of each doped silicon layer in this embodiment was approximately 48%.

[0135] Example 4:

[0136] Methods for manufacturing solar cells:

[0137] The solar cell fabrication method in this embodiment is basically the same as that in Embodiment 1, except that: in step (2), the first deposition temperature is 150°C, and in step (3), the deposition temperature is 130°C. The thickness of the first incubation layer is about 2.5 nm, and the thickness of the second incubation layer is about 3.0 nm.

[0138] Raman spectroscopy analysis revealed that the overall crystallinity of each doped silicon layer in this embodiment was approximately 42%.

[0139] Example 5:

[0140] Methods for manufacturing solar cells:

[0141] The solar cell fabrication method in this embodiment is basically the same as that in Embodiment 1, except that: in step (2), the deposition temperature in the first deposition is 170°C; in step (3), the deposition temperature in the first deposition is 150°C. The thickness of the first incubation layer is about 3.6 nm, and the thickness of the second incubation layer is about 4.2 nm.

[0142] Raman spectroscopy analysis revealed that the overall crystallinity of each doped silicon layer in this embodiment was approximately 46%.

[0143] Comparative Example 1

[0144] Methods for manufacturing solar cells:

[0145] The difference between the solar cell fabrication method of Comparative Example 1 and Example 1 is that: in step (2), the process parameters of the first deposition and the second deposition are the same; in step (3), the process parameters of the first deposition and the second deposition are the same. The thickness of the first incubation layer is 6.4 nm, and the thickness of the second incubation layer is 7.3 nm.

[0146] Raman spectroscopy analysis revealed that the overall crystallinity of each doped silicon layer in this embodiment was approximately 32%.

[0147] Comparative Example 2

[0148] Methods for manufacturing solar cells:

[0149] The difference between the solar cell preparation method of Comparative Example 2 and Example 1 is that in step (3), the process parameters of the first deposition and the process parameters of the second deposition are the same.

[0150] Comparative Example 3

[0151] Methods for manufacturing solar cells:

[0152] The difference between the solar cell preparation method of Comparative Example 3 and Example 1 is that in step (2), the process parameters of the first deposition and the process parameters of the second deposition are the same.

[0153] The photoelectric performance and conversion efficiency of the HJT solar cells prepared in each embodiment and comparative example were tested. The electrical performance of the cells was tested by simulating sunlight and then contacting the cell electrodes with probes. Specific test results are shown in Table 1.

[0154] Table 1

[0155]

[0156] As can be seen from the crystallization rate and the data in Table 1, in the initial stage of depositing the doped silicon layer, by reducing the silane flow rate, increasing the ignition power, and lowering the deposition temperature of the first deposition, more microcrystals can be precipitated in the initial stage of the preparation process of the doped silicon layer, thereby reducing the thickness of the incubation layer, improving the overall crystallization rate of the doped silicon layer, and improving the short-circuit current, open-circuit voltage and photoelectric conversion efficiency of the solar cell.

[0157] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0158] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims, and the specification and drawings can be used to interpret the content of the claims.

Claims

1. A method for fabricating a solar cell, characterized in that, Includes the following steps: An intrinsic silicon layer is formed on the surface of the substrate; A first deposition and a second deposition are sequentially performed on at least one surface of the intrinsic silicon layer to sequentially form an incubation layer and a doped microcrystalline silicon layer on at least one surface of the intrinsic silicon layer; in the first deposition, the silane flow rate is 10 sccm to 30 sccm, the deposition time is 5 s to 10 s, and the ignition power is 10000 W to 15000 W; in the second deposition, the silane flow rate is 100 sccm to 300 sccm, the deposition time is 150 s to 200 s, and the ignition power is 6000 W to 8000 W.

2. The method for preparing a solar cell according to claim 1, characterized in that, The deposition temperature of the first deposition is 15°C to 30°C lower than that of the second deposition.

3. The method for preparing a solar cell according to claim 1, characterized in that, The first deposition satisfies at least one of the following characteristics: (1) The flow rate ratio of silane, doped gas and hydrogen is 1:(0.5~5):(1000~3000); (2) The gas pressure is 5 Torr~7 Torr; (3) The deposition temperature is 130℃~180℃.

4. The method for preparing a solar cell according to claim 1, characterized in that, The second deposition satisfies at least one of the following characteristics: (1) The flow rate ratio of silane, doped gas and hydrogen is 1:(0.5~5):(100~300); (2) The gas pressure is 3 Torr~6 Torr; (3) The deposition temperature is 150℃~200℃.

5. The method for preparing a solar cell according to claim 1, characterized in that, The thickness of the incubation layer is 2nm~5nm; and / or, The thickness of the doped microcrystalline silicon layer is 15 nm to 40 nm.

6. The method for preparing a solar cell according to claim 5, characterized in that, The incubation layer comprises the following elements in the following mass percentages: 1%~1.5% carbon, 2%~3% oxygen, 1%~3% dopant elements, and the balance silicon; and / or, The doped microcrystalline silicon layer comprises the following elements in the following mass percentages: 1%~1.5% carbon, 2%~3% oxygen, 1%~3% dopant elements, and the balance silicon.

7. The method for preparing a solar cell according to any one of claims 1 to 6, characterized in that, Forming an intrinsic silicon layer on the surface of a substrate includes the following steps: A first intrinsic amorphous silicon sublayer is prepared on the surface of a substrate using process gases including silane and carbon dioxide; A second intrinsic amorphous silicon sublayer is prepared on the surface of the first intrinsic amorphous silicon sublayer using a process gas including silane; A third intrinsic amorphous silicon sublayer is prepared on the surface of the second intrinsic amorphous silicon sublayer using process gases including silane and hydrogen.

8. The method for preparing a solar cell according to any one of claims 1 to 6, characterized in that, Forming an intrinsic silicon layer on the surface of a substrate; sequentially performing a first deposition and a second deposition on at least one surface of the intrinsic silicon layer to sequentially form an incubation layer and a doped microcrystalline silicon layer on at least one surface of the intrinsic silicon layer includes the following steps: A first intrinsic amorphous silicon layer is formed on the front side of the substrate, and a first incubation layer and a first doped microcrystalline silicon layer are formed sequentially on the surface of the first intrinsic amorphous silicon layer away from the substrate by the first deposition and the second deposition performed in sequence. A second intrinsic amorphous silicon layer is formed on the back side of the substrate, and a second incubation layer and a second doped microcrystalline silicon layer are formed sequentially on the surface of the second intrinsic amorphous silicon layer away from the substrate by the first deposition and the second deposition performed in sequence. The first doped microcrystalline silicon layer and the second doped microcrystalline silicon layer have opposite doping types.

9. A solar cell, characterized in that, The solar cell is prepared by the method described in any one of claims 1 to 8.

10. The solar cell according to claim 9, characterized in that, The substrate includes: a first intrinsic amorphous silicon layer, a first incubation layer, a first doped microcrystalline silicon layer, a first transparent conductive layer, and a first electrode, which are sequentially stacked on the front side of the substrate, and the thickness of the first incubation layer is 2nm~5nm; and a second intrinsic amorphous silicon layer, a second incubation layer, a second doped microcrystalline silicon layer, a second transparent conductive layer, and a second electrode, which are sequentially stacked on the back side of the substrate, and the thickness of the second incubation layer is 2nm~5nm.

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