System and method for testing power consumption of integrated circuit

Abstract

The invention relates to the technical field of integrated circuit power consumption testing, in particular to an integrated circuit power consumption testing system and method. The method comprises the following steps: setting a dynamic sampling control strategy for the integrated circuit; based on the dynamic sampling control strategy, pulse testing is carried out on the integrated circuit, IR Drop distribution calculation is carried out, and local power consumption voltage calibration grid points are generated; dynamically analyzing an instantaneous power consumption component space heat map according to a local power consumption voltage calibration grid point, and performing temperature field thermal evolution processing to generate dynamic coupling temperature stable field data; and evaluating an electromigration original risk index through the local power consumption voltage calibration grid point and the instantaneous power consumption component space heat map, and performing interconnection line risk state mapping to obtain an integrated circuit risk map. According to the invention, high-precision real-time measurement of power consumption distribution of the integrated circuit is realized, and hot spot areas and electromigration risks in the integrated circuit are accurately evaluated based on a differential processing strategy of an active area and a passive area.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit power consumption test, in particular to an integrated circuit power consumption test system and method. BACKGROUND

[0002] In high-density integrated circuits, the power consumption distribution presents a high degree of non-uniformity, and local areas will form power consumption hot spots. The temperature of these hot spot areas is significantly higher than that of the surrounding areas. The main cause of the problem is that there is a significant uneven distribution of power consumption inside the integrated circuit. Some key functional units will produce instantaneous power peaks far exceeding the average level under certain working modes, causing a sharp rise in local temperature. This temperature gradient not only accelerates the process of electron migration, but also causes changes in interconnection line impedance, further exacerbating the voltage drop condition, forming a vicious cycle. However, the traditional integrated circuit power consumption test method mainly relies on static power consumption models and empirical thermal analysis, and usually uses full-chip average power consumption or a preset power consumption template for evaluation. These methods perform well when dealing with integrated circuits with simple structures and single functions, but they cannot accurately capture the instantaneous power consumption distribution under dynamic working loads when faced with modern high-power density integrated circuits. It is easy to confuse local instantaneous power peaks with average power consumption, resulting in serious deviations in hot spot area prediction. SUMMARY

[0003] Based on this, the present application provides an integrated circuit power consumption test system and method to solve at least one of the above technical problems.

[0004] To achieve the above-mentioned purpose, an integrated circuit power consumption test method includes the following steps: Step S1: Deploying Hall sensors on the integrated circuit and setting a dynamic sampling control strategy; performing pulse testing on the integrated circuit based on the dynamic sampling control strategy, and performing circuit measurement channel connected domain gradient analysis to generate interconnection layer gradient marking data; Step S2: Obtain the integrated circuit GDSII layout data; calculate the IR Drop distribution according to the integrated circuit GDSII layout data and the interconnection layer gradient marking data, and perform grid merging processing to generate local power consumption voltage calibration grid; Step S3: Based on the integrated circuit GDSII layout data, identify the active transistor area of the local power consumption voltage calibration grid, and then perform dynamic grid power consumption source analysis and reference leakage power consumption calculation respectively to obtain the instantaneous power consumption component space thermal map; Step S4: Perform temperature field thermal evolution processing according to the instantaneous power consumption component space thermal map to generate dynamic coupling temperature stable field data; evaluate the electron migration original risk index through the local power consumption voltage calibration grid and the instantaneous power consumption component space thermal map, and map the interconnection line risk state according to the integrated circuit GDSII layout data to obtain the integrated circuit risk atlas.

[0005] Preferably, the present application also provides an integrated circuit power consumption test system for performing the integrated circuit power consumption test method as described above, and the integrated circuit power consumption test system comprises: a circuit signal acquisition module, configured to perform Hall sensor deployment on the integrated circuit, and set a dynamic sampling control strategy; perform pulse test on the integrated circuit based on the dynamic sampling control strategy, and perform circuit measurement channel connected domain gradient analysis to generate interconnection layer gradient marking data; a voltage drop mapping module, configured to obtain integrated circuit GDSII layout data; perform IR Drop distribution calculation based on the integrated circuit GDSII layout data and the interconnection layer gradient marking data, and perform grid point merging processing to generate a local power consumption voltage calibration grid point; an intelligent power consumption analysis module, configured to perform active transistor region identification on the local power consumption voltage calibration grid point based on the integrated circuit GDSII layout data, and then perform dynamic grid point power consumption source analysis and reference leakage power consumption calculation to obtain a transient power consumption component space heat map; a thermal risk assessment module, configured to perform temperature field thermal evolution processing based on the transient power consumption component space heat map, and then assess an electromigration original risk index, and perform interconnection line risk state mapping based on the integrated circuit GDSII layout data to obtain an integrated circuit risk atlas.

[0006] The application realizes real-time high-precision monitoring of current distribution by deploying a Hall sensor and a dynamic sampling control strategy, overcoming the limitations of traditional power consumption tests relying on static models. The combination of pulse testing and connected domain gradient analysis enables the system to accurately capture transient current changes and distinguish between local power consumption peaks and average power consumption, avoiding the loss of key information in traditional methods. The collaborative analysis of GDSII layout data and interconnection layer gradient markers enables the mapping and conversion from physical structure to electrical characteristics, significantly improving the accuracy of IR Drop calculation and solving the problem of inaccurate voltage drop prediction in traditional methods. The active transistor area identification mechanism enables power consumption subdivision at the functional unit level, allowing the system to distinguish the power consumption contributions of different functional modules under various operating modes. The combination of dynamic grid power consumption source analysis and reference leakage power consumption calculation successfully decouples dynamic and static power consumption components, avoiding the confusion between instantaneous power peaks and average power consumption in traditional methods. The generation of instantaneous power consumption component spatial heat maps visualizes the power consumption distribution and intuitively presents the formation mechanism and distribution characteristics of power consumption hotspots. The temperature field thermal evolution processing technology establishes an accurate mapping relationship from power consumption to temperature, enabling the prediction of temperature gradients and evolution trends in hotspot areas under complex workloads, overcoming the reliance on empirical models in traditional thermal analysis methods. Based on the current density spatio-temporal distribution matrix, the electromigration risk assessment, combined with thermal conductivity characteristic parameters, realizes accurate prediction of interconnection line reliability, effectively preventing changes in interconnection line impedance and voltage drop deterioration caused by temperature gradients. This scheme is particularly suitable for multi-functional complex integrated circuits, effectively preventing performance degradation and failure caused by excessive local temperature, prolonging device service life, reducing maintenance costs, and providing more accurate reliability guarantees for high-density integrated circuit design and manufacturing, promoting the development of integrated circuit technology towards higher integration and lower power consumption. Therefore, the integrated circuit power consumption test method of the application realizes accurate IR Drop calculation by combining GDSII layout data and interconnection layer gradient marker technology; generates high-resolution power consumption spatial heat maps through power source analysis methods that distinguish between active and passive areas; realizes thermal-electric coupling analysis based on temperature field thermal evolution algorithms of multi-material layer thermal properties; introduces multi-physical domain collaborative calculation models of current interference, joule self-heating, and thermal-induced mechanical stress to evaluate electromigration risk, accurately predict the electromigration risk of high-power density integrated circuits, and effectively improve the reliability evaluation accuracy of high-power density integrated circuits. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 The flowchart of the steps of the integrated circuit power consumption test method of the application is shown in the figure. The realization of the purpose, functional characteristics and advantages of the application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0008] The technical method of the present application will be described clearly and completely below in conjunction with the drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0009] In addition, the drawings are only schematic illustrations of the present application and are not necessarily drawn to scale. Identical reference numerals in the drawings represent identical or similar parts, and thus repeated descriptions thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities, which do not necessarily have to correspond to physically or logically independent entities. The functional entities can be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different network and / or processor methods and / or microcontroller methods.

[0010] It should be understood that although the terms "first", "second" and the like can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the exemplary embodiments, a first element can be referred to as a second element, and similarly a second element can be referred to as a first element. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0011] To achieve the above-mentioned purpose, please refer to Figure 1 The present application provides a method for testing the power consumption of an integrated circuit, comprising the following steps: Step S1: deploying a Hall sensor on the integrated circuit and setting a dynamic sampling control strategy; performing pulse testing on the integrated circuit based on the dynamic sampling control strategy, and performing gradient analysis on the connected domain of the circuit measurement channel to generate interconnection layer gradient marking data; Step S2: obtaining GDSII layout data of the integrated circuit; performing IR Drop distribution calculation based on the GDSII layout data of the integrated circuit and the interconnection layer gradient marking data, and performing grid merging processing to generate local power consumption voltage calibration grid; Step S3: identifying the active transistor region of the local power consumption voltage calibration grid based on the GDSII layout data of the integrated circuit, and then performing dynamic grid power consumption source analysis and reference leakage power consumption calculation, respectively, to obtain a transient power consumption component spatial heat map; Step S4: Perform temperature field thermal evolution processing based on the instantaneous power consumption component spatial heat map to generate dynamic coupled temperature stable field data; evaluate the original electromigration risk index through local power consumption voltage calibration grid points and instantaneous power consumption component spatial heat map, and perform interconnect risk state mapping based on integrated circuit GDSII layout data to obtain integrated circuit risk map.

[0012] In this embodiment of the invention, the integrated circuit power consumption testing method includes the following steps: Step S1: Deploy Hall sensors on the integrated circuit and set a dynamic sampling control strategy; perform pulse testing on the integrated circuit based on the dynamic sampling control strategy, and perform gradient analysis of the connected domains of the circuit measurement channels to generate interconnect layer gradient label data; In this embodiment of the invention, an MSA-600 microsystem analyzer is used to scan the surface of the integrated circuit. A Leica LMS-7500 laser marking system is used to etch 64×64 grid reference points in the metal pad area, with the grid spacing precisely controlled at 25 micrometers. Subsequently, an ABB-IRB360 parallel robot from Switzerland, coupled with a Cognex vision system, is used to place Hall sensors one by one at the reference point positions, maintaining a 3-micrometer gap between the sensor sensing surface and the integrated circuit surface. Electrical connections to the sensors are achieved using a SHIBAHARA-5000 bonding device from Japan, with a gold wire diameter of 15 micrometers. The system is set to a standard sampling frequency of 10kHz. When a current density exceeding [a certain value] is detected... The clock speed is automatically increased to 1MHz. A pulse test is then performed, using a Keysight B2962A to generate stepped voltage pulses from 0.8V to 3.6V, which are simultaneously acquired across multiple channels via an FPGA controller. The system constructs a three-dimensional matrix from the acquired current density values ​​according to the measurement channel coordinates and timestamps. The spatial gradient is calculated using the finite difference method, and the gradient values ​​are subjected to a threshold determined by the OTSU algorithm for binarization and classification. Finally, a recursive labeling algorithm is used to perform connected component analysis, identify adjacent high-gradient points, and perform clustering to generate interconnect layer gradient labeling data.

[0013] Step S2: Obtain integrated circuit GDSII layout data; calculate IR Drop distribution based on integrated circuit GDSII layout data and interconnect layer gradient marker data, and perform grid merging processing to generate local power consumption voltage calibration grid points; In the embodiment of the present application, the interconnection layer gradient mark data is aligned with the GDSII layout data in spatial coordinates by multi-level registration technology. The system sets the mark coordinate system origin (0, 0) corresponding to the (150 μm, 150 μm) position in the GDSII coordinate system, and calculates the accurate coordinate transformation matrix by the least square registration algorithm to ensure that the alignment error is less than 0.8 microns. Then the layout analysis engine is used to extract the metal interconnection line geometric parameters, including line width W (0.1 μm-10 μm), line length L (0.5 μm-1000 μm) and metal layer thickness T (Metal1 is 0.4 μm to Metal6 is 1.2 μm). The system calculates the resistance value of each metal line according to the interconnection line geometric parameters, and distributes the current measurement value to the corresponding line segment, and corrects the resistivity considering the temperature effect. The improved Dijkstra algorithm is used for power network topology analysis, and the power network path is divided into discrete resistance units from the power pad node to the active area node. The system uses a matrix solver to calculate the voltage drop of each path and accumulates it to generate IR Drop distribution data. Finally, a 5 μm×5 μm uniform grid is defined for the whole chip, and the current density and IR Drop data are fused by spatial weighted average algorithm, and the power density value and voltage drop value are saved in each grid point to form a local power voltage calibration grid.

[0014] Step S3: Based on the integrated circuit GDSII layout data, the local power voltage calibration grid is identified as an active transistor area, and then dynamic grid power source analysis and reference leakage power calculation are performed to obtain a transient power component spatial thermal map; In the embodiment of the present application, the GDSII format layout data is loaded through a hierarchical parser, and the graphic data of DIFFUSION, POLY and METAL1-6 layers is extracted, and all graphic data is rasterized into a 5 μm×5 μm uniform grid. Spatial overlap detection is performed on each grid point, and when the point is located in the DIFFUSION and POLY overlapping area, it is marked as an "active transistor area". For the grid points with active area attribute, the local voltage scaling factor is calculated, and the actual switching power consumption is calculated in combination with the preset nominal switching power density value (25 ) of 28 nm process. For the passive area grid points, the joule heat power consumption is calculated based on the current density and metal resistivity. The system maps the two kinds of power consumption data to the unified 320×320 full chip grid through the data registration engine. At the same time, the system applies the subthreshold leakage current model to calculate the reference leakage power consumption based on the 35℃ reference temperature, and considers the comprehensive effect of gate leakage and junction leakage. Finally, the dynamic power and static power are numerically superimposed in the spatial position by the data fusion processor, and the power density thermal map is generated by the pseudo-color mapping technology to form a transient power component spatial thermal map.

[0015] Step S4: generating dynamic coupling temperature stable field data by temperature field thermal evolution processing according to the transient power consumption component space thermal map; and evaluating the electromigration original risk index through the local power consumption voltage calibration grid and the transient power consumption component space thermal map, and mapping the interconnection line risk state according to the integrated circuit GDSII layout data to obtain the integrated circuit risk atlas.

[0016] In the embodiment of the present application, the standard layered structure parameters of the 28nm process node are obtained by a process database parser, and the physical dimensions and thermophysical properties of 14 layers of materials from the silicon substrate to the passivation layer. The system establishes a three-dimensional grid model, with a horizontal resolution of 5μm×5μm and a vertical resolution of 14 layers. Each grid cell is assigned a heat capacity, thermal conductivity, and interface thermal resistance parameter. The finite-difference time-domain algorithm performs thermal diffusion calculations with a 1 picosecond time step, and power consumption data is injected as a heat source term into the corresponding region. The system performs multiple iterations by coupling the thermal power consumption analyzer to achieve feedback correction of temperature and leakage power consumption, and finally generates dynamic coupling temperature stable field data. Subsequently, the system extracts the current density peak value and stable operating temperature for each metal interconnection line, considers the current interference caused by adjacent high-power modules, calculates the joule self-heating effect, and activates the thermal mechanical stress factor when the temperature exceeds 105℃. The risk index calculation considers current density, temperature acceleration factor, and geometric correction coefficient, and sets the risk threshold through statistical distribution analyzer for grade division. Finally, the system maps the risk state to the GDSII layout in a three-color scheme of green (safe), yellow (warning), and red (high risk) to form an integrated circuit risk atlas.

[0017] Preferably, the Hall sensor deployment on the integrated circuit in step S1 and the setting of the dynamic sampling control strategy include: The surface metal pad area of the integrated circuit is marked with a sensor array positioning marker, a 64×64 grid reference point is established, and the grid spacing is set to 25 microns, aligned with the wiring spacing of the internal metal interconnection layer in the integrated circuit, to obtain sensor positioning reference data. Based on the sensor positioning reference data, the Hall sensor is precisely mounted, and the Hall sensor is placed one by one at the reference point position, with a 3-micron gap between the sensor sensing surface and the metal layer on the surface of the integrated circuit, to obtain sensor array layout data. Each sensor's signal pin is connected to a dedicated multiplexing acquisition circuit in the integrated circuit through the sensor array layout data to perform electrical connection configuration. The working power supply of the multiplexing acquisition circuit and the integrated circuit are synchronously controlled, and the standard sampling frequency is set to 10kHz. When any Hall sensor detects that the current density value exceeds When the sensor and its surrounding 3x3 neighborhood of 9 sensors are detected, the sampling frequency of the sensor and its surrounding 3x3 neighborhood of 9 sensors is automatically switched to 1MHz, obtaining a dynamic sampling control strategy.

[0018] In the embodiment of the application, for example, a JEOL JSM-7800F scanning electron microscope is used to perform high-resolution imaging on the surface of the integrated circuit, and the resolution is set to 10 nanometers. Then, a DMG-4 precision laser etching system is used to draw 64x64 grid reference points on the surface of the metal pad, the diameter of the laser beam is controlled to be 5 microns, the laser power is set to 0.8 watts, and the exposure time is 50 nanoseconds per point. The grid spacing is accurately controlled to be 25 microns, and the integrated circuit mask layout data is compared and calibrated with the actual etching position to ensure that the grid reference points are completely aligned with the wiring spacing of the internal metal interconnection layers M4-M6, and the deviation is controlled within ±0.5 microns.

[0019] The ML-5098 semiconductor chip mounting equipment is used to perform the precise mounting operation of the Hall sensor. Before mounting, the PDMA-550 high-purity anhydrous ethanol is used to clean the surface of the integrated circuit, and the cleaning time is 30 seconds, and then the surface is dried at 100°C for 5 minutes. During the mounting process, the precise coordinates of each reference point are read from the sensor positioning reference data file, and the XYZ three-axis positioning system of the ML-5098 equipment is used to place each AHS-377 Hall sensor (20μm x 20μm x 5μm in size) at the corresponding reference point position one by one. During the mounting process, the laser interferometer is used to monitor the distance between the sensor and the surface of the integrated circuit in real time, and when the distance is detected to be less than 5 microns, the special UV-321 type epoxy resin adhesive is injected for fixation, and the ultraviolet curing time is set to 8 seconds, and the curing temperature is controlled to be After the mounting of each sensor is completed, the three-dimensional profile scanner is used to measure and verify the position of the sensor, and the sensor array layout data table is generated.

[0020] The FIB-4500 focused ion beam micro-connection system is used to complete the electrical connection and configuration of the Hall sensor. According to the sensor array layout data, first, a gold / titanium double-layer metal pad with a thickness of 800 nanometers is evaporated at the signal pin of each sensor, and the evaporation temperature is controlled to be 220°C, and the gas pressure is maintained at ​The pins are then deposited with metal interconnects between the pins and the integrated circuit multiplexing acquisition circuit using a focused ion beam, with a width of 2 microns and a thickness of 1 micron. The metal interconnects are made of copper / aluminum alloy material, and the deposition rate is controlled at 50 nanometers per minute. Each interconnect is measured by a four-point probe tester to ensure that the resistance value is less than 0.5 ohms. An additional 70 nanometer thick silicon oxide protective layer is added to the signal path to prevent external environmental interference. The connection paths of all 4096 sensors are tested for continuity by a TEIV-7000 type electrical integrity verification system, with a test voltage of 0.5 volts and a test current of 10 microamperes, to ensure that each sensor is correctly connected to the dedicated multiplexing acquisition circuit.

[0021] Based on the STC89C52 single-chip microcomputer and the FPGA XC7K325T controller, the system clock is set to 80 MHz, and the multiplexing acquisition circuit is connected to the FPGA through a 32-channel ADC AD7606 module. The sampling frequency is set to 10 kHz under standard conditions, corresponding to a sampling period of 100 microseconds for each sensor. The acquisition circuit and the integrated circuit power supply are synchronously controlled by a phase-locked loop circuit built into the FPGA, with a phase difference of less than 5 nanoseconds. The real-time data processing unit continuously calculates the current density value detected by each Hall sensor, and the calculation method is to convert the Hall sensor output voltage value into the corresponding magnetic field strength by table lookup method, and then calculate the current density according to the integrated circuit metal layer thickness at the sensor position. When any sensor detects a current density value exceeding A / cm², the FPGA controller immediately modifies the sampling control register value, increases the sampling frequency of the sensor and the 9 sensors in the surrounding 3x3 area to 1 MHz, corresponding to a sampling period of 1 microsecond, and the remaining sensors remain at a sampling frequency of 10 kHz. The sampling duration is 500 milliseconds, and then automatically returns to the standard sampling frequency.

[0022] Preferably, the step S1 of performing pulse testing on the integrated circuit based on the dynamic sampling control strategy and performing circuit measurement channel connected domain gradient analysis includes: Based on the dynamic sampling control strategy, the integrated circuit is configured for multi-channel synchronous acquisition, and a pulse test sequence is performed to obtain multi-channel original time sequence readings; According to the multi-channel original time sequence readings, a space-time data matrix is constructed, and the current density values collected within 10 seconds are arranged in three dimensions according to the measurement channel coordinates and time stamps to obtain a current density space-time distribution matrix; The current density space-time distribution matrix is subjected to spatial neighborhood difference calculation, and the current density change rate of adjacent measurement points is calculated with a step size of 25 microns to obtain neighborhood current change rate data; Based on the neighborhood current change rate data, the current density gradient amplitude of each measurement point is evaluated; The current density gradient amplitude is binarized and classified by setting a gradient threshold value, and the region greater than the threshold value is marked as 1, and the region less than or equal to the threshold value is marked as 0, to obtain gradient classification mark data; wherein 1 represents a high gradient mark point, and 0 represents a low gradient mark point; The channel coordinate data is measured according to the multi-channel original time sequence reading extraction circuit; The gradient classification mark data is associated with the circuit measurement point coordinate data by position indexing, and the corresponding relationship between the gradient category and the spatial position is established, to obtain spatial gradient index data; According to the spatial gradient index data, the connected domain analysis is performed, the adjacent high gradient mark points are identified and the region clustering is divided, to obtain the interconnection layer gradient mark data.

[0023] In the embodiment of the application, the multi-channel synchronous acquisition configuration adopts an LTC2358-18 type 18-bit precision ADC converter and an FPGA XC7A200T to work cooperatively. First, 64 groups of acquisition control registers are configured by the FPGA, each group of which controls 64 channels, forming a 4096-channel matrix type acquisition network. The acquisition clock synchronization signal is generated by a crystal oscillator with a 50MHz reference frequency, which is distributed to each ADC through a frequency divider, and the phase deviation is controlled within 2 nanoseconds. The pulse test sequence is generated by an HP8110A pulse generator, with a pulse width of 20 nanoseconds, a rise / fall time of 5 nanoseconds, an amplitude of 1.8 volts, and a repetition frequency of 1MHz. The test sequence contains 5 different working modes, namely: standby mode, low load mode, standard load mode, high load mode and peak load mode, each mode lasting for 2 seconds and being executed in sequence. During the execution process, the FPGA is dispatched by the ARM Cortex-M4 microcontroller to perform real-time sampling on all 4096 Hall sensors, with a standard sampling frequency of 10kHz and a high-frequency sampling area of 1MHz. After being converted by the 18-bit ADC, all sampling data are temporarily stored through the cache to form multi-channel original time sequence readings, each reading containing a 64-bit timestamp, a 12-bit channel number and an 18-bit voltage value.

[0024] The multi-channel original time sequence readings are sorted according to the timestamp, and the sorting algorithm adopts radix sorting with a time complexity of O(n). The sorted data are segmented according to a 10-second time window, each segment containing 100,000 sampling points of the standard area and 10,000,000 sampling points of the high-frequency area. Subsequently, the sorted data are reorganized into a three-dimensional matrix structure, and the matrix dimension is , wherein The space coordinates of the sensor are represented by T, and the number of sampling points on the time axis is represented by T. In the standard sampling area, the value of T is 100,000, and in the high-frequency sampling area, the value of T is 10,000,000. For each sampling point, the voltage value is converted into the corresponding magnetic field strength by querying the calibration table pre-stored in the SRAM, and the conversion resolution is 0.1 microtesla. Further, the current density value is calculated by the inverse calculation of the Biot-Savart law, and the calculation accuracy is 0.1 A / cm². The calculation result is written back into the three-dimensional matrix, replacing the original voltage value, and finally forming the current density space-time distribution matrix.

[0025] The current density space-time distribution matrix data is transmitted from the host memory to the GPU memory at a transmission rate of 8 GB / s. On the GPU, 4096 parallel threads are started, each responsible for processing all data of a spatial measurement point on the time axis. For each spatial point (i, j), the current density difference values in the four adjacent directions (i+1, j), (i-1, j), (i, j+1), and (i, j-1) are calculated respectively, and the central difference format is used in the calculation. The spatial step is fixed at 25 microns, and the calculation formula uses a second-order accuracy finite difference format, and the boundary points are processed using one-sided difference. The calculation result forms four direction gradient component matrices, each with the same size as the original current density matrix. For each sampling point on the time axis, the calculation process is repeated to capture the characteristics of the current distribution over time. The difference calculation result is saved as neighborhood current change rate data, with a data format of 32-bit floating point number, containing four direction gradient components and gradient calculation time stamp.

[0026] The four direction gradient components in the neighborhood current change rate data are read, and the data is packed into 512-bit registers in groups of 16 floating point numbers. For the four direction gradient components of each spatial point (i, j) at time t, the Euclidean norm is calculated as the gradient amplitude. The calculation process uses AVX-512 instructions to process the data of 16 measurement points at a time, first squares the four direction gradient components, then sums them, and finally takes the square root of the result. The calculation uses 32-bit floating point format, with an accuracy of 0.01 For special areas such as chip edges, the missing gradient components are handled by zero padding. The calculation result forms a gradient amplitude matrix, with a matrix size of 64x64xT, consistent with the time dimension of the original current density matrix. For ease of subsequent processing, the maximum value, minimum value, and average value of each spatial point in the gradient amplitude matrix over the entire time window are extracted to form a statistical feature matrix.

[0027] The gradient amplitude distribution characteristics are analyzed by a histogram statistical method. The gradient amplitude data of the entire measurement area is divided into 256 intervals according to the value size, the number of points in each interval is counted, and a gradient amplitude histogram is generated. The optimal gradient threshold is calculated based on the OTSU algorithm, which determines the threshold by maximizing the inter-class variance, and the implementation uses the built-in lookup table of FPGA for acceleration. The typical value of the calculated gradient threshold is . Then, each element in the gradient amplitude matrix is compared with the threshold, and the points greater than the threshold are marked as 1 (high gradient marker points), and the points less than or equal to the threshold are marked as 0 (low gradient marker points). To reduce noise interference, a 3x3 median filter is implemented, with a filter kernel size of 3x3 pixels, to smooth isolated high gradient points or low gradient points. The binary result after processing is saved as gradient classification marker data.

[0028] The 12-bit channel number information is extracted from the multi-channel original time sequence readings, with the channel number ranging from 0 to 4095. The channel number is converted to physical coordinates through a pre-defined channel mapping table, which is stored in ROM and contains the X coordinate, Y coordinate and Z layer information corresponding to each channel number. The X and Y coordinate ranges are 0 to 63, corresponding to a 64x64 grid; the Z layer information represents the metal interconnection layer where the sensor is located, ranging from 1 to 6, corresponding to M1 to M6 layers. The coordinate extraction process uses a hash table to accelerate the query, with an average query time of less than 50 nanoseconds. For each valid channel, its physical coordinates and channel state information are recorded, including the channel validity flag, calibration coefficient and noise level. To ensure the accuracy of the coordinate data, the extracted coordinate data is checked by cyclic redundancy check (CRC32), and the channels found to have check errors are marked as invalid channels. Finally, the circuit measurement channel coordinate data table is formed, containing the physical position information and state flags of 4096 valid channels, stored in a structure array format.

[0029] A spatial index structure is constructed, and the grid space is recursively divided into multiple sub-regions by a quadtree structure, with each leaf node containing information of a single measurement point. The quadtree construction process uses a depth-first strategy, with a maximum depth of 6 layers, and occupies about 2MB of memory space after construction. Then, each marker point (value 0 or 1) in the gradient classification marker data is mapped to the corresponding position in the circuit measurement channel coordinate data table. The mapping process is implemented through a coordinate hash function, which maps the (x, y) coordinate pair to a unique hash value, and hash collisions are solved by a linked list method. For each high gradient marker point (value 1), its physical coordinates, the metal layer it belongs to and the corresponding channel number are recorded; for low gradient marker points (value 0), only statistical information is recorded. After the association process is completed, the spatial gradient index data is formed, which contains the position information and topological relationship of all high gradient points.

[0030] An adjacency matrix is constructed based on the spatial gradient index data, the matrix dimension is the number of high gradient points , and the matrix element value is 0 or 1, indicating whether two points are adjacent. The adjacency determination criterion is Manhattan distance less than or equal to 25 microns (equivalent to adjacent grid points). Subsequently, the adjacency matrix is processed by a two-stage connected component labeling algorithm, the first stage uses a parallel scanning method to assign a temporary label to each high gradient point, and the second stage solves the equivalent label problem by iteration merging. To speed up the processing, the algorithm realizes a pipeline parallel architecture on the FPGA, and the processing speed reaches 100M points / second. After the connected component labeling is completed, the geometric features of each connected region are calculated, including area, perimeter, centroid and principal axis direction. The area calculation is the number of points in the region multiplied by the grid cell area ); the perimeter is estimated by the number of boundary points; the centroid and the principal axis are calculated by the region matrix features. Based on the geometric features, the connected regions are classified to identify high gradient regions corresponding to different metal interconnection layers, and interconnection layer gradient labeling data is generated, which includes the boundary point set of each connected region, the region label and the metal layer information.

[0031] Preferably, the IR Drop distribution calculation in step S2 according to the integrated circuit GDSII layout data and the interconnection layer gradient labeling data, and the grid point merging processing include: Align the spatial coordinates of the interconnection layer gradient labeling data and the integrated circuit GDSII layout data to obtain layout alignment current data; Extract the metal interconnection line geometric dimensions corresponding to each test channel current vector path in the layout alignment current data from the integrated circuit GDSII layout data to generate interconnection line geometric parameters; Based on the interconnection line geometric parameters, calculate the point-by-point current density of the layout alignment current data to obtain instantaneous current density data; According to the instantaneous current density data, perform path accumulation calculation to obtain IR Drop distribution data; Merge the instantaneous current density data and the IR Drop distribution data to generate local power consumption voltage calibration grid points.

[0032] In the embodiment of the present application, the spatial coordinate alignment of the interconnection layer gradient mark data and the integrated circuit GDSII layout data is performed by using the Cadence Virtuoso Layout Suite XL platform. First, the coordinate mapping relationship is established by using the Calibre three-point alignment algorithm, and the left lower corner origin (0, 0), the right upper corner point (1600 μm, 1600 μm) and the center point (800 μm, 800 μm) of the chip are selected as the reference points. The affine transformation matrix is constructed by using the accurate coordinate values measured by the Hall sensor at the three positions. The transformation matrix calculation accuracy is 0.1 nanometer, which ensures that the measurement coordinate system and the layout coordinate system are strictly aligned. Subsequently, the affine transformation is applied to each high gradient region in the interconnection layer gradient mark data, so as to convert it from the measurement coordinate system to the GDSII layout coordinate system. The conversion process adopts the bilinear interpolation algorithm, which ensures that the conversion accuracy is better than 0.5 microns. For each converted high gradient region, the metal layer information at the corresponding position in the GDSII layout is extracted, including the layer number (M1-M6), the layer thickness (0.2 μm-1.5 μm) and the resistivity (1.68-2.65 μΩ·cm). By searching for the nearest metal interconnection line segment, the corresponding relationship between the high gradient region and the specific interconnection line is established, and the layout alignment current data is formed. The layout alignment current data includes the coordinates of each high gradient region, the belonging metal layer, the corresponding interconnection line identifier and the measured current value.

[0033] The geometric size of the metal interconnection line is extracted from the integrated circuit GDSII layout data by using the Synopsys ICValidator tool. For each interconnection line marked in the layout alignment current data, the DRC (design rule check) analysis is performed to extract the geometric information. First, the GDSII file is parsed, and the binary data is converted into a memory data structure, and the parsing speed reaches 150 MB / s. For each identified interconnection line, the region query is performed to extract the polygon contour point set. The interconnection line width is calculated by using the polygon processing algorithm, and the minimum distance method is used to sample once every 5 microns in the vertical direction of the line segment, the distance between the two side edges is measured, and the average value is taken as the line width. The line width measurement accuracy is 10 nanometers. The line length is calculated by accumulating the lengths of multiple line segments, and the curved part is approximated by using the segmented straight line. The line thickness is extracted from the process file, and the corresponding table is obtained according to the metal layer number. The M1 layer thickness is 0.2 μm, the M2-M3 layer thickness is 0.5 μm, the M4-M5 layer thickness is 0.8 μm, and the M6 layer thickness is 1.5 μm. For the via and contact regions, their positions and sizes are additionally marked. All geometric parameters are organized into structured data, including the interconnection line ID, the starting coordinate, the ending coordinate, the line width, the line length, the line thickness, the metal layer number and the resistivity, to form the interconnection line geometric parameter table.

[0034] The interconnection line geometry parameters and layout alignment current data are loaded to the GPU memory, and the data transmission rate is 16 GB / s. 2048 CUDA thread blocks are started on the GPU, each containing 256 threads, forming a highly parallel computing architecture. For each interconnection line, it is divided into microsegments with a length of 1 micrometer, and each microsegment is regarded as a current density calculation unit. According to Ohm's law and the principle of current continuity, the current density value of each microsegment is calculated. The specific calculation formula is wherein represents the current density (unit: A / cm2), , represents the current value through the microsegment (unit: A), represents the microsegment cross-sectional area (unit: cm2), , , is the line width (unit: cm), is the line thickness (unit: cm). The temperature effect is considered in the calculation, and the correction formula of the resistivity changing with temperature is wherein is the resistivity at the current temperature, is the resistivity at the reference temperature , is the temperature coefficient (0.0039 / ℃ for copper), is the current temperature. The calculation result of each microsegment is saved as a 32-bit floating point number, forming the instantaneous current density data, which contains the microsegment ID, spatial coordinates, current density value and timestamp information.

[0035] The integrated circuit power distribution network topology graph is constructed, in which the nodes represent the intersection points of metal interconnection lines, and the edges represent the interconnection line segments, and the edge weight is the line segment resistance value. The resistance value calculation formula is wherein is the resistance value (unit: Ω), is the material resistivity (unit: Ω·cm), is the line segment length (unit: cm), is the line width (unit: cm), is the line thickness (unit: cm). From the power supply node, the voltage drop is calculated along the power distribution network. For each path, starting from the power supply end (the nominal voltage is 1.2 V), the voltage drop of each segment is accumulated according to the current direction, and the voltage drop calculation formula is wherein is the voltage drop (unit: V), is the line segment current (unit: A), is the resistance of the line segment (unit: Ω). The calculation process adopts a breadth-first search strategy to ensure that the shortest path from the power supply node to each load node is calculated. For the case of multiple power supplies, the superposition principle is used to calculate the voltage value of each point. Considering the effects of capacitance and inductance, an RC delay model is introduced to correct the transient response, and the RC time constant wherein is the equivalent capacitance (unit: F). The final IR Drop distribution data is generated, including the coordinates, voltage values, and timestamps of each node in the network, with a data resolution of 1 mV.

[0036] A uniform grid is established in the chip area, with a grid spacing of 5 microns, forming a 320x320 grid matrix. For each grid point, search for all measurement points in the transient current density data and IR Drop distribution data within a 10-micron radius. The data search uses the KD-tree algorithm, with a search time complexity of wherein is the total number of data points. A weighted average is performed on the searched measurement points, with a weight function of wherein is the distance from the measurement point to the grid point (unit: μm), is the smoothing factor (set to 5 μm). For the current density value, use the weighted average formula wherein is the current density value at the grid point , is the current density value of the measurement point , is the weight. Similarly, for the voltage drop value, use a similar formula to calculate the grid point value. At each grid point position, calculate the power density, with the formula wherein is the power density (unit: W / cm²), is the current density (unit: A / cm²), is the resistivity (unit: Ω·cm), is the voltage value (unit: V). Finally, generate the local power voltage calibration grid data, including the coordinates, current density, voltage drop, and power density values of each grid point, with a data precision of 16-bit floating point numbers.

[0037] Preferably, the path accumulation calculation according to the transient current density data includes: extracting the power network topology structure from the integrated circuit GDSII layout data, and constructing power network topology node data; identifying the current path from the power pad to the active area in the integrated circuit based on the power network topology node data, and generating a current conduction path sequence; The current conduction path sequence is used to divide each path into discrete resistance units, to obtain discretized resistance path data; According to the instantaneous current density data, a corresponding current value is matched for each resistance unit in the discretized resistance path data, to obtain path segment current value data; Based on the path segment current value data and the discretized resistance path data, a step-by-step pressure drop calculation is performed and accumulated along the path, to generate IR Drop distribution data.

[0038] In the embodiment of the application, the GDSII format file is loaded into the Assura database, and the parsing speed is 350 MB / min. The power network related layers are screened out through a layer selection filter, including VDD and VSS networks in M1 to M6 metal layers, and the screening condition is set as metal traces containing "VDD", "VCC", "VSS" or "GND" in the network name. The polygon data is extracted from the screening result, the connected regions are identified through a boundary tracking algorithm, and the algorithm resolution is 5 nanometers. Skeletonization processing is performed on the connected regions, the center line representation is converted from the metal traces with uneven width by using the axis transformation algorithm, and the key topological information is retained. The node types are marked on the skeleton graph, the intersection points, T-shaped connection points and terminal points are marked as "intersection nodes", "branch nodes" and "terminal nodes" respectively. For the power pad area, the metal area with an area greater than 1000 square microns and located at the edge of the chip is marked as a "power pad node" through morphological feature recognition. All nodes together with their connection relationship are stored in an adjacency list data structure, and the node attributes include spatial coordinates (x, y, z), node type, belonging metal layer and connected edge list, to form power network topology node data.

[0039] All power pad nodes are identified in the power network topology node data, and a typical 7*7mm chip contains 8 power pad nodes and 12 ground pad nodes. All active region terminal nodes are also identified, and the determination is made through cross-checking with device layers (such as polysilicon gate layer and diffusion layer), and a typical design contains 2000-5000 active region terminal nodes. From each power pad node, a multi-start parallel shortest path search is performed to find the paths to all active region terminal nodes. In the path search, the edge weight is defined as the resistance value, and the calculation formula is , wherein is the resistance value (Ω), is the material resistivity (Ω·m), is the edge length (m), is the metal line width (m), is the metal thickness (m). The search algorithm uses a priority queue to achieve a time complexity of , wherein is the number of edges, The number of nodes. The complete paths are constructed from the terminal nodes to the power pad nodes by backtracking, each path contains a sequence of nodes and a corresponding sequence of metal segments. Redundancy elimination is performed on all paths, removing duplicate paths. The final current conduction path sequence is generated, containing the shortest resistance paths from each power pad to each active area.

[0040] For each path in the current conduction path sequence, first analyze its metal line segment geometry, including the starting point coordinates , the end point coordinates , the metal layer number ML and the line width W. For each metal line segment, it is segmented according to a fixed step size, which is set to 10 microns, and the line segment with a length less than 10 microns is kept intact without segmentation. The coordinates of the segmentation points are calculated by linear interpolation, and the interpolation formula is , where is the starting point coordinates, is the end point coordinates, is the interpolation parameter , and the step size is increments. The resistance value of each segmented segment is calculated, taking into account the influence of the temperature-dependent material resistivity, using the formula , where is the resistivity at the reference temperature (typically 25°C), is the temperature coefficient (0.0039 / °C for copper), is the current temperature (measured by an infrared thermal imager), is the length of the segmented segment, is the line width, is the metal thickness. Each resistance unit after segmentation contains starting point coordinates, end point coordinates, metal layer number, line width, length, resistance value and temperature value, forming discrete resistance path data, which is organized according to path ID and unit sequence number.

[0041] A three-dimensional spatial index structure is constructed, and the entire chip space is divided into hierarchical sub-regions using an octree, each leaf node contains no more than 8 instantaneous current density data points. The octree construction process is executed recursively, and the termination condition is that the number of points in the region is less than the threshold or the maximum depth (set to 10) is reached. For each resistance unit in the discrete resistance path data, a range query is performed in the octree, and the query radius is set to 50% of the length of the resistance unit, usually 5 microns. The query result is all current density measurement points within the spatial range of the resistance unit. When the query result contains multiple points, the current value of the resistance unit is calculated using distance-weighted averaging, and the weighting formula is , where is the current value of the measurement point , is the weight factor, , For measurement points The shortest distance to the center line of the resistor unit. To handle sparse measurement data areas, a minimum measurement point threshold (set to 3) is introduced. When the number of query results is less than the threshold, the query radius is expanded to 10 micrometers and the query is executed again. For areas that still do not have enough measurement points, nearest neighbor interpolation is used to estimate the current value. Finally, path segment current value data is generated, including the ID of each resistor unit and the corresponding current value I (unit: A).

[0042] Segment-by-segment voltage drop calculations are performed based on path segment current data and discretized resistance path data, considering dynamic resistance effects. First, all paths are grouped according to power pads, with paths powered by the same power pad grouped together. For each group of paths, the voltage drop is calculated from the power pad (nominal voltage). Starting with 1.2V or 0.9V (depending on the process node), calculate the voltage drop segment by segment along the path. The calculation formula is as follows: ,in For voltage drop (V), The value is the current (A). The resistance value (Ω) For the current nonlinearity coefficient (values ​​range from 0.05 to 0.15), The nominal current value (A) is used to normalize the high current effect. At the path branch points, Kirchhoff's current law is applied to calculate the current in each branch, taking into account the current shunting effect. The voltage drop is accumulated along each path to calculate the voltage value at each node, using the following formula: ,in For nodes voltage value, This is the power supply voltage. From power pads to nodes The sum of all voltage drops along the path. For multi-power pad cases, the superposition principle is applied to determine the final voltage of each node. Finally, IR Drop distribution data is generated, containing the three-dimensional coordinates of each node in the network. Voltage value timestamp And the corresponding function block information, with a data resolution of 0.1 millivolts.

[0043] Preferably, step S3 includes the following steps: Step S31: Based on the integrated circuit GDSII layout data, identify the physical attributes of each grid point in the local power consumption voltage calibration grid point, and generate regional attribute annotation grid point data; Step S32: When the grid attribute in the region attribute annotation grid data is an active transistor region, extract the local voltage value to obtain the active region voltage data; otherwise, extract the current value to obtain the passive region current data. Step S33: Dynamic grid power source analysis is performed according to the active region voltage data and the passive region current data, and dynamic power source distribution data is generated; Step S34: Based on the active region voltage data and the initial reference temperature of 35 degrees Celsius, the reference leakage power consumption is calculated, and static power source distribution data is obtained. Step S35: The dynamic power source distribution data and the static power source distribution data are subjected to numerical superposition processing in spatial position, and a transient power component spatial heat map is generated.

[0044] In the embodiment of the application, the functional layer information is extracted from the GDSII database, including the polysilicon gate layer (POLY), the diffusion layer (DIFF), the metal interconnection layer (M1-M6), the contact hole (CONT) and the via hole (VIA1-VIA5). For each 5 microns x 5 microns calibration grid point, spatial overlap analysis is performed to determine the overlapping relationship between the grid center point and each layer. When the grid point overlaps with the POLY layer and the DIFF layer at the same time, it is marked as "active transistor region"; when the grid point only overlaps with the metal interconnection layer, it is marked as "interconnection metal region"; when the grid point overlaps with the CONT or VIA layer, it is marked as "contact / via region"; when the grid point does not overlap with any of the above layers, it is marked as "blank region". The attribute recognition process uses a quadtree spatial index to accelerate, and the processing time of 640,000 grid points is less than 10 seconds. Further subdivision of transistor types, when the grid point falls in the PMOS region (NWELL overlaps with POLY and P+DIFF), it is marked as "PMOS region"; when the grid point falls in the NMOS region (POLY overlaps with N+DIFF but without NWELL), it is marked as "NMOS region". Finally, the region attribute labeled grid point data is generated, which contains grid point coordinates, region attribute identification and the name of the functional block to which it belongs.

[0045] The grid point data is stored according to the attribute type, and four independent data sets are established: active transistor region set, interconnection metal region set, contact / via region set and blank region set. For each grid point in the active transistor region set, the voltage value of the corresponding position is extracted from the local power consumption voltage calibration grid point data (unit: volt), and the voltage value resolution is 0.1 millivolt. The extraction process is realized by a hash table Fast query of time complexity. Considering the deviation of sampling position from the center of the grid, when the deviation exceeds 1 micron, the voltage value of the grid center point is calculated by bilinear interpolation. Extract the results to form active area voltage data, including grid coordinates, transistor type (NMOS / PMOS), voltage value and timestamp. For non-active areas (interconnect metal area, contact / via area and blank area), extract current value I (unit: milliampere) from local power consumption voltage calibration grid data, with a current resolution of 1 microampere. For interconnect metal areas, additional extraction of metal layer number ML and line width W information. Extract the results to form passive area current data, including grid coordinates, area type, current value, metal layer information (if applicable) and timestamp.

[0046] Load the active area voltage data and passive area current data into the GPU memory, with a total data size of about 1.2 GB. For each grid point in the active area voltage data, calculate the dynamic power Pd, the calculation formula is , where α is the activity factor (extracted from waveform analysis, range 0.01-0.5), is the gate capacitance (unit: farad, obtained from the process library), is the voltage value (unit: volt), is the clock frequency (unit: hertz, obtained from the test configuration). In the specific implementation, the unit area capacitance values of different types of transistors are queried from the process library: NMOS is , and PMOS is under 90 nanometer process. The calculation process uses CUDA kernel functions for parallel processing, with a single calculation throughput of 1 billion grid points / second. For each grid point in the passive area current data, calculate the dynamic power , the calculation formula is , where is the current value (unit: ampere), is the local resistance (unit: ohm, , is the resistivity, is the line segment length, is the line width, is the metal thickness). The calculation results are smoothed by spatial Gaussian filtering, with a filter kernel size of 3x3 and σ=1.0, to eliminate calculation noise. Finally, generate dynamic power source distribution data, including the coordinates of each grid point, power value (unit: watt / square centimeter) and timestamp.

[0047] A leakage power consumption model is constructed, which is based on the BSIM4 transistor model and considers three main components: subthreshold leakage current, gate leakage current, and junction leakage current. For each grid point in the active area voltage data, the leakage current density per unit area is calculated according to the transistor type (NMOS / PMOS), process parameters, and local voltage V. The formula for calculating the subthreshold leakage current is wherein is a process-related parameter, is the gate-source voltage, is the threshold voltage, is the subthreshold swing factor, is the thermal voltage (kT / q), , is the Boltzmann constant, is the temperature, is the electronic charge), is the drain-source voltage. The formula for calculating the gate leakage current is wherein , , is a process fitting parameter, is the gate oxide thickness. The temperature dependence is considered in the leakage power consumption calculation, and the formula is wherein is the temperature coefficient (usually 2-3). The final static power consumption source distribution data is generated, including the coordinates of each grid point, the static power consumption value (unit: W / cm2), and the temperature value.

[0048] A unified spatial grid system is constructed, with a grid resolution of 5 microns x 5 microns, covering the entire chip area (7 mm x 7 mm), forming a high-resolution grid of 1400 x 1400. For each grid point , the power consumption values at the corresponding positions are extracted from the dynamic power consumption source distribution data and the static power consumption source distribution data and , and the total power consumption is calculated The data extraction process adopts a hash table to realize the position index with O(1) time complexity.For the case that multiple time point data exist for the same position, the superimposed data from the same moment is ensured through timestamp matching.The superimposed result is processed through a bicubic spline interpolation algorithm, the empty area in the grid is filled, and the interpolation kernel size is 4x4.In order to enhance the visualization effect of the hot spot area, pseudo-color mapping is applied to the total power consumption data, and a nonlinear mapping relationship between the power consumption value and the color space is established: the low power consumption area (<0.1W / mm²) is mapped to blue, the medium power consumption area (0.1-1.0W / mm²) is mapped to green to yellow, and the high power consumption area (>1.0W / mm²) is mapped to red.Finally, the spatial heat map of the instantaneous power consumption component is generated, which contains complete power consumption distribution data and corresponding visual representation, and the heat map resolution is 1400x1400 pixels and the color depth is 24 bits.

[0049] Preferably, the dynamic grid power consumption source analysis according to the active area voltage data and the passive area current data in step S33 comprises: calculating a local voltage scaling factor of each grid point relative to a preset nominal power supply voltage based on the active area voltage data; calculating the switch power consumption based on the local voltage scaling factor and a preset switch power consumption value, and generating active area switch power consumption distribution data; calculating the Joule heat based on the passive area current data and a preset interconnection line resistance value, and generating passive area Joule heat power consumption distribution data; spatial grid aligning processing of the active area switch power consumption distribution data and the passive area Joule heat power consumption distribution data to generate power consumption component alignment data; performing grid point by grid point numerical summation processing on the power consumption component alignment data to generate dynamic power consumption source distribution data.

[0050] In the embodiment of the application, the nominal power supply voltage value is set to 1.2V for a 65nm process node, 0.9V for a 28nm process node, and 0.7V for a 7nm process node, and the nominal value is read from the design specification file.For each grid point in the active area voltage data, the actual measured voltage value is extracted, the local voltage scaling factor is calculated, and the calculation formula is , wherein is the nominal power supply voltage.During the calculation process, the AVX-512 instruction set is optimized, 16 grid point data are processed at a time, and the calculation precision is 32-bit floating point number.Considering the voltage measurement error, a Gaussian noise filter with a standard deviation of 0.5% is implemented, and a 5x5 convolution kernel is used.For grid points with obviously abnormal voltage values or ), which is modified by median filter with a 3x3 grid window. The data structure is represented by sparse matrix, only storing the lambda value of active grid.

[0051] The preset switching power consumption value is obtained by a power consumption analysis tool Synopsys PrimeTime PX in design, which calculates the average switching power consumption of each standard cell at the nominal voltage based on the RTL design and standard cell characteristic library, and generates a power consumption map file (PWR format) with the standard cell as the granularity. The reference switching power consumption value of each cell is extracted from the PWR file , and the position and size information of the standard cell is extracted from the layout data. The spatial mapping process distributes the power consumption of each standard cell to the grid covering its physical area, using an area-weighted distribution algorithm, and the distribution formula is = ( ), wherein is the power consumption value distributed to the grid, is the total power consumption of the standard cell, is the area of the grid overlapping with the cell, is the total area of the cell. The local power scale calculation uses the formula , wherein is the actual switching power consumption, is the preset nominal switching power consumption, is the local voltage scale factor. Considering the timing information, an activity factor α is introduced, which is extracted from the waveform database, and α represents the flip probability of the cell in the clock cycle. Finally, the active area switching power consumption distribution data is generated.

[0052] The preset interconnection line resistance value is extracted from the process parameter library. For different metal layer resistivity, M1 layer is 50 mΩ, M2-M3 layer is 35 mΩ, M4-M5 layer is 25 mΩ, and M6 layer is 15 mΩ. For each passive grid, first identify its belonging metal layer ML and line width W. For typical 28 nm process, the minimum line width is 80 nm, the standard line width is 120 nm, and the power line width is 500 nm-2 μm. The metal line segment resistance calculation formula is , wherein is the resistivity (Ω·m), is the line segment length (m), is the line width (m), is the metal thickness (m). The joule heat calculation formula is , wherein is the joule heat power consumption (W), is the current value (A), is the resistance value (Ω). The temperature effect is considered in the calculation, and the resistance temperature coefficient is 0.0039 / ℃. The real-time temperature is obtained by measuring with an infrared thermal imager. For the case of multiple interconnected lines in the same grid point, the superposition method is used to calculate the total power consumption, and the joule heat power density is wherein is the grid area . The calculation result is stored as a floating-point array, and the joule heat power consumption distribution data of the passive region is generated.

[0053] A unified spatial grid coordinate system is constructed, and the grid resolution is 5 μm x 5 μm, covering the entire chip area (typical size is 7 mm x 7 mm), forming a 1400 x 1400 grid matrix. The spatial index structure based on quadtree is used to map the active region switching power consumption distribution data and the passive region joule heat power consumption distribution data to the unified grid. The mapping process considers the positional relationship between the data points and the grid nodes. When the data point falls exactly on the grid node, the value is directly assigned; when the data point falls inside the grid cell, the value of the grid node is calculated by bilinear interpolation. The interpolation formula is wherein , , , are the four grid nodes surrounding the data point. Considering the time synchronization, only the data of the same timestamp (time difference < 100 ns) is aligned. The processing result forms the power consumption component alignment data, which includes the switching power consumption and the joule heat power consumption of each grid point.

[0054] Based on the power consumption component alignment data, the numerical summation operation is performed on each grid point, and the calculation formula is wherein is the total dynamic power consumption, is the switching power consumption component, is the joule heat power consumption component, is the grid coordinate. The calculation process is optimized by using 512-bit VSX instruction set, which processes 16 grid point data at a time, realizing high throughput calculation. For the overlapping region containing switching power consumption and joule heat power consumption, such as the region overlapping the standard cell and the metal interconnection above it, the cumulative method is used to calculate the total power consumption. In order to reduce the influence of noise, 5x5 Gaussian smoothing filter is applied to the calculation result, and the filter kernel parameters are kept constant. The filtered data keeps the total power consumption constant. The data format uses floating-point numbers, and the power consumption unit is W / mm². The data resolution is 1 μW / mm². The finally generated dynamic power source distribution data contains the power consumption values and timestamp information of 1400 x 1400 grid points, forming a complete dynamic power spatial distribution map.

[0055] Preferably, the temperature field thermal evolution processing according to the instantaneous power consumption component spatial thermal map in step S4 comprises: acquiring material layer structure information of the integrated circuit; assigning heat capacity, heat conductivity and interface thermal resistance parameters to each grid point of the transient power consumption component space heat map through the material layer structure information of the integrated circuit to obtain global thermal property parameter data; taking the transient power consumption component space heat map as heat injection, calculating a temperature increment of a first time step based on the global thermal property parameter data to obtain initial temperature rise distribution data, with 1 picosecond as a time step; performing heat conduction calculation based on a temperature difference in the initial temperature rise distribution data and the thermal resistance in the global thermal property parameter data, and updating a temperature field to generate a single-step evolution temperature field; repeating the heat injection and conduction calculation with the single-step evolution temperature field as new input, and feeding back a result to correct leakage power consumption, and repeating the current round of thermal evolution calculation twice to obtain a self-consistent converged temperature field; performing final state confirmation on the self-consistent converged temperature field, and locking the data as dynamic coupling temperature stable field data when temperature change of any grid point is less than 0.1 degrees Celsius.

[0056] In the embodiment of the application, complete material stack structure is extracted from a chip manufacturing process file. For a 28nm process node, a typical structure includes 6 metal interconnection layers, 1 polysilicon layer and 1 silicon substrate layer. A Synopsys Star-RCXT tool is used to analyze a GDSII layout file to extract geometric dimensions and distribution of each layer, including thickness, width and spatial position information. Metal layer thickness data is obtained from a process specification file: M1 layer is 0.05um, M2-M3 layer is 0.07um, M4-M5 layer is 0.11um, and M6 layer is 0.9um. Silicon dioxide dielectric layer thickness is 0.12um between M1-M2, 0.15um between M2-M3, 0.15um between M3-M4, 0.18um between M4-M5, 0.2um between M5-M6, and 1.5um between M6-packing layer. Silicon substrate thickness is 300um. A three-dimensional voxel model is constructed through a material stack analysis tool, with voxel size set to 5um*5um*0.01um to ensure capturing fine structures in the vertical direction. Model data is stored as a structured grid, including material type identifier, coordinate information and hierarchical relationship, forming a material layer structure database.

[0057] Based on the material layer structure information, a thermal property parameter lookup table is constructed, which includes thermal conductivity, specific heat capacity and density data of each material. The thermal conductivity of silicon material is 149W / (m·K), the specific heat capacity is 712J / (kg·K), and the density is 2330 ; the thermal conductivity of silicon dioxide is 1.4W / (m·K), the specific heat capacity is 730J / (kg·K), and the density is 2200 ; the thermal conductivity of copper interconnect is 401 W / (m K), the specific heat capacity is 385 J / (kg K), and the density is 8960 ; the thermal conductivity of aluminum is 237 W / (m K), the specific heat capacity is 897 J / (kg K), and the density is 2700 For each 5 pm x 5 pm grid point, its material type is determined by spatial mapping, and the corresponding thermal property parameters are extracted from the lookup table. For mixed grid points containing multiple materials, the volume-weighted average method is used to calculate the equivalent thermal properties: wherein is the equivalent thermal conductivity, is the thermal conductivity of the th material, is the volume of the th material in the grid point. The equivalent specific heat capacity is calculated in the same way. The interface thermal resistance parameter is obtained by experimental measurement, and the typical values are for the silicon / silicon dioxide interface and for the copper / silicon dioxide interface. Finally, the global thermal property parameter data is generated.

[0058] The spatial heat map of the instantaneous power consumption component is taken as the heat injection source, with a data resolution of 5 pm x 5 pm covering a 7 mm x 7 mm chip area. The time step Δt is 1 picosecond, and the temperature increment is calculated based on the principle of energy conservation. The temperature increment calculation formula is wherein is the temperature increment (K), is the power density , is the time step (s), is the material density , is the specific heat capacity , is the volume , is the three-dimensional grid coordinate. The power density conversion formula is wherein is the area power density , is the active layer thickness (m). The calculation process uses the HIP (Heterogeneous Interface for Portability) programming model, which divides the chip area into 256 computing blocks for parallel processing. Considering the initial temperature distribution, the environmental temperature is set to 35°C as the reference temperature , and the calculation result is , forming the initial temperature rise distribution data.

[0059] Heat conduction is based on the Fourier heat conduction law, and the finite difference method is used for solving. The heat conduction equation is discretized using the central difference scheme in three-dimensional space: where is the thermal diffusivity, is the thermal conductivity, p is the density, and c is the specific heat capacity. The discretized equation is where represents the temperature at the time step, is the spatial step size. For different material interfaces, the influence of the interface thermal resistance is considered, and the heat flow formula is corrected as where is the heat flux density (W / m²), and are the temperatures on both sides of the interface (K), is the interface thermal resistance . The boundary conditions are set as follows: the top of the chip is in contact with the heat sink, and the convection boundary condition is used, with the convection heat transfer coefficient h set to 500 ; the bottom of the chip is in contact with the PCB board, and is set to a constant temperature of 35°C; the boundaries around the chip are set to adiabatic conditions. In the calculation, the ADI (Alternating Direction Implicit) algorithm is used to improve numerical stability, with a time step of 1 ps. After single-step calculation, the single-step evolution temperature field is obtained.

[0060] The single-step evolution temperature field is used as the new input, and the heat injection and conduction calculation is repeated. The updated temperature field is used to correct the leakage power consumption, and the correction formula is where is the leakage power consumption at the temperature , is the leakage power consumption at the reference temperature , and the exponential term 2 represents the characteristic of doubling the leakage power consumption for every 10K temperature increase. The total power consumption update formula is where is the total power consumption, is the dynamic power consumption, is the temperature-dependent leakage power consumption. The corrected power distribution is used as the heat source input again, and the temperature field is calculated repeatedly. The entire process is repeated for two complete cycles to ensure self-consistent convergence of the power-temperature interdependence. The calculation architecture uses a pipeline parallel design, dividing the heat conduction calculation into multiple stages and executing them in parallel on the FPGA. For each cycle, the temperature field change is recorded, and when is less than the preset threshold of 0.5K, it is considered to have converged for this round of cycle. After two complete cycles, the self-consistent convergence temperature field is generated, containing complete three-dimensional temperature distribution data.

[0061] The stability of the self-consistent convergence temperature field is analyzed, and the temperature change wherein represents the temperature field at the time step is the grid coordinate. When the value of all grid points is less than 0.1℃, it is determined that the system reaches a thermal equilibrium state. In a specific implementation, a reduction algorithm is used to calculate the maximum temperature change on FPGA in parallel, and the time complexity of the algorithm is , where is the total number of grids. For a complete chip containing 1.4 million grids, the calculation time does not exceed 200 microseconds. At the same time, the rationality of the temperature field distribution is checked, and the measured data of the thermal imager is checked, and it is required that the deviation between the simulated temperature and the measured temperature at the key point position is not more than 3℃. When the temperature stability criterion and the rationality check meet the requirements, the current temperature field data is locked and marked as the final state, and the dynamic coupling temperature stable field data is generated. The data format includes three-dimensional coordinates, temperature values, time stamps, and convergence history information, realizing complete thermal field analysis and tracing.

[0062] Especially important is that after the self-consistent converged temperature field is confirmed as the final state, a thermal-electric coupling effect analysis is also included, specifically: Based on the vertical layering information of the integrated circuit GDSII layout data, a three-dimensional spatial mapping of the spatial thermal map of the instantaneous power consumption component is performed, and a three-dimensional power source grid data including the physical positions of the silicon substrate, logic gates and metal interconnection layers is constructed; Based on the hierarchical attribute of the three-dimensional power source grid data, an interface thermal resistance value is set between adjacent grid points of different material contacts, and interface thermal resistance distribution data is generated; Performing a preliminary thermal transient analysis on the three-dimensional power source grid data, and calculating the heat diffusion in three-dimensional space according to the interface thermal resistance distribution data to obtain a preliminary iteration temperature field; Extracting the grid temperature of the active transistor region from the preliminary iteration temperature field to generate an updated transistor junction temperature set; Based on the nonlinear relationship between the transistor junction temperature in the updated transistor junction temperature set and the leakage current, the leakage power consumption is recalculated to obtain corrected leakage power consumption distribution data; The corrected leakage power consumption distribution data is fed back and updated to the three-dimensional power source grid data to generate feedback corrected power source data; Repeat the thermal transient analysis on the feedback corrected power source data until convergence, thereby generating dynamic coupling temperature stable field data.

[0063] In the embodiment of the present application, the complete layered structure is extracted from the GDSII data, including silicon substrate (thickness 300 μm), active device layer (thickness 0.2 μm) and 6 layers of metal interconnection (M1 thickness 0.05 μm, M2-M3 thickness 0.07 μm, M4-M5 thickness 0.11 μm, M6 thickness 0.9 μm). A three-dimensional grid is constructed, with a horizontal direction (X-Y plane) resolution of 5 μm and a vertical direction (Z axis) resolution set according to the layer thickness, 10 μm for the substrate layer, 0.1 μm for the active layer and 0.05 μm for the metal interconnection layer, forming a non-uniform grid. The two-dimensional transient power consumption component space heat map data is mapped to the corresponding vertical level by a geometric mapping algorithm, with the mapping rule being: switching power consumption is mapped to the active device layer; and Joule heat power consumption is mapped to the corresponding interconnection layer according to the metal layer number. The data mapping process adopts a bicubic interpolation algorithm to ensure energy conservation, with the total mapped power consumption deviating from the original two-dimensional power consumption heat map value being controlled within 0.1%. Finally, three-dimensional power consumption source grid data containing about 2.5 million grids are generated, with each grid containing spatial coordinates, level identification, material properties and power consumption density value. About 250 million grids of three-dimensional power consumption source grid data are generated, with each grid containing spatial coordinates, level identification, material properties and power consumption density value. All material contact interfaces in the three-dimensional power consumption source grid data are identified, mainly including: silicon / silicon dioxide interface, metal / silicon dioxide interface, metal / metal contact interface (via hole area). Different thermal resistance values are set for each type of interface: the silicon / silicon dioxide interface thermal resistance is , the copper / silicon dioxide interface thermal resistance is , the copper / tungsten (via hole) interface thermal resistance is , and the aluminum / silicon dioxide interface thermal resistance is . The interface identification algorithm adopts the adjacent grid material property comparison method, and when the materials of the adjacent two grids are different, an interface thermal resistance is set on the shared surface. The thermal resistance value calculation considers the interface roughness factor, and a modified formula is adopted, where is the actual interface thermal resistance, is the ideal smooth interface thermal resistance, and is the root mean square value of the interface roughness (nm), and the typical value is obtained from process control parameters. For special areas such as flip-chip bump connections, a lower thermal resistance value is set. The generated interface thermal resistance distribution data contains about 500,000 interface units, each unit recording the interface position, contact material type, area and thermal resistance value. Based on the existing three-dimensional unsteady heat conduction equation, the equation is discretized by the finite volume method, and the full implicit format is adopted for the time term to ensure numerical stability. For the grid point pair containing the interface thermal resistance, the heat flow calculation is modified as , where is the heat flux density between grid points and , and are the grid point temperatures, and for grid spacing, and for grid thermal conductivity, for interface thermal resistance. Initial condition is set as 35 °C for the whole computational domain. Boundary conditions are set as 50 °C for the top heat sink interface, convective heat transfer condition for the bottom PCB contact surface with heat transfer coefficient , ambient temperature 35 °C; side boundaries are set as adiabatic condition. Time step is set as 0.1 μs, total simulation time is set as 10 ms to ensure capturing the fast thermal transient process. Conjugate gradient solver is used for the computation with convergence criterion of residual less than , complete temperature field is stored every 100 time steps during the solution process. All grid indices marked as “active transistor region” are extracted from the 3D power source grid data, a typical 28 nm process design contains about 100,000 transistor cells. Spatial index algorithm (R-tree) is used to locate the exact position of each transistor cell in the temperature field grid quickly, the query time complexity is O(log n). For each transistor cell, all grid point temperature values it occupies are extracted, and the weighted average junction temperature is calculated, the weighting factor is proportional to the grid point power consumption. The calculation formula is , where is the transistor junction temperature, is the grid point temperature, is the grid point power density. For power transistors with larger area, the internal maximum temperature point and temperature gradient information are recorded additionally. Junction temperature data is organized as a structured array, each record contains transistor identifier, position coordinates, average junction temperature, maximum junction temperature, temperature gradient and time stamp. Data precision is set as 0.01 °C to ensure capturing the tiny temperature change. For transistors with abnormal temperature (junction temperature exceeding 85 °C), they are marked as hot spot regions and their sampling density is increased. Leakage power temperature dependence modeling uses an improved exponential relationship: , where is the leakage power at temperature T, is the leakage power at reference temperature (set as 35 °C), is the temperature coefficient. Temperature coefficient varies according to process node: 1.91 for 65 nm process, 2.19 for 45 nm process, 2.47 for 28 nm process, 2.73 for 14 nm process. Leakage power at reference temperature is extracted from standard cell library, the numerical range is in nano-watt level. AVX-512 instruction set is used to accelerate the calculation process, 16 transistor data are processed at a time. For high temperature regions (T > 75 °C), a second order correction term is introduced: , where is the second order coefficient, a typical value is 0.0002 / °C2, used to capture the super-linear increase of leakage current at high temperature more accurately. The calculation results are limited by threshold to ensure physical reasonableness, the upper limit of leakage power consumption is set to 10 times the nominal value, and the corrected leakage power consumption distribution data is finally generated. A bidirectional mapping relationship between the transistor unit and the three-dimensional grid point is established, and a space hash table is used for storage, with a query efficiency of O(1). For each transistor unit, the corrected leakage power consumption value is proportionally distributed to all grid points covered by the transistor according to the area. The distribution formula is , wherein is the leakage power consumption distributed to the grid point, is the total leakage power consumption of the transistor unit, is the area of the grid point overlapping with the unit, is the total area of the unit. In the calculation, the non-uniformity of the internal power consumption distribution of the transistor is considered, and the proportion of the channel region is higher than that of the source and drain region, and the proportion is 3:1. The updated total power consumption is calculated as , wherein is the original dynamic power consumption (including switching power consumption and joule heat power consumption), is the newly calculated leakage power consumption. The update process is executed in parallel by an FPGA hardware accelerator, with a processing speed of 10 billion grid points per second. After the update is completed, a power conservation check is performed to ensure that the total power consumption change of the whole chip conforms to the physical law, and the leakage power consumption increase ratio is usually in the range of 5%-25%. The final feedback corrected power source data is generated, and the data structure is the same as the original three-dimensional power source grid point data, but the power consumption value already includes the leakage component corrected by temperature. The iteration process is designed as an automated pipeline, and each iteration round includes four stages: thermal transient analysis, temperature field extraction, leakage power consumption update, and convergence determination. The thermal transient analysis uses the same method as the initial analysis, but the time step is adaptively adjusted according to the temperature change rate, ranging from 0.05μs to 0.5μs. The temperature field change is calculated after each iteration round, defined as , wherein represents the temperature field of the th iteration round, is the grid coordinate. The power consumption change is also calculated. The convergence criterion is set as and . To accelerate convergence, a relaxation factor is introduced, and the update formula is , wherein takes a value of 0.7 to avoid oscillation. During the iteration process, the positions of the maximum change points of the temperature field and the power distribution of each round are recorded to form a thermal-electric coupling sensitivity map. When the convergence condition is met or the maximum number of iterations (set to 10 times) is reached, the iteration is stopped, and the final dynamic coupling temperature stable field data is output.

[0064] Preferably, the step S4 includes evaluating the electromigration original risk index by the local power consumption voltage calibration grid point and the transient power consumption component space thermal map, and mapping the interconnection line risk state according to the integrated circuit GDSII layout data, which includes: For each metal interconnection line in the integrated circuit GDSII layout data, the transient current density peak of the metal interconnection line is extracted from the local power consumption voltage calibration grid point, and the stable working temperature of the metal interconnection line is extracted from the dynamic coupling temperature stable field data, so as to generate an interconnection line risk factor pair. The electromigration original risk index is calculated for the interconnection line risk factor pair. The electromigration original risk index is graded by a preset risk threshold to obtain a risk grade division result. According to the risk grade division result, the interconnection line risk state of each metal interconnection line in the integrated circuit is labeled; wherein the interconnection line risk state includes three states of safety, warning and high risk. According to the interconnection line risk state, a preset color is mapped to the integrated circuit GDSII layout data to generate an integrated circuit risk map.

[0065] In the embodiment of the application, all metal interconnection lines in the GDSII layout are extracted by Calibre DRC, including M1 to M6 layers of metal, a total of about 860,000 line segments. For each line segment, the layer number, width, length, starting and ending coordinates and network name are recorded. Then, all grid points overlapping with the line segment are queried in the local power consumption voltage calibration grid point data by using the KD tree space indexing algorithm, and the query radius is set to 5 microns. The maximum current density value in the covered area of each line segment is extracted as the current density peak , and the unit is A / cm². At the same time, the average temperature and the highest temperature of the line segment region are extracted from the dynamic coupling temperature stable field data by using the trilinear interpolation method, and the unit is Celsius. For the line segment with uneven current density distribution (standard deviation exceeding 30% of the average value), the line segment is subdivided into multiple sub-segments for evaluation. The data aggregation process uses the parallel computing framework Apache Spark, and the processing speed reaches 10,000 line segments per second to generate an interconnection line risk factor pair dataset.

[0066] According to the interconnection line risk factor pair data, the electromigration risk index of each interconnection line is calculated by using the modified model of the Black equation. The calculation formula is , wherein is the risk index (dimensionless), is the current density peak , is the critical current density , which is related to the metal material and geometric size. For the 28nm process copper interconnection, the M1 layer is , M2-M3 layer is , M4-M6 layer is ; is the current density exponent, typical value is 2; is the activation energy, 0.8 eV for copper interconnects; is the Boltzmann constant, ; is the reference temperature, set to 85℃ (358.15K); is the maximum operating temperature (K). The calculation process uses CUDA kernel functions for parallel processing, processing 4096 line segment data at a time. For special structures such as vias and contact areas, a correction coefficient is used to adjust the risk index, with a via correction coefficient of 1.5 and a contact area correction coefficient of 1.2. Considering the current fluctuation factor, a fluctuation coefficient is introduced, and the correction formula is , where is the standard deviation of current density, is the average current density, is the fluctuation sensitivity coefficient, with a value of 0.3.

[0067] The preset risk threshold is determined by analyzing a large amount of historical electromigration failure data. The K-means clustering algorithm is used to cluster the relationship between risk index and actual failure rate in historical data, and two key threshold points are identified: RI_1=3.5 and RI_2=7.8. Based on these two thresholds, the risk level is divided into three levels: RI<3.5 is safe (green), 3.5≤RI<7.8 is warning (yellow), and RI≥7.8 is high risk (red). The risk level division process uses the binary search algorithm, with a time complexity of O(log n). To ensure the robustness of risk assessment, confidence calculation is introduced, and the confidence formula is , where is the threshold, and σ is the uncertainty parameter, with a value of 0.8. When the confidence is lower than 85%, the risk level is marked as "pending" state, which needs further analysis. The division process uses the OpenMP parallel programming framework to accelerate, dividing 860,000 line segments into 36 batches for parallel processing. Finally, the risk level division results are generated, including the identifier of each interconnect line, the original risk index, the risk level and the confidence value.

[0068] A metal interconnect line network topology graph is constructed, with nodes representing line segment endpoints and edges representing line segments, and edge weights being risk level values. The graph construction uses an adjacency list storage structure, and for each interconnect line, a label state is set according to its risk level: line segments with a risk index RI < 3.5 are labeled as a "safe" state (state code 0); line segments with 3.5 ≤ RI < 7.8 are labeled as a "warning" state (state code 1); and line segments with RI ≥ 7.8 are labeled as a "high risk" state (state code 2). For network-level analysis, a propagation rule is introduced: when three consecutive adjacent line segments are all in the "warning" state, the middle line segment is promoted to the "high risk" state; and when a "high risk" line segment is connected to a critical power supply network, all line segments within a radius of 50 μm around the connection point are marked as "high risk". The labeling process uses a breadth-first search algorithm to traverse the entire network, with a time complexity of O(V+E), where V is the number of nodes and E is the number of edges.

[0069] The GDSII layout data is imported into the Virtuoso environment to construct a metal layer view. The default color mapping scheme is: safe state (state code 0) is mapped to green (RGB: 0, 255, 0), warning state (state code 1) is mapped to yellow (RGB: 255, 255, 0), and high risk state (state code 2) is mapped to red (RGB: 255, 0, 0). The interconnect line risk state database is read through the API interface to construct a color lookup table (LUT), with the key being the line segment ID and the value being the corresponding color code. The layout rendering uses a hierarchical processing strategy: first, the bottom metal (M1-M2) is drawn, then the middle metal (M3-M4) is drawn, and finally the top metal (M5-M6) is drawn. The rendering resolution is set to 10 pixels per micron, and a 7 mm x 7 mm chip generates a 70,000 x 70,000 pixel image. For risk hotspot areas, the details are automatically enlarged by 5 times. In the image processing stage, a Gaussian blur (kernel size 5x5, σ=1.0) is applied to smooth the color boundaries, and a nonlinear contrast enhancement algorithm (γ=1.2) is applied to highlight the risk areas, finally generating a multi-level risk map, including a full-chip overview, a functional block enlarged view, and a high-risk hotspot detail view.

[0070] Especially important is that the interconnect line risk factor pair is used to calculate the electromigration original risk index, including: The instantaneous current density in the interconnect line risk factor pair and the physical proximity relationship between functional modules in the integrated circuit GDSII layout data are analyzed to analyze the current spike interference caused by adjacent high-power modules, quantify an additional current component, and obtain an interference-corrected current density set; The joule self-heating effect of each interconnect line is calculated based on the interference-corrected current density set, and is superimposed on the background temperature in the interconnect line risk factor pair to generate a self-heating-corrected temperature set; The temperature values ​​of the temperature set after self-heating correction are judged. If the temperature exceeds 105 degrees Celsius, a thermo-mechanical stress factor proportional to the temperature difference is activated to obtain a thermo-stress factor set. The multi-physics domain degradation rate is obtained by multiplying the square value of the current density set after interference correction, the Arrhenius acceleration factor of the temperature set after self-heating correction, and the thermal stress factor set. The physical domain degradation rate is multiplied by a preset geometric correction coefficient based on the metal interconnect layer width and via redundancy to generate the original electromigration risk index.

[0071] In this embodiment of the invention, the boundaries of functional modules are extracted from GDSII layout data, and the distance matrix between modules is calculated. The distance threshold is set to 200 μm. When the distance between two modules is less than the threshold, the parasitic inductance between them is extracted. (Unit: Pihen), the calculation formula is as follows: ,in The permeability of free space, The distance between lines. and For line width, Let be the length of the parallel line. For each interconnect, calculate the induced current. ,in Mutual inductance coefficient ( , (Coupling coefficient 0.1-0.8) The current change rate of adjacent high-power modules is extracted from the measured waveform, with a typical value being... A / s. Current density interference is calculated as follows: ,in For line width, Line thickness. Final current density after interference correction. ,in This represents the peak value of the original current density. For each interconnect, a detailed 3D finite element model is constructed, with a mesh resolution set to 1 / 10 of the linewidth to ensure temperature gradient capture. The Joule heating calculation formula is as follows: ,in Joule heat power (watts). For the current density after interference correction ( ), Resistivity (Ω·m) Volume of a line segment ( The temperature dependence of resistivity is modeled linearly. ,in Reference temperature The resistivity below, 0.0039 / K for copper). The thermal conduction boundary conditions are set as: top, in contact with silicon dioxide medium, thermal resistance 0.5 K / W; bottom, connected to the lower metal layer through via, thermal resistance 0.5 K / W; and four sides, surrounded by silicon dioxide medium. The transient thermal analysis time step is 1 μs, and the total simulation time is 1 ms to capture the temperature fluctuation caused by the pulse current. The temperature rise calculation formula is where is the thermal resistance (K / W). The self-heating corrected temperature where is the background temperature. The temperature threshold is set, and the self-heating corrected temperature of each interconnect line is evaluated. When , the thermal stress factor (no additional risk); when , the thermal stress calculation module is activated. The thermal stress calculation is based on the linear thermal expansion theory, considering the difference in thermal expansion coefficients between the copper interconnect line and the surrounding silicon dioxide medium (copper , and silicon dioxide ). The thermal stress calculation formula is where is the thermal stress (Pa), is the Young's modulus of copper (128 GPa), and are the material thermal expansion coefficients, is the stress release temperature (350 °C, annealing temperature). The thermal stress factor is calculated as where is the stress sensitivity coefficient, which is 1.5-3.0 according to the different metal layers, with the M1 layer being the highest and the M6 layer being the lowest. The stress concentration positions are identified through finite element analysis, and the typical hot spots are sharp corners, line width abrupt changes, and via connection points. The final thermal stress factor set is generated. The interference corrected current density J_corr is standardized to obtain the ratio relative to the critical current density where is the critical current density, which is for the M1 layer, for the M2-M3 layers, and for the M4-M6 layers for the 28 nm process. The current density quadratic term is calculated as , which represents the quadratic effect of current density on electromigration. The temperature Arrhenius acceleration factor calculation formula is where is the activation energy (0.8 eV for copper), is the Boltzmann constant , is the reference temperature (85 °C or 358.15 K). K is the self-heating corrected temperature (K). The multi-physics degradation rate calculation formula is wherein is the thermal stress factor. The calculation process adopts a batch processing mode, processing 4096 line segment data at a time, fully utilizing the GPU parallel computing capability. For the alternating current scenario, an equivalent direct current model is introduced, and the equivalent coefficient depends on the root mean square value and peak value ratio of the current waveform, and finally a multi-physics degradation rate dataset is generated. Two key parameters are considered: metal interconnection line width and via redundancy. The line width correction formula is wherein is the actual line width (μm), is the process minimum line width (0.08 μm for a 28 nm process), is the line width index (value 1.2). The via redundancy correction formula is wherein is the number of redundant vias, is the via coefficient (value 0.4). The total geometric correction coefficient is . For special structures such as angle turns, T-shaped connections and via arrays, a shape coefficient is additionally applied, with a value range of 1.1-1.8. The electromigration original risk index calculation formula is wherein is the historical data correction term, which is learned from historical failure data through a Bayesian network. The calculation result is normalized to a standard scale of 0-100, facilitating risk level division: 0-25 is low risk, 25-50 is medium risk, 50-75 is high risk, and 75-100 is extremely high risk. The contribution proportion of each component is recorded during the risk index calculation process, forming a risk cause analysis data. The electromigration original risk index dataset is finally generated, containing the risk index value, risk level and main contributing factors of each interconnection line.

[0072] Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting, the scope of the present application being defined by the appended claims rather than the above description, and it is intended to encompass all variations falling within the meaning and range of equivalents of the essential features of the application.

[0073] The above description is merely one specific implementation of the present application, enabling a person skilled in the art to understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to these embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for testing the power consumption of an integrated circuit, characterized in that, Includes the following steps: Step S1: Deploy Hall sensors on the integrated circuit and set a dynamic sampling control strategy; perform pulse testing on the integrated circuit based on the dynamic sampling control strategy, and perform gradient analysis of the connected domains of the circuit measurement channels to generate interconnect layer gradient label data; Step S2: Obtain integrated circuit GDSII layout data; calculate IR Drop distribution based on integrated circuit GDSII layout data and interconnect layer gradient marker data, and perform grid merging processing to generate local power consumption voltage calibration grid points; Step S3: Based on the integrated circuit GDSII layout data, the active transistor region is identified by the local power consumption voltage calibration grid. Then, dynamic grid power source analysis and reference leakage power calculation are performed to obtain the instantaneous power consumption component spatial heat map. Step S4: Perform temperature field thermal evolution processing based on the instantaneous power consumption component spatial heat map to generate dynamic coupled temperature stable field data; evaluate the original electromigration risk index through local power consumption voltage calibration grid points and instantaneous power consumption component spatial heat map, and perform interconnect risk state mapping based on integrated circuit GDSII layout data to obtain integrated circuit risk map.

2. The integrated circuit power consumption testing method according to claim 1, characterized in that, Step S1 involves deploying a Hall sensor on the integrated circuit and setting a dynamic sampling control strategy, including: Sensor array positioning marks are made on the surface metal pad area of ​​the integrated circuit, and a 64×64 grid reference point is established with a grid spacing of 25 micrometers, which is aligned with the wiring spacing of the internal metal interconnect layer in the integrated circuit to obtain sensor positioning reference data. Based on the sensor positioning reference data, a precise mounting operation is performed on the Hall sensor. The Hall sensor is placed one by one at the reference point position, and the sensor sensing surface and the metal layer on the surface of the integrated circuit are kept at a 3-micrometer interval to obtain the sensor array layout data. Electrical connection configuration is performed on each Hall sensor using sensor array layout data, and the signal pins of each sensor are connected to a dedicated multiplexed acquisition circuit in an integrated circuit. Synchronous control is achieved between the multiplexed acquisition circuit and the integrated circuit's power supply. A standard sampling frequency of 10kHz is set. When any Hall sensor detects a current density value exceeding 2×10⁻⁶... 6 A / cm 2 When the sampling frequency of the sensor and its surrounding 3×3 neighborhood of 9 sensors is automatically switched to 1MHz, a dynamic sampling control strategy is obtained.

3. The integrated circuit power consumption testing method according to claim 1, characterized in that, Step S1 involves performing pulse testing on the integrated circuit based on a dynamic sampling control strategy and conducting connected component gradient analysis of the circuit measurement channels, including: Based on the dynamic sampling control strategy, the integrated circuit is configured for multi-channel synchronous acquisition, and pulse test sequence processing is performed to obtain the raw timing readings of multiple channels. A spatiotemporal data matrix is ​​constructed based on the original time-series readings from multiple channels. The current density values ​​collected within 10 consecutive seconds are arranged in three dimensions according to the coordinates of the measurement channels and the timestamps to obtain the spatiotemporal distribution matrix of the current density. Spatial neighborhood difference calculation is performed on the spatiotemporal distribution matrix of current density, and the rate of change of current density at adjacent measurement points is calculated with a step size of 25 micrometers to obtain neighborhood current change rate data. The magnitude of the current density gradient at each measurement point is evaluated based on neighborhood current change rate data. The current density gradient magnitude is binarized and classified by setting a gradient threshold. Regions greater than the threshold are marked as 1, and regions less than or equal to the threshold are marked as 0, thus obtaining gradient classification label data; where 1 represents a high gradient label point and 0 represents a low gradient label point. Extract circuit measurement channel coordinate data based on multi-channel raw timing readings; By associating gradient classification label data with circuit measurement point coordinate data using location indexing, a correspondence between gradient categories and spatial locations is established, resulting in spatial gradient index data. Connectivity analysis is performed based on spatial gradient index data to identify adjacent high-gradient marker points and perform regional clustering to obtain interconnection layer gradient marker data.

4. The integrated circuit power consumption testing method according to claim 1, characterized in that, Step S2 involves calculating the IR Drop distribution based on the integrated circuit GDSII layout data and interconnect layer gradient marker data, followed by gridding and merging processing: The interconnect layer gradient marker data is spatially aligned with the integrated circuit GDSII layout data to obtain the layout alignment current data. Extract the metal interconnect geometric dimensions corresponding to the current vector paths of each test channel in the layout alignment current data from the integrated circuit GDSII layout data, and generate interconnect geometric parameters; The instantaneous current density data is obtained by calculating the point-by-point current density of the layout alignment current data based on the interconnect geometry parameters. The IR Drop distribution data is obtained by performing path accumulation calculation based on instantaneous current density data; The instantaneous current density data and IR Drop distribution data are gridded and merged to generate local power consumption voltage calibration grids.

5. The integrated circuit power consumption testing method according to claim 4, characterized in that, Path accumulation calculation based on instantaneous current density data includes: Extract the power network topology from the integrated circuit GDSII layout data and construct the power network topology node data; Based on the power network topology node data, the current path from the power pad to the active region in the integrated circuit is identified, and a current conduction path sequence is generated. Each path is divided into discrete resistance units based on the current conduction path sequence to obtain discretized resistance path data. Based on the instantaneous current density data, the current value of each resistor unit in the discretized resistor path data is matched with its corresponding current value to obtain the path segment current value data; Based on the path segment current value data and the discretized resistance path data, the voltage drop is calculated segment by segment and accumulated along the path to generate IR Drop distribution data.

6. The integrated circuit power consumption testing method according to claim 1, characterized in that, Step S3 includes the following steps: Step S31: Based on the integrated circuit GDSII layout data, identify the physical attributes of each grid point in the local power consumption voltage calibration grid point, and generate regional attribute annotation grid point data; Step S32: When the grid attribute in the region attribute annotation grid data is an active transistor region, extract the local voltage value to obtain the active region voltage data; otherwise, extract the current value to obtain the passive region current data. Step S33: Perform dynamic grid power source analysis based on the active region voltage data and the passive region current data to generate dynamic power source distribution data; Step S34: Calculate the reference leakage power consumption based on the active region voltage data and the initial reference temperature of 35 degrees Celsius to obtain the static power source distribution data; Step S35: Perform spatial overlay processing on the dynamic power source distribution data and the static power source distribution data to generate a spatial heat map of instantaneous power consumption components.

7. The integrated circuit power consumption testing method according to claim 6, characterized in that, Step S33, which involves dynamic grid power source analysis based on active region voltage data and passive region current data, includes: The local voltage scaling factor of each grid point relative to the preset nominal power supply voltage is calculated based on the active region voltage data. The switching power consumption is calculated based on the local voltage scaling factor and the preset switching power consumption value, and active region switching power consumption distribution data is generated. Joule heating is calculated based on passive region current data and preset interconnect resistance values, generating passive region Joule heating power consumption distribution data. The power consumption distribution data of the active region switch and the Joule thermal power consumption distribution data of the passive region are spatially gridded to generate power component alignment data. The power consumption component is summed bitwise to generate dynamic power source distribution data.

8. The integrated circuit power consumption testing method according to claim 1, characterized in that, Step S4, which involves processing the temperature field thermal evolution based on the spatial thermal map of the instantaneous power consumption components, includes: Obtain material layering information for integrated circuits; By using the material layering structure information of integrated circuits, each grid point of the instantaneous power consumption component spatial heat map is assigned thermal capacity, thermal conductivity and interface thermal resistance parameters to obtain global thermal property parameter data. Using 1 picosecond as the time step, the instantaneous power consumption component spatial heat map is used as the heat injection. The temperature increment of the first time step is calculated based on the global thermal attribute parameter data to obtain the initial temperature rise distribution data. Heat conduction is calculated based on the temperature difference in the initial temperature rise distribution data and the thermal resistance in the global thermal attribute parameter data, and the temperature field is updated to generate a single-step evolving temperature field. The single-step evolution temperature field is used as a new input to repeatedly perform heat injection and conduction calculations, and the results are fed back to correct leakage power consumption. This round of thermal evolution calculation is repeated twice to obtain a self-consistent convergent temperature field. The self-consistent convergent temperature field is finally confirmed. When the temperature change at any grid point is less than 0.1 degrees Celsius, the data is locked as the dynamic coupled temperature stable field data.

9. The integrated circuit power consumption testing method according to claim 1, characterized in that, Step S4 involves evaluating the original electromigration risk index using local power consumption voltage calibration grid points and instantaneous power consumption component spatial heatmaps, and mapping interconnect risk states based on integrated circuit GDSII layout data, including: For each metal interconnect in the integrated circuit GDSII layout data, the peak value of its instantaneous current density is extracted from the local power consumption voltage calibration grid, and its stable operating temperature is extracted from the dynamic coupling temperature stability field data to generate interconnect risk factor pairs. The interconnect risk factor is used to calculate the original electromigration risk index; The original risk index of electromigration is classified into levels by setting a preset risk threshold, and the risk level classification results are obtained. Based on the risk level classification results, the interconnect risk status is marked for each segment of metal interconnect in the integrated circuit; the interconnect risk status includes three states: safe, warning, and high risk. Based on the interconnect risk status, a risk map of the integrated circuit is generated by mapping the risk status of the interconnects onto the integrated circuit GDSII layout data with preset colors.

10. An integrated circuit power consumption testing system, characterized in that, For performing the integrated circuit power consumption test method as described in claim 1, the integrated circuit power consumption test system includes: The circuit signal acquisition module is used to deploy Hall sensors on integrated circuits and set dynamic sampling control strategies; based on the dynamic sampling control strategies, it performs pulse tests on integrated circuits and performs gradient analysis of the connected domains of circuit measurement channels to generate interconnect layer gradient label data. The voltage drop mapping module is used to acquire integrated circuit GDSII layout data; based on the integrated circuit GDSII layout data and interconnect layer gradient marker data, it calculates the IR drop distribution and performs grid merging processing to generate local power consumption voltage calibration grid points. The intelligent power consumption analysis module is used to identify active transistor regions by local power consumption voltage calibration grid points based on integrated circuit GDSII layout data, and then perform dynamic grid point power consumption source analysis and reference leakage power consumption calculation to obtain a spatial heat map of instantaneous power consumption components. The thermal risk assessment module is used to perform temperature field thermal evolution processing based on the instantaneous power consumption component spatial thermal map, then evaluate the original electromigration risk index, and perform interconnect risk state mapping based on integrated circuit GDSII layout data to obtain the integrated circuit risk map.

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