Test optimization method and device for high-precision chip and storage medium

Abstract

The invention discloses a test optimization method and device for a high-precision chip and a storage medium, and relates to the technical field of chip testing, and the method comprises the following steps: collecting the test time and the test passing condition of each test item in a CP test, and obtaining the basic test data of each test item; performing project correlation analysis according to the basic test data of each project to obtain related project data of each project; performing project necessity analysis based on the basic test data of each project and the related project data to obtain test project stable data; optimizing the test items of the CP test according to the test time of each test item and the test item stable data; the method and the device are used for solving the problem that the chip test time and the chip test cost cannot be reduced while the chip test time is shortened and the chip test cost cannot be reduced by analyzing test items on the premise of ensuring the chip quality when the CP test is optimized by the existing chip test technology.

Description

TECHNICAL FIELD

[0001] The application relates to the chip testing technical field, in particular to a high-precision chip testing optimization method, device and storage medium. BACKGROUND

[0002] Chip testing technology is a technology system for detecting and verifying the functional integrity, performance index, reliability and manufacturing yield of a chip through a series of professional technical means, equipment and methods in the whole life cycle of the chip.

[0003] The existing chip testing relies on automatic testing equipment, the cost of a single piece of such equipment is high, the service life of each piece of equipment is limited, and the automatic testing equipment is charged according to the service time, which leads to high chip testing cost, and the testing cost accounts for a very high proportion of the total chip cost, and the proportion is even higher and higher; therefore, under the premise of ensuring the quality of the chip, reducing the chip testing cost can effectively reduce the total cost of the chip; the existing chip testing technology often lacks optimization of the test items when optimizing the CP testing, only adjusts the test parameters dynamically according to the batch data of the chip, lacks systematic correlation analysis and necessity evaluation, and leads to a large amount of redundant testing; for example, the patent application with the publication number CN 118194730A discloses a chip wafer testing optimization method, which adjusts the parameters used during testing dynamically by collecting the data during the manufacturing of the current wafer batch, which can improve the testing efficiency to a certain extent, but cannot effectively reduce the chip testing cost; therefore, the existing chip testing technology cannot reduce the chip testing cost while reducing the chip testing time by analyzing the test items under the premise of ensuring the quality of the chip when optimizing the CP testing. SUMMARY

[0004] The application aims to at least solve one of the technical problems in the prior art, by collecting the test time and test passing condition of each test item in CP testing to obtain basic test data of each test item, performing project correlation analysis to obtain related project data of each item, performing project necessity analysis based on the basic test data and related project data of each item to obtain test item stability data, and optimizing the test items of the CP testing according to the test time of each test item and the test item stability data, so as to solve the problem that the existing chip testing technology cannot reduce the chip testing cost while reducing the chip testing time by analyzing the test items under the premise of ensuring the quality of the chip when optimizing the CP testing.

[0005] To achieve the above-mentioned purpose, in a first aspect, the application provides a high-precision chip testing optimization method, including the following steps:

[0006] Collecting test time and test passing condition of each test item in CP test, and obtaining basic test data of each test item;

[0007] Carrying out project correlation analysis according to the basic test data of each item, and obtaining correlation item data of each item;

[0008] Carrying out project necessity analysis based on the basic test data and the correlation item data of each item, and obtaining test item stability data;

[0009] Optimizing the test items of CP test according to the test time of each test item and the test item stability data.

[0010] Further, the collecting of the test time and the test passing condition of each test item in CP test, and the obtaining of the basic test data of each test item include the following sub-steps:

[0011] For all test stages in CP test of a chip, the test stages are sequentially recorded as CP1, CP2, …, CPn according to the test order, wherein n is the total number of the test stages; all test items of all test stages are sequentially recorded as test item 1, test item 2, …, test item m according to the test order, wherein m is the total number of the test items, and any one test item is recorded as a first test item;

[0012] The time of testing one chip by the first test item is obtained and recorded as a single test time.

[0013] Further, the collecting of the test time and the test passing condition of each test item in CP test, and the obtaining of the basic test data of each test item include the following sub-steps:

[0014] A first time period is set as T1, the test passing rate of the first test item in each first time period is repeatedly obtained, and is arranged in a time order from far to near and recorded as a test passing sequence;

[0015] Whether each chip tested by the first test item passes the test is obtained, and if yes, is marked as 1, and if not, is marked as 0, and is sequentially arranged according to the test order and recorded as a test result sequence;

[0016] The single test time, the test passing sequence and the test result sequence of the first test item are recorded as the basic test data of the first test item, and the basic test data of all test items is repeatedly obtained.

[0017] Further, the carrying out of the project correlation analysis according to the basic test data of each item, and the obtaining of the correlation item data of each item include the following sub-steps:

[0018] Any one test item other than the first test item is recorded as a second test item, and the test passing sequences of the first test item and the second test item are recorded as a first passing sequence and a second passing sequence in order respectively;

[0019] The average and the standard deviation of the first passing sequence are obtained and recorded as PA1 and PB1 in order respectively, and the average and the standard deviation of the second passing sequence are obtained and recorded as PA2 and PB2 in order respectively; and [PA1-k1*PB1, PA1+k1*PB1] and [PA2-k1*PB12, PA12+k1*PB1] are recorded as the general fluctuation ranges of the first passing sequence and the second passing sequence in order respectively, wherein k1 is a set proportion coefficient;

[0020] All passing rates exceeding the corresponding general fluctuation range in the first passing sequence and the second passing sequence are obtained and recorded as fluctuation points;

[0021] The position sequence numbers of each fluctuation point in the corresponding test passing sequence are obtained, and the position sequence numbers of the fluctuation points in the first passing sequence and the second passing sequence are recorded as co-occurrence positions, and the two fluctuation points of the co-occurrence positions are recorded as a co-occurrence fluctuation group;

[0022] The total number of the fluctuation points in the first passing sequence and the second passing sequence is obtained respectively and recorded as AH1 and AH2 in order respectively; and the total number of the co-occurrence positions is recorded as AH3; and the first synchronization index AD of the first test item and the second test item is calculated, wherein AD=2*AH3 / (AH1+AH2).

[0023] Further, the project correlation analysis is performed according to the basic test data of each item, and the related project data of each item further includes the following sub-steps:

[0024] For any one co-occurrence fluctuation group, recorded as a first fluctuation group, if the two fluctuation points of the first fluctuation group are both higher than the corresponding general fluctuation range or both lower than the corresponding general fluctuation range, it is marked as a same-direction fluctuation group, otherwise it is marked as an opposite-direction fluctuation group;

[0025] All the same-direction fluctuation groups are repeatedly obtained, and the total number of the same-direction fluctuation groups is recorded as BH1, and the second synchronization index BD of the first test item and the second test item is calculated, wherein BD=BH1 / AH3;

[0026] For any one of the same wave fluctuation group, denoted as the first same direction group, the wave fluctuation point belonging to the first through sequence of the first same direction group is recorded as CA1, and the wave fluctuation point belonging to the second through sequence is recorded as CA2; the fluctuation ratio of CA1 and CA2 is calculated respectively, and is recorded as CE1 and CE2 in order, wherein CE1 = |CA1-PA1| / PB1, CE2 = |CA2-PA2| / PB2; and the fluctuation ratio CR of the first same direction group is calculated, wherein CR = CE1 / CE2;

[0027] The fluctuation ratio of all same wave fluctuation groups is repeatedly obtained, and the standard deviation is calculated, denoted as CB; the third synchronization index CD of the first test item and the second test item is calculated, wherein CD = 1-[CB / (1+CB)];

[0028] The covariation fluctuation index GD of the first test item and the second test item is calculated, wherein GD = (AD+BD+CD) / 3; the covariation fluctuation index of the first test item and all other test items is repeatedly obtained, and is arranged in order from small to large, denoted as the covariation fluctuation sequence.

[0029] Further, the project correlation analysis is performed according to the basic test data of each item, and the related item data of each item further includes the following sub-steps:

[0030] The test result sequence of the first test item and the second test item is recorded as the first result sequence and the second result sequence in order respectively;

[0031] The data of the first result sequence and the second result sequence at the same sequence position are recorded as the first result and the second result in order respectively;

[0032] For the first result sequence and the second result sequence, the number of times that the first result and the second result are equal to 0 is counted, denoted as FA; the number of times that the first result is equal to 0 and the second result is equal to 1 is counted, denoted as FB; the number of times that the first result is equal to 1 and the second result is equal to 0 is counted, denoted as FC; and the number of times that the first result and the second result are equal to 1 is counted, denoted as FD;

[0033] The co-occurrence failure index GX of the first test item and the second test item is calculated, wherein GX = [FA / (FA+FB)]*[FA / (FA+FC)]*[FA / (FA+FB+FC)]; the co-occurrence failure index of the first test item and all other test items is repeatedly obtained, and is arranged in order from small to large, denoted as the co-occurrence failure sequence;

[0034] Obtaining the position sequence number of the second test item in the co-volatility sequence and the co-occurrence failure sequence, and summing up, recording as the correlation score of the first test item and the second test item, repeating the correlation score of the first test item and all other test items, and recording the test items corresponding to the maximum k2 correlation scores as the correlation test items of the first test item, and marking the correlation project data of the first test item, repeating the correlation project data of all test items, wherein k2 is the number set.

[0035] Further, based on the basic test data and the correlation project data of each project, the project necessity analysis is performed to obtain the test project stability data, including the following sub-steps:

[0036] All test items are divided into important test items and general test items, and any one general test item is recorded as a third test item;

[0037] According to the basic test data of the third test item, the test pass rate in each first time period within the recent first time length is obtained, recorded as the recent pass set, wherein the first time length is ET1;

[0038] The average value and the standard deviation of the recent pass set are calculated, recorded in order as the average pass UP and the pass standard deviation UB of the third test item, and the coefficient of variation of the third test item is calculated, recorded as CV, wherein CV=(UB / UP)*100%;

[0039] If the recent pass set of the third test item is not less than k3, and the average pass UP is not less than k4, and the coefficient of variation CV is not greater than k5, the third test item is marked as a general stable item, otherwise it is marked as a general fluctuation item, wherein k3, k4 and k5 are set threshold values;

[0040] Repeating the acquisition of all general stable items and the corresponding average pass and coefficient of variation, recording as the test project stability data.

[0041] Further, according to the test time of each test item and the test project stability data and the test item for CP test, the test item is optimized, including the following sub-steps:

[0042] For the first stable item, the first stable item and the corresponding correlation test item are recorded as a first test item group;

[0043] If the correlation test items of the first stable item are not all general stable items, the first stable item is changed to the sampling inspection mode;

[0044] If all the first test item groups are general stable items, a single test time of all the test items in the first test item group is obtained, if the single test time of the first stable item is not the shortest, the first stable item is changed to the sampling inspection mode, if the single test time of the first stable item is the shortest, the first stable item is not changed to the sampling inspection mode.

[0045] In a second aspect, the present application provides an electronic device, comprising a processor and a memory, wherein the memory stores computer readable instructions, when the computer readable instructions are executed by the processor, the steps in the above method are executed.

[0046] In a third aspect, the present application provides a storage medium, wherein the storage medium stores a computer program, when the computer program is executed by a processor, the steps in the above method are executed.

[0047] The present application has the following beneficial effects: the present application obtains basic test data of each test item by collecting test time and test passing condition of each test item in CP test; obtains relevant item data of each item by performing item correlation analysis according to the basic test data of each item; obtains stable data of test item by performing item necessity analysis based on the basic test data and the relevant item data of each item; optimizes the test item of CP test according to the test time and the stable data of test item; when optimizing the CP test, the chip test time is reduced and the chip test cost is reduced by analyzing the test item under the premise of ensuring the quality of the chip;

[0048] The present application quantifies the frequency of simultaneous abnormal points by the first synchronization indicator, quantifies the correlation of fluctuation in the same direction by the second synchronization indicator, quantifies the correlation of fluctuation amplitude by the third synchronization indicator, and combines the three indicators, which has the advantages that the synchronization of abnormal fluctuation can better reflect the internal correlation of test items, is more targeted than traditional trend correlation, and avoids distortion of a single indicator; by calculating the co-occurrence failure index of different test items, a probability type indicator is given for two test items being 0 at the same time, which can accurately identify whether there is a strong dependent relationship between the two test items, can reveal the correlation between test items better than only looking at the pass rate, and can quickly locate the related test items. BRIEF DESCRIPTION OF DRAWINGS

[0049] Figure 1 The flowchart of the steps of the method of the present application is shown in the figure;

[0050] Figure 2 The flowchart of the co-variation fluctuation sequence acquisition of the present application is shown in the figure;

[0051] Figure 3 The flowchart of the related test item acquisition of the present application is shown in the figure;

[0052] Figure 4 Structure diagram of electronic device of the present application. DETAILED DESCRIPTION

[0053] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0054] Embodiment 1, please refer to Figure 1 As shown in the figure, the present application provides a test optimization method for high-precision chips, comprising the following steps:

[0055] Step S1, collecting the test time and test passing situation of each test item in CP test to obtain basic test data of each test item; step S1 comprises the following sub-steps:

[0056] Step S101, for all test stages in CP test of the chip, sequentially record as CP1, CP2, …, CPn according to the test order, wherein n is the total number of test stages; record all test items of all test stages as test item 1, test item 2, …, test item m according to the test order, wherein m is the total number of test items, and record any one test item as the first test item;

[0057] Step S102, obtaining the time for testing one chip by the first test item, recorded as single test time; the service life of the automatic test equipment of the chip is limited, and the automatic test equipment is charged according to the usage time, so all test time directly determines the test cost.

[0058] Step S103, setting the first time period as T1, repeatedly obtaining the test passing rate of the first test item in each first time period, and arranging from far to near according to the time order, recorded as test passing sequence; in this embodiment, the first time period T1 = 24 hours, that is, repeatedly obtaining the test passing rate of the first test item every day, that is, the ratio of the number of chips passing the first test item to the number of chips performing the first test item;

[0059] Step S104, obtaining whether each chip tested by the first test item passes the test, if yes, marking as 1, if not, marking as 0, and sequentially arranging according to the test order, recorded as test result sequence; for example, the test result sequence is 11101, which means that the fourth chip tested by the first test item does not pass, and the rest all pass;

[0060] Step S105, record the single test time, the single test cost, the test pass sequence and the test result sequence of the first test item as the basic test data of the first test item, and repeat to obtain the basic test data of all test items;

[0061] In the specific implementation process, the CP test is a key test link of the wafer level in the chip manufacturing process, mainly detects each exposed chip on the wafer which has not been cut and packaged, and is a core quality screening step between the chip manufacturing from the wafer and the cutting and packaging; the CP test occurs after the wafer completes all manufacturing processes and before cutting and packaging; at this time, the wafer is still full of a large number of unseparated dies, the CP test directly contacts the pads of the dies through the probe to detect each die; the dies with functional defects, substandard performance or parameter exceeding are removed to avoid sending unqualified dies to the subsequent packaging link.

[0062] Step S2, perform item correlation analysis according to the basic test data of each item to obtain the related item data of each item; step S2 includes the following substeps:

[0063] Step S201, please refer to Figure 2 The first test item is recorded as the second test item, and the test pass sequences of the first test item and the second test item are recorded as the first pass sequence and the second pass sequence in order; the time windows of the first pass sequence and the second pass sequence are aligned, that is, the data at the same sequence number position of the first pass sequence and the second pass sequence are the data of the same time period, and if the first pass sequence and the second pass sequence are too long, part of them can be intercepted for subsequent processing;

[0064] Step S202, obtain the average value and the standard deviation of the first pass sequence, and record them as PA1 and PB1 in order, obtain the average value and the standard deviation of the second pass sequence, and record them as PA2 and PB2 in order; record [PA1-k1*PB1, PA1+k1*PB1] and [PA2-k1*PB12, PA12+k1*PB1] as the general fluctuation range of the first pass sequence and the second pass sequence in order, wherein k1 is a set proportion coefficient; based on the normal distribution principle, the general fluctuation range is determined based on the mean and the standard deviation to filter out the time points that significantly deviate from the normal fluctuation, and in this embodiment, k1=2, which can be flexibly set;

[0065] Step S203, obtain the pass rates of all the fluctuation points in the first pass sequence and the second pass sequence that exceed the corresponding general fluctuation range;

[0066] Step S204, obtaining the position sequence number of each fluctuation point in the corresponding test passing sequence, recording the position sequence number of the fluctuation point in the first passing sequence and the second passing sequence as a co-occurrence position, and recording the two fluctuation points of the co-occurrence position as a co-occurrence fluctuation group;

[0067] Step S205, obtaining the total number of fluctuation points in the first passing sequence and the second passing sequence respectively, and recording the total number of co-occurrence positions as AH3; calculating the first synchronization index AD of the first test item and the second test item, where AD = 2*AH3 / (AH1+AH2); AD measures whether the fluctuations of the first passing sequence and the first passing sequence occur at the same time; if the fluctuations of the two occur at the same time frequently, it is indicated that they may be affected by the same process defects, such as photolithography deviation and uneven doping, that is, the chips that do not pass the first test item are likely to simultaneously fail the second test item.

[0068] Step S206, for any one co-occurrence fluctuation group, recording the two fluctuation points of the co-occurrence fluctuation group as a first fluctuation group, if the two fluctuation points of the first fluctuation group are simultaneously higher than the corresponding general fluctuation range or simultaneously lower than the corresponding general fluctuation range, marking the first fluctuation group as a same-direction fluctuation group, otherwise marking the first fluctuation group as an opposite-direction fluctuation group;

[0069] Step S207, repeating the obtaining of all same-direction fluctuation groups, obtaining the total number of same-direction fluctuation groups, and recording the total number of same-direction fluctuation groups as BH1; calculating the second synchronization index BD of the first test item and the second test item, where BD = BH1 / AH3; AH3 is equal to the total number of co-occurrence fluctuation groups; BD judges whether the fluctuation directions of the first test item and the second test item are consistent; if the fluctuation of the first test item is a pass rate decrease and the fluctuation of the second test item is a pass rate increase, it is indicated that the two are irrelevant;

[0070] Step S208, for any one same-direction fluctuation group, recording the two fluctuation points of the same-direction fluctuation group as a first same-direction group, recording the fluctuation points belonging to the first passing sequence of the first same-direction group as CA1, and recording the fluctuation points belonging to the second passing sequence of the first same-direction group as CA2; calculating the fluctuation proportions of CA1 and CA2 respectively, and recording the fluctuation proportions of CA1 and CA2 as CE1 and CE2 in sequence, where CE1 = |CA1-PA1| / PB1 and CE2 = |CA2-PA2| / PB2; and calculating the fluctuation ratio CR of the first same-direction group, where CR = CE1 / CE2.

[0071] Step S209, repeat to obtain the fluctuation ratio of all the same direction fluctuation groups, and calculate the standard deviation, denoted as CB; calculate the third synchronization index CD of the first test item and the second test item, wherein CD = 1 - [CB / (1 + CB)]; CD measures whether the severity of the fluctuation of the first test item and the second test item matches; if the fluctuation amplitude of the first test item is large, the fluctuation amplitude of the second test item is also large, which indicates that the two are affected by the same defect to a similar degree; if the fluctuation amplitude difference is large, it may be affected by different factors;

[0072] Step S210, calculate the covariation fluctuation index GD of the first test item and the second test item, wherein GD = (AD + BD + CD) / 3; repeat to obtain the covariation fluctuation index of the first test item and all other test items, and arrange them in order from small to large, denoted as the covariation fluctuation sequence; obtain a comprehensive score of 0-1 by comprehensively considering the synchronization of the three dimensions of time, direction and amplitude, and quantify the correlation between the first test item and the second test item; the higher the score, the higher the correlation between the first test item and the second test item.

[0073] Step S211, arrange the test result sequence of the first test item and the second test item in order as the first result sequence and the second result sequence respectively;

[0074] Step S212, arrange the data at the same sequence position of the first result sequence and the second result sequence as the first result and the second result respectively;

[0075] Step S213, please refer to Figure 3 the number of times that the first result and the second result are equal to 0 at the same time, denoted as FA; the number of times that the first result is equal to 0 and the second result is equal to 1, denoted as FB; the number of times that the first result is equal to 1 and the second result is equal to 0, denoted as FC; the number of times that the first result and the second result are equal to 1 at the same time, denoted as FD; FA represents that the chip fails both the first test item and the second test item; FB represents that the chip fails the first test item but passes the second test item; FC represents that the chip passes the first test item but fails the second test item; FD represents that the chip passes both the first test item and the second test item; the larger FA is, the stronger the potential correlation between the first test item and the second test item is; the larger FB and FC are, the weaker the potential correlation between the first test item and the second test item is.

[0076] Step S214, calculate the co-occurrence failure index GX of the first test item and the second test item, wherein GX=[FA / (FA+FB)]*[FA / (FA+FC)]*[FA / (FA+FB+FC)]; repeat to obtain the co-occurrence failure indexes of the first test item and all other test items, and arrange them in ascending order, and mark as a co-occurrence failure sequence; the value of GX is closer to 1, the higher the probability that the chip fails to pass the second test item when it fails to pass the first test item; also the higher the probability that the chip fails to pass the first test item when it fails to pass the second test item, that is, the higher the correlation of the first test item and the second test item;

[0077] Step S215, obtain the position sequence numbers of the second test item in the co-varying fluctuation sequence and the co-occurrence failure sequence, and sum them up, mark as the correlation score of the first test item and the second test item, repeat to obtain the correlation scores of the first test item and all other test items, and mark the test items corresponding to the maximum k2 correlation scores as the correlation test items of the first test item, mark as the correlation item data of the first test item, and repeat to obtain the correlation item data of all test items, wherein k2 is the number set; in this embodiment, k2=2, which can be flexibly set according to actual application scenarios;

[0078] In the specific implementation process, in the CP test of the chip, normal process fluctuation will cause the pass rate to change slightly and randomly, but the same process defect will cause multiple associated items to appear large fluctuations at the same time, such as sudden drop or sudden rise of the pass rate; in the chip test, the correlation of normal fluctuation has no actual significance, while the synchronism of abnormal fluctuation can better reflect the internal correlation of different test items, and the synchronism of time, direction and amplitude directly corresponds to the fluctuation caused by the same reason, which is more targeted than the traditional method.

[0079] Step S3, perform item necessity analysis based on the basic test data and the correlation item data of each item to obtain test item stability data; step S3 includes the following sub-steps:

[0080] Step S301, divide all test items into important test items and general test items, and mark any one general test item as a third test item; the division can be made according to actual application scenarios;

[0081] Step S302, according to the basic test data of the third test item, obtain the test pass rate in each first time period within the recent first time length, mark as a recent pass set, wherein the first time length is ET1, and in this embodiment, ET1=2 months;

[0082] Step S303, calculate the average and standard deviation of the recent pass set, sequentially recorded as the average pass UP and the pass standard deviation UB of the third test item, and calculate the coefficient of variation of the third test item, recorded as CV, wherein CV=(UB / UP)*100%;

[0083] Step S304, if the recent pass set of the third test item is all not less than k3, and the average pass UP is not less than k4, and the coefficient of variation CV is not greater than k5, mark the third test item as a general stable item, otherwise mark it as a general fluctuation item, wherein k3, k4 and k5 are set threshold values; in this embodiment, k3=98.0%, k4=99.0%, and k5=2%; the general stable item needs to meet the following two conditions at the same time: the overall pass rate of the test item is long-term at a very high level, indicating that almost no defective product is detected, and the detection value is low; and the fluctuation of the pass rate is extremely small, indicating that the process has been completely mature, and the result of this test item is no longer affected by the process fluctuation, and there is no need to continue monitoring;

[0084] Step S305, repeat the acquisition of all general stable items, and the corresponding average pass and coefficient of variation, recorded as test item stable data.

[0085] In the specific implementation process, after the long-term mass production of the chip, the process and performance of the chip tend to be stable, and the pass rate of some detection items is extremely high and extremely stable; such items have very low contribution to screening of defective products after the process is stable, and the actual value of continuing to detect all is not high and will increase the cost, and can be appropriately changed to sampling detection, which can reduce the detection time and thus reduce the detection cost; and the screening of such detection items needs to meet high pass rate and high stability at the same time.

[0086] Step S4, optimize the test items for CP test according to the test time of each test item and the test item stable data; step S4 includes the following sub-steps:

[0087] Step S401, for the first stable item, record the first stable item and the corresponding related test items as a first test item group;

[0088] Step S402, if the related test items of the first stable item are not all general stable items, change the first stable item to a sampling detection mode; that is, there are important test items or general fluctuation items in the related test items of the first stable item, because the important test items or general fluctuation items are full detection models, and have strong correlation with the first stable item, when the detection result of the important test items or general fluctuation items fluctuates greatly, the first stable item can be changed from the sampling detection mode to the full detection mode in time, avoiding missing defective chips when the chip manufacturing process fluctuates, and causing losses.

[0089] Step S403, if all the first test item groups are general stable items, the single test time of all test items in the first test item group is obtained, if the single test time of the first stable item is not the shortest, the first stable item is changed to the sampling inspection mode; if the single test time of the first stable item is the shortest, the first stable item is not changed to the sampling inspection mode; that is, the test item with the shortest single test time is left as a monitoring item, when the detection result of the monitoring item fluctuates greatly, the related test item is changed from the sampling inspection mode to the full inspection mode in time, so as to avoid missing detection; and the reason why the test item with the shortest single test time is left as a monitoring item is that the shorter the test time is, the lower the detection cost is;

[0090] In the specific implementation process, all the general stable items can also be changed to the sampling inspection mode, for the general stable items of the first test item group, the sampling inspection result can be judged, when the sampling inspection result fluctuates greatly, the full inspection mode is changed in time, and the sampling inspection ratio can be flexibly set according to the actual application scene.

[0091] Embodiment 2, please refer to Figure 4 As shown in the figure, Figure 4 An example of a structural schematic diagram of an electronic device is shown, which can include a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete the communication among each other through the communication bus. The memory stores computer readable instructions, and the processor can call the instructions in the memory, when the computer readable instructions are executed by the processor, the steps in a kind of high-precision chip test optimization method are run, to realize the following functions: collecting the test time and test passing condition of each test item in CP test, obtaining the basic test data of each test item;According to the basic test data of each item, project correlation analysis is carried out, and the related item data of each item is obtained;Based on the basic test data and related item data of each item, project necessity analysis is carried out, and test item stability data is obtained;According to the test time of each test item and test item stability data, the test item of CP test is optimized.

[0092] In addition, the logic instructions in the above-mentioned memory can be implemented in the form of a software function unit and sold or used as an independent product, and can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in various embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0093] In embodiment 3, the present application also provides a computer readable storage medium, and the present application provides a storage medium, which stores a computer program. When the computer program is executed by a processor, the steps in the method for testing and optimizing a high-precision chip are run to realize the following functions: collecting test time and test passing conditions of each test item in CP testing to obtain basic test data of each test item; performing project correlation analysis according to the basic test data of each item to obtain relevant item data of each item; performing project necessity analysis based on the basic test data and the relevant item data of each item to obtain test item stability data; and optimizing the test items in CP testing according to the test time of each test item and the test item stability data.

[0094] Through the description of the above embodiments, the embodiments of the present application can be provided as a method, a system or a computer program product. Based on such understanding, the above technical solutions essentially or the part that contributes to the prior art can be embodied in the form of a software product. The computer software product can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the method described in each embodiment or some part of the embodiment.

[0095] In the embodiments of the present application, it should be understood that the disclosed system or method can be implemented in other ways. The embodiments described above are only illustrative, for example, the division of modules or units is only a logical function division, and other division manners can be used in actual implementation, for example, a plurality of modules or units can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed each other can be through some communication interface, the indirect coupling or communication connection between the system, the module and the unit can be electrical, mechanical or other forms.

[0096] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for optimizing the testing of high-precision chips, characterized in that, Includes the following steps: Collect the test time and pass status of each test item in the CP test to obtain the basic test data for each test item; Based on the basic test data of each project, a project correlation analysis is performed to obtain the relevant project data for each project. Based on the basic test data and related project data of each project, a necessity analysis of the project is conducted to obtain stable data for the test project; Optimize the test items based on the test time and stability data of each test item, as well as the test items of CP test.

2. The testing optimization method for a high-precision chip according to claim 1, characterized in that, The process of collecting test time and pass / fail status for each test item in the CP test, and obtaining basic test data for each test item, includes the following sub-steps: For all test stages in the CP test of the chip, they are sequentially labeled as CP1, CP2, ..., CPn, where n is the total number of test stages; all test items in all test stages are sequentially labeled as test item 1, test item 2, ..., test item m, where m is the total number of test items, and any test item is designated as the first test item. The time taken to test one chip in the first test item is recorded as the single test time.

3. The testing optimization method for a high-precision chip according to claim 2, characterized in that, Collecting the test time and pass / fail status of each test item in the CP test, and obtaining the basic test data for each test item, also includes the following sub-steps: Set the first time period to T1, repeatedly obtain the test pass rate of the first test item in each first time period, and arrange them in chronological order from oldest to newest, and record them as the test pass sequence; Obtain whether each chip in the first test item passes the test. If it passes, mark it as 1; if it fails, mark it as 0. Arrange them in the order of testing and record them as the test result sequence. The single test time, test pass sequence, and test result sequence of the first test item are recorded as the basic test data of the first test item, and the basic test data of all test items are obtained repeatedly.

4. The testing optimization method for a high-precision chip according to claim 3, characterized in that, Based on the basic test data of each project, a project correlation analysis is performed to obtain the relevant project data for each project, including the following sub-steps: Any test item other than the first test item is designated as the second test item, and the test pass sequences of the first test item and the second test item are designated as the first pass sequence and the second pass sequence, respectively. Obtain the mean and standard deviation of the first pass sequence, and denote them as PA1 and PB1 respectively. Obtain the mean and standard deviation of the second pass sequence, and denote them as PA2 and PB2 respectively. Denote [PA1-k1*PB1, PA1+k1*PB1] and [PA2-k1*PB12, PA12+k1*PB1] as the general fluctuation range of the first pass sequence and the second pass sequence respectively, where k1 is the set proportional coefficient. Obtain the pass rates of all data exceeding the corresponding general fluctuation range in the first pass sequence and the second pass sequence, and denote them as fluctuation points; Obtain the position number of each fluctuation point in the corresponding test pass sequence. Record the position numbers of fluctuation points in both the first pass sequence and the second pass sequence as co-occurrence positions. Record the two fluctuation points at the co-occurrence positions as co-occurrence fluctuation groups. Obtain the total number of fluctuation points in the first and second passing sequences respectively, and denote them as AH1 and AH2 in order; and the total number of co-occurrence positions, denote them as AH3; calculate the first synchronization index AD of the first test item and the second test item, where AD = 2*AH3 / (AH1+AH2).

5. The testing optimization method for a high-precision chip according to claim 4, characterized in that, Based on the basic test data of each project, the project correlation analysis to obtain the relevant project data for each project also includes the following sub-steps: For any co-occurring fluctuation group, denoted as the first fluctuation group, if the two fluctuation points of the first fluctuation group are simultaneously higher than or simultaneously lower than the corresponding general fluctuation range, they are marked as the same-direction fluctuation group; otherwise, they are marked as the opposite-direction fluctuation group. Repeatedly obtain all the same-direction fluctuation groups and obtain the total number of same-direction fluctuation groups, denoted as BH1. Calculate the second synchronization index BD of the first test item and the second test item, where BD = BH1 / AH3. For any group of fluctuations in the same direction, denoted as the first group, the fluctuation points belonging to the first passing sequence of the first group are denoted as CA1, and the fluctuation points belonging to the second passing sequence are denoted as CA2. The fluctuation ratios of CA1 and CA2 are calculated respectively and denoted as CE1 and CE2 in order, where CE1 = |CA1-PA1| / PB1, CE2 = |CA2-PA2| / PB2; and the fluctuation ratio CR of the first group is calculated, where CR = CE1 / CE2. Repeatedly obtain the volatility ratio of all groups of unidirectional volatility and calculate the standard deviation, denoted as CB; calculate the third synchronization index CD of the first test item and the second test item, where CD = 1 - [CB / (1+CB)]; Calculate the covariance volatility index GD for the first and second test items, where GD = (AD + BD + CD) / 3; repeatedly obtain the covariance volatility index of the first test item and all other test items, and arrange them in ascending order, denoted as the covariance volatility sequence.

6. The testing optimization method for a high-precision chip according to claim 5, characterized in that, Based on the basic test data of each project, the project correlation analysis to obtain the relevant project data for each project also includes the following sub-steps: The test result sequences of the first test item and the second test item are respectively denoted as the first result sequence and the second result sequence in sequence; The data in the first result sequence and the second result sequence that are at the same index position are recorded as the first result and the second result respectively in order; For the first result sequence and the second result sequence, count the number of times the first result and the second result are both equal to 0, denoted as FA; The number of instances where the first result is 0 and the second result is 1 is denoted as FB; the number of instances where the first result is 1 and the second result is 0 is denoted as FC; the number of instances where both the first and second results are 1 is denoted as FD. Calculate the co-occurrence failure index GX for the first test item and the second test item, where GX = [FA / (FA+FB)]*[FA / (FA+FC)]*[FA / (FA+FB+FC)]; Repeatedly obtain the co-occurrence failure index of the first test item and all other test items, and arrange them in ascending order, denoted as the co-occurrence failure sequence; Obtain the position number of the second test item in the covariance fluctuation sequence and co-occurrence failure sequence, and sum them up. Record this as the relevant score of the first test item and the second test item. Repeatedly obtain the relevant scores of the first test item and all other test items, and record the test items corresponding to the largest k2 relevant scores as the relevant test items of the first test item. Mark these as the relevant item data of the first test item. Repeatedly obtain the relevant item data of all test items, where k2 is the set number.

7. The testing optimization method for a high-precision chip according to claim 6, characterized in that, Based on the basic test data and related project data for each project, a project necessity analysis is conducted to obtain stable test project data, including the following sub-steps: All test items are divided into important test items and general test items, and any one of the general test items is designated as the third test item. Based on the basic test data of the third test item, obtain the test pass rate for each first time period within the most recent first time length, and record it as the recent pass set, where the first time length is ET1; Calculate the mean and standard deviation of the recent pass set, and record them as the mean pass UP and standard deviation pass UB of the third test item in order. Calculate the coefficient of variation of the third test item, denoted as CV, where CV = (UB / UP) * 100%. If the recent pass set of the third test item is not less than k3, the average pass UP is not less than k4, and the coefficient of variation CV is not greater than k5, then the third test item is marked as a generally stable item; otherwise, it is marked as a generally fluctuating item. Here, k3, k4, and k5 are the set thresholds. Repeatedly obtain all general stable items, along with their corresponding average pass and coefficient of variation, and record them as the stable data for the test items.

8. The testing optimization method for a high-precision chip according to claim 7, characterized in that, Based on the testing time and stability data of each test item, and the optimization of the CP test items, the following sub-steps are included: For the first stable project, the first stable project and its corresponding related test projects are referred to as the first test project group; If the relevant test items of the first stable project are not all general stable projects, then the first stable project will be changed to a sampling inspection mode. If the first test project group consists entirely of general stable projects, then obtain the individual test time of all test projects within the first test project group. If the individual test time of the first stable project is not the shortest, then change the first stable project to the sampling mode; if the individual test time of the first stable project is the shortest, then do not change the first stable project to the sampling mode.

9. An electronic device, characterized in that, It includes a processor and a memory, the memory storing computer-readable instructions that, when executed by the processor, perform the steps of the method as described in any one of claims 1-8.

10. A storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it performs the steps of the method as described in any one of claims 1-8.

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