Signal test system and test method

Abstract

The invention discloses a signal test system and a test method, the signal test system is used for testing an HRPWM signal, the signal test system comprises a frequency division module and an operation module, the frequency division module is used for carrying out frequency division on a reference PWM signal based on the period of the HRPWM signal to generate a frequency division signal, and the operation module is connected with the frequency division module and is used for calculating the period ratio of the frequency division signal to the HRPWM signal; and generating an operation result. According to the signal testing system and the signal testing method, the parameters of the HRPWM signal can be tested by using a simple hardware instrument, and the signal testing system and the signal testing method have the advantages of high testing precision, short testing time and easiness in automatic testing under various testing conditions.

Description

Technical Field

[0001] This invention belongs to the field of signal testing technology, specifically relating to a signal testing system and testing method. Background Technology

[0002] In MCU or DSP chips, there are HRPWM (high resolution PWM) circuit modules, whose control accuracy reaches within 100~200pS, or even tens of pS. It is necessary to use an ultra-high speed oscilloscope to test its circuit performance. This testing method is not only costly and time-consuming, but also inconvenient to obtain test data.

[0003] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a signal testing system and method that can easily test HRPWM.

[0005] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution:

[0006] A signal testing system for testing HRPWM signals, the signal testing system comprising:

[0007] The frequency divider module is used to divide the reference PWM signal based on the period of the HRPWM signal to generate a frequency divider signal;

[0008] The arithmetic module, connected to the frequency divider module, is used to calculate the period ratio of the frequency divider signal to the HRPWM signal and generate the calculation result.

[0009] In one or more embodiments of the present invention, the arithmetic module includes a first logic unit, a counting unit, and a reset unit. The first logic unit is connected to a frequency division module to perform logical operations on the HRPWM signal and the frequency division signal to generate a first logic signal. The reset unit is connected to the frequency division module to generate a reset signal based on the frequency division signal. The counting unit is connected to the first logic unit and the reset unit to count the first logic signal to generate a counting signal characterizing the operation result, and to control the reset based on the reset signal.

[0010] In one or more embodiments of the present invention, the first logic unit includes an AND gate, the first input terminal of the AND gate is used to receive an HRPWM signal, the second input terminal of the AND gate is connected to a frequency divider module to receive a frequency divider signal, and the output terminal of the AND gate is used to generate a first logic signal.

[0011] In one or more embodiments of the present invention, the reset unit includes a first delay unit and a second logic unit. The first delay unit is connected to a frequency division module to perform a first delay on the frequency division signal to generate a first delay signal and a second delay on the frequency division signal to generate a second delay signal. The second logic unit is connected to the first delay unit to perform logical operations on the first delay signal and the second delay signal to generate a reset signal.

[0012] In one or more embodiments of the present invention, the second logic unit includes a NOT gate and an OR gate, the NOT gate being connected to a first delay unit to invert the second delay signal to generate a second delayed NOT signal, the first input terminal of the OR gate being connected to the first delay unit to receive a first delayed signal, the second input terminal of the OR gate being connected to the NOT gate to receive the second delayed NOT signal, and the output terminal of the OR gate being used to generate a reset signal.

[0013] In one or more embodiments of the present invention, the arithmetic module further includes a latch unit, which is connected to the counting unit to latch the counting signal.

[0014] In one or more embodiments of the present invention, the arithmetic module further includes a second delay unit, which is connected to the frequency division module to delay the frequency division signal. The first logic unit is connected to the second delay unit to perform logical operations on the delayed frequency division signal and the HRPWM signal to generate a first logic signal. The frequency division signal is also used to control the latch unit.

[0015] In one or more embodiments of the present invention, the signal testing system further includes a duty cycle testing module, which is used to test the duty cycle of the HRPWM signal.

[0016] In one or more embodiments of the present invention, the duty cycle test module includes a filtering unit and a voltage detection unit. The filtering unit is used to filter the HRPWM signal to generate a voltage signal, and the voltage detection unit is connected to the filtering unit to detect the voltage value of the voltage signal and generate a voltage value signal.

[0017] A specific embodiment of the present invention also provides a signal testing method, which, based on the above-described signal testing system, includes:

[0018] The frequency divider module divides the reference PWM signal based on the period of the HRPWM signal to generate a frequency divider signal;

[0019] The calculation module calculates the period ratio of the frequency division signal to the HRPWM signal and generates the calculation result.

[0020] Compared with the prior art, the signal testing system and method of the present invention can use simple hardware instruments to test the parameters of HRPWM signals, and has the advantages of high testing accuracy, short testing time and easy automation under various testing conditions. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a system structure diagram of a signal testing system according to an embodiment of the present invention.

[0023] Figure 2 This is a flowchart of a signal testing method in one embodiment of the present invention.

[0024] Figure 3 This is a partial flowchart of a signal testing method in one embodiment of the present invention.

[0025] Figure 4 This is a waveform diagram of each signal in one embodiment of the present invention. Detailed Implementation

[0026] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.

[0027] The terms "coupled," "connected," or "linked" in the specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in the invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0028] In the detailed description of this specification, reference is made to the accompanying drawings, which form a part thereof, wherein like reference numerals always denote like parts, and wherein exemplary embodiments are shown by way of example that may be implemented. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this application. Therefore, the following detailed description should not be considered limiting.

[0029] The various operations in the specification may be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0030] For the purposes of this application, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this application, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0031] Various components and devices may be mentioned or shown in the singular form herein, but only for the convenience of discussion, and any element mentioned in the singular form may include multiple such elements as taught herein.

[0032] The description uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," each of which can refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used in relation to embodiments of this application are synonymous.

[0033] like Figure 1 As shown, in one embodiment of the present invention, the signal testing system is used to test HRPWM signals. Specifically, the signal testing system includes a frequency division module 10, an arithmetic module 20, and a duty cycle testing module 30.

[0034] The frequency divider module 10 is used to divide the reference PWM signal based on the period of the HRPWM signal to generate a divided frequency signal VA. The arithmetic module 20 is connected to the frequency divider module 10 and is used to calculate the period ratio of the divided frequency signal VA to the HRPWM signal and generate the calculation result. The duty cycle test module 30 is used to test the duty cycle of the HRPWM signal.

[0035] In one embodiment, both the HRPWM signal and the reference PWM signal are generated by the HRPWM module, wherein the period of the reference PWM signal and the duration of the high and low levels are integer multiples of the system clock period Tck of the HRPWM module.

[0036] The HRPWM module can generate two types of HRPWM signals: the high-precision period signal HR-period and the high-precision duty cycle signal HR-duty.

[0037] The high-level duration of the periodic high-precision signal HR-period is an integer multiple of the system clock cycle of the HRPWM module. Its period is processed with high precision, being a superposition of an integer multiple and a fractional multiple of the system clock cycle. Specifically, the signal period of the periodic high-precision signal HR-period can be written as (N1 + K1 / P1) * Tck, and its high-level duration can be written as M1 * Tck. Here, M1, N1, K1, and P1 are all positive integers, with M1 less than N1 and K1 less than P1.

[0038] The period of the high-precision duty cycle signal HR-duty is an integer multiple of the system clock period of the HRPWM module. Its high-level time (i.e., duty cycle) is processed with high precision and is the sum of an integer multiple and a fractional multiple of the system clock period. Specifically, the signal period of the high-precision duty cycle signal HR-duty can be written as N2 * Tck, and its high-level time can be written as (M2 + K2 / P2) * Tck. Where M2, N2, K2, and P2 are all positive integers, with M2 less than N2 and K2 less than P2.

[0039] The period of the reference PWM signal can be written as N3 * Tck, and the high-level duration of the reference PWM signal can be written as M3 * Tck. Here, M3 and N3 are both positive integers, with M3 being less than N3. That is, the reference PWM signal is a regular PWM signal generated based on the same system clock period as the HRPWM signal.

[0040] Preferably, by configuring the HRPWM module, N1=N2=N3. In this case, both the periodic high-precision signal HR-period and the duty cycle high-precision signal HR-duty have the same integer period as the reference PWM signal.

[0041] Furthermore, the HRPWM module also includes a multiplexer, which is used to selectively output a high-precision period signal HR-period and a high-precision duty cycle signal HR-duty. The signal testing system may also include a control module 40, which is used to control the multiplexer in the HRPWM module to output either the high-precision period signal HR-period or the high-precision duty cycle signal HR-duty.

[0042] In other embodiments, the HRPWM signal and the reference PWM signal can also be generated by different signal modules, as long as the HRPWM signal and the reference PWM signal have the same system clock period, or the system clock period of the reference PWM signal and the system clock period of the HRPWM signal are integer multiples of each other.

[0043] In other embodiments, the HRPWM module may not generate a high-precision duty cycle signal HR-duty. The frequency division module 10 and the arithmetic module 20 in this signal testing system are mainly used to test the high-precision periodic signal HR-period, while the duty cycle testing module 30 can test both the high-precision periodic signal HR-period and the high-precision duty cycle signal HR-duty.

[0044] like Figure 1 As shown, the duty cycle test module 30 includes a filtering unit 31 and a voltage detection unit 32. The filtering unit 31 is connected to the multiplexer in the HRPWM module and is used to filter the HRPWM signal to generate a voltage signal. The voltage detection unit 32 is connected to the filtering unit 31 to detect the voltage value of the voltage signal and generate a voltage value signal.

[0045] In one embodiment, the filtering unit 31 includes a resistor R and a capacitor C. The first end of the resistor R is connected to the multiplexer in the HRPWM module to receive the HRPWM signal. The second end of the resistor R and the first end of the capacitor C are connected to the voltage detection unit 32 to generate a voltage signal. The second end of the capacitor C is connected to ground. The resistor R and the capacitor C form a low-pass filter, which can filter the HRPWM signal to generate a DC voltage signal.

[0046] Since the voltage value of the voltage signal output by the filter unit 31 will change with the duty cycle of the HRPWM signal, the corresponding duty cycle value can be calculated as long as the voltage value of the voltage signal is measured.

[0047] like Figure 1 As shown, in one embodiment, the frequency division module 10 includes a first frequency divider and a second frequency divider.

[0048] The first frequency divider is connected to the HRPWM module, and it divides the reference PWM signal by a ratio of 1 / (P1*N1+K1). The second frequency divider is connected to the first frequency divider, and it further divides the signal after the first frequency divider by a ratio of M3 / N3 (i.e., the duty cycle of the reference PWM signal) to generate the divided signal VA.

[0049] After passing through the first and second frequency dividers, the period of the divided signal VA is extended to (P1*N1+K1)*(N3). 2The high-level time of / M3)* Tck is (P1*N1+K1)*N3* Tck, and the low-level time is (P1*N1+K1)*(N3 / (N3-M3))* Tck.

[0050] In one specific embodiment, M3 / N3=1 / 2, that is, the duty cycle of the reference PWM signal is 1 / 2. Then, the second frequency divider further divides the signal after the first frequency divider with a division ratio of 1 / 2. The period of the divided signal VA is extended to (P1*N1+K1)*2*N3*Tck, and its high level time is (P1*N1+K1)*N3*Tck.

[0051] In other embodiments, the frequency division module 10 may also include one or more frequency dividers, as long as they can achieve the corresponding frequency division function.

[0052] like Figure 1 As shown, in one embodiment, the arithmetic module 20 includes a first logic unit, a counting unit, a reset unit, a latching unit, and a second delay unit 21.

[0053] The second delay unit 21 is connected to the frequency divider module 10 to delay the frequency divider signal VA to generate a delayed frequency divider signal VB. The first logic unit is connected to the second delay unit 21 and the multiplexer to perform logical operations on the delayed frequency divider signal VB and the high-precision periodic signal HR-period to generate a first logic signal VE. The reset unit is connected to the second delay unit 21 to generate a reset signal VF based on the delayed frequency divider signal VB. The counting unit is connected to the first logic unit and the reset unit to count the first logic signal VE to generate a counting signal VG representing the operation result, outputs the counting signal VG through its own signal output terminal QN, and resets the signal based on the control of the reset signal VF. The signal input terminal Din of the latch unit is connected to the signal output terminal QN of the counting unit to latch the counting signal VG.

[0054] The control terminal CK of the latch unit is also connected to the second frequency divider to receive the frequency division signal VA. The frequency division signal VA is also used to control the latch unit to perform latching. In one embodiment, when the frequency division signal VA is high, the latch unit outputs a latch signal VH through its own signal output terminal QD, which follows the change of the counting signal VG. When the frequency division signal VA is low, the latch signal VH is maintained. In other embodiments, the latch unit may also be controlled by the frequency division signal VA based on other control logic.

[0055] For example, the second delay unit 21 can delay the frequency division signal VA by M1*Tck to generate the delayed frequency division signal VB.

[0056] In one embodiment, the first logic unit may include an AND gate, the first input of which is connected to a multiplexer to receive a periodic high-precision signal HR-period, the second input of which is connected to a second delay unit 21 to receive a delayed frequency-divided signal VB, and the output of which is connected to the signal terminal CK of a counting unit to generate a first logic signal VE.

[0057] In one embodiment, the reset unit includes a first delay unit 22 and a second logic unit. The first delay unit 22 is connected to the second delay unit 21 to perform a first delay on the delayed frequency-divided signal VB to generate a first delayed signal VC, and a second delay on the delayed frequency-divided signal VD to generate a second delayed signal VD. The second logic unit is connected to the first delay unit 22 to perform logical operations on the first delayed signal VC and the second delayed signal VD to generate a reset signal VF.

[0058] The first delay unit 22 includes a first delayer and a second delayer. The first delayer is connected to the second delay unit 21 to delay the delayed frequency division signal VB to generate a first delayed signal VC. The second delayer is connected to the first delayer to delay the first delayed signal VC to generate a second delayed signal VD.

[0059] For example, the first delay unit can delay the delayed frequency-divided signal VB by 4 * Tck, and the second delay unit can delay the first delayed signal VC by 1 * Tck.

[0060] The second logic unit may include an NOT gate and an OR gate. The NOT gate is connected to the second delay unit to invert the second delayed signal VD to generate a second delayed NOT signal. The first input of the OR gate is connected to the first delay unit to receive the first delayed signal VC. The second input of the OR gate is connected to the NOT gate to receive the second delayed NOT signal. The output of the OR gate is connected to the reset terminal Reset of the counting unit to generate a reset signal VF.

[0061] like Figure 2 As shown, this embodiment also provides a signal testing method. Based on the above-described signal testing system, the signal testing method includes:

[0062] The frequency divider module 10 divides the reference PWM signal based on the period of the high-precision periodic signal HR-period to generate the frequency divider signal VA.

[0063] The calculation module 20 calculates the period ratio of the frequency-divided signal VA to the period-high precision signal HR-period and generates the calculation result.

[0064] For example, the frequency division ratio of the reference PWM signal by the frequency division module 10 is M3 / ((P1*N1+K1)*N3), and the period of the frequency division signal VA is (P1*N1+K1)*(N3).2 / M3)* Tck, its high level time is (P1*N1+K1)* N3* Tck, and its low level time is (P1*N1+K1)* (N3 / (N3-M3))* Tck.

[0065] In one specific embodiment, M3 / N3=1 / 2, and the frequency division ratio of the frequency divider module 10 to the reference PWM signal is 1 / ((P1*N1+K1)*2).

[0066] like Figure 3 As shown, the calculation module 20 calculates the period ratio of the frequency-divided signal to the high-precision periodic signal HR-period and generates the calculation result. In this embodiment, the specific steps may include:

[0067] The frequency division signal VA is delayed by the second delay unit 21.

[0068] The first logic signal VE is generated by performing logical operations on the delayed frequency-divided signal VB and the periodic high-precision signal HR-period through the first logic unit.

[0069] The reset unit generates a reset signal VF based on the delayed frequency-divided signal VB.

[0070] The counting unit counts the first logic signal VE to generate a counting signal VG representing the operation result, and resets it based on the control of the reset signal VF.

[0071] The counting signal VG is latched by the latch unit, and the latch unit is controlled by the frequency division signal VA.

[0072] Combination Figure 4 As shown, in one embodiment, the second delay unit 21 delays the frequency division signal VA by M1*Tck to obtain the delayed frequency division signal VB.

[0073] Next, the first logic signal VE is generated by performing an AND operation between the delayed frequency-divided signal VB and the periodic high-precision signal HR-period through an AND gate in the first logic unit. It can be seen that within the positive half-cycle of the delayed frequency-divided signal VB, the periodic high-precision signal HR-period experiences a total of P1*N3 cycles, and the first logic signal VE will generate P1*N3 or P1*N3+1 high-level signals. Specifically, if the rising edge of the delayed frequency-divided signal VB falls on the low level of the periodic high-precision signal HR-period, the first logic signal VE will generate P1*N3 high-level signals; if the rising edge of the delayed frequency-divided signal VB falls on the high level of the periodic high-precision signal HR-period, the first logic signal VE will generate P1*N3+1 high-level signals.

[0074] Next, the reset unit generates a reset signal VF based on the delayed frequency-divided signal VB. In this embodiment, this may specifically include the following steps:

[0075] The first delay unit 22 performs a first delay on the delayed frequency-divided signal VB to generate a first delayed signal VC, and performs a second delay on the delayed frequency-divided signal VB to generate a second delayed signal VD.

[0076] The second logic unit performs logical operations on the first delayed signal VC and the second delayed signal VD to generate a reset signal VF.

[0077] Combination Figure 4 As shown, in one embodiment, the delayed frequency division signal VB is delayed by 4 * Tck by the first delay unit in the first delay unit 22 to obtain the first delayed signal VC, and the first delayed signal VC is delayed by 1 * Tck by the second delay unit to obtain the second delayed signal VD.

[0078] Next, the second delayed signal VD is inverted by the NOT gate in the second logic unit to generate the second delayed NOT signal, and then the first delayed signal VC and the second delayed NOT signal are ORed by the OR gate in the second logic unit to generate the reset signal VF.

[0079] It can be seen that by selecting appropriate delay times for the first and second delay units, the reset signal VF will be located within the negative half-cycle of the delayed frequency divider signal VB. This means that the reset signal VF will reset the counting unit when the frequency divider signal VB is low, ensuring that the output of the counting unit is: the number of cycles experienced by the periodic high-precision signal HR-period within the positive half-cycle of each frequency divider signal VB.

[0080] Finally, the counting signal VG is latched by the latch unit, and the latch unit is controlled by the frequency division signal VA.

[0081] In one embodiment, the latch unit latches the counting signal VG when the frequency division signal VA is high, and its output latch signal VH follows the change of the counting signal VG. When the frequency division signal VA is low, the latch signal VH is maintained.

[0082] Combination Figure 4As shown, the delayed frequency divider signal VB is delayed by M1*Tck relative to the frequency divider signal VA, which is equivalent to a high-level time of the periodic high-precision signal HR-period. This ensures that during the last M1*Tck period of the positive half-cycle of the delayed frequency divider signal VB, the output of the latch unit will not change with the calculation result. This guarantees that even if the rising edge of the delayed frequency divider signal VB falls on the high level of the periodic high-precision signal HR-period, the latch unit will not latch to the last count of the calculation result, and the maximum value of the latch signal VH is P1*N3. This value represents the period ratio of the frequency divider signal VA to the periodic high-precision signal HR-period as P1*N3:1.

[0083] Based on the above derivation, when the frequency of the high-precision periodic signal HR-period is correct, the latch signal VH should output P1*N3, that is, P1*N1. Knowing the values ​​of K1=(1,2,3...P1-1), the period (N1+K1 / P1)*Tck of the high-precision periodic signal HR-period can be accurately calculated.

[0084] Understandably, the frequency divider module 10 can also use other frequency division ratios to divide the reference PWM signal. For example, it can further add a multiple of 1 / X, where X is a positive integer, to the base M3 / (P1*N1+K1)*N3, extending the period of the frequency divider signal VA to (P1*N1+K1)*(N3). 2 / M3)*X* Tck, extending its high-level time to (P1*N1+K1)* N3* X*Tck. This increases the number of high-precision HR-period cycles within the positive half-cycle of the frequency divider signal VA, and also increases the value of the latch signal VH, which helps improve test accuracy.

[0085] Of course, based on the above principle, the ratio of the period of the frequency divider signal VA to the period of the high-precision periodic signal HR-period can be calculated by counting the number of periods of the high-precision periodic signal HR-period within the negative half-cycle of the frequency divider signal VA. Then, the working principle and control logic of each device can be adaptively adjusted.

[0086] In other embodiments, the first logic unit may also include NOR gates or other logic operation gates, in which case the counting logic of the counting unit and the logic of the reset unit generating the reset signal VF can be adjusted accordingly.

[0087] In other embodiments, the reset unit can also be directly connected to the frequency divider module 10 and directly generate the reset signal VF based on the frequency divider signal VA. The first delay unit 22 can also be set with other delay times, and the second logic unit can also use other operational logic, as long as it can generate the required reset signal VF in the negative half-cycle of the frequency divider signal.

[0088] In other embodiments, the second delay unit 21 may be omitted from the signal testing system. In this case, the first logic unit is connected to the frequency divider module 10 to perform logical operations on the high-precision periodic signal HR-period and the frequency divider signal VA to generate the first logic signal VE. The reset unit is connected to the frequency divider module 10 to generate a reset signal VF based on the frequency divider signal. At this time, the latch signal VH output by the latch will follow the counting signal VG. Both may result in a P*N+1 error. This error can be avoided by controlling the delay between the frequency divider signal VA and the high-precision periodic signal HR-period.

[0089] In other embodiments, the signal testing system may not have a latch unit and the period of the high-precision periodic signal HR-period may be directly calculated from the counting signal VG. In this case, the error can also be avoided by controlling the delay between the frequency division signal and the high-precision periodic signal HR-period.

[0090] In other embodiments, the duty cycle test module 30 may not be included in the signal test system.

[0091] Preferably, the signal testing method may further include: testing the duty cycle of the HRPWM signal using the duty cycle testing module 30. In this embodiment, this may specifically include the following steps:

[0092] The HRPWM signal is filtered by the filtering unit 31 to generate a voltage signal.

[0093] The voltage value of the voltage signal is detected by the voltage detection unit 32, and a voltage value signal is generated.

[0094] For the high-duty cycle signal HR-duty, its period is N2*Tck, the high level time is (M2+K2 / P2)*Tck, and the voltage value of the voltage signal is VDDP*(M2+K2 / P2) / N2, where VDDP is the high-level voltage value of the high-duty cycle signal HR-duty.

[0095] For the periodic high-precision signal HR-period, the voltage value of the voltage signal is VDDP*M1 / (N1+K1 / P1), where VDDP is the high-level voltage value of the periodic high-precision signal HR-period.

[0096] By appropriately adjusting the values ​​of M1 and N1, M2 and N2 and selecting a voltage detection unit 32 with appropriate precision, when K2=(1,2,3...P2-1), it is easy to make the voltage signal change step size much larger than the precision of the voltage detection unit 32. Based on the test voltage value of the voltage detection unit 32, the duty cycle of the HRPWM signal can be accurately obtained.

[0097] Preferably, the signal testing method may further include: controlling the multiplexer in the HRPWM module to output a high-precision period signal HR-period or a high-precision duty cycle signal HR-duty through the control module 40.

[0098] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0099] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0100] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0101] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0102] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0103] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A signal testing system for testing HRPWM signals, characterized in that, The signal testing system includes: The frequency divider module is used to divide the reference PWM signal based on the period of the HRPWM signal to generate a frequency divider signal; The arithmetic module, connected to the frequency divider module, is used to calculate the period ratio of the frequency divider signal to the HRPWM signal and generate the calculation result.

2. The signal testing system according to claim 1, characterized in that, The arithmetic module includes a first logic unit, a counting unit, and a reset unit. The first logic unit is connected to the frequency division module to perform logical operations on the HRPWM signal and the frequency division signal to generate a first logic signal. The reset unit is connected to the frequency division module to generate a reset signal based on the frequency division signal. The counting unit is connected to the first logic unit and the reset unit to count the first logic signal to generate a counting signal representing the operation result, and to control the reset based on the reset signal.

3. The signal testing system according to claim 2, characterized in that, The first logic unit includes an AND gate, the first input of which is used to receive an HRPWM signal, the second input of which is connected to a frequency divider module to receive a frequency divider signal, and the output of which is used to generate a first logic signal.

4. The signal testing system according to claim 2, characterized in that, The reset unit includes a first delay unit and a second logic unit. The first delay unit is connected to the frequency division module to delay the frequency division signal once to generate a first delay signal and delay the frequency division signal twice to generate a second delay signal. The second logic unit is connected to the first delay unit to perform logical operations on the first delay signal and the second delay signal to generate a reset signal.

5. The signal testing system according to claim 4, characterized in that, The second logic unit includes a NOT gate and an OR gate. The NOT gate is connected to the first delay unit to NOT the second delay signal to generate a second delayed NOT signal. The first input of the OR gate is connected to the first delay unit to receive the first delayed signal. The second input of the OR gate is connected to the NOT gate to receive the second delayed NOT signal. The output of the OR gate is used to generate a reset signal.

6. The signal testing system according to claim 2, characterized in that, The arithmetic module also includes a latch unit, which is connected to the counting unit to latch the counting signal.

7. The signal testing system according to claim 6, characterized in that, The arithmetic module further includes a second delay unit, which is connected to the frequency division module to delay the frequency division signal. The first logic unit is connected to the second delay unit to perform logical operations on the delayed frequency division signal and the HRPWM signal to generate a first logic signal. The frequency division signal is also used to control the latch unit.

8. The signal testing system according to claim 1, characterized in that, The signal testing system also includes a duty cycle testing module, which is used to test the duty cycle of the HRPWM signal.

9. The signal testing system according to claim 8, characterized in that, The duty cycle test module includes a filtering unit and a voltage detection unit. The filtering unit is used to filter the HRPWM signal to generate a voltage signal. The voltage detection unit is connected to the filtering unit to detect the voltage value of the voltage signal and generate a voltage value signal.

10. A signal testing method, based on the signal testing system according to any one of claims 1 to 9, characterized in that, The signal testing method includes: The frequency divider module divides the reference PWM signal based on the period of the HRPWM signal to generate a frequency divider signal; The calculation module calculates the period ratio of the frequency division signal to the HRPWM signal and generates the calculation result.

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