Method, device, electronic equipment and computer program product for increasing information density of a translation lookaside buffer

Abstract

The application provides a method, device, electronic equipment and computer program product for increasing the storage information density of a translation lookaside buffer. In the method, when an address translation request of a first virtual address is received, a plurality of continuous address mapping data is obtained according to the first virtual address, each address mapping data containing a mapping relationship between a virtual address and a physical address; when the plurality of continuous address mapping data satisfies a preset merging condition, the plurality of continuous address mapping data is merged into one merged entry; the merged entry is stored in the translation lookaside buffer, and a target physical address corresponding to the first virtual address is returned to an address request unit according to the merged entry. Thus, by merging the plurality of continuous address mapping data into a single entry and sharing the same high-bit part, the storage density of the effective address mapping is significantly improved while keeping the physical capacity of the translation lookaside buffer unchanged.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of chips, and particularly relates to a method and device for increasing the storage information density of a translation lookaside buffer, an electronic device, and a computer program product. BACKGROUND

[0002] With the rapid development of high-performance computing, big data, and artificial intelligence applications, higher requirements are put forward for the memory access efficiency of a processor. A translation lookaside buffer (TLB) in a memory management unit (MMU) is a key component that determines the address translation efficiency, and the capacity and efficiency of the TLB directly affect the overall performance of the system.

[0003] In related technologies, the TLB adopts a structure of storing a single address mapping in a single entry, and each entry independently stores complete high bits of a virtual address and high bits of a physical address. When there are continuous virtual address mappings in an address space, this structure causes a large amount of same high bit address information to be repeatedly stored in different entries, resulting in significant waste of storage space, limiting the improvement of the effective capacity of the TLB under limited chip area, and further affecting the processing performance of the system. SUMMARY

[0004] The embodiments of the application provide a method and device for increasing the storage information density of a translation lookaside buffer, an electronic device, and a computer program product, which can significantly improve the storage information density of the TLB.

[0005] A first aspect of the embodiments of the application provides a method for increasing the storage information density of a translation lookaside buffer, comprising: in a case where an address translation request of a first virtual address is received, obtaining a plurality of continuous address mapping data according to the first virtual address, wherein the request source corresponding to the first virtual address is an address request unit, and each address mapping data contains a mapping relationship between a virtual address and a physical address; in a case where the plurality of continuous address mapping data satisfy a preset merging condition, merging the plurality of continuous address mapping data into one merged entry, wherein the merged entry stores the same high bit part of the virtual address, the same high bit part of the physical address, and the address low bit part and the valid bit corresponding to each address mapping data in the plurality of continuous address mapping data, respectively; storing the merged entry into the translation lookaside buffer, and returning a target physical address corresponding to the first virtual address to the address request unit according to the merged entry.

[0006] In the technical solution of the application, the plurality of continuous address mapping data are merged into a single entry and the same high bit part is shared, so that the storage density of the effective address mapping is significantly improved while the physical capacity of the TLB remains unchanged.

[0007] Optionally, in a possible implementation manner of the first aspect, before the plurality of continuous address mapping data are merged into one merged entry under the condition that the plurality of continuous address mapping data satisfy the preset merging condition, the method further includes: determining a to-be-checked bit range of a virtual address (VA) and a physical address (PA) in the plurality of continuous address mapping data according to a page size corresponding to the address translation request; determining whether the high-order parts of all virtual addresses in the to-be-checked bit range are same and whether the high-order parts of all physical addresses in the to-be-checked bit range are same based on the plurality of continuous address mapping data; and determining that the plurality of continuous address mapping data satisfy the merging condition in a case that the high-order parts of all virtual addresses in the to-be-checked bit range are same and the high-order parts of all physical addresses in the to-be-checked bit range are same. In this way, by dynamically determining the to-be-checked bit range according to the page size and performing corresponding high-order part consistency verification, it is ensured that the merging operation can adapt to address mapping scenarios of different page specifications, and the generality and reliability of the scheme are improved.

[0008] Optionally, in another possible implementation manner of the first aspect, before the merged entry is stored into the translation bypass cache, the method further includes: sending the same virtual address high-order part and the same physical address high-order part in the merged entry to an address region buffer in the translation bypass cache, where the same virtual address high-order part and the same physical address high-order part in the address region buffer are associated with a set address region buffer identifier (ARB); and replacing the same virtual address high-order part and the same physical address high-order part in the merged entry with the address region buffer identifier. In this way, by introducing the address region buffer and replacing the storage of the actual high-order address value with the identifier, the storage space occupation of the merged entry is further compressed, and a two-level compression effect is achieved.

[0009] Optionally, in still another possible implementation manner of the first aspect, the method further includes: in a case that an address translation request of a second virtual address is received, the translation bypass cache is queried, and the merged entry is hit, reading the address region buffer identifier and the address high-order part corresponding to the second virtual address from the merged entry; acquiring the physical address high-order part corresponding to the address region buffer identifier from the address region buffer according to the address region buffer identifier; and obtaining the physical address corresponding to the second virtual address by combining the physical address high-order part and the address high-order part corresponding to the second virtual address. In this way, by using the ARB identifier to restore the complete physical address when the address translation is queried, the correct decoding and use of the compressed storage data are achieved while the query efficiency is maintained.

[0010] Optionally, in a further possible implementation of the first aspect, the storing the merged entry into the translation lookaside buffer comprises: extracting a bit sequence of a preset width from the first virtual address as an index; using the index to address a target set (SET) in the translation lookaside buffer; and storing the merged entry into the target set. In this way, by extracting a configurable bit-width sequence from the virtual address as an index, different TLB organization structures can be flexibly adapted, and efficient addressing and storage distribution of the merged entry in the TLB are ensured.

[0011] Optionally, in a further possible implementation of the first aspect, after the storing the merged entry into the translation lookaside buffer, the method further comprises: in a case where an address translation request of a third virtual address is received, reading a physical address corresponding to the third virtual address from the merged entry in the translation lookaside buffer, wherein the third virtual address is one of the remaining virtual addresses in the merged entry other than the first virtual address. In this way, by directly responding to a translation request of another virtual address in the entry after storing the merged entry, a mapping prefetch effect is achieved by using address space locality, and the delay of subsequent address translation is greatly reduced.

[0012] Optionally, in a further possible implementation of the first aspect, before the acquiring, in a case where an address translation request of a first virtual address is received, a plurality of continuous address mapping data according to the first virtual address, the method further comprises: configuring a capacity proportion of the translation lookaside buffer available for storing the merged entry; and dividing the translation lookaside buffer into a merged entry storage area according to the capacity proportion of the merged entry, wherein the merged entry storage area is used to perform merging and storing of the merged entry. In this way, by partitioning the TLB storage area and limiting the storage range of the merged entry, a flexible area and performance trade-off mechanism is provided in a hardware resource limited environment.

[0013] The second aspect of the embodiment of the present application provides a device for increasing storage information density of a translation lookaside buffer, comprising:

[0014] The acquiring module is configured to acquire, in a case where an address translation request of a first virtual address is received, a plurality of continuous address mapping data according to the first virtual address, wherein a request source corresponding to the first virtual address is an address request unit, and each address mapping data contains a mapping relationship between a virtual address and a physical address.

[0015] The merging module is configured to merge, in a case where the plurality of continuous address mapping data meet a preset merging condition, the plurality of continuous address mapping data into one merged entry, wherein the merged entry stores a same high-bit part of a virtual address, a same high-bit part of a physical address, and address low-bit parts and valid bits of each address mapping data respectively.

[0016] The processing module stores the merged entries in the translation bypass cache and returns the target physical address corresponding to the first virtual address to the address request unit based on the merged entries.

[0017] A third aspect of this application provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method of increasing the storage information density of the translation bypass cache described in the first aspect.

[0018] A fourth aspect of this application provides a computer program product that, when run on an electronic device, causes the electronic device to perform the method described in the first aspect for increasing the density of information stored in the translation bypass cache.

[0019] It is understood that the beneficial effects of the second to fourth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of a system architecture;

[0022] Figure 2 This is a schematic diagram of a basic TLB structure;

[0023] Figure 3 This is a diagram illustrating the mapping between virtual and physical addresses;

[0024] Figure 4 This is a schematic diagram of a system architecture provided in an embodiment of this application;

[0025] Figure 5 This is a flowchart illustrating a method for increasing the storage density of translation bypass cache information provided in an embodiment of this application;

[0026] Figure 6 This is a schematic diagram of virtual address and physical address mapping provided in an embodiment of this application;

[0027] Figure 7 This is a schematic diagram of the address region cache provided in an embodiment of this application;

[0028] Figure 8 This is a schematic diagram of the TLB structure provided in an embodiment of this application;

[0029] Figure 9 This is a comparison example diagram of the items provided in the embodiments of this application;

[0030] Figure 10 These are example diagrams of entries provided in the embodiments of this application;

[0031] Figure 11 This is a schematic diagram of a device for increasing the storage information density of a translation bypass cache, provided in an embodiment of this application.

[0032] Figure 12 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0033] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0034] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0035] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0036] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0037] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0038] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0039] It should be understood that the sequence number of each step in this embodiment does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of this application embodiment.

[0040] Figure 1 A schematic diagram of a system architecture is shown. (For example...) Figure 1 As shown, the system includes:

[0041] The Memory Management Unit (MMU) is a module inside the processor used to manage the translation of virtual addresses into physical addresses and to handle access requests that translate virtual addresses into physical addresses.

[0042] The Page Table Walk (PTW) unit is the module that performs the translation of virtual addresses into physical addresses.

[0043] Translation Bypass Cache (TLB) is a storage cache used to store the mapping relationship between virtual and physical addresses. Compared with page table traversal units, it can speed up the processing of address translation requests.

[0044] The Instruction Fetch Unit (IFU) is a module inside the processor that fetches instructions. Specifically, it is used to retrieve instructions from memory. In a typical system, accessing the instruction cache (ICache) within this unit requires obtaining the physical address, which will initiate a request to translate the virtual address into a physical address.

[0045] The instruction cache (ICache) is a storage unit used to store instructions. It is a small storage unit inside the processor that stores instructions. When accessing this component in a typical system, a mapping between virtual and physical addresses is required.

[0046] The Instruction Translation Lookaside Buffer (ITLB) is a storage unit used to store the mapping relationship between instruction virtual addresses and physical addresses. It is a smaller TLB than the Translation Lookaside Buffer (TLB) and is used only to store the mapping between instruction virtual addresses and instruction physical addresses.

[0047] The Load Store Unit (LSU) is used to execute load and store instructions. In a typical system, this unit needs to obtain a physical address to access the Data Translation Lookaside Buffer (DTLB), and will initiate a virtual translation of the physical address request.

[0048] Data cache (DCache) is a small storage unit inside the processor used to store data. In this typical system, accessing this component requires obtaining a mapping between virtual and physical addresses.

[0049] The Data Translation Bypass Cache (DTLB) is a storage unit used to store the mapping relationship between data virtual addresses and physical addresses. The LSU contains a smaller TLB than the Translation Bypass Cache (DTLB) and is used only to store the mapping between data virtual addresses and data physical addresses.

[0050] The Level 2 Cache (L2 Cache) is a larger cache from which the MMU requests addresses to translate the data it needs.

[0051] Taking the instruction side as an example, the address generation unit (VA generator) generates virtual addresses for accessing the ITLB and ICache. This ITLB is typically integrated within the instruction fetch unit, is relatively small, usually containing 32 to 128 entries, and is commonly referred to as the L1 ITLB in processor microarchitecture. Within a single clock cycle, the system executes two operations in parallel: firstly, it queries the ITLB; if the address matches, it outputs the corresponding physical address; secondly, it accesses the ICache to retrieve the stored physical address and corresponding instruction content. When the physical addresses obtained from the two operations match, the instruction output by the ICache is deemed valid and transmitted to the subsequent processing module.

[0052] When an ITLB lookup fails, the system sends an address translation request to the MMU. The MMU first queries its internal instruction and data shared TLB, a large cache typically containing over 2000 entries. If a physical address is successfully matched in this cache, the result is returned immediately; otherwise, the request is forwarded to the PTW to perform the complete address translation process. After completing the address translation, the PTW stores the newly generated address mapping in the TLB and returns the translated physical address to the original requester.

[0053] During address translation, the translation from virtual address to physical address is performed on a page-by-page basis. Taking a typical 4KB page as an example, the virtual address VA[47:12] is translated into the physical address PA[47:12], while the lower bits VA[11:0] are used as page offsets and do not participate in the translation process. The TLB uses a set-associative structure, whose structure is determined by the index bit width parameter n. When an address translation request arrives, the system uses the VA[n-1:12] bit field of the virtual address as the index to select the target SET. Each SET contains y roads. After determining the SET, the system reads all entries (Entries, the smallest storage unit for storing virtual and physical address mappings) of all WAYs within that SET in parallel, and determines whether a correct address mapping exists by comparing the VA[47:n] bit field with the address tags stored in each Entry. If a match exists, the corresponding physical address is returned; otherwise, the request is sent to the PTW to perform a complete address translation. The total TLB capacity is calculated using the following formula: One Entry, of which y represents the number of SETs, and y represents the number of WAYs contained in each SET.

[0054] Figure 2 A schematic diagram of a basic TLB structure is shown. Figure 2As shown, a specific example with n=3 and y=4 is used for illustration. The TLB contains 8 SETs (SET0-SET7), each SET is equipped with 4 WAYs (WAY0-WAY3), forming a storage structure with a total capacity of 32 address-mapped Entries. When the IFU or LSU initiates an address translation request, the virtual address it carries is divided into three parts: VA[14:12] as the index to select the SET, VA[47:15] as the tag to be compared with the tags stored in all Entries within the selected SET, and VA[11:0] as the page offset. For example, when the value of VA[14:12] is 000, SET0 is accessed; when the value is 001, SET1 is accessed; and so on for the other SETs. Each Entry stores a complete mapping relationship between a virtual address and a physical address. The specific simplified information stored includes: the virtual address tag of the VA[47:15] bit field, the physical address page number of the PA[47:12] bit field, and the valid status bit indicating whether the Entry is valid. Figure 3 A schematic diagram illustrating the mapping between virtual and physical addresses is shown. For example... Figure 3 The virtual address and physical address mapping shown is stored in the TLB location as follows: Figure 2 As shown, the simplified information stored in Entry0 is: VA0[47:15], PA0[47:12], Valid; the simplified information stored in Entry1 is: VA1[47:15], PA1[47:12], Valid; the simplified information stored in Entry2 is: VA2[47:15], PA2[47:12], Valid; and the simplified information stored in Entry3 is: VA3[47:15], PA3[47:12], Valid.

[0055] In related technologies, TLB uses a single-entry storage structure for a single address mapping, with each entry independently storing the complete high-order bits of the virtual address and the high-order bits of the physical address. When consecutive virtual address mappings occur in the address space, this structure leads to a large number of identical high-order address information being stored repeatedly in different entries, resulting in significant waste of storage space. This limits the improvement of the effective capacity of TLB within a limited chip area, thereby affecting system processing performance.

[0056] In view of this, embodiments of this application provide a method, apparatus, electronic device, and computer program product for increasing the storage information density of the translation bypass cache. First, upon receiving an address translation request for a first virtual address, multiple consecutive address mapping data are obtained based on the first virtual address. The request source corresponding to the first virtual address is an address request unit, and each address mapping data contains a mapping relationship between a virtual address and a physical address. Then, if the multiple consecutive address mapping data meet preset merging conditions, the multiple consecutive address mapping data are merged into a single merge entry. The merge entry stores the same high-order virtual address portion, the same high-order physical address portion, and the low-order address portion and valid bits corresponding to each address mapping data. Finally, the merge entry is stored in the translation bypass cache, and the target physical address corresponding to the first virtual address is returned to the address request unit based on the merge entry. Thus, by merging multiple consecutive address mapping data into a single entry and sharing the same high-order portion, the storage density of the effective address mapping is significantly improved while maintaining the TLB physical capacity unchanged.

[0057] To illustrate the technical solution of this application, specific embodiments are described below.

[0058] Figure 4 This is a schematic diagram of a system architecture provided in an embodiment of this application. For example... Figure 4 As shown, compared to Figure 1 In this embodiment of the system, a merge detection module is added to the second-level cache. This merge detection module is a control module used to detect the merging of virtual and physical addresses. Additionally, the system adds an instruction translation bypass cache area buffer (ITLB ARB), a data translation bypass cache area buffer (DTLB ARB), and a second-level translation bypass cache area buffer (L2TLB ARB), which are used to store the high-order bits of the virtual and physical addresses of the ITLB, DTLB, and L2 TLB, respectively.

[0059] In the above Figure 4 Based on the system architecture shown, Figure 5 A flowchart illustrating a method for increasing the storage information density of a translation bypass cache according to an embodiment of this application is shown. The following is a further explanation... Figure 5 The steps shown will be explained.

[0060] Step 501: Upon receiving an address translation request for the first virtual address, obtain multiple consecutive address mapping data based on the first virtual address.

[0061] The request source corresponding to the first virtual address is an address request unit, and each address mapping data contains a mapping relationship between a virtual address and a physical address. It should be understood that the number of address mapping data must conform to a power of 2, such as 2, 4, 8, etc.

[0062] In this embodiment, the address request unit refers to the functional module that initiates the address translation request, which can be an instruction fetch unit (IFU) or a load memory unit (LSU). When the address request unit issues a translation request for a first virtual address, the system obtains multiple consecutive address mapping data based on that virtual address. These address mapping data originate from the page table traversal process, and each address mapping data contains a complete correspondence between a virtual address and a physical address. These virtual addresses are arranged consecutively in the address space.

[0063] In one embodiment, when an IFU or LSU needs to translate a virtual address into a physical address (PA), it first accesses its respective L1 TLB (ITLB or DTLB). If the L1 TLB misses (i.e., no corresponding address mapping is found), the request is sent to the MMU. Upon receiving the request, the MMU checks the shared L2 TLB. If the L2 TLB hits, it directly returns the physical address; otherwise, it initiates a PTW (Physical Address Shift Warp) to retrieve the address mapping data from the L2 Cache. Then, the merge detection module intervenes and executes step 501.

[0064] It should be noted that when the merge detection module receives a 64-bit data request from the MMU, it will continuously retrieve N 64-bit data units from the second-level cache for the merge detection operation. The length of these 64-bit data units is specified by industry standards, and their structural characteristics are as follows: data storage areas of a specific format are accessed through virtual addresses, and the corresponding physical address information is encoded within these 64-bit data units. The final required physical address will be parsed and extracted from these 64-bit data units.

[0065] In one embodiment, before step 501 and before obtaining multiple consecutive address mapping data based on the first virtual address, the method further includes: configuring a proportion of the translation bypass cache available for storing merge entries; and dividing the translation bypass cache into a merge entry storage area based on the proportion of the merge entry capacity, wherein the merge entry storage area is used for subsequent merging and storage of merge entries. Thus, by partitioning the TLB storage area and limiting the storage range of merge entries, a flexible area and performance trade-off mechanism is provided in hardware resource-constrained environments.

[0066] It should be noted that in conventional implementations, the entire TLB can be designed to support a structure that supports merged entries. It should be understood that the embodiments of this application do not limit the proportion of merged entries in the overall TLB capacity; the TLB can contain a hybrid architecture of merged and non-merged entries. In practice, the number of merged entries can be configured as a specific proportion of the total number of TLB entries, such as a 50% capacity allocation scheme. This design reflects the technical trade-off between storage density optimization and hardware overhead: while merging four address mappings into one merged entry can improve storage efficiency, the merging operation introduces additional circuit area overhead, and different application scenarios have different access patterns for address mappings. It should also be understood that if the TLB contains only merged Entry formats, but there is actually a certain proportion of entries that cannot be merged, then these non-merged entries can only be placed in the merged Entries, resulting in some resource waste. Therefore, some designs fix the TLB in two formats to balance this situation. The TLB can be flexibly configured with a mixed proportion of storage schemes according to actual needs.

[0067] Step 502: If multiple consecutive address mapping data meet the preset merging conditions, merge the multiple consecutive address mapping data into a single merge entry.

[0068] The merged entry stores the same high-order virtual address portion, the same high-order physical address portion, and the low-order address portion and valid bits corresponding to each address mapping data in multiple consecutive address mapping data.

[0069] In this embodiment, after obtaining multiple consecutive address mapping data, the system checks whether these data meet preset merging conditions. The merging conditions mainly include: all virtual addresses have identical high-order bits, and all physical addresses have identical high-order bits. When these conditions are met, the system merges these address mapping data into a single merge entry. In this merge entry, the shared high-order bits of the virtual and physical addresses are stored only once, while the unique low-order bits and valid bits of each mapping data are stored separately, thus forming a compressed storage structure.

[0070] In one embodiment, when the L2 Cache receives a read data request for address translation, the merge detection module performs merge detection and merge operations on the page mapping. This process is performed synchronously during the address translation. In traditional schemes, the MMU only acquires 64 bits of data for a single address translation at a time; however, when using the method provided in this application embodiment to increase the storage density of the translation bypass cache, 256 bits of data are acquired at once during the translation process (taking four merges as an example), followed by merge condition detection. If the detection meets the merge condition, the data is organized according to a specific merge format and the merged page mapping result is returned. Finally, the MMU completes the actual page translation work and fills the merged page content back into the TLB / ITLB / DTLB. Through this merge mechanism that is completed synchronously during the translation process, the technical goal of storing multiple virtual address and physical address mapping relationships in a single Entry is achieved. Compared with the traditional technology that requires four independent translation operations, this application embodiment can acquire four address mapping relationships in one translation process.

[0071] In one embodiment, it is necessary to determine whether the merging conditions are met before merging. Specifically, based on the page size corresponding to the address translation request, the range of virtual and physical addresses to be checked in multiple consecutive address mapping data is determined; based on multiple consecutive address mapping data, it is determined whether the high-order bits of all virtual addresses within the range of the check bits are the same, and it is also determined whether the high-order bits of all physical addresses within the range of the check bits are the same; if the high-order bits of all virtual addresses and all physical addresses within the range of the check bits are the same, then the multiple consecutive address mapping data are determined to meet the merging conditions.

[0072] For example, see: Figure 6The diagram shows the virtual and physical address mapping. Before implementing the address mapping merging operation, the system first needs to determine the specific merging detection rules based on the page size parameters provided by the MMU. When the MMU issues a 4KB page request, the 4KB page merging detection process is initiated. Taking the merging configuration of N=4 as an example, the system needs to verify whether four consecutive address mapping data meet specific structural characteristics: the lowest two bits VA[13:12] of these mapped virtual addresses must present a continuous numerical arrangement (00, 01, 10, 11 in sequence), while the high bits VA[47:14] of all virtual addresses remain completely identical—this characteristic is guaranteed by the continuous address acquisition mechanism. In terms of physical address verification, the high bits PA[47:14] of all corresponding physical addresses must be detected as consistent, while the low bits PA[13:12] of the physical addresses are allowed to have arbitrary values ​​and are not required to maintain a specific order. Thus, by dynamically determining the range of bits to be checked based on the page size and performing corresponding high bit consistency verification, the merging operation can be adapted to address mapping scenarios with different page specifications, improving the versatility and reliability of the solution.

[0073] It should be understood that if the MMU sends a 2MB page request, a 2MB merge check is performed. The difference between the 2MB merge check and the 4KB merge check is that the check bits are different. The VA and PA addresses for the 2MB check are [47:21].

[0074] It should also be understood that the address size of the merged mapping can be any of the standard-supported address sizes, such as 4KB / 16KB / 2MB.

[0075] Step 503: Store the merged entry in the translation bypass cache, and return the target physical address corresponding to the first virtual address to the address request unit according to the merged entry.

[0076] In this embodiment, the system stores the generated merged entries in the translation bypass cache, thus updating the address mapping information. Simultaneously, based on the merged entries stored in the aforementioned embodiments, the system queries the target physical address corresponding to the first virtual address and returns this physical address to the address request unit that initially initiated the request, completing the processing flow of this address translation request.

[0077] It should be noted that, see, for example, Figure 7The diagram shown illustrates the address region caching. The high-order bits of the virtual address and the high-order bits of the physical address are stored in a buffer. This buffer is very small. Taking 16 entries as an example, each Entry stores one high-order bit of the address. Here, we take 47:30 as an address region as an example. The stored Entry corresponds to a fixed ID. This ID will eventually be stored in the TLB to reduce the number of VA and PA bits stored. The stored address does not distinguish between VA and PA. Different values ​​are stored in different Entry, and the ID obtained from the same address is consistent.

[0078] In one embodiment, before storing the merged entry in the translation bypass cache, the method further includes: sending the same high-order virtual address portion and the same high-order physical address portion of the merged entry to an address region buffer in the translation bypass cache, wherein the same high-order virtual address portion and the same high-order physical address portion in the address region buffer are associated with a defined address region buffer identifier (ARB); in the merged entry, the address region buffer identifier is used to replace the storage of the same high-order virtual address portion and the same high-order physical address portion. Thus, by introducing an address region buffer and replacing the actual high-order address value with an identifier, the storage space occupied by the merged entry is further compressed, achieving a two-stage compression effect.

[0079] In one embodiment, after introducing an address region buffer and replacing the actual high-order address value with an identifier, if an address translation request for the second virtual address is received, and the translation bypass cache is queried and a merge entry is hit, the address region buffer identifier and the address position part corresponding to the second virtual address are read from the merge entry. Based on the address region buffer identifier, the high-order part of the physical address corresponding to the address region buffer identifier is obtained from the address region buffer. Combining the high-order part of the physical address and the address position part corresponding to the second virtual address, the physical address corresponding to the second virtual address is obtained. Thus, by using the ARB identifier to restore the complete physical address during address translation query, the correct decoding and use of compressed storage data can be achieved while maintaining query efficiency.

[0080] It should be noted that, see, for example, Figure 8The diagram shows the TLB structure. After the merge detection module returns the merged data to the MMU, the MMU stores the high-order bits of the virtual address and the high-order bits of the physical address in the L2 ARB, and obtains the corresponding virtual address ARB ID and physical address ARB ID respectively. Taking a 4KB page as an example, the merged entry stored in the TLB specifically includes the following: ARB identifier, four low-order bits of the physical address PA0[13:12] to PA3[13:12], and four valid bits Valid0 to Valid3. Through this storage structure, the mapping relationship between the four virtual addresses and physical addresses is merged and stored in a single entry. The same mechanism is used for the processing of 2MB pages. After the system obtains the corresponding ARB identifier, it stores the merged result in the corresponding entry of the 2MB TLB. In addition, storing 4KB pages and 2MB pages separately can reduce the redundant information that needs to be stored in 2MB pages. For a detailed comparison of the entries, please refer to the diagram. Figure 9 The example diagram showing the comparison of the items is shown.

[0081] In this embodiment, under the same area budget, taking the merging of four address mapping data as an example, one entry can store the address mapping data that originally required four entries. With the addition of ARB technology, the average area required for each page address mapping is even lower.

[0082] For example, the traditional Entry bit width is 100, the 4KB TLB bit width with quad-packing and ARB technology is 77, and the Entry bit width of the 2MB TLB with quad-packing and ARB technology is 58. If quad-packing is fully implemented, the final average mapping bit width per 4KB page is 19.25, and the average mapping bit width per 2MB page is 14.5. Compared with the traditional 100 bit width, the area is greatly reduced (and the information density of storage is increased).

[0083] In one embodiment, a bit sequence of a preset width is extracted from the first virtual address as an index; the index is used to address and translate the target set (SET) in the bypass cache; and the merged entry is stored in the target set. Thus, by extracting a configurable bit-width sequence from the virtual address as an index, different TLB organizational structures can be flexibly adapted, ensuring efficient addressing and storage distribution of merged entries in the TLB. It should be understood that this application embodiment does not limit the specific structure of the TLB. For example, the number of WAYs, the number of bits in the index, or whether the L2 TLB itself distinguishes between instruction L2 TLB and data L2 TLB can all be determined based on the actual application scenario and requirements. Furthermore, this application embodiment does not limit whether the L2 TLB uses a paging structure, i.e., different pages have separate storage structures.

[0084] In this embodiment, during the data merging process, since there are partially identical address information in the four address mappings, the system merges and stores these identical address parts to achieve information compression. Specifically, the merged storage information includes: the shared high-order virtual address bits VA[47:17], the shared high-order physical address bits PA[47:14], the four independent low-order physical address bits PA0[13:12] to PA3[13:12], and the corresponding four valid bits Valid0 to Valid3. The shared virtual address bit segment VA[16:14] is used as an index for accessing the TLB. The adjustment of the index bit width stems from the characteristics of the merging technology. In the traditional TLB structure, the virtual address bit segment VA[13:12] serves as the index, while the merging technology stores these four consecutive mappings into a single Entry, allowing the two bits VA[13:12] to reflect differences within the Entry. To maintain the TLB organizational structure, a higher-order VA[16:14] needs to be selected as the new index. The choice of index bit width is configurable, and other bit fields such as VA[18:14] can also be used in actual implementations. In the traditional unmerged scheme, the system uses VA[14:12] as the index and stores VA[47:15] in the Entry for matching and comparison. In the merged scheme, the system uses VA[16:14] as the index and completes address matching by comparing the VA[47:17] and VA[13:12] of the accessed address with the corresponding bit fields stored in the Entry. Both schemes ultimately ensure that the accessed complete virtual address VA[47:12] is consistent with the stored address information. Different parameter choices only affect the specific storage location of the address mapping in the TLB, without changing the basis for the correctness of the address translation.

[0085] It should be noted that some identical virtual address fields are used as indexes. Since multiple Entries are merged into a single storage entry, the indexes corresponding to these Entries must remain consistent. In fact, the merged address structure contains three distinct parts: the first part is the field where differences are allowed; in the four-merge instance, this means the two least significant bits of the virtual address can be different; the second part is the identical address field assigned as an index; and the third part is the identical address field stored within the TLBEntry. The bit width of the index can be flexibly chosen according to design requirements, and different bit width values ​​will directly affect the overall capacity of the TLB. Regarding the basic principle of address matching, the TLB access mechanism requires that the virtual address used for querying must be completely consistent with the stored virtual address. For example, the TLB stores two sets of mapping relationships: VA0-PA0 and VA1-PA1. When the system initiates an address query again, only if the input address equals VA0 or VA1 can the corresponding physical address PA0 or PA1 be successfully obtained. This mechanism ensures the accuracy and reliability of the address translation results and is a fundamental condition for the normal operation of the TLB.

[0086] In one embodiment, the merge detection module can be located not only in the L2 cache, but also in the MMU or the DCache, depending on the specific requirements. For example, when the module is placed inside the MMU, its processing flow is basically the same as that of the L2 cache, the main difference being the transmission path from the source of unmerged data to the processing module: in this case, the unmerged data obtained from the L2 cache is directly transmitted to the merge detection module inside the MMU for processing, and the subsequent merge operation and data backfilling process remain unchanged. If the merge detection module is integrated into the DCache, its overall workflow is exactly the same as that of the L2 cache. In this case, the main difference between the DCache and the L2 cache lies in storage capacity and access speed: the DCache has a smaller storage capacity but a faster access speed, while the L2 cache provides a larger storage capacity but a relatively slower access speed. This different location setting reflects the comprehensive trade-off between performance indicators and timing requirements in the chip design process.

[0087] In this embodiment, after processing the address translation request, the system returns the merged data to the ITLB and DTLB respectively. During the data return process, the L2 ARB needs to be accessed to obtain the corresponding virtual address and physical address high-order information. After the data is returned to the ITLB or DTLB, this address high-order information will be re-stored in their respective independent ITLB ARB or DTLB ARB. These three ARBs (L2 ARB, ITLB ARB, and DTLB ARB) are completely independent in hardware structure. In specific execution, the system routes data according to the request source identifier: if the request comes from the ITLB, the merged data is returned to the ITLB; if the request comes from the DTLB, the data is returned to the DTLB. Each request contains a source ID identifying its initiator, and the MMU accurately determines the target object to which the data should be sent by identifying this source ID. An example diagram of the L1 ITLB and L1 DTLB entries is shown below. Figure 10 As shown.

[0088] In one embodiment, after storing the merge entry in the translation bypass cache, upon receiving an address translation request for a third virtual address, the physical address corresponding to the third virtual address can be read from the merge entry in the translation bypass cache. The third virtual address is one of the remaining virtual addresses within the merge entry, excluding the first virtual address. Therefore, by directly responding to translation requests for other virtual addresses within the entry after storing the merge entry, the mapping prefetching effect is achieved using address space locality, significantly reducing the latency of subsequent address translation.

[0089] It should be noted that in practice, only the first virtual address in the merged address mapping data is immediately needed by the current request. While the other three address mappings are not the target of this access, due to the spatial locality of memory access patterns in computer systems—that is, processors tend to access adjacent memory spaces within a short period—these prefetched address mappings have a high probability of being used in subsequent operations. By merging four address mappings into TLB entries during each address translation process, the system achieves pre-storage of address mappings. This mechanism leverages the principle of spatial locality to produce a prefetching effect, thereby significantly reducing the access latency in subsequent address translation processes.

[0090] The method for increasing the storage density of translation bypass cache disclosed in the above embodiments of this application firstly, upon receiving an address translation request for a first virtual address, obtains multiple consecutive address mapping data based on the first virtual address. The request source corresponding to the first virtual address is an address request unit, and each address mapping data contains a mapping relationship between a virtual address and a physical address. Then, if the multiple consecutive address mapping data meet preset merging conditions, they are merged into a single merge entry. This merge entry stores the same high-order virtual address portion, the same high-order physical address portion, and the low-order address portion and valid bits corresponding to each address mapping data. Finally, the merge entry is stored in the translation bypass cache, and the target physical address corresponding to the first virtual address is returned to the address request unit based on the merge entry. Thus, by merging multiple consecutive address mapping data into a single entry and sharing the same high-order portion, the storage density of effective address mapping is significantly improved while maintaining the TLB physical capacity.

[0091] See Figure 11 The diagram shows a structural schematic of a device for increasing the storage information density of a translation bypass cache according to an embodiment of this application. For ease of explanation, only the parts related to the embodiment of this application are shown.

[0092] The device for increasing the density of translation bypass cache storage information may specifically include the following modules:

[0093] The acquisition module 1101 is used to acquire multiple consecutive address mapping data based on the first virtual address when receiving an address translation request for the first virtual address. The request source corresponding to the first virtual address is an address request unit, and each address mapping data contains a mapping relationship between a virtual address and a physical address.

[0094] The merging module 1102 is used to merge multiple consecutive address mapping data into a single merge entry when multiple consecutive address mapping data meet preset merging conditions. The merge entry stores the same high-order virtual address portion, the same high-order physical address portion, and the low-order address portion and valid bit corresponding to each address mapping data in the multiple consecutive address mapping data.

[0095] The processing module 1103 is used to store the merged entries in the translation bypass cache and return the target physical address corresponding to the first virtual address to the address request unit according to the merged entries.

[0096] The apparatus for increasing the storage density of the translation bypass cache disclosed in the above embodiments of this application firstly, upon receiving an address translation request for a first virtual address, acquires multiple consecutive address mapping data based on the first virtual address. The request source corresponding to the first virtual address is an address request unit, and each address mapping data contains a mapping relationship between a virtual address and a physical address. Then, if the multiple consecutive address mapping data meet preset merging conditions, they are merged into a single merge entry. This merge entry stores the common high-order bits of the virtual address, the common high-order bits of the physical address, and the low-order bits and effective bits corresponding to each address mapping data. Finally, the merge entry is stored in the translation bypass cache, and the target physical address corresponding to the first virtual address is returned to the address request unit based on the merge entry. Thus, by merging multiple consecutive address mapping data into a single entry and sharing the same high-order bits, the storage density of the effective address mapping is significantly improved while maintaining the TLB physical capacity.

[0097] Furthermore, in one possible implementation of this application embodiment, the above-mentioned device for increasing the density of translation bypass cache storage information may further include the following modules:

[0098] The first determining module is used to determine the range of virtual and physical address bits to be checked in multiple consecutive address mapping data based on the page size corresponding to the address translation request.

[0099] The second determining module is used to determine, based on multiple consecutive address mapping data, whether the high-order bits of all virtual addresses are the same within the range to be checked, and whether the high-order bits of all physical addresses are the same within the range to be checked.

[0100] The third determining module is used to determine that multiple consecutive address mapping data satisfy the merging condition when all virtual addresses have the same high-order address portion within the range to be checked, and all physical addresses have the same high-order address portion within the range to be checked.

[0101] Therefore, by dynamically determining the range of bits to be checked based on the page size and performing corresponding high-order part consistency verification, the merging operation can be adapted to address mapping scenarios with different page specifications, thereby improving the versatility and reliability of the solution.

[0102] Furthermore, in another possible implementation of this application embodiment, the above-mentioned device for increasing the density of translation bypass cache storage information may further include the following modules:

[0103] The first sending module is used to send the same high-order virtual address portion and the same high-order physical address portion in the merged entry to the address region buffer in the translation bypass cache, wherein the same high-order virtual address portion and the same high-order physical address portion in the address region buffer are associated with a set address region buffer identifier.

[0104] The first processing module is used to replace the high-order part of the same virtual address and the high-order part of the same physical address with the address region buffer identifier in the merged entry.

[0105] Therefore, by introducing an address region buffer and using an identifier to replace the actual high-order address value, the storage space occupied by the merged entries can be further compressed, achieving a two-stage compression effect.

[0106] Furthermore, in another possible implementation of this application embodiment, the above-mentioned device for increasing the density of translation bypass cache storage information may further include the following modules:

[0107] The first acquisition module is used to read the address region buffer identifier and the address position part corresponding to the second virtual address from the merge entry when it receives the address translation request of the second virtual address, queries the translation bypass cache, and hits the merge entry.

[0108] The second acquisition module is used to obtain the high-order part of the physical address corresponding to the address region buffer identifier from the address region buffer based on the address region buffer identifier.

[0109] The second processing module is used to combine the high-order part of the physical address and the low-order part of the address corresponding to the second virtual address to obtain the physical address corresponding to the second virtual address.

[0110] Therefore, by using the ARB identifier to restore the complete physical address during address translation queries, the correct decoding and use of compressed storage data can be achieved while maintaining query efficiency.

[0111] Furthermore, in another possible implementation of this application embodiment, the above-mentioned processing module 1103 may specifically include the following units:

[0112] The third processing module is used to extract a bit sequence of a preset width from the first virtual address as an index.

[0113] The fourth processing module is used to translate target groups in the bypass cache using index addressing.

[0114] The first storage module is used to store merged entries into the target group.

[0115] Therefore, by extracting a configurable bit-width sequence from the virtual address as an index, different TLB organizational structures can be flexibly adapted to ensure efficient addressing and storage distribution of merged entries in the TLB.

[0116] Furthermore, in another possible implementation of this application embodiment, the above-mentioned device for increasing the density of translation bypass cache storage information may further include the following modules:

[0117] The third acquisition module is used to read the physical address corresponding to the third virtual address from the merge entry in the translation bypass cache when an address translation request for the third virtual address is received. The third virtual address is one of the other virtual addresses in the merge entry besides the first virtual address.

[0118] Therefore, by directly responding to translation requests from other virtual addresses within an entry after storing and merging entries, the mapping prefetching effect is achieved by leveraging address space locality, which greatly reduces the latency of subsequent address translation.

[0119] Furthermore, in another possible implementation of this application embodiment, the above-mentioned device for increasing the density of translation bypass cache storage information may further include the following modules:

[0120] The fifth processing module is used to configure the proportion of the translation bypass cache that can be used to store merged entries.

[0121] The sixth processing module is used to divide the translation bypass cache into a merged entry storage area according to the capacity ratio of the merged entries. The merged entry storage area is used to perform the merging and storage of merged entries.

[0122] Therefore, by partitioning the TLB storage area and limiting the storage range of merged entries, a flexible area and performance trade-off mechanism is provided in environments with limited hardware resources.

[0123] The device for increasing the density of translation bypass cache storage information provided in this application embodiment can be applied in the foregoing method embodiment. For details, please refer to the description of the above method embodiment, which will not be repeated here.

[0124] Figure 12 This is a schematic diagram of the structure of the electronic device provided in an embodiment of this application. For example... Figure 12 As shown, the electronic device 1200 of this embodiment includes: at least one processor 1210 ( Figure 12 The diagram shows only one processor, a memory 1220, and a computer program 1221 stored in the memory 1220 and executable on the at least one processor 1210. When the processor 1210 executes the computer program 1221, it implements the steps described above in the method embodiment for increasing the storage information density of the translation bypass cache.

[0125] The electronic device 1200 can be a desktop computer, laptop, handheld computer, cloud server, or other computing device. This electronic device may include, but is not limited to, a processor 1210 and a memory 1220. Those skilled in the art will understand that... Figure 12 This is merely an example of electronic device 1200 and does not constitute a limitation on electronic device 1200. It may include more or fewer components than shown, or combine certain components, or different components, such as input / output devices, network access devices, etc.

[0126] The processor 1210 may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0127] In some embodiments, the memory 1220 may be an internal storage unit of the electronic device 1200, such as a hard disk or memory of the electronic device 1200. In other embodiments, the memory 1220 may be an external storage device of the electronic device 1200, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the electronic device 1200. Furthermore, the memory 1220 may include both internal and external storage units of the electronic device 1200. The memory 1220 is used to store operating systems, applications, boot loaders, data, and other programs, such as the program code of computer programs. The memory 1220 can also be used to temporarily store data that has been output or will be output.

[0128] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0129] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0130] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0131] In the embodiments provided in this application, it should be understood that the disclosed devices / electronic devices and methods can be implemented in other ways. For example, the device / electronic device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings or direct couplings or communication connections may be through some interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0132] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0133] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0134] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0135] The implementation of all or part of the processes in the methods of the above embodiments can also be accomplished by a computer program product. When the computer program product is run on an electronic device, the electronic device can implement the steps in the various method embodiments described above.

[0136] The embodiments described above are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for increasing the information density of a translation bypass cache, applied to a system, characterized in that, The system includes a second-level cache, which contains a merge detection module. The method includes: Upon receiving an address translation request for a first virtual address, multiple consecutive address mapping data are obtained based on the first virtual address. The request source corresponding to the first virtual address is an address request unit, and each address mapping data contains a mapping relationship between a virtual address and a physical address. The multiple consecutive address mapping data are obtained by the merging detection module and merging condition detection is performed. If multiple consecutive address mapping data satisfy a preset merging condition, the multiple consecutive address mapping data are merged into a single merge entry. The merge entry stores the same high-order virtual address portion, the same high-order physical address portion, and the low-order address portion and valid bit corresponding to each of the multiple consecutive address mapping data. The preset merging condition includes: the low-order physical address portions of the multiple consecutive address mapping data are either consecutive or out of order. In the merged entry, the same high-order virtual address portion and the same high-order physical address portion are replaced by an address region buffer identifier, wherein the same high-order virtual address portion, the same high-order physical address portion and the address region buffer identifier are associatedly stored in the address region buffer corresponding to the translation bypass cache; The merged entry is stored in the translation bypass cache, and the target physical address corresponding to the first virtual address is returned to the address request unit according to the merged entry.

2. The method according to claim 1, characterized in that, Before merging the multiple consecutive address mapping data into a single merge entry when the multiple consecutive address mapping data meet the preset merging conditions, the method further includes: Based on the page size corresponding to the address translation request, determine the range of virtual and physical address bits to be checked in the multiple consecutive address mapping data; Based on the multiple consecutive address mapping data, it is determined whether the high-order bits of all virtual addresses are the same within the range to be checked, and it is also determined whether the high-order bits of all physical addresses are the same within the range to be checked. If all virtual addresses have the same high-order bits within the range to be checked, and all physical addresses have the same high-order bits within the range to be checked, then the plurality of consecutive address mapping data are determined to satisfy the merging condition.

3. The method according to claim 1, characterized in that, The method further includes: Upon receiving an address translation request for the second virtual address and querying the translation bypass cache, and finding a match in the merge entry, the address region buffer identifier and the address position portion corresponding to the second virtual address are read from the merge entry. Based on the address region buffer identifier, obtain the high-order part of the physical address corresponding to the address region buffer identifier from the address region buffer; By combining the high-order part of the physical address and the low-order part of the address corresponding to the second virtual address, the physical address corresponding to the second virtual address is obtained.

4. The method according to claim 1, characterized in that, The step of storing the merged entries in the translation bypass cache includes: From the first virtual address, extract a bit sequence of a preset width as an index; Use the index to address the target group in the translation bypass cache; The merged entries are stored in the target group.

5. The method according to claim 1, characterized in that, After storing the merged entry in the translation bypass cache, the method further includes: Upon receiving an address translation request for a third virtual address, the physical address corresponding to the third virtual address is read from the merge entry in the translation bypass cache, wherein the third virtual address is one of the other virtual addresses in the merge entry besides the first virtual address.

6. The method according to claim 1, characterized in that, Before obtaining multiple consecutive address mapping data based on the first virtual address upon receiving an address translation request for the first virtual address, the method further includes: Configure the proportion of the translation bypass cache that can be used to store merged entries; Based on the capacity ratio of the merged entries, the translation bypass cache is divided into a merged entry storage area, wherein the merged entry storage area is used to perform the merging and storage of the merged entries.

7. The method according to claim 1, characterized in that, The address request unit is either an instruction fetch unit or a load-store unit. The instruction fetch unit includes an instruction translation bypass cache area buffer, and the load-store unit includes a data translation bypass cache area buffer. After storing the merged entry in the translation bypass cache and returning the target physical address corresponding to the first virtual address to the address request unit according to the merged entry, the method further includes: When the request source of the first virtual address is an instruction fetching unit, the same high-order part of the virtual address and the same high-order part of the physical address are stored in the instruction translation bypass cache area buffer. When the request source of the first virtual address is a loading storage unit, the same high-order part of the virtual address and the same high-order part of the physical address are stored in the data translation bypass cache area buffer.

8. An apparatus for increasing the information density of a translation bypass cache, applied to a system, characterized in that, The system includes a second-level cache, which contains a merge detection module. The device includes: The acquisition module is used to acquire multiple consecutive address mapping data based on the first virtual address when an address translation request for the first virtual address is received. The request source corresponding to the first virtual address is an address request unit, and each address mapping data contains a mapping relationship between a virtual address and a physical address. The multiple consecutive address mapping data are acquired and merged under conditions by the merging detection module. A merging module is used to merge multiple consecutive address mapping data into a single merge entry when the multiple consecutive address mapping data meet preset merging conditions. The merge entry stores the same high-order virtual address portion, the same high-order physical address portion, and the low-order address portion and valid bit corresponding to each of the multiple consecutive address mapping data. The preset merging conditions include: the low-order physical address portions of the multiple consecutive address mapping data are either consecutive or out of order. The first processing module is used to replace the storage of the same high-order virtual address portion and the same high-order physical address portion in the merged entry with an address region buffer identifier, wherein the same high-order virtual address portion, the same high-order physical address portion and the address region buffer identifier are associatedly stored in the address region buffer corresponding to the translation bypass cache; The processing module is used to store the merged entry in the translation bypass cache, and return the target physical address corresponding to the first virtual address to the address request unit according to the merged entry.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method as described in any one of claims 1 to 7.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when run on an electronic device, causes the electronic device to perform the method as described in any one of claims 1 to 7.

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