Method and system for optimizing impedance of power distribution network of digital system

Abstract

The invention discloses a digital system power distribution network impedance optimization method and system, and the method comprises the following steps: S1, obtaining the frequency-varying parasitic parameters Jg (f), Jr (f) and Jz (f) of a digital system power supply through a vector network analyzer, and enabling f to be a frequency variable; s2, calculating a dynamic matching coefficient DsC based on the frequency-varying parasitic parameter, and calling a PDN decoupling scheme set from a decoupling scheme database according to a DsC matching interval; s3, inputting the PDN decoupling scheme set into ADS software for segmented variable step size impedance simulation, wherein the step size of the frequency band from 1 MHz to 100 MHz is 0.5 MHz, and the step size of the frequency band from 100 MHz to 3 GHz is 5 MHz; and generating a surface-mounted PCB decoupling index DI containing a resonance penalty term and a micro-system substrate decoupling index WI. According to the method, the high-frequency resonance suppression capability is improved, frequency change parasitic parameter extraction is combined with resonance point penalty term design, impedance peak fluctuation is compressed to be within + / -8% of a target value in a 1-3GHz frequency band, and actually measured power supply noise of a 10Gbps SerDes interface is reduced by 62%.

Description

Technical Field

[0001] This invention relates to the field of power distribution network technology, specifically to a method and system for optimizing the impedance of a power distribution network in a digital system. Background Technology

[0002] The information industry is a crucial driver of industrial development. With the continuous advancement of the electronics industry, the demands on the size, response speed, and other performance aspects of electronic products are constantly increasing. In recent years, the emergence of new packaging structures and processes, continuous progress in chip manufacturing technology, and the increasing integration within packages have made microsystems a new product form. Simultaneously, the development of microsystems also exhibits trends such as increased signal frequency, increased device integration, increased operating current, and decreased operating voltage. These trends place higher demands on power integrity (PI) design. Impedance simulation and optimization of power distribution networks (PDNs) are important aspects of power integrity design and play an increasingly vital role in substrate or PCB design.

[0003] Current digital system power distribution network (PDN) design faces two major technical bottlenecks:

[0004] Insufficient high-frequency resonance suppression: Traditional PDN decoupling schemes (such as CN 118228681 B) use a linear weighted impedance matching model. In the >500MHz frequency band, due to the failure to consider the parasitic parameter frequency-varying characteristics caused by skin effect and dielectric loss, the impedance curve has a significant resonance peak (typical peak value exceeds the standard by 40%), which causes high-speed chip power supply noise.

[0005] Heterogeneous integration space conflict: In the multi-level capacitor layout of microsystem substrates and mounting PCBs, high-density integration leads to insufficient wiring space on the microsystem substrate layer. Existing solutions (such as patent CN 118228681 B) only optimize a single level and do not establish a dynamic migration mechanism for cross-level capacitors, which forces small-sized capacitors to be stacked on the substrate layer, deteriorating the high-frequency decoupling effect;

[0006] Low convergence efficiency: The decoupling scheme relies on a static parameter library for matching, and cannot dynamically correct the matching rules based on the actual impedance simulation results. It requires multiple manual iterations (average time > 72 hours), which is difficult to meet the needs of rapid iteration. Summary of the Invention

[0007] The purpose of this invention is to provide a method and system for optimizing the impedance of a power distribution network in a digital system, so as to solve the problems mentioned in the background art.

[0008] To achieve the above objectives, the present invention provides the following technical solution: a method for optimizing the impedance of a power distribution network in a digital system, comprising the following steps:

[0009] S1. Use a vector network analyzer to obtain the frequency-varying parasitic parameters J of the digital system power supply. g (f), J r (f) and J z (f), where f is the frequency variable;

[0010] S2. Calculate the dynamic matching coefficient DsC based on the frequency-varying parasitic parameters, and retrieve the PDN decoupling scheme set from the decoupling scheme database according to the DsC matching interval.

[0011] S3. Input the PDN decoupling scheme set into ADS software for piecewise variable step size impedance simulation:

[0012] The frequency band from 1MHz to 100MHz has a step size of 0.5MHz, and the frequency band from 100MHz to 3GHz has a step size of 5MHz.

[0013] Generate the PCB decoupling index DI and the microsystem substrate decoupling index WI with resonance penalty terms;

[0014] S4. Integrate DI and WI to generate a collaborative gain-type PDN decoupling index PDQ, and select the scheme corresponding to the maximum PDQ as the benchmark PDN decoupling scheme.

[0015] S5. Based on the benchmark PDN decoupling scheme matching optimization scheme set, calculate the consistency constraint evaluation index (OSE) of each optimization scheme, and select the scheme corresponding to the maximum OSE as the optimal PDN decoupling scheme.

[0016] S6. When the capacitor layout area of ​​the microsystem substrate exceeds the threshold A, cross-level capacitor migration is triggered: capacitors with a capacitance value ≤100pF are migrated to the mounting PCB layer, and steps S3-S5 are executed again.

[0017] S7. If OSE does not reach the preset threshold TH, adjust the matching parameter CJ. g CJ r and CJ z And update the decoupling scheme database.

[0018] The formula for calculating the dynamic matching coefficient DsC in step S2 is as follows:

[0019]

[0020] Where x∈{g,r,z} corresponds to inductance, capacitance, and resistance, respectively, and CJ x The matching parameters are pre-stored in the decoupling scheme database, ΔDx is the allowable deviation value for matching the corresponding parameter, and α is the matching parameter. kAs a weighting factor, satisfying γk(f) is the frequency-varying weighting factor, calculated according to γ1(f) = 0.8 + 0.2·e -0.01f Dynamic adjustment.

[0021] The formula for calculating the PCB decoupling index (DI) in step S3 is as follows:

[0022]

[0023] Among them, PSZ ij PYZ represents the actual impedance value at frequency point (i,j). ij PQZ represents the required impedance value at frequency point (i,j). ij Z is the expected impedance value at the frequency point. peak,k Z represents the measured peak impedance at the k-th resonant point. target,k λ represents the target impedance value at the k-th resonant point, and λ≥0.5 is the resonance penalty factor.

[0024] The formula for calculating the PDQ metric of the cooperative gain-type PDN decoupling index in step S4 is as follows:

[0025] PDQ=v1·DI·WI+v2·min(DI,WI)

[0026] Where v1 and v2 are weighting factors, and v1+v2=1, min(DI,WI) means taking the minimum value of the two exponents to force performance balance.

[0027] The formula for calculating the Consistency Constraint Evaluation Index (OSE) in step S5 is as follows:

[0028]

[0029] Wherein, SOD is the decoupling index for optimized PCB mounting, MSO is the decoupling index for optimized microsystem substrate, β1 and β2 are weighting factors, satisfying β1+β2=1, and η≥0.1 is the cooperative deviation penalty coefficient.

[0030] The calculation of SOD and MSO must meet the following constraints:

[0031]

[0032] Among them, the difference rate of the two-level optimization is ≤15%.

[0033] The cross-stage capacitor migration in step S6 includes:

[0034] When the microsystem substrate layout area A micro >A th When, select from the set of values ​​{C1,C2,...,Cn} that satisfy C pCapacitors ≤100pF are moved to the surface mount PCB layer;

[0035] After migration, the microsystem substrate impedance curve needs to be regenerated and the MSO index updated.

[0036] A digital system power distribution network impedance optimization system, including:

[0037] The parasitic parameter extraction module is used to perform step S1;

[0038] The solution matching engine is used to execute step S2;

[0039] The co-simulation module is used to perform the segmented frequency scan and exponent generation in step S3;

[0040] The dynamic optimization decision-making module is used to perform the index calculation and scheme selection in steps S4-S5;

[0041] The scheme library update module is used to perform deviation detection and parameter correction in step S6.

[0042] Compared with the prior art, the beneficial effects of the present invention are:

[0043] This invention improves high-frequency resonance suppression capability: by extracting frequency-varying parasitic parameters and designing a resonant point penalty term, the impedance peak fluctuation is compressed to within ±8% of the target value in the 1–3 GHz band (compared to ±25% of the prior art). The measured power supply noise of the 10Gbps SerDes interface is reduced by 62%.

[0044] This invention features cross-level spatial resource collaborative optimization: a dynamic capacitance migration mechanism between the microsystem substrate and the PCB layer, releasing 35% of the wiring area of ​​the substrate layer, while ensuring balanced decoupling performance through a collaborative gain model (product plus minimum constraint), improving the system-level impedance compliance rate to 98%.

[0045] This invention achieves a breakthrough in design efficiency: based on the closed-loop parameter update of the consistency constraint evaluation index, it realizes the self-optimization and convergence of the scheme, reduces the number of manual interventions to zero, and shortens the overall design cycle to 4 hours;

[0046] The system stability of this invention is significantly enhanced: the forced constraint with a two-level difference rate of ≤15% avoids local over-optimization, and the impedance offset is <5% in the temperature range of -40℃–125℃, meeting the automotive-grade reliability requirements;

[0047] This invention achieves a breakthrough in compatibility: the dynamic frequency-varying weighting factor is adapted to various power devices based on silicon, silicon carbide, and gallium nitride, enabling PDN optimization across process platforms without model reconstruction. Attached Figure Description

[0048] Figure 1 This is a schematic diagram of the process of the present invention;

[0049] Figure 2 This is a schematic diagram of the framework of the present invention. Detailed Implementation

[0050] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0051] Please see Figure 1-2 This invention provides a technical solution: a method for optimizing the impedance of a power distribution network in a digital system, comprising the following steps:

[0052] S1. Use a vector network analyzer to obtain the frequency-varying parasitic parameters J of the digital system power supply. g (f), J r (f) and J z (f), where f is the frequency variable;

[0053] S2. Calculate the dynamic matching coefficient DsC based on the frequency-varying parasitic parameters, and retrieve the PDN decoupling scheme set from the decoupling scheme database according to the DsC matching interval.

[0054] S3. Input the PDN decoupling scheme set into ADS software for piecewise variable step size impedance simulation:

[0055] The frequency band from 1MHz to 100MHz has a step size of 0.5MHz, and the frequency band from 100MHz to 3GHz has a step size of 5MHz.

[0056] Generate the PCB decoupling index DI and the microsystem substrate decoupling index WI with resonance penalty terms;

[0057] S4. Integrate DI and WI to generate a collaborative gain-type PDN decoupling index PDQ, and select the scheme corresponding to the maximum PDQ as the benchmark PDN decoupling scheme.

[0058] S5. Based on the benchmark PDN decoupling scheme matching optimization scheme set, calculate the consistency constraint evaluation index (OSE) of each optimization scheme, and select the scheme corresponding to the maximum OSE as the optimal PDN decoupling scheme.

[0059] S6. When the capacitor layout area of ​​the microsystem substrate exceeds the threshold A, cross-level capacitor migration is triggered: capacitors with a capacitance value ≤100pF are migrated to the mounting PCB layer, and steps S3-S5 are executed again.

[0060] S7. If OSE does not reach the preset threshold TH, adjust the matching parameter CJ.g CJ r and CJ z And update the decoupling scheme database.

[0061] The formula for calculating the dynamic matching coefficient DsC in step S2 is as follows:

[0062]

[0063] Where x∈{g,r,z} corresponds to inductance, capacitance, and resistance, respectively, and CJ x The matching parameters are pre-stored in the decoupling scheme database, ΔDx is the allowable deviation value for matching the corresponding parameter, and α is the matching parameter. k As a weighting factor, satisfying γk(f) is the frequency-varying weighting factor, calculated according to γ1(f) = 0.8 + 0.2·e -0.01f Dynamic adjustment.

[0064] The formula for calculating the PCB decoupling index (DI) in step S3 is as follows:

[0065]

[0066] Among them, PSZ ij PYZ represents the actual impedance value at frequency point (i,j). ij PQZ represents the required impedance value at frequency point (i,j). ij Z is the expected impedance value at the frequency point. peak,k Z represents the measured peak impedance at the k-th resonant point. target,k λ represents the target impedance value at the k-th resonant point, and λ≥0.5 is the resonance penalty factor.

[0067] The formula for calculating the PDQ metric of the cooperative gain-type PDN decoupling index in step S4 is as follows:

[0068] PDQ=v1·DI·WI+v2·min(DI,WI)

[0069] Where v1 and v2 are weighting factors, and v1+v2=1, min(DI,WI) means taking the minimum value of the two exponents to force performance balance.

[0070] The formula for calculating the Consistency Constraint Evaluation Index (OSE) in step S5 is as follows:

[0071]

[0072] Wherein, SOD is the decoupling index for optimized PCB mounting, MSO is the decoupling index for optimized microsystem substrate, β1 and β2 are weighting factors, satisfying β1+β2=1, and η≥0.1 is the cooperative deviation penalty coefficient.

[0073] The calculation of SOD and MSO must meet the following constraints:

[0074]

[0075] Among them, the difference rate of the two-level optimization is ≤15%.

[0076] The cross-stage capacitor migration in step S6 includes:

[0077] When the microsystem substrate layout area A micro >A th When, select from the set of values ​​{C1,C2,...,Cn} that satisfy C p Capacitors ≤100pF are moved to the surface mount PCB layer;

[0078] After migration, the microsystem substrate impedance curve needs to be regenerated and the MSO index updated.

[0079] A digital system power distribution network impedance optimization system, including:

[0080] The parasitic parameter extraction module is used to perform step S1;

[0081] The solution matching engine is used to execute step S2;

[0082] The co-simulation module is used to perform the segmented frequency scan and exponent generation in step S3;

[0083] The dynamic optimization decision-making module is used to perform the index calculation and scheme selection in steps S4-S5;

[0084] The scheme library update module is used to perform deviation detection and parameter correction in step S6.

[0085] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

Claims

1. A method of optimizing impedance of a power distribution network of a digital system, characterized by, The method comprises the following steps: S1, obtain the frequency-dependent parasitic parameters J of the digital system power supply using a vector network analyzer g (f), J r (f), J z (f), where f is the frequency variable; S2, calculating a dynamic matching coefficient DsC based on the frequency-varying parasitic parameter, and retrieving a PDN decoupling scheme set from a decoupling scheme database according to a DsC matching interval; S3, inputting the PDN decoupling scheme set into ADS software for segmented variable-step impedance simulation: 1MHz to 100MHz frequency band step is 0.5MHz, 100MHz to 3GHz frequency band step is 5MHz; generating a mounted PCB decoupling index DI containing a resonance penalty term and a microsystem substrate decoupling index WI; S4, generating a synergistic gain type PDN decoupling index PDQ by fusing DI and WI, and selecting a scheme corresponding to the maximum PDQ as a reference PDN decoupling scheme; S5, matching an optimization scheme set based on the reference PDN decoupling scheme, calculating a consistency constraint evaluation index OSE of each optimization scheme, and selecting a scheme corresponding to the maximum OSE as an optimal PDN decoupling scheme; S6, when the microsystem substrate capacitance layout area exceeds a threshold A, triggering cross-level capacitance migration: migrating the capacitance with a capacitance value ≤100pF to the mounted PCB layer, and re-executing steps S3-S5; S7, if the OSE does not reach the preset threshold TH, correct the matching parameter CJ g , CJ r and CJ z and update the decoupling scheme database.

2. The method of claim 1, wherein: The dynamic matching coefficient DsC calculation formula in the step S2 is: where x e {g, r, z} corresponds to inductance, capacitance and resistance, respectively, CJ x is the pre-stored matching parameter in the decoupling scheme database, ΔDx is the matching allowed deviation value of the corresponding parameter, α k is the weight factor, satisfying γk(f) is the frequency-variable weight factor, satisfying γ1(f) = 0.8 + 0.2·e -0.01f is dynamically adjusted.

3. The method for optimizing the impedance of a digital system power distribution network according to claim 1, characterized in that: The mounted PCB decoupling index DI calculation formula in the step S3 is: where PSZ ij is the actual impedance value at frequency point (i,j), PYZ ij is the required impedance value at frequency point (i,j), PQZ ij is the expected impedance value at frequency point, Z peak,k is the measured impedance peak value at the kth resonance point, Z target,k is the target impedance value at the kth resonance point, λ ≥ 0.5 is the resonance penalty factor.

4. The method of claim 1, wherein: The synergistic gain type PDN decoupling index PDQ calculation formula in the step S4 is: PDQ=v1·DI·WI+v2·min(DI,WI) Wherein, v1 and v2 are weight factors, and v1+v2=1, min(DI,WI) represents taking the minimum value of the two indexes to force performance balance.

5. The method of claim 1, wherein: The consistency constraint evaluation index OSE calculation formula in the step S5 is: ​ Wherein, SOD is a mounted PCB optimization decoupling index, MSO is a microsystem substrate optimization decoupling index, β1 and β2 are weight factors, and β1+β2=1, η≥0.1 is a synergistic deviation penalty coefficient.

6. The method of claim 1, wherein: The calculation of SOD and MSO needs to meet the constraint condition: Wherein, the double-level optimization difference rate ≤15%.

7. The method of claim 1, wherein: The cross-level capacitance migration in the step S6 comprises: ​ When the microsystem substrate layout area A micro A th When the microsystem substrate layout area A p ≤ 100 pF is migrated to the mounted PCB layer; After migration, the microsystem substrate impedance curve needs to be regenerated and the MSO index is updated.

8. A digital system power distribution network impedance optimization system applying the method of any of claims 1-7, characterized by, Comprise: A parasitic parameter extraction module for performing step S1; A scheme matching engine for performing step S2; A synergistic simulation module for performing segmented frequency scanning and index generation of step S3; A dynamic optimization decision module for performing index calculation and scheme selection of steps S4-S5; A scheme library updating module for performing deviation detection and parameter correction of step S6.

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