A fast capacitor voltage balancing method and device for a three-level NPC-DAB converter

Abstract

The application provides a kind of three-level NPC-DAB converter's fast capacitor voltage balancing method and device, its method includes: the upper capacitor voltage and lower capacitor voltage of NPC bridge arm are collected, whether to enter fast balancing mode is judged, if yes, then calculate power control degree;According to power control degree and current operating point parameter, calculate inductance current value, and according to inductance current value, the operation condition is classified;According to the classification of operation condition, calculate voltage balancing control degree;According to the classification of operation condition and capacitor voltage imbalance, determine the current balancing mode;In the start switch cycle and the closing switch cycle of fast balancing mode, according to power control degree and current operating point parameter, calculate the DC bias suppression degree of inductance current;From the above parameters, the phase shift ratio and duty cycle of each power switch driving signal are obtained, and the driving signal is sent into digital signal processor to drive three-level NPC-DAB converter to work.The application can improve the balancing speed of capacitor voltage in three-level NPC-DAB converter.

Description

Technical Field

[0001] This invention relates to the field of power electronic converter control technology, and in particular to a fast capacitor voltage balancing method and apparatus for a three-level NPC-DAB converter. Background Technology

[0002] In recent years, with the development of distributed energy sources such as distributed photovoltaic power generation and offshore wind power generation, DC power grids have been widely used as the power architecture for distributing distributed energy. Among them, multi-level dual active bridge converters have gradually replaced traditional two-level dual active bridge converters in DC power grid applications with higher voltage levels due to their higher voltage blocking capability and power density. Among them, the three-level neutral point-clamped dual active bridge (NPC-DAB) converter is considered one of the most competitive topologies due to its high integration and low control complexity.

[0003] In actual operation, non-ideal factors such as asymmetrical drive signals and mismatched capacitor values ​​can lead to voltage imbalances in the upper and lower capacitors of an NPC-DAB converter. Slight voltage imbalances can increase voltage stress on power devices and power losses. Severe voltage imbalances can directly damage the converter. Therefore, for the safe and reliable operation of the converter, capacitor voltages must be balanced as soon as possible. In practice, the voltages of the upper and lower capacitors in the NPC bridge arm can only be adjusted independently during the ±1 / 2 level switching state, i.e., during the neutral point current operation, and the voltage adjustment is positively correlated with the magnitude of the neutral point current. However, the neutral point current and inductor current overlap in the ±1 / 2 level switching state, and their amplitudes are relatively small under light loads.

[0004] Therefore, the balancing speed of conventional capacitor voltage balancing methods slows down significantly under light load conditions. In this case, the converter will operate in an unbalanced voltage state for an extended period, which significantly increases the risk of converter failure. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a fast capacitor voltage balancing method and apparatus for a three-level NPC-DAB converter, thereby improving the capacitor voltage balancing speed in the three-level NPC-DAB converter.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] In a first aspect, the present invention provides a fast capacitor voltage balancing method for a three-level NPC-DAB converter, comprising:

[0008] Step S1: Collect the upper capacitor voltage and lower capacitor voltage of the NPC bridge arm. Determine whether to enter the fast balancing mode based on the upper capacitor voltage and lower capacitor voltage. If yes, proceed to step S2.

[0009] Step S2: Calculate the power control degree D in the fast balancing mode. f ;

[0010] Step S3: Based on the power control degree D f Based on the current operating point parameters, calculate the inductor current value in the fast balancing mode, and classify the operating conditions according to the inductor current value;

[0011] Step S4: Calculate the voltage balance control degree D in the fast balancing mode according to the classification of the operating conditions. z ;

[0012] Step S5: Determine the current balancing mode based on the operating conditions and capacitor voltage imbalance.

[0013] Step S6: During the start-up and stop-down switching cycles of the fast balancing mode, according to the power control degree D... f Calculate the DC bias suppression degree d of the inductor current based on the current operating point parameters;

[0014] Step S7: Based on the power control degree D f The voltage balance control degree D z The DC bias suppression degree d and the current balance mode are used to obtain the shift ratio and duty cycle of each power switch drive signal, and the drive signal is sent to the pulse width modulation generator of the digital signal processor to drive the three-level NPC-DAB converter.

[0015] The beneficial effects of this invention are as follows: by judging the actual capacitor voltage imbalance condition and operating conditions, and applying different switching states, balanced control of the capacitor voltage can be achieved. Simultaneously, by applying a voltage balance control degree D... z By tracking the zero point of the inductor current and maximizing the neutral point current area, the capacitor voltage balancing speed of the three-level NPC-DAB converter under light load is greatly accelerated.

[0016] Optionally, step S2 includes:

[0017] Calculate the power control degree D in the fast balancing mode according to the power control degree formula. f The power control degree formula is:

[0018] ;

[0019] ;

[0020] In the formula, f s L is the switching frequency. eq P is the inductance value of the phase-shifting inductor. FBS Where is the transmission power, n is the intermediate transformer turns ratio, U1 is the converter input voltage, U2 is the converter output voltage, and T is the power transferred. h For half a switching cycle, U ab (t) is the primary-side full-bridge output voltage function, i L (t) is the inductor current function.

[0021] As described above, by designing the power control degree D f This ensures that the power transmitted during the rapid balancing process is consistent with the power transmitted in the steady state, thus maintaining the stability of the output voltage.

[0022] Optionally, the classification of operating conditions based on the inductor current value in step S3 includes the following:

[0023] Based on the polarity of the inductor current value at the initial time t0 and the next time t1 in the fast balancing mode, the operating conditions are divided into three categories, where i L (t0)<0 and i L The operating condition (t1)>0 is operating condition 1, i L (t0)<0 and i L The operating condition where (t1)<0 is condition 2, i L (t0)>0 and i L The operating condition with (t1)>0 is operating condition 3.

[0024] Optionally, in step S3, based on the power control degree D f The calculation of the inductor current value in the fast balancing mode, based on the current operating point parameters, includes the following:

[0025] According to the power control degree D f Using the current operating point parameters and inductor current value formula, calculate the inductor current value i at the initial time t0 in the fast balancing mode. L The inductor current values ​​i at (t0) and the next time t1 L (t1), the formula for the inductor current value is:

[0026] ;

[0027] In the formula, n is the turns ratio of the intermediate transformer, U2 is the output voltage of the converter, and f s L is the switching frequency. eq is the inductance value of the phase-shifting inductor, and k is the voltage transformation ratio.

[0028] Optionally, step S4 includes the following:

[0029] Based on the classification of operating conditions and the voltage balance control degree formula, calculate the voltage balance control degree D in the fast balancing mode. z The voltage balance control degree formula is:

[0030] ;

[0031] In the formula, k is the voltage transformation ratio.

[0032] Optionally, step S5 includes the following:

[0033] Based on three operating conditions and capacitor voltage imbalance, the current balancing mode is determined from six rapid balancing modes. The evaluation index for the capacitor voltage imbalance is the capacitor voltage difference ΔU. C The capacitor voltage difference ΔU C The voltage U of the upper capacitor c1 With lower capacitor voltage U c2 The difference, the six fast balancing modes include:

[0034] Operating condition is condition 1 and ΔU C <0 Fast Equilibrium Mode 1;

[0035] Operating condition is condition 1 and ΔU C Fast balancing mode two with >0;

[0036] Operating condition is condition 2 and ΔU C <0 Fast Equilibrium Mode 3;

[0037] Operating condition is condition 2 and ΔU C >0 Fast Equilibrium Mode 4;

[0038] Operating condition is condition 3 and ΔU C <0 Fast Equilibrium Mode Five;

[0039] Operating condition is condition 3 and ΔU C >0 Fast Balance Mode 6.

[0040] Optionally, in the six fast balancing modes of step S5, the driving signal Q... a1 With drive signal Q a3 Complementary conduction, driving signal Q a2 With drive signal Q a4 Complementary conduction, driving signal Q b1 With drive signal Q b3 Complementary conduction, driving signal Q b2 With drive signal Q b4If the drive signals are complementary and conducting, then the shift ratio α and duty cycle φ of the drive signals for the NPC full-bridge switch in fast balancing mode 1 are:

[0041] ;

[0042] In the formula, T h It is half a switching cycle;

[0043] In fast balancing mode 2, the drive signal shift ratio α and duty cycle φ of the NPC full-bridge switch are:

[0044] ;

[0045] In fast balancing mode 3, the drive signal shift ratio α and duty cycle φ of the NPC full-bridge switch are:

[0046] ;

[0047] In the fast balancing mode 4, the drive signal shift ratio α and duty cycle φ of the NPC full-bridge switch are:

[0048] ;

[0049] In fast balancing mode 5, the drive signal shift ratio α and duty cycle φ of the NPC full-bridge switch are:

[0050] ;

[0051] In fast balancing mode 6, the drive signal shift ratio α and duty cycle φ of the NPC full-bridge switch are:

[0052] .

[0053] Optionally, step S6 includes the following:

[0054] During the start-up and stop-down switching cycles of the fast balancing mode, according to the power control degree D f The DC bias suppression degree d of the inductor current is calculated using the current operating point parameters and the DC bias suppression degree formula. The DC bias suppression degree formula is as follows:

[0055] ;

[0056] In the formula, f s L is the switching frequency. eq i is the inductance value of the phase-shifting inductor. L_i U1 is the initial value of the inductor current at the start of the fast balancing mode, which is determined by the steady-state modulation strategy. U1 is the input voltage of the converter, and k is the voltage transformation ratio.

[0057] As described above, by applying the DC bias suppression degree d to the initial and final moments of the primary-side full-bridge drive signal, the peak inductor current during the start-up and shutdown cycles of the fast balancing method can be made the same as the peak current in other fast balancing modes. This avoids current overshoot caused by the converter switching between steady state and fast balancing state, thereby suppressing the DC bias of the inductor current.

[0058] Optionally, step S1 includes:

[0059] Collect the upper and lower capacitor voltages of the NPC bridge arm, and obtain the capacitor voltage difference ΔU based on the upper and lower capacitor voltages. C Determine the capacitor voltage difference ΔU C Is the absolute value greater than or equal to the voltage error threshold U? th If so, proceed to step S2 to enter the fast balancing mode; otherwise, enter the steady-state modulation mode.

[0060] In a second aspect, the present invention provides a fast capacitor voltage balancing device for a three-level NPC-DAB converter, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements a fast capacitor voltage balancing method for a three-level NPC-DAB converter according to the first aspect.

[0061] The technical effects of the fast capacitor voltage balancing device for a three-level NPC-DAB converter provided in the second aspect are described in the relevant description of the fast capacitor voltage balancing method for a three-level NPC-DAB converter provided in the first aspect. Attached Figure Description

[0062] Figure 1 This is a schematic diagram of the main process of a fast capacitor voltage balancing method for a three-level NPC-DAB converter according to an embodiment of the present invention.

[0063] Figure 2 This is the topology of the three-level NPC-DAB converter involved in the embodiments of the present invention.

[0064] Figure 3 This is a block diagram illustrating the principle of fast capacitor voltage balance control according to an embodiment of the present invention.

[0065] Figure 4 This is a schematic diagram of the six fast balancing modes involved in the embodiments of the present invention.

[0066] Figure 5 This is a schematic diagram illustrating the DC bias suppression of inductor current according to an embodiment of the present invention.

[0067] Figure 6The above are experimental waveforms of the capacitor voltage balancing process in an embodiment of the present invention.

[0068] Figure 7 The experimental waveforms for DC bias suppression of inductor current are shown in this embodiment of the invention.

[0069] Figure 8 This is a schematic diagram of the structure of a fast capacitor voltage balancing device for a three-level NPC-DAB converter according to an embodiment of the present invention.

[0070] Explanation of reference numerals in the attached figures:

[0071] 1: A fast capacitor voltage balancing device for a three-level NPC-DAB converter;

[0072] 2: Processor;

[0073] 3: Memory. Detailed Implementation

[0074] To better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present invention can be understood more clearly and thoroughly, and that the scope of the present invention can be fully conveyed to those skilled in the art.

[0075] Example 1

[0076] In existing technologies, under light load conditions, the capacitor voltage balancing speed of three-level NPC-DAB converters slows down significantly, severely increasing the risk of converter failure. This embodiment addresses this problem by judging the actual capacitor voltage imbalance conditions and operating conditions, applying different switching states, and applying a voltage balance control degree D. z Tracking the zero point of the inductor current improves the balancing speed of the capacitor voltage in a three-level NPC-DAB converter. See the discussion below for details.

[0077] Please refer to Figures 1 to 7 A fast capacitor voltage balancing method for a three-level NPC-DAB converter, comprising:

[0078] Step S1: Collect the upper and lower capacitor voltages of the NPC bridge arm. Determine whether to enter the fast balancing mode based on the upper and lower capacitor voltages. If so, proceed to step S2.

[0079] In this embodiment, step S1 includes:

[0080] Collect the upper and lower capacitor voltages of the NPC bridge arm, and obtain the capacitor voltage difference ΔU based on the upper and lower capacitor voltages.C Determine the capacitor voltage difference ΔU C Is the absolute value greater than or equal to the voltage error threshold U? th If so, proceed to step S2 to enter the fast balancing mode; otherwise, enter the steady-state modulation mode.

[0081] The topology of the three-level NPC-DAB converter involved in this embodiment is as follows: Figure 2 As shown, it includes a primary-side full-bridge H1, a high-frequency transformer, and a secondary-side full-bridge H2. The NPC bridge arm refers to the two capacitors in the primary-side full-bridge H1 that divide the DC input voltage U1, while also providing a stable neutral point voltage for the midpoint clamping structure of the NPC bridge arm.

[0082] Reference Figure 2 It can be seen that if |ΔU C |≥U th If the condition is met, the system enters a fast balancing mode; otherwise, it enters a steady-state modulation mode.

[0083] Step S2: Calculate the power control degree D in the fast balance mode. f .

[0084] In this embodiment, based on the U in the adopted modulation strategy ab (t) and i L (t) waveform, its transmission power P FBS It can be calculated that:

[0085] .

[0086] Therefore, refer to Figure 3 It can be seen that step S2 includes:

[0087] Calculate the power control degree D in the fast balancing mode according to the power control degree formula. f The power control degree formula is:

[0088] ;

[0089] ;

[0090] In the formula, f s L is the switching frequency. eq P is the inductance value of the phase-shifting inductor. FBS Where is the transmission power, n is the intermediate transformer turns ratio, U1 is the converter input voltage, U2 is the converter output voltage, and T is the power transferred. h For half a switching cycle, U ab (t) is the primary-side full-bridge output voltage function, i L (t) is the inductor current function.

[0091] Therefore, by designing the power control degree D f This ensures that the power transmitted during the rapid balancing process is consistent with the power transmitted in the steady state, thus maintaining the stability of the output voltage.

[0092] Step S3: Based on the power control degree D f Based on the current operating point parameters, calculate the inductor current value in the fast balancing mode, and classify the operating conditions according to the inductor current value.

[0093] In this embodiment, refer to Figure 3 It can be seen that step S3 includes the following:

[0094] According to power control degree D f Given the current operating point parameters and inductor current value formula, calculate the inductor current value i at the initial time t0 in the fast balancing mode. L The inductor current values ​​i at (t0) and the next time t1 L (t1), the formula for the inductor current value is:

[0095] ;

[0096] In the formula, n is the turns ratio of the intermediate transformer, U2 is the output voltage of the converter, and f s L is the switching frequency. eq is the inductance value of the phase-shifting inductor, and k is the voltage transformation ratio.

[0097] In this embodiment, k = U1 / nU2.

[0098] Based on the polarity of the inductor current value at the initial time t0 and the next time t1 in the fast balancing mode, the operating conditions are divided into three categories, among which, i L (t0)<0 and i L The operating condition (t1)>0 is operating condition 1, i L (t0)<0 and i L The operating condition where (t1)<0 is condition 2, i L (t0)>0 and i L The operating condition with (t1)>0 is operating condition 3.

[0099] Step S4: Calculate the voltage balance control degree D in the fast balancing mode according to the classification of operating conditions. z .

[0100] In this embodiment, refer to Figure 3 It can be seen that step S4 includes the following:

[0101] Based on the classification of operating conditions and the voltage balance control degree formula, calculate the voltage balance control degree D in the fast balancing mode. z The formula for voltage balance control degree is:

[0102] ;

[0103] In the formula, k is the voltage transformation ratio.

[0104] Step S5: Determine the current balancing mode based on the operating conditions and capacitor voltage imbalance.

[0105] In this embodiment, refer to Figure 3 and Figure 4 It can be seen that step S5 includes the following:

[0106] Based on three operating conditions and capacitor voltage imbalance, the current balancing mode is determined from six rapid balancing modes. The evaluation index for capacitor voltage imbalance is the capacitor voltage difference ΔU. C capacitor voltage difference ΔU C The voltage U of the upper capacitor c1 With lower capacitor voltage U c2 The difference. (Refer to...) Figure 3 It can be seen that the six fast balancing modes in this embodiment include:

[0107] Operating condition is condition 1 and ΔU C <0 Fast Equilibrium Mode 1;

[0108] Operating condition is condition 1 and ΔU C Fast balancing mode two with >0;

[0109] Operating condition is condition 2 and ΔU C <0 Fast Equilibrium Mode 3;

[0110] Operating condition is condition 2 and ΔU C >0 Fast Equilibrium Mode 4;

[0111] Operating condition is condition 3 and ΔU C <0 Fast Equilibrium Mode Five;

[0112] Operating condition is condition 3 and ΔU C >0 Fast Balance Mode 6.

[0113] Among them, the driving signal Q in the six fast balancing modes of step S5 a1 With drive signal Q a3 Complementary conduction, driving signal Q a2 With drive signal Q a4 Complementary conduction, driving signal Q b1 With drive signal Q b3 Complementary conduction, driving signal Q b2 With drive signal Q b4If the drive signals are complementary and conducting, then the shift ratio α and duty cycle φ of the drive signals for the NPC full-bridge switch in fast balancing mode 1 are:

[0114] ;

[0115] In the formula, T h It is half a switching cycle;

[0116] In fast balancing mode 2, the drive signal shift ratio α and duty cycle φ of the NPC full-bridge switch are:

[0117] ;

[0118] In fast balancing mode 3, the drive signal shift ratio α and duty cycle φ of the NPC full-bridge switch are:

[0119] ;

[0120] In the fast balancing mode 4, the drive signal shift ratio α and duty cycle φ of the NPC full-bridge switch are:

[0121] ;

[0122] In fast balancing mode 5, the drive signal shift ratio α and duty cycle φ of the NPC full-bridge switch are:

[0123] ;

[0124] In fast balancing mode 6, the drive signal shift ratio α and duty cycle φ of the NPC full-bridge switch are:

[0125] .

[0126] Step S6: During the start-up and stop-up switching cycles of the fast balancing mode, based on the power control degree D... f The DC bias suppression degree d of the inductor current is calculated based on the current operating point parameters.

[0127] In this embodiment, step S6 includes the following:

[0128] During the start-up and stop-up switching cycles in fast balancing mode, according to the power control degree D f The DC bias suppression degree d of the inductor current is calculated using the current operating point parameters and the DC bias suppression degree formula. The DC bias suppression degree formula is as follows:

[0129] ;

[0130] In the formula, f s L is the switching frequency. eq i is the inductance value of the phase-shifting inductor. L_iU1 is the initial value of the inductor current at the start of the fast balancing mode, which is determined by the steady-state modulation strategy. U1 is the input voltage of the converter, and k is the voltage transformation ratio.

[0131] By applying the DC bias suppression factor d to the initial and final moments of the primary-side full-bridge drive signal, the peak inductor current during the start-up and shutdown cycles of the fast balancing method can be made the same as the peak current in other fast balancing modes. This avoids current overshoot caused by the converter switching between steady-state and fast balancing states, thereby suppressing the DC bias of the inductor current.

[0132] Step S7: Based on the power control degree D f Voltage balance control degree D z The DC bias suppression degree d and the current balance mode are used to obtain the shift ratio and duty cycle of each power switch drive signal, and the drive signal is sent to the pulse width modulation generator of the digital signal processor to drive the three-level NPC-DAB converter.

[0133] In this embodiment, the ±1 / 2 level switching states used in the three-level NPC-DAB converter are shown in Table 1. The neutral point current i0 flows directly into the upper or lower capacitor, and its direction will change the capacitor voltage balance. State A can output the same voltage level as states D, B, and C, but will cause the neutral point current i0 to flow in opposite directions. Furthermore, the neutral point current i0 and the inductor current i... L In state-controlled AD converters, the amplitude is the same, but the polarity is different in different switching states.

[0134] Table 1. ±1 / 2 level switching states used in the three-level NPC-DAB converter

[0135]

[0136] Therefore, by judging the actual capacitor voltage imbalance conditions and operating conditions, and applying different switching states, capacitor voltage balance control can be achieved. Meanwhile, under light load, the inductor current and neutral point current are small, which will significantly slow down the capacitor voltage balancing speed of the converter. This can be addressed by using ±1 / 2 level switching states throughout the balanced mode and applying a voltage balance control degree D. z By tracking the zero point of the inductor current and maximizing the neutral point current area, the capacitor voltage balancing speed of the three-level NPC-DAB converter under light load is greatly accelerated.

[0137] Combination Figures 5 to 7 To understand the technical effects of this embodiment.

[0138] like Figure 5As shown in (a), when the fast balancing method is started, the converter transitions from a steady state to a switching state. In the switching state, the calculated DC bias suppression control degree d is applied, and the inductor current i is adjusted. L Waveform. This achieves the current peak value i in the switching state. L_p The current peak value is consistent with that in the fast equilibrium state, thus avoiding the current overshoot caused by the direct transition from steady state to fast equilibrium state.

[0139] like Figure 5 As shown in (b), when the fast balancing method is off, the converter transitions from the fast balancing state to the switching state. In the switching state, the calculated DC bias suppression control degree d is applied, and the inductor current i is adjusted. L Waveform. This achieves the current peak value i in the switching state. L_p The current peak value is consistent with that in the fast equilibrium state, thus avoiding the current overshoot caused by the direct transition from the fast equilibrium state to the steady state.

[0140] like Figure 6 As shown, under experimental conditions of input voltage 100V, output voltage 250V, capacitor voltage error 40V, capacitor value 470uF, switching frequency 20kHz, and transmission power 250W, the balancing time of this embodiment of the invention is 12.60ms, achieving rapid capacitor voltage balancing.

[0141] like Figure 7 As shown, this embodiment of the invention achieves suppression of DC bias in the inductor current during the rapid balancing of the capacitor voltage. The maximum inductor current is 8.83A, which is within the safe operating range.

[0142] In summary, this invention achieves rapid capacitor voltage balancing under light load conditions and also suppresses inductor current fluctuations during the balancing process.

[0143] Example 2

[0144] Please refer to Figure 8 A fast capacitor voltage balancing device 1 for a three-level NPC-DAB converter includes a memory 3, a processor 2, and a computer program stored in the memory 3 and executable on the processor 2. When the processor 2 executes the computer program, it implements the steps in Embodiment 1 above.

[0145] Since the systems / devices described in the above embodiments of the present invention are systems / devices used to implement the methods of the above embodiments of the present invention, those skilled in the art can understand the specific structure and modifications of the systems / devices based on the methods described in the above embodiments of the present invention, and therefore will not be repeated here. All systems / devices used in the methods of the above embodiments of the present invention fall within the scope of protection of the present invention.

[0146] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0147] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (devices), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, as well as combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions.

[0148] It should be noted that any reference numerals placed between parentheses in the claims should not be construed as limiting the claims. The word "comprising" does not exclude the presence of components or steps not listed in the claims. The word "a" or "an" preceding a component does not exclude the presence of a plurality of such components. The invention can be implemented by means of hardware comprising several different components and by means of a suitably programmed computer. In claims that enumerate several means, several of these means may be embodied by the same hardware. The use of the terms first, second, third, etc., is merely for convenience of expression and does not indicate any order. These terms can be understood as part of the component names.

[0149] Furthermore, it should be noted that in the description of this specification, the terms "one embodiment," "some embodiments," "embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0150] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the claims should be interpreted to include both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0151] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, then this invention should also include these modifications and variations.

Claims

1. A fast capacitor voltage balancing method for a three-level NPC-DAB converter, characterized in that, include: Step S1: Collect the upper capacitor voltage and lower capacitor voltage of the NPC bridge arm. Determine whether to enter the fast balancing mode based on the upper capacitor voltage and lower capacitor voltage. If yes, proceed to step S2. Step S2: Calculate the power control degree D in the fast balancing mode. f ,include: Calculate the power control degree D in the fast balancing mode according to the power control degree formula. f The power control degree formula is: ； ； In the formula, f s L is the switching frequency. eq P is the inductance value of the phase-shifting inductor. FBS Where is the transmission power, n is the intermediate transformer turns ratio, U1 is the converter input voltage, U2 is the converter output voltage, and T is the power transferred. h For half a switching cycle, U ab (t) is the primary-side full-bridge output voltage function, i L (t) is the inductor current function; Step S3: Based on the power control degree D f Based on the current operating point parameters, calculate the inductor current value in the fast balancing mode, and classify the operating conditions according to the inductor current value, including the following: According to the power control degree D f Using the current operating point parameters and inductor current value formula, calculate the inductor current value i at the initial time t0 in the fast balancing mode. L The inductor current values ​​i at (t0) and the next time t1 L (t1), the formula for the inductor current value is: ； In the formula, n is the turns ratio of the intermediate transformer, U2 is the output voltage of the converter, and f s L is the switching frequency. eq Where k is the inductance value of the phase-shifting inductor, and k is the voltage transformation ratio; Based on the polarity of the inductor current value at the initial time t0 and the next time t1 in the fast balancing mode, the operating conditions are divided into three categories, where i L (t0)<0 and i L The operating condition (t1)>0 is operating condition 1, i L (t0)<0 and i L The operating condition where (t1)<0 is condition 2, i L (t0)>0 and i L The operating condition with (t1)>0 is operating condition 3; Step S4: Calculate the voltage balance control degree D in the fast balancing mode according to the classification of the operating conditions. z Including the following: Based on the classification of operating conditions and the voltage balance control degree formula, calculate the voltage balance control degree D in the fast balancing mode. z The voltage balance control degree formula is: ； In the formula, k is the voltage transformation ratio; Step S5: Determine the current balancing mode based on the operating conditions and capacitor voltage imbalance, including: Based on the three operating conditions and the capacitor voltage imbalance, the current balance mode is determined. The evaluation index for the capacitor voltage imbalance is the capacitor voltage difference ΔU. C The capacitor voltage difference ΔU C The voltage U of the upper capacitor c1 With lower capacitor voltage U c2 The difference; Step S6: During the start-up and stop-down switching cycles of the fast balancing mode, according to the power control degree D... f Calculate the DC bias suppression degree d of the inductor current based on the current operating point parameters; Step S7: Based on the power control degree D f The voltage balance control degree D z The DC bias suppression degree d and the current balance mode are used to obtain the shift ratio and duty cycle of each power switch drive signal, and the drive signal is sent to the pulse width modulation generator of the digital signal processor to drive the three-level NPC-DAB converter.

2. The fast capacitor voltage balancing method for a three-level NPC-DAB converter according to claim 1, characterized in that, Determining the current balance mode includes the following: The current equilibrium mode is determined from six fast equilibrium modes, which include: Operating condition is condition 1 and ΔU C <0 Fast Equilibrium Mode 1; Operating condition is condition 1 and ΔU C Fast balancing mode two with >0; Operating condition is condition 2 and ΔU C <0 Fast Equilibrium Mode 3; Operating condition is condition 2 and ΔU C >0 Fast Equilibrium Mode 4; Operating condition is condition 3 and ΔU C <0 Fast Equilibrium Mode Five; Operating condition is condition 3 and ΔU C >0 Fast Balance Mode 6.

3. The fast capacitor voltage balancing method for a three-level NPC-DAB converter according to claim 2, characterized in that, The driving signal Q in the six fast balancing modes of step S5 a1 With drive signal Q a3 Complementary conduction, driving signal Q a2 With drive signal Q a4 Complementary conduction, driving signal Q b1 With drive signal Q b3 Complementary conduction, driving signal Q b2 With drive signal Q b4 If the drive signals are complementary and conducting, then the shift ratio α and duty cycle φ of the drive signals for the NPC full-bridge switch in fast balancing mode 1 are: ； In the formula, T h It is half a switching cycle; In fast balancing mode 2, the drive signal shift ratio α and duty cycle φ of the NPC full-bridge switch are: ； In fast balancing mode 3, the drive signal shift ratio α and duty cycle φ of the NPC full-bridge switch are: ； In the fast balancing mode 4, the drive signal shift ratio α and duty cycle φ of the NPC full-bridge switch are: ； In fast balancing mode 5, the drive signal shift ratio α and duty cycle φ of the NPC full-bridge switch are: ； In fast balancing mode 6, the drive signal shift ratio α and duty cycle φ of the NPC full-bridge switch are: 。 4. The fast capacitor voltage balancing method for a three-level NPC-DAB converter according to claim 1, characterized in that, Step S6 includes the following: During the start-up and stop-down switching cycles of the fast balancing mode, according to the power control degree D f The DC bias suppression degree d of the inductor current is calculated using the current operating point parameters and the DC bias suppression degree formula. The DC bias suppression degree formula is as follows: ； In the formula, f s L is the switching frequency. eq i is the inductance value of the phase-shifting inductor. L_i U1 is the initial value of the inductor current at the start of the fast balancing mode, which is determined by the steady-state modulation strategy. U1 is the input voltage of the converter, and k is the voltage transformation ratio.

5. A fast capacitor voltage balancing method for a three-level NPC-DAB converter according to any one of claims 1 to 4, characterized in that, Step S1 includes: Collect the upper and lower capacitor voltages of the NPC bridge arm, and obtain the capacitor voltage difference ΔU based on the upper and lower capacitor voltages. C Determine the capacitor voltage difference ΔU C Is the absolute value greater than or equal to the voltage error threshold U? th If so, proceed to step S2 to enter the fast balancing mode; otherwise, enter the steady-state modulation mode.

6. A fast capacitor voltage balancing device for a three-level NPC-DAB converter, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements a fast capacitor voltage balancing method for a three-level NPC-DAB converter as described in any one of claims 1 to 5.

Images