Parallel inverter system and synchronization method thereof

Abstract

The application relates to the field of parallel inverters and discloses a parallel inverter system and a synchronization method thereof. The synchronization method of the parallel inverter system comprises the following steps: a main inverter generates a synchronization signal and outputs the synchronization signal to a synchronization signal bus through a synchronization signal output port, wherein the synchronization signal is a PWM signal, and the synchronization signal cycle value is a preset output voltage cycle value; a slave inverter receives the synchronization signal from the synchronization signal bus through a synchronization signal receiving port, calculates an output voltage cycle reference according to a first preset jump edge of the synchronization signal, performs output voltage phase synchronization, and performs carrier synchronization according to a second preset jump edge of the synchronization signal. Thus, only a single synchronization signal line is used, the output voltage frequency, the phase synchronization and the carrier synchronization among multiple inverters can be realized, the interconnection wiring among the inverters can be simplified, the output voltage frequency, the phase synchronization and the carrier synchronization are time-multiplexed with the same synchronization signal, and time sequence conflicts can be avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of parallel inverters, in particular to a parallel inverter system and a synchronization method thereof. BACKGROUND

[0002] With the development of power electronics technology and the increasing complexity of energy application scenarios, the performance and system architecture of inverters, as the core equipment for converting DC power into AC power, are facing increasingly high requirements. Traditional single-machine high-power inverter solutions gradually show limitations in dealing with certain key application scenarios. Parallel inverter technology connects multiple standard power module inverters together in AC to supply power to a load or a power grid, thereby economically and flexibly achieving smooth expansion of the total system power.

[0003] In order to achieve excellent parallel machine performance, it is necessary to ensure that the output voltage amplitudes, frequencies, and phases of each single-machine inverter in the parallel machine system are synchronized, and at the same time, the circulating current between multiple inverters is suppressed. The prior art achieves synchronization of multiple inverters by adding two synchronization signals of power frequency and carrier wave between the inverters, wherein the power frequency synchronization is used to achieve synchronization of the frequency and phase of the inverter output, and the carrier wave synchronization is used to keep the PWM carrier phase consistent between multiple inverters, thereby suppressing the high-frequency circulating current between multiple inverters. In this way, the increase in the number of interconnections between modules will significantly increase the system complexity and potential failure risk. SUMMARY

[0004] Embodiments of the present application aim to provide a parallel inverter system and a synchronization method thereof, which can solve the problem of the large number of interconnections between modules in the existing parallel inverter system synchronization scheme, thereby significantly increasing the system complexity and potential failure risk.

[0005] To solve the above technical problems, a first aspect of the present application provides a synchronization method of a parallel inverter system, applied to a parallel inverter system, wherein the parallel inverter system comprises a master inverter and at least one slave inverter connected in parallel with the master inverter, and the master inverter and the slave inverter are connected in communication through a synchronization signal bus; the synchronization method comprises:

[0006] The master inverter generates a synchronization signal and outputs the synchronization signal to the synchronization signal bus through a synchronization signal output port, wherein the synchronization signal is a PWM signal (Pulse Width Modulation signal), and the synchronization signal period value is a preset output voltage period value;

[0007] The inverter receives the synchronization signal from the synchronization signal bus through the synchronization signal receiving port, calculates an output voltage period reference according to a first preset rising edge of the synchronization signal and performs output voltage phase synchronization according to the synchronization signal, and performs carrier synchronization according to a second preset rising edge of the synchronization signal.

[0008] Optionally, the main inverter generates the synchronization signal includes:

[0009] When the synchronization timer value of the main inverter is equal to zero, a first preset rising edge of the synchronization signal is generated.

[0010] When the synchronization timer value of the main inverter is equal to the synchronization pulse width of the current period, a second preset rising edge of the synchronization signal is generated, wherein the synchronization pulse width of the current period is calculated by taking the carrier timer count value of the main inverter when the synchronization timer value of the main inverter is equal to zero as a second count value, subtracting N times of the preset inverter carrier period value from the second count value, and taking the difference as the synchronization pulse width of the current period, wherein N is a positive integer less than the quotient of the synchronization signal period value divided by the preset inverter carrier period value.

[0011] Optionally, when the synchronization timer value of the main inverter is equal to zero, the first preset rising edge of the synchronization signal is generated, including:

[0012] When the synchronization timer value of the main inverter is equal to zero for the first time, the carrier timer count value of the main inverter at this time is recorded as a second count value, and a first preset rising edge of the synchronization signal is generated.

[0013] Optionally, when the synchronization timer value of the main inverter is equal to zero for the first time, the second count value is calculated by taking the carrier timer count value of the main inverter when the synchronization timer value of the main inverter is equal to zero in the last period as a first count value, dividing the sum of the synchronization signal period value and the first count value by the preset inverter carrier period value, and taking the remainder as the second count value.

[0014] Optionally, the output voltage period reference is calculated according to the first preset rising edge of the synchronization signal, including:

[0015] The interval time of the continuous first preset rising edge of the synchronization signal is captured, and the interval time is taken as the output voltage period reference.

[0016] Optionally, the output voltage phase synchronization is performed according to the first preset rising edge of the synchronization signal, including:

[0017] The first preset rising edge of the synchronization signal is phase-locked at the moment to realize the output voltage phase synchronization.

[0018] Optionally, the carrier synchronization according to the second preset rising edge of the synchronization signal comprises:

[0019] capturing the second preset rising edge of the synchronization signal, and recording the carrier timer count value of the slave inverter at this time;

[0020] judging whether the carrier timer count value of the slave inverter is zero;

[0021] if the carrier timer count value of the slave inverter is zero, completing the carrier synchronization;

[0022] if the carrier timer count value of the slave inverter is not zero, taking the carrier timer count value of the slave inverter as a carrier phase error of the slave inverter, multiplying the carrier phase error by a preset adjustment coefficient, and taking the product as a period adjustment amount;

[0023] judging whether the carrier phase error is greater than or equal to half of the preset inverter carrier period value;

[0024] if the carrier phase error is greater than or equal to half of the preset inverter carrier period value, taking the sum of the preset inverter carrier period value and the period adjustment amount as the carrier period of the slave inverter, and returning to the step of capturing the second preset rising edge of the synchronization signal;

[0025] if the carrier phase error is less than half of the preset inverter carrier period value, taking the difference between the preset inverter carrier period value and the period adjustment amount as the carrier period of the slave inverter, and returning to the step of capturing the second preset rising edge of the synchronization signal.

[0026] Optionally, before judging whether the carrier phase error is greater than or equal to half of the preset inverter carrier period value, the method further comprises:

[0027] judging whether the carrier phase error is less than or equal to a maximum adjustment step;

[0028] if the carrier phase error is less than or equal to the maximum adjustment step, performing the step of judging whether the carrier phase error is greater than or equal to half of the preset inverter carrier period value;

[0029] if the carrier phase error is greater than the maximum adjustment step, first taking the maximum adjustment step as the period adjustment amount, and then performing the step of judging whether the carrier phase error is greater than or equal to half of the preset inverter carrier period value.

[0030] Optionally, the first preset rising edge is a rising edge and the second preset rising edge is a falling edge, or the first preset rising edge is a falling edge and the second preset rising edge is a rising edge.

[0031] Accordingly, the second aspect of the present application also provides a parallel inverter system, which comprises a master inverter and at least one slave inverter connected in parallel with the master inverter, and the master inverter and the slave inverter are connected in communication through a synchronization signal bus, so as to realize the steps of the synchronization method of the parallel inverter system as described in the first aspect.

[0032] Compared with the prior art, the present application provides a parallel inverter system and a synchronization method thereof, wherein the synchronization method comprises the following steps: the master inverter generates a synchronization signal, and outputs the synchronization signal to a synchronization signal bus through a synchronization signal output port, wherein the synchronization signal is a PWM signal, and a synchronization signal period value is a preset output voltage period value; the slave inverter receives the synchronization signal from the synchronization signal bus through a synchronization signal receiving port, calculates an output voltage period reference according to a first preset jump edge of the synchronization signal, and performs output voltage phase synchronization, and performs carrier synchronization according to a second preset jump edge of the synchronization signal. Thus, only one synchronization signal line is used to realize the output voltage frequency, phase synchronization and carrier synchronization among multiple inverters, so as to simplify the interconnection wiring among the inverters, save the communication cost among the inverters, avoid the timing conflict by time-division multiplexing the same synchronization signal for the output voltage frequency, phase synchronization and carrier synchronization, and improve the reliability of the parallel inverter system. BRIEF DESCRIPTION OF DRAWINGS

[0033] One or more embodiments are illustrated by way of example in the figures that are part of this disclosure and which are illustrative, but not restrictive, of the embodiments, wherein elements having the same reference number designates like elements throughout the various figures, unless otherwise expressly provided for in the patent claim. The figures of the drawing are not to scale.

[0034] Figure 1 is a flowchart of a synchronization method of a parallel inverter system provided by the present application;

[0035] Figure 2 is a synchronization signal bus structure diagram of a parallel inverter system provided by the present application;

[0036] Figure 3 is a flowchart of a master inverter generating a synchronization signal provided by the present application;

[0037] Figure 4 is a principle diagram of a master inverter generating a synchronization signal provided by the present application;

[0038] Figure 5 is a principle diagram of a slave inverter output voltage frequency and phase synchronization provided by the present application;

[0039] Figure 6is a flowchart of a synchronization process from an inverter carrier provided by the present application;

[0040] Figure 7 is a flowchart of a synchronization process from an inverter carrier provided by the present application;

[0041] Figure 8 is a flowchart of a synchronization process from an inverter carrier provided by the present application;

[0042] Figure 9 is a structural diagram of a parallel inverter system provided by the present application. DETAILED DESCRIPTION

[0043] In order to facilitate the understanding of the present application, the present application will be described in more detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that when an element is described as "fixed to" another element, it can be directly on the other element or one or more intervening elements can be present therebetween. When an element is described as "connected to" another element, it can be directly connected to the other element or one or more intervening elements can be present therebetween. The terms "upper", "lower", "inner", "outer", "bottom", etc. used in the present specification indicate the orientation or positional relationship shown in the drawings and are only used for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", "third", etc. are only for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0044] Unless otherwise defined, all technical and scientific terms used in the present specification have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used in the specification of the present application are only for the purpose of describing the specific embodiments and are not intended to limit the present application. The term "and / or" used in the present specification includes any and all combinations of one or more related listed items.

[0045] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0046] In one embodiment, the present application provides a synchronization method of a parallel inverter system, applied to a parallel inverter system including a main inverter and at least one slave inverter connected in parallel with the main inverter, the main inverter and the slave inverter being communicatively connected through a synchronization signal bus SYN_BUS, as shown in Figure 1 , Figure 1is a flowchart of a synchronization method of a parallel inverter system provided by the present application, and the synchronization method comprises the following steps:

[0047] In step S1, the main inverter generates a synchronization signal PWMsyn, and outputs the synchronization signal PWMsyn to the synchronization signal bus SYN_BUS through a synchronization signal output port SYN_OUT, wherein the synchronization signal PWMsyn is a PWM signal, and a synchronization signal period value Tinv is a preset output voltage period value.

[0048] In step S2, the slave inverter receives the synchronization signal PWMsyn from the synchronization signal bus SYN_BUS through a synchronization signal receiving port SYN_CAP, calculates an output voltage period reference and performs output voltage phase synchronization according to a first preset jump edge of the synchronization signal, and performs carrier synchronization according to a second preset jump edge of the synchronization signal.

[0049] In the present embodiment, considering the problem in the prior art that the addition of two synchronization signals of power frequency and carrier between inverters leads to a large number of interconnections between modules, thereby significantly increasing the complexity of the system and the potential risk of failure, the present embodiment provides a synchronization method of a parallel inverter system, which generates a synchronization signal PWMsyn through a main inverter, and outputs the synchronization signal PWMsyn to a synchronization signal bus SYN_BUS through a synchronization signal output port SYN_OUT, wherein the synchronization signal PWMsyn is a PWM signal, and a synchronization signal period value Tinv is a preset output voltage period value; a slave inverter receives the synchronization signal PWMsyn from the synchronization signal bus SYN_BUS through a synchronization signal receiving port SYN_CAP, calculates an output voltage period reference and performs output voltage phase synchronization according to a first preset jump edge of the synchronization signal, and performs carrier synchronization according to a second preset jump edge of the synchronization signal. Thus, only a single synchronization signal line is used to realize the output voltage frequency, phase synchronization and carrier synchronization between multiple inverters, which can simplify the interconnection wiring between inverters, save the communication cost between inverters, and avoid timing conflicts by time-division multiplexing the output voltage frequency, phase synchronization and carrier synchronization of the same synchronization signal, thereby improving the reliability of the parallel inverter system.

[0050] The above steps will be described in detail below in combination with a specific embodiment.

[0051] In step S1, the main inverter generates a synchronization signal PWMsyn, and outputs the synchronization signal PWMsyn to the synchronization signal bus SYN_BUS through a synchronization signal output port SYN_OUT, wherein the synchronization signal PWMsyn is a PWM signal, and a synchronization signal period value Tinv is a preset output voltage period value.

[0052] Specifically, refer to Figure 2 , Figure 2 is a synchronization signal bus structure schematic diagram of a parallel inverter system provided by the application, wherein the parallel inverter system includes three parallel inverters INV1#, INV2# and INV3#, the 1# inverter is designated as a master inverter, and the 2# and 3# inverters are designated as slave inverters, and the master inverter outputs a synchronization signal PWMsyn to a synchronization signal bus SYN_BUS through a synchronization signal output port SYN_OUT. The synchronization signal period value Tinv is a preset output voltage period value. The synchronization signal PWMsyn is a PWM signal, a first preset rising edge of which contains output voltage phase information, and a second preset rising edge of which contains carrier phase information, so that the phase information of the two signals can be transmitted by using the rising and falling edges of the PWM form of the synchronization signal.

[0053] In step S2, the slave inverter receives the synchronization signal PWMsyn from the synchronization signal bus SYN_BUS through a synchronization signal receiving port SYN_CAP, calculates an output voltage period reference according to a first preset rising edge of the synchronization signal, performs output voltage phase synchronization, and performs carrier synchronization according to a second preset rising edge of the synchronization signal.

[0054] Specifically, refer to Figure 2 The slave inverter receives the synchronization signal PWMsyn from the synchronization signal bus SYN_BUS through a synchronization signal receiving port SYN_CAP, calculates an output voltage period reference according to a first preset rising edge of the synchronization signal, performs output voltage phase synchronization according to the first preset rising edge of the synchronization signal, and performs carrier synchronization according to a second preset rising edge of the synchronization signal. Thus, only a single synchronization signal line is used to realize output voltage frequency, phase synchronization and carrier synchronization among multiple inverters, the interconnection wiring among the inverters can be simplified, the communication cost among the inverters can be saved, and the output voltage frequency, phase synchronization and carrier synchronization are time-multiplexed in the same synchronization signal, so that timing conflicts can be avoided and the reliability of the parallel inverter system can be improved.

[0055] Optionally, the first preset rising edge is a rising edge and the second preset rising edge is a falling edge, or the first preset rising edge is a falling edge and the second preset rising edge is a rising edge.

[0056] Specifically, the first preset rising edge is a rising edge, and the second preset rising edge is a falling edge, that is, the synchronization signal PWMsyn is a high-level synchronization pulse between the first preset rising edge and the second preset rising edge, at this time, the rising edge of the synchronization signal PWMsyn contains the output voltage phase information, and the falling edge contains the carrier phase information, thus the phase information of the two signals can be transmitted by using the rising and falling edges of the same synchronization signal. Alternatively, the first preset rising edge is a falling edge, and the second preset rising edge is a rising edge, that is, the synchronization signal PWMsyn is a low-level synchronization pulse between the first preset rising edge and the second preset rising edge, at this time, the falling edge of the synchronization signal PWMsyn contains the output voltage phase information, and the rising edge contains the carrier phase information, and the phase information of the two signals can also be transmitted by using the rising and falling edges of the same synchronization signal.

[0057] In an embodiment, referring to Figure 3 , Figure 3 is a flowchart of a method for generating a synchronization signal by a main inverter provided by the present application, and the main inverter generates a synchronization signal PWMsyn, which specifically includes:

[0058] S101, generating a first preset rising edge of the synchronization signal PWMsyn when the synchronization timer value of the main inverter is equal to zero.

[0059] S102, generating a second preset rising edge of the synchronization signal PWMsyn when the synchronization timer value of the main inverter is equal to the synchronization pulse width Tpulse of the current period, wherein the calculation method of the synchronization pulse width Tpulse of the current period is as follows: taking the carrier timer count value of the main inverter when the synchronization timer value of the main inverter is equal to zero as a second count value T2, subtracting N times of the preset inverter carrier period value Tpwm from the second count value T2, and taking the obtained difference as the synchronization pulse width Tpulse of the current period, wherein N is a positive integer less than the quotient obtained by dividing the synchronization signal period value Tinv by the preset inverter carrier period value Tpwm.

[0060] In an embodiment, referring to Figure 4 , Figure 4is a principle diagram of generating a synchronization signal by a master inverter provided by the present application, wherein a first preset jump edge is a rising edge, a second preset jump edge is a falling edge, N equals to 2 is taken as an example for illustration, a dashed line is a synchronization timer value of the master inverter, a solid line is a carrier timer count value of the master inverter, and PWMsyn is the synchronization signal. Because a synchronization signal period value Tinv is a preset output voltage period value, when the synchronization timer value of the master inverter equals to the synchronization signal period value Tinv and is reset to zero, a rising edge of the synchronization signal PWMsyn is generated, which can not only transmit the preset output voltage period value to a slave inverter through continuous rising edges of the synchronization signal PWMsyn, but also make the slave inverter synchronize the output voltage phase of itself based on the phase of the output voltage of the master inverter at the rising edge time. The carrier timer count value of the master inverter when the synchronization timer value of the master inverter equals to zero in the current period is taken as a second count value T2, the preset inverter carrier period value Tpwm multiplied by 2 is subtracted from the second count value T2, and the obtained difference is taken as a synchronization pulse width Tpulse in the current period. When the synchronization timer value of the master inverter equals to the synchronization pulse width Tpulse in the current period, a falling edge of the synchronization signal PWMsyn is generated, which just corresponds to the second time when the carrier timer is reset to zero after the synchronization timer value of the master inverter is reset to zero. Therefore, whether the carrier phase of the slave inverter is synchronized with the master inverter can be judged according to whether the carrier timer count value of the slave inverter is zero at the falling edge time. If the carrier timer count value of the slave inverter is zero, the carrier phase of the slave inverter is synchronized with the master inverter. If the carrier timer count value of the slave inverter is not zero, the carrier of the slave inverter is adjusted so that the carrier timer count value of the slave inverter is zero at the falling edge time, and thus the carrier phase of the slave inverter is synchronized with the master inverter. In the embodiment, the high level interval of the synchronization signal PWMsyn is [0, Tpulse), and the low level interval is [Tpulse, Tinv). The value of N is determined by the falling edge of the synchronization signal PWMsyn and the time when the carrier timer is reset to zero for the first time after the synchronization timer value of the master inverter is reset to zero. For example, if the falling edge of the synchronization signal PWMsyn corresponds to the time when the carrier timer is reset to zero for the second time after the synchronization timer value of the master inverter is reset to zero, the value of N is 2. If the falling edge of the synchronization signal PWMsyn corresponds to the time when the carrier timer is reset to zero for the fifth time after the synchronization timer value of the master inverter is reset to zero, the value of N is 5.

[0061] In an embodiment, the first preset jump edge of the synchronization signal generated when the synchronization timer value of the master inverter equals to zero comprises:

[0062] When the synchronization timer value of the master inverter equals to zero for the first time, the carrier timer count value of the master inverter at this time is recorded as a second count value T2, and the first preset jump edge of the synchronization signal is generated.

[0063] In the embodiment, please refer to Figure 4When the synchronization timer value of the main inverter is equal to zero for the first time, the carrier timer count value of the main inverter at this time is recorded, and the carrier timer count value of the main inverter at this time is taken as the second count value T2, based on which the synchronization pulse width Tpulse of the first synchronization signal period is calculated.

[0064] In an embodiment, when the synchronization timer value of the main inverter is equal to zero for the first time, the second count value T2 is calculated as follows: the carrier timer count value of the main inverter at the time when the synchronization timer value of the main inverter is equal to zero in the previous period is taken as the first count value T1, and the sum of the synchronization signal period value Tinv and the first count value T1 is divided by the preset inverter carrier period value Tpwm, and the remainder is the second count value T2.

[0065] In the embodiment, please refer to Figure 4 When the synchronization timer value of the main inverter is equal to zero for the first time, the carrier timer count value of the main inverter at the time when the synchronization timer value of the main inverter is equal to zero in the previous period is taken as the first count value T1. For example, when the synchronization timer value of the main inverter is equal to zero for the second time, the carrier timer count value of the main inverter at the time when the synchronization timer value of the main inverter is equal to zero in the previous period (i.e. the first synchronization signal period) is taken as the first count value T1. The sum of the synchronization signal period value Tinv and the first count value T1 is divided by the preset inverter carrier period value Tpwm, and the remainder is the second count value T2. In this way, the second count value T2 of each synchronization signal period is calculated, based on which the synchronization pulse width Tpulse of each synchronization signal period is calculated.

[0066] In an embodiment, the output voltage period reference is calculated according to the first preset rising edge of the synchronization signal.

[0067] The interval time of the first preset rising edge of the synchronization signal PWMsyn is captured, and the interval time is taken as the output voltage period reference.

[0068] In the embodiment, please refer to Figure 5 , Figure 5is a schematic diagram of the principle of synchronizing the output voltage frequency and phase of the slave inverter provided by the present application, wherein the first preset jump edge is the rising edge and the second preset jump edge is the falling edge, the upper half is the synchronization signal PWMsyn captured from the slave inverter, and the lower half is the sine signal generated from the slave inverter according to the captured synchronization signal PWMsyn. Because the synchronization signal period value Tinv is the preset output voltage period value, the master inverter generates the rising edge of the synchronization signal PWMsyn when the synchronization timer value thereof is equal to the synchronization signal period value Tinv and is reset to zero, so the slave inverter can calculate the interval time of the continuous rising edges by capturing the continuous rising edges of the synchronization signal PWMsyn, and take the interval time as the output voltage period reference.

[0069] In an embodiment, the output voltage phase synchronization according to the first preset jump edge of the synchronization signal comprises:

[0070] Phase locking at the moment of the first preset jump edge of the synchronization signal to realize the output voltage phase synchronization.

[0071] In the embodiment, please refer to Figure 5 Because the synchronization signal period value Tinv is the preset output voltage period value, the master inverter generates the rising edge of the synchronization signal PWMsyn when the synchronization timer value thereof is equal to the synchronization signal period value Tinv and is reset to zero, so the slave inverter can synchronize the phase of the output voltage of the master inverter at the moment of the rising edge to synchronize the phase of the output voltage of the slave inverter.

[0072] In an embodiment, please refer to Figure 6 , Figure 6 is a flowchart of the carrier synchronization of the slave inverter provided by the present application, and the carrier synchronization according to the second preset jump edge of the synchronization signal comprises:

[0073] S201, capturing the second preset jump edge of the synchronization signal and recording the carrier timer count value Tcarry of the slave inverter at this moment;

[0074] S202, judging whether the carrier timer count value Tcarry of the slave inverter is zero;

[0075] S203, if the carrier timer count value Tcarry of the slave inverter is zero, completing the carrier synchronization;

[0076] S204, if the carrier timer count value Tcarry of the slave inverter is not zero, taking the carrier timer count value Tcarry of the slave inverter as the carrier phase error e of the slave inverter, multiplying the carrier phase error e by the preset adjustment coefficient Kp, and taking the product as the period adjustment amount ΔTadjust;

[0077] S205, determining whether the carrier phase error e is greater than or equal to half of the preset inverter carrier period value Tpwm;

[0078] S206, if the carrier phase error e is greater than or equal to half of the preset inverter carrier period value Tpwm, then taking the sum of the preset inverter carrier period value Tpwm and the period adjustment amount ATadjust as the carrier period Tprd of the slave inverter, and returning to the step of capturing the second preset jump edge of the synchronization signal;

[0079] S207, if the carrier phase error e is less than half of the preset inverter carrier period value Tpwm, then taking the difference between the preset inverter carrier period value Tpwm and the period adjustment amount ATadjust as the carrier period Tprd of the slave inverter, and returning to the step of capturing the second preset jump edge of the synchronization signal.

[0080] In this embodiment, please refer to Figure 4 Because the falling edge of the synchronization signal PWMsyn corresponds to the second zero-crossing moment of the carrier timer after the synchronization timer value of the master inverter is zeroed, the slave inverter can determine whether its carrier phase is synchronized with the master inverter according to whether the carrier timer count value of the slave inverter is zero at the falling edge moment of the synchronization signal PWMsyn. If the carrier timer count value is zero, the carrier phase of the slave inverter is synchronized with the master inverter. If the carrier timer count value is not zero, the carrier of the slave inverter is adjusted so that the carrier timer count value of the slave inverter is zero at the falling edge moment of the synchronization signal PWMsyn, and thus the carrier phase of the slave inverter is synchronized with the master inverter. The process of adjusting the carrier of the slave inverter is as follows: taking the carrier timer count value Tcarry of the slave inverter as the carrier phase error e of the slave inverter, multiplying the carrier phase error e by a preset adjustment coefficient Kp, taking the product as the period adjustment amount ATadjust, taking the sum of the preset inverter carrier period value Tpwm and the period adjustment amount ATadjust as the carrier period Tprd of the slave inverter when the carrier phase error e is greater than or equal to half of the preset inverter carrier period value Tpwm, and taking the difference between the preset inverter carrier period value Tpwm and the period adjustment amount ATadjust as the carrier period Tprd of the slave inverter when the carrier phase error e is less than half of the preset inverter carrier period value Tpwm. Thus, the carrier period Tprd of the slave inverter is gradually adjusted until the carrier timer count value Tcarry of the slave inverter is zero at the falling edge of the synchronization signal PWMsyn, and the carrier phase is synchronized. The value of the preset adjustment coefficient Kp can be determined according to an empirical value, a pre-calculated experimental value or an estimated value, and the specific value of the preset adjustment coefficient Kp is not limited in this embodiment.

[0081] For example, please refer to Figure 7 ,Figure 7 is a schematic diagram of a slave inverter carrier synchronization process provided by the present application, wherein a first preset jump edge is a rising edge and a second preset jump edge is a falling edge. In the figure, the first dashed line from the left represents that the carrier of the slave inverter is not synchronized with the carrier of the master inverter, and the second dashed line from the left represents that the master-slave inverter carrier synchronization is achieved through gradual dynamic adjustment of the carrier period of the slave inverter.

[0082] In an embodiment, refer to Figure 8 , Figure 8 is another schematic diagram of a slave inverter carrier synchronization process provided by the present application, and before determining whether the carrier phase error e is greater than or equal to half of the preset inverter carrier period value Tpwm, the method further comprises:

[0083] S208, determining whether the carrier phase error e is less than or equal to the maximum adjustment step ΔTmax;

[0084] S209, if the carrier phase error e is less than or equal to the maximum adjustment step ΔTmax, then performing the step of determining whether the carrier phase error e is greater than or equal to half of the preset inverter carrier period value Tpwm;

[0085] S210, if the carrier phase error e is greater than the maximum adjustment step ΔTmax, then first taking the maximum adjustment step ΔTmax as the period adjustment amount ΔTadjust, and then performing the step of determining whether the carrier phase error e is greater than or equal to half of the preset inverter carrier period value Tpwm.

[0086] In the embodiment, by setting the maximum adjustment step ΔTmax, when the carrier phase error e is greater than the maximum adjustment step ΔTmax, the maximum adjustment step ΔTmax is taken as the period adjustment amount ΔTadjust, so that the amplitude of each adjustment is not too large, and the parallel inverter system can be stably operated during the slave inverter carrier synchronization process.

[0087] In order to facilitate understanding of the above inventive concept of the present application, the following will be described in detail in combination with the accompanying Figures 1-8 For the sake of convenience, the synchronization method of the parallel inverter system of the present application will be described in more detail by taking the output voltage frequency of the parallel inverter system as 60 Hz, the inverter switching frequency as 10 kHz, and the time base clock frequency of the inverter master control unit as 10 MHz as examples. According to the output voltage frequency, the inverter switching frequency, and the time base clock frequency of the inverter master control unit, the inverter synchronization signal period value Tinv = 166667 (specifically 10 MHz / 60 Hz) and the preset inverter carrier period value Tpwm = 1000 (specifically 10 MHz / 10 kHz) are calculated.

[0088] The 1# inverter is designated as the master inverter of the parallel inverter system, and the rest of the inverters are designated as slave inverters. If the initial parameter T1=200, in order to prevent the interval time between the synchronization timer and the carrier timer from being too short to affect the capture of the slave inverter to the synchronization signal edge, the synchronization pulse width is defined as Tpulse=2Tpwm-Tx(Tx represents the corresponding carrier timer count value of the master inverter when the synchronization timer of the current period is zero), and the synchronization pulse width of the current period is Tpulse=1800 (specifically, 2Tpwm-Tx=2Tpwm-200). According to the formula Figure 4 It can be seen that the remainder of (Tinv+T1) / Tpwm is calculated, and T2=867 is calculated. The synchronization pulse width of the next period is Tpulse=1133 (specifically, 2Tpwm-T2=2Tpwm-867).

[0089] The specific process of generating the synchronization signal of the master inverter is as follows:

[0090] The master control unit of the INV1# inverter (master inverter) performs the following loop operation to generate the synchronization signal PWMsyn:

[0091] a. When the synchronization timer count of the master control unit is zero, control the synchronization signal output port SYN_OUT to output a high level.

[0092] b. When the count value of the synchronization timer reaches the pulse width value Tpulse (such as the initial value 1800) set in the current period, control the synchronization signal output port SYN_OUT to output a low level.

[0093] c. When the synchronization timer count is zero again, the following operations are performed simultaneously:

[0094] Control the synchronization signal output port SYN_OUT to output a high level again (i.e., start a new period), and update the pulse width: load the synchronization pulse width Tpulse (such as 1133) calculated in the next period as the pulse width value Tpulse used in the next period in step b.

[0095] d. Repeat steps a to c. Through this loop process, the 1# inverter continuously generates the synchronization signal PWMsyn with a period of Tinv (166667) and a dynamically updated pulse width of Tpulse (such as 1800, 1133,...).

[0096] The process of capturing the synchronization signal by the slave inverter is as follows:

[0097] Output voltage frequency and phase synchronization: the continuous rising edge of the synchronization signal PWMsyn captured from the inverter is calculated, and the interval time of the continuous rising edge (166667) is calculated. The period 60Hz can be obtained by dividing the interval time by the time base clock frequency of the master unit, and the rising edge time is phase-locked adjusted. When the phase-locked phase from the inverter and the rising edge phase of the synchronization signal have an error of 0, the output voltage phase synchronization is realized as shown in Figure 5 .

[0098] Carrier synchronization control: when the falling edge of the synchronization signal PWMsyn captured from the inverter is recorded, the carrier timer count value Tcarry from the inverter is defined, the carrier phase error e = Tcarry is calculated, the period adjustment amount ΔTadjust = Kp × e is calculated, and ΔTmax is defined as the maximum adjustment step ΔTmax. When Tcarry >= Tpwm / 2, the carrier period value Tprd from the inverter is Tpwm+ΔTadjust, and when Tcarry < Tpwm / 2, the carrier period value Tprd from the inverter is Tpwm-ΔTadjust. The carrier timer period value Tprd from the inverter is dynamically adjusted until Tcarry = 0, and the carrier phase synchronization is realized as shown in Figure 7 .

[0099] The synchronization method of the parallel type inverter system of the embodiment generates a synchronization signal PWMsyn through a master inverter, and outputs the synchronization signal PWMsyn to a synchronization signal bus SYN_BUS through a synchronization signal output port SYN_OUT. The synchronization signal PWMsyn is a PWM signal, and the synchronization signal period value Tinv is a preset output voltage period value. A slave inverter receives the synchronization signal PWMsyn from the synchronization signal bus SYN_BUS through a synchronization signal receiving port SYN_CAP, calculates an output voltage period reference according to a first preset jump edge of the synchronization signal, and performs output voltage phase synchronization. The carrier is synchronized according to a second preset jump edge of the synchronization signal. Thus, only one synchronization signal line is used to realize the output voltage frequency, phase synchronization and carrier synchronization among multiple inverters, which can simplify the interconnection wiring among inverters and save the communication cost among inverters. Moreover, the output voltage frequency, phase synchronization and carrier synchronization time-multiplex the same synchronization signal, which can avoid timing conflicts and improve the reliability of the parallel type inverter system.

[0100] Based on the same concept, in another embodiment, please refer to Figure 9 , Figure 9is a structural schematic diagram of a parallel inverter system provided by the present application, wherein the parallel inverter system 100 includes one main inverter 110 and two slave inverters 120, and the present application also provides a parallel inverter system 100 including a main inverter 110 and at least one slave inverter 120 connected in parallel with the main inverter, wherein the main inverter 110 and the slave inverter 120 are connected in communication through a synchronization signal bus SYN_BUS, and are used to implement the steps of the synchronization method of the parallel inverter system as described in the above embodiments.

[0101] In this embodiment, a parallel inverter system is provided, wherein the main inverter generates a synchronization signal PWMsyn, and outputs the synchronization signal PWMsyn to the synchronization signal bus SYN_BUS through a synchronization signal output port SYN_OUT, wherein the synchronization signal PWMsyn is a PWM signal, and the synchronization signal period value Tinv is a preset output voltage period value; the slave inverter receives the synchronization signal PWMsyn from the synchronization signal bus SYN_BUS through a synchronization signal receiving port SYN_CAP, calculates an output voltage period reference according to a first preset jump edge of the synchronization signal, and performs output voltage phase synchronization, and performs carrier synchronization according to a second preset jump edge of the synchronization signal. Thus, only one synchronization signal line is used to realize the output voltage frequency, phase synchronization and carrier synchronization among multiple inverters, the interconnection wiring among the inverters can be simplified, the communication cost among the inverters can be saved, and the output voltage frequency, phase synchronization and carrier synchronization are time-multiplexed with the same synchronization signal, so that the timing conflict can be avoided, and the reliability of the parallel inverter system is improved.

[0102] It should be noted that the parallel inverter system embodiments and the synchronization method of the parallel inverter system embodiments belong to the same concept, and the specific implementation process is described in the synchronization method of the parallel inverter system embodiments, and the technical features in the synchronization method of the parallel inverter system embodiments are all applicable in the above parallel inverter system embodiments, which will not be described here.

[0103] It should be noted that in this document, the terms "comprising", "comprising" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article or device including the element.

[0104] The above examples are only used to illustrate the technical solutions of the present application, but not to limit the present application; the technical features in the above examples or different examples can also be combined, the steps can be implemented in any order, and there are many other changes of different aspects of the present application as described above, which are not provided in details for simplicity; although the present application has been described in detail with reference to the foregoing examples, it should be understood by those of ordinary skill in the art that the technical solutions recorded in the foregoing examples can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A synchronization method for a parallel inverter system, characterized in that, The parallel inverter system includes a master inverter and at least one slave inverter connected in parallel with the master inverter. The master inverter and the slave inverter are communicatively connected via a synchronization signal bus. The synchronization method includes: The main inverter generates a synchronization signal and outputs the synchronization signal to the synchronization signal bus through the synchronization signal output port. The synchronization signal is a PWM signal, and the period value of the synchronization signal is a preset output voltage period value. The inverter receives the synchronization signal from the synchronization signal bus through the synchronization signal receiving port, calculates the output voltage period reference based on the first preset transition edge of the synchronization signal and performs output voltage phase synchronization, and performs carrier synchronization based on the second preset transition edge of the synchronization signal. The main inverter generates a synchronization signal including: When the synchronization timer value of the main inverter is equal to zero, the first preset transition edge of the synchronization signal is generated. When the synchronization timer value of the main inverter is equal to the synchronization pulse width of the current cycle, a second preset transition edge of the synchronization signal is generated. The synchronization pulse width of the current cycle is calculated as follows: when the synchronization timer value of the main inverter in the current cycle is equal to zero, its carrier timer count value is taken as the second count value. The second count value is subtracted from the preset inverter carrier cycle value by N times. The difference is taken as the synchronization pulse width of the current cycle. N is a positive integer less than the quotient obtained by dividing the synchronization signal cycle value by the preset inverter carrier cycle value.

2. The synchronization method according to claim 1, characterized in that, The first preset transition edge for generating the synchronization signal when the synchronization timer value of the main inverter is equal to zero includes: When the synchronization timer value of the main inverter is equal to zero for the first time, the carrier timer count value of the main inverter at this time is recorded as the second count value, and the first preset transition edge of the synchronization signal is generated.

3. The synchronization method according to claim 1, characterized in that, When the synchronization timer value of the main inverter is not equal to zero for the first time, the second count value is calculated as follows: take the carrier timer count value when the synchronization timer value of the main inverter in the previous cycle is equal to zero as the first count value, divide the sum of the synchronization signal period value and the first count value by the preset inverter carrier period value, and the remainder is the second count value.

4. The synchronization method according to any one of claims 1-3, characterized in that, The output voltage period reference calculated based on the first preset transition edge of the synchronization signal includes: The interval between consecutive first preset transition edges of the synchronization signal is captured, and the interval is used as the reference for the output voltage period.

5. The synchronization method according to any one of claims 1-3, characterized in that, The output voltage phase synchronization based on the first preset transition edge of the synchronization signal includes: Phase-locking is performed at the first preset transition edge of the synchronization signal to achieve phase synchronization of the output voltage.

6. The synchronization method according to any one of claims 1-3, characterized in that, The carrier synchronization based on the second preset transition edge of the synchronization signal includes: Capture the second preset transition edge of the synchronization signal and record the carrier timer count value from the inverter at this time; Determine whether the carrier timer count value of the slave inverter is zero; If the carrier timer count value of the slave inverter is zero, then carrier synchronization is complete; If the carrier timer count value of the slave inverter is not zero, then the carrier timer count value of the slave inverter is used as the carrier phase error of the slave inverter, the carrier phase error is multiplied by the preset adjustment coefficient, and the product is used as the periodic adjustment amount; Determine whether the carrier phase error is greater than or equal to half of the preset inverter carrier period value; If the carrier phase error is greater than or equal to half of the preset inverter carrier period value, then the sum of the preset inverter carrier period value and the period adjustment amount is taken as the carrier period of the slave inverter, and the process returns to the step of capturing the second preset transition edge of the synchronization signal. If the carrier phase error is less than half of the preset inverter carrier period value, then the difference between the preset inverter carrier period value and the period adjustment amount is taken as the carrier period of the slave inverter, and the process returns to the step of capturing the second preset transition edge of the synchronization signal.

7. The synchronization method according to claim 6, characterized in that, Before determining whether the carrier phase error is greater than or equal to half of the preset inverter carrier period value, the method further includes: Determine whether the carrier phase error is less than or equal to the maximum adjustment step size; If the carrier phase error is less than or equal to the maximum adjustment step size, then the step of determining whether the carrier phase error is greater than or equal to half of the preset inverter carrier period value is executed. If the carrier phase error is greater than the maximum adjustment step size, the maximum adjustment step size is first used as the period adjustment amount, and then the step of determining whether the carrier phase error is greater than or equal to half of the preset inverter carrier period value is executed.

8. The synchronization method according to any one of claims 1-3, characterized in that, The first preset transition edge is a rising edge and the second preset transition edge is a falling edge, or the first preset transition edge is a falling edge and the second preset transition edge is a rising edge.

9. A parallel inverter system, characterized in that, The parallel inverter system includes a master inverter and at least one slave inverter connected in parallel with the master inverter. The master inverter and the slave inverter are connected in communication via a synchronization signal bus to implement the synchronization method of the parallel inverter system as described in any one of claims 1-8.

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