Circuit unit, circuit arrangement and method for reducing switching loss of semiconductor switch

Abstract

The invention relates to a circuit unit, a circuit arrangement and a method for reducing switching losses of a semiconductor switch (T1), comprising a semiconductor switch (T1), an auxiliary switch (S1), a capacitor (C1) and a logic unit (10), a series circuit consisting of the auxiliary switch (S1) and the capacitor (C1) being connected in parallel to a load path of the semiconductor switch (T1), the logic unit (10) is configured to determine a current intensity of a current (IL) flowing along the load path and to be switched by the semiconductor switch (T1) in an on state of the semiconductor switch (T1), to close the auxiliary switch (S1) or to hold the auxiliary switch (S1) in a closed state before a switching-off process of the semiconductor switch (T1) if the determined current intensity is higher than a predefined current threshold value, and to switch off the auxiliary switch (S1) before the switching-off process of the semiconductor switch (T1). If the determined current intensity is not higher than the predefined current threshold value, the auxiliary switch (S1) is switched off or is kept in the switched-off state before the switching-off process of the semiconductor switch (T1).

Description

Technical Field

[0001] The present invention relates to a circuit unit, a circuit arrangement, and a method for reducing switching losses of semiconductor switches. Background Technology

[0002] Zero-voltage switching (ZVS) is a known method in the prior art, in which the semiconductor switch is always turned on when the voltage applied to the semiconductor switch is essentially zero in order to reduce switching losses.

[0003] Furthermore, it is known from the prior art that by connecting an external capacitor in parallel with the semiconductor switch, switching losses can be reduced under high current switching conditions via the semiconductor switch. Additionally, this method can reduce the du / dt of the semiconductor switch, thereby improving the electromagnetic compatibility (EMV) of circuits with one or more semiconductor switches. Summary of the Invention

[0004] According to a first aspect of the invention, a circuit unit for reducing switching losses of a semiconductor switch is proposed, wherein the circuit unit has a semiconductor switch, an auxiliary switch, a capacitor (which may be a single capacitor or a combination of multiple capacitors connected in parallel), and a logic unit.

[0005] For example, a semiconductor switch can be constructed as a single semiconductor switch or as a parallel circuit consisting of multiple semiconductor switches connected in parallel. Since a semiconductor switch is an actual switch used to block or conduct load current, it can also be considered as the main switch of a circuit unit.

[0006] The capacitor refers to the external capacitor connected to the semiconductor switch, and does not represent the internal capacitance of the semiconductor switch.

[0007] A series circuit consisting of an auxiliary switch and a capacitor is connected in parallel with the load path of the semiconductor switch. This does not explicitly preclude other electrical components (such as damping resistors) from being connected in parallel and / or in series with the capacitor.

[0008] The logic unit can be constructed as an integrated and / or discrete logic circuit, configured to determine the current intensity of the current flowing along the semiconductor switch load path through the semiconductor switch when the semiconductor switch is switched on. For example, the determination can be based on a measurement and / or estimation of the current to be switched through the semiconductor switch.

[0009] The logic unit can also be a subunit of the control unit and / or the drive unit, which is used to control the semiconductor switch.

[0010] According to the present invention, the logic unit is further configured to: if the calculated current intensity is higher than a predefined current threshold, then close the auxiliary switch or keep it in a closed state before the turn-off process of the semiconductor switch. According to the present invention, the logic unit is also configured to: if the calculated current intensity is not higher than a predefined current threshold, then open the auxiliary switch or keep it in an open state before the turn-off process of the semiconductor switch.

[0011] Depending on the configuration of the auxiliary switch and / or logic unit, it may be reasonable or necessary to operate the auxiliary switch by an auxiliary switch drive unit connected between the logic unit and the auxiliary switch, which converts the corresponding control signals provided by the logic unit for turning the auxiliary switch on and off into control signals suitable for the auxiliary switch.

[0012] The capacitance value and current threshold of the capacitor are preferably determined based on the expected range of the current switched by the semiconductor switch, so as to achieve the lowest possible total circuit unit loss when switching between high and low currents.

[0013] In an exemplary case, such as in a bidirectional charger where a circuit unit is used to switch a first current and a second current higher than the first current at different times, the capacitance value and current threshold of the capacitor can be advantageously designed to accommodate these expected currents.

[0014] Furthermore, the circuit unit of the present invention can be used in many other applications, such as switching power supplies and other applications different from this.

[0015] It should generally be noted that the current threshold can be constructed as an immutable or adjustable current threshold. In the latter case, the current threshold can be adjusted in an appropriate manner, for example, based on current boundary conditions (such as varying switching current).

[0016] In summary, the present invention has the following advantages: it can achieve low switching losses over a wide operating range. In particular, it can maintain low switching losses in the case of zero-voltage switching (or near-zero-voltage switching, in which there is a certain residual voltage before the switching process of the semiconductor switch), and can also achieve zero-voltage (or near-zero-voltage) switching at low currents (i.e., currents below the current threshold) by disconnecting the external capacitor at low currents.

[0017] The following shows a preferred extension of the present invention.

[0018] In a preferred embodiment of the invention, the semiconductor switch is configured as a power transistor and / or a Si, SiC, or GaN-based semiconductor switch and / or a MOSFET, HEMT, IGBT, JFET, FinFET, CAVET, or bipolar transistor. More preferably, the auxiliary switch is also configured as a semiconductor switch (e.g., in one of the previously mentioned types) and / or an electromechanical switch. The specific type of auxiliary switch is preferably determined based on the desired switching frequency and / or allowable space requirements and / or allowable cost and / or the current and / or voltage load capacity required by the auxiliary switch.

[0019] In another advantageous embodiment of the invention, the current threshold is an upper threshold of hysteresis, and the logic unit is configured to move the auxiliary switch from a closed state to an open state only when the current threshold is below the lower current threshold of hysteresis, which is less than the upper current threshold. This hysteresis is particularly advantageous for anticipating non-monotonic rising and / or falling currents switched by the semiconductor switch, to avoid undesirable back-and-forth switching between a capacitor-connected state and a capacitor-unconnected state when the current is near the threshold. In this way, instability and / or switching losses in the upper-level circuitry of the circuit unit can also be reduced or avoided. For example, the use of this hysteresis may be particularly advantageous when the circuit unit of the invention is used as part of a dual active bridge, a resonant converter, or other applications with similar load current characteristics. Alternatively or additionally, the circuit unit is configured to substantially determine the current intensity of the current switched by the semiconductor switch immediately before the turn-off process of the semiconductor switch begins, in this way, for example, for the aforementioned non-monotonic rising and / or falling currents switched by the semiconductor switch, undesirable back-and-forth switching between capacitor-connected and capacitor-unconnected states can also be reduced or avoided.

[0020] Particularly advantageous is that the capacitor is a first capacitor, and the circuit unit has at least one second capacitor. Depending on the requirements of the circuit unit of the invention and / or existing boundary conditions, the capacitance value of the second capacitor can be determined to be the same as or different from that of the first capacitor. Furthermore, the auxiliary switch is a first auxiliary switch, and the circuit unit has at least one second auxiliary switch. Additionally, the current threshold corresponds to the first current threshold. The series circuit consisting of the second auxiliary switch and the second capacitor is connected in parallel with the load path of the semiconductor switch. Based on this, the logic unit is configured to: if the determined current intensity is higher than a second predefined current threshold greater than the first current threshold, then close the second auxiliary switch or keep it closed before the semiconductor switch's turn-off process. The logic unit is also configured to: if the determined current intensity is not higher than the second predefined current threshold, then open the second auxiliary switch or keep it open before the semiconductor switch's turn-off process. In this way, the size of the capacitor connected in parallel with the semiconductor switch can be more precisely adapted to the currently present switching current. In other words, the second auxiliary switch and the second capacitor provide additional gradation for the parallel capacitance, thereby further reducing switching losses, especially under varying switching currents. Of particular advantage, this method allows for the provision of more auxiliary switches and corresponding capacitors, enabling finer grading or adjustment of the respective switching currents. It should be noted that the logic unit can also consist of multiple logic units, each capable of controlling one or more auxiliary switches.

[0021] Furthermore, the circuit unit is advantageously configured to determine the current intensity of the current switched by the semiconductor switch based on current measurements within the semiconductor switch (e.g., based on a shunt) and / or voltage measurements on the load path of the semiconductor switch and / or information provided from the outside (e.g., from a higher-level unit that sets and / or monitors the current to be switched, etc.) and / or the operating state of the circuit unit and / or the operating state of the higher-level circuit arrangement containing the circuit unit.

[0022] Particularly preferred is that the semiconductor switches and / or auxiliary switches and / or capacitors and / or logic units are constructed as integrated, particularly partially or fully monolithically integrated. For this purpose, the aforementioned components, or portions thereof, are located, for example, on separate chips, which form a module and / or are located on a single chip. Alternatively or additionally, a measuring unit for determining the current intensity of the current to be switched (e.g., measuring current and / or voltage and / or temperature, from which the current to be switched can be derived) and / or a first drive circuit for controlling the semiconductor switches and / or a second drive circuit for controlling the auxiliary switches are integrated with the circuit unit, particularly partially or fully monolithically integrated with the circuit unit.

[0023] In another advantageous embodiment of the invention, at least the semiconductor switch and the auxiliary switch are constructed on a substrate electrically isolated from each other. Alternatively or additionally, the capacitor is connected to the circuit unit in a low-inductance manner, so that the capacitance of the capacitor can function effectively within the relevant frequency range without being affected by connections with excessively high inductance. This is particularly advantageous when the capacitor is constructed as a discrete element, for example, electrically connected to the semiconductor switch and / or the auxiliary switch via bonding wires.

[0024] According to a second aspect of the invention, a circuit arrangement is proposed having at least one circuit unit according to the first aspect of the invention and a control unit, wherein the control unit is configured to connect the semiconductor switch of at least one circuit unit at zero voltage. The features, combinations of features, and resulting advantages are the same as those described in conjunction with the first aspect of the invention; therefore, to avoid repetition, reference is made to the above description.

[0025] In an advantageous embodiment of the circuit arrangement of the invention, the circuit arrangement is configured such that the turn-on loss of the semiconductor switch is determined based on the current and / or pre-set switching state of the auxiliary switch, and the auxiliary switch is configured in accordance with the current intensity determined when the semiconductor switch is turned off only if this does not exceed the predefined maximum permissible turn-on loss of the semiconductor switch. In this way, for example, it can be ensured that the overall balance of turn-on loss and turn-off loss is minimized by avoiding turning on or off the capacitor in a manner detrimental to turn-on loss.

[0026] According to a third aspect of the invention, a method for reducing switching losses in a semiconductor switch is provided, wherein the method comprises: a first step, when the semiconductor switch is in an on state, determining the current intensity of a current flowing along the load path of the semiconductor switch switched by the semiconductor switch; a second step, if the determined current intensity is higher than a predefined current threshold, closing an auxiliary switch or keeping it closed before the semiconductor switch is turned off, the auxiliary switch being connected in series with a capacitor and in parallel with the load path of the semiconductor switch; or if the determined current intensity is not higher than the predefined current threshold, opening the auxiliary switch or keeping it open before the semiconductor switch is turned off. The features, combinations of features, and resulting advantages are the same as those described in conjunction with the first and second aspects of the invention, and therefore, reference is made to the above description to avoid repetition. Attached Figure Description

[0027] Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In the drawings:

[0028] Figure 1 An exemplary first embodiment of a circuit arrangement according to the invention, having circuit units according to the invention, is shown;

[0029] Figure 2 A first exemplary embodiment of the partially integrated circuit unit of the present invention is shown;

[0030] Figure 3 A second exemplary embodiment of the partially integrated circuit unit of the present invention is shown; and

[0031] Figure 4 An exemplary second embodiment of the circuit arrangement according to the invention, having two circuit units of the invention, is shown. Detailed Implementation

[0032] Figure 1 An exemplary embodiment of a circuit arrangement according to the present invention, having circuit units, is shown, wherein the circuit arrangement includes a semiconductor switch T1 configured as a HEMT, a first auxiliary switch S1 configured as a semiconductor switch, a second auxiliary switch S2 configured as a semiconductor switch, a first capacitor C1, a second capacitor C2, a logic unit 10, a control unit 50, a first gate driver 30, and a second gate driver 35. Furthermore, the parasitic capacitances Cm, Cgs, and Cds of the semiconductor switch T1 are also shown.

[0033] The series circuit consisting of the first auxiliary switch S1 and the first capacitor C1, and the series circuit consisting of the second auxiliary switch S2 and the second capacitor C2 are respectively connected in parallel with the load path of the semiconductor switch T1.

[0034] The control unit 50 is configured to output a control signal to the first gate driver 30 for turning the semiconductor switch T1 on and off. Based on this, the gate driver 30 is configured to output a corresponding gate voltage to the gate of the semiconductor switch T1.

[0035] Logic unit 10, based on voltage measurement unit 20, is configured to determine the current intensity IL of the current flowing along the load path through semiconductor switch T1 when semiconductor switch T1 is switched on. For this purpose, logic unit 10 has information about the characteristic curve of semiconductor switch T1, and based on this, logic unit 10 is configured to convert the voltage value measured on the load path into the currently present load current IL. For example, the information about the characteristic curve is stored in a (not shown) memory unit, which is connected to logic unit 10 in an information technology aspect.

[0036] Based on this configuration, logic unit 10 is set to: if the calculated current intensity is higher than a predefined first current threshold, then close the first auxiliary switch S1 or keep it in the closed state before the turn-off process of semiconductor switch T1; if the calculated current intensity is not higher than the predefined current threshold, then open the first auxiliary switch S1 or keep it in the open state.

[0037] The logic unit 10 is further configured to: if the calculated current intensity is higher than a second predefined current threshold greater than the first current threshold, then close the second auxiliary switch S2 or keep it closed before the turn-off process of the semiconductor switch T1; if the calculated current intensity is not higher than the second predefined current threshold, then open the second auxiliary switch S2 or keep it open.

[0038] Preferably, at least the semiconductor switch T1, the first auxiliary switch S1, the second auxiliary switch S2, the first capacitor C1, and the second capacitor are constructed as monolithic or non-monolithic integrated components.

[0039] It should be noted that the logic unit 10 can be connected to the control unit 50 in terms of information technology so as to receive, for example, information about the switching state and / or future switching time of the semiconductor switch T1 from the control unit 50, based on which the appropriate time point for determining the load current IL to be switched can be determined.

[0040] Alternatively or additionally, logic unit 10 may be configured to determine the current switching state of semiconductor switch T1 based on voltage measurement via voltage measurement unit 20.

[0041] It should also be noted that the logic unit 10 and / or the control unit 50 and / or the first gate driver 30 and / or the second gate driver 35 and / or the voltage measurement unit 20 may be configured to be integrated together in one or more components.

[0042] When the circuit arrangement of the present invention does not exhibit a monotonically decreasing and / or increasing load current, the logic unit 10 is preferably configured to perform the switching on and off of the respective auxiliary switches S1 and S2 based on the hysteresis corresponding to each of the respective auxiliary switches S1 and S2, so as to avoid unwanted back-and-forth switching of the auxiliary switches S1 and S2 due to non-monotonic increasing or decreasing load current.

[0043] based on Figure 1 The circuit unit or upper-level circuit arrangement described herein can achieve particularly low-loss switching operation of semiconductor switch T1 by activating and deactivating the first capacitor C1 and the second capacitor C2 according to their respective existing or expected load currents.

[0044] Figure 2 A first exemplary embodiment of a partially integrated circuit unit of the present invention is shown.

[0045] In this embodiment, the semiconductor switch T1, the auxiliary switch S1, and the capacitor C1 are monolithically integrated on a single substrate 40. Therefore, the drain connections 60 and 62 of the semiconductor switch T1 and the auxiliary switch S1 are electrically connected to each other, while the source connections 70 and 72 of the semiconductor switch T1 and the auxiliary switch S1 are connected to each other through the capacitor C1.

[0046] It should be noted that the logic units of the circuit arrangement of the present invention (see Figure 1 It can also be integrated with the above components T1, S1, C1, either as a single chip or a non-single chip.

[0047] Figure 3 A second exemplary embodiment of the partially integrated circuit unit of the present invention is shown.

[0048] In this embodiment, the semiconductor switch T1 and the auxiliary switch S1 are monolithically integrated on the first substrate 40, while the capacitor C1 is located on a separate second substrate 45. For example, the capacitor C1 is electrically connected to the semiconductor switch T1 and the auxiliary switch S1 via bonding wires or other electrical conductors, preferably with low inductance. The first substrate 40 and the second substrate 45, along with the respective mounted components T1, C1, and C2, are preferably configured as a co-packaged module.

[0049] It should be noted that the logic units of the circuit arrangement of the present invention (see Figure 1 Additionally, it can be integrated with the aforementioned components T1, S1, and C1, either as a single chip or a non-single chip.

[0050] Figure 4 A second embodiment of the circuit arrangement according to the invention, configured as a buck converter, is shown, having two circuit units of the invention, wherein the input voltage UE is converted into the desired output voltage UA by the respective switches T1, T2 (both configured as HEMT transistors here) of the half-bridge of the circuit arrangement, the appropriate manipulation of the switches T1, T2 and the inductor L.

[0051] The appropriate control of drive switches T1 and T2 is achieved through the first control unit 50 and the second control unit 50' (which may be the same control unit), the corresponding (not shown) gate drivers and the corresponding gate resistors RG1 and RG2.

[0052] Control units 50 and 50' are also configured to ensure that switches T1 and T2 are connected at near zero voltage based on an appropriate switching scheme, so as to keep the switching losses of switches T1 and T2 as low as possible.

[0053] In addition, the parasitic capacitances Cm, Cgs, Cds, Cm', Cgs', and Cds' of the two switches T1 and T2 are shown. For clarity, the parasitic inductances of switches T1 and T2 and the circuit layout are not shown separately.

[0054] Since the above components correspond to buck converters in the prior art, to avoid repetition, the specific functions of the buck converter will not be described in detail, but will be referred to in the prior art.

[0055] Unlike existing technologies, this circuit arrangement (i.e., buck converter) is built on two circuit units of the present invention, which consist of a first auxiliary switch S1, a first capacitor C1, a second auxiliary switch S2, a second capacitor C2, and a logic unit 10.

[0056] The logic unit 10 is configured, based on its (not shown) information technology connection with the first control unit 50 and the second control unit 50', to independently turn on and off the corresponding auxiliary switches S1 and S2, so as to reduce the turn-off losses of switches T1 and T2 according to the respective load currents to be switched.

Claims

1. A circuit unit for reducing switching losses of a semiconductor switch (T1), comprising: Semiconductor switch (T1), Auxiliary switch (S1), Capacitor (C1), and Logic unit (10), in, The series circuit consisting of the auxiliary switch (S1) and the capacitor (C1) is connected in parallel with the load path of the semiconductor switch (T1), and The logic unit (10) is configured as follows: With the semiconductor switch (T1) in the ON state, calculate the current intensity (IL) of the current flowing along the load path through the semiconductor switch (T1) to be switched. If the current intensity is higher than a predefined current threshold, then the auxiliary switch (S1) is closed or held closed before the turn-off process of the semiconductor switch (T1), and If the current intensity is not higher than the predefined current threshold, the auxiliary switch (S1) is turned off or the auxiliary switch is kept off before the turn-off process of the semiconductor switch (T1).

2. The circuit unit according to claim 1, wherein The semiconductor switch (T1) is configured as a power transistor, and / or Semiconductor switches based on Si, SiC, or GaN, and / or MOSFET, HEMT, IGBT, JFET, FinFET, CAVET or bipolar transistor, and / or The auxiliary switch (S1) is a semiconductor switch and / or an electromechanical switch.

3. The circuit unit according to any one of the preceding claims, wherein... The current threshold is a hysteretic upper threshold, and the logic unit (10) is configured to move the auxiliary switch (S1) from the closed state to the open state only when the current threshold is lower than the hysteretic lower threshold, and / or The circuit unit is configured to determine the current intensity of the current switched by the semiconductor switch (T1) substantially immediately before the turn-off process of the semiconductor switch (T1) begins.

4. The circuit unit according to any one of the preceding claims, wherein... The capacitor is a first capacitor (C1), and the circuit unit has at least one second capacitor (C2). The auxiliary switch is a first auxiliary switch (S1), and the circuit unit has at least one second auxiliary switch (S2). The current threshold is a first current threshold. The series circuit consisting of the second auxiliary switch (S2) and the second capacitor (C2) is connected in parallel with the load path of the semiconductor switch (T1), and The logic unit (10) is configured as follows: If the current intensity is higher than the second predefined current threshold, then the second auxiliary switch (S2) is closed or the second auxiliary switch is kept closed before the turn-off process of the semiconductor switch (T1), wherein the second predefined current threshold is greater than the first current threshold, and If the current intensity is not higher than the second predefined current threshold, the second auxiliary switch (S2) is turned off or the second auxiliary switch is kept off before the turn-off process of the semiconductor switch (T1).

5. The circuit unit according to any one of the preceding claims, wherein, The circuit unit is configured to determine the current intensity of the current switched by the semiconductor switch (T1) based on the following: Current measurement inside the semiconductor switch (T1), and / or Voltage measurement on the load path of the semiconductor switch (T1), and / or Information provided from external sources, and / or The operating state of the circuit unit and / or the operating state of the upper-level circuit arrangement containing the circuit unit.

6. The circuit unit according to any one of the preceding claims, wherein... The semiconductor switch (T1) and / or the auxiliary switch (S1) and / or the capacitor (C1) and / or the logic unit (10) are constructed as integrated, particularly partially or fully monolithically integrated, and / or The measuring unit (20) for determining the current intensity of the current to be switched and / or the first driving circuit (30) for controlling the semiconductor switch (T1) and / or the second driving circuit (35) for controlling the auxiliary switch (S1) are configured to be integrated with the circuit unit, particularly partially or completely monolithically integrated with the circuit unit.

7. The circuit unit according to claim 6, wherein At least the semiconductor switch (T1) and the auxiliary switch (S2) are constructed on substrates (40, 45) that are electrically isolated from each other, and / or The capacitor (C1) is connected to the circuit unit in a low-inductance manner.

8. A circuit arrangement, comprising: At least one circuit unit according to any one of the preceding claims, and Control unit (50), in, The control unit (50) is configured to turn on the semiconductor switch (T1) of the at least one circuit unit at essentially zero voltage.

9. The circuit arrangement according to claim 8, wherein, The circuit arrangement is configured to determine the turn-on loss of the semiconductor switch (T1) based on the current and / or pre-set switch state of the auxiliary switch (S1), and to set the auxiliary switch (S1) in accordance with the current intensity determined when the semiconductor switch (T1) is turned off only if the current intensity does not exceed the predefined maximum allowable turn-on loss of the semiconductor switch (T1).

10. A method for reducing switching losses in a semiconductor switch (T1), comprising: First step: When the semiconductor switch (T1) is in the ON state, calculate the current intensity (IL) of the current flowing along the load path of the semiconductor switch (T1) to be switched. Second step: If the current intensity (IL) is higher than the predefined current threshold, the auxiliary switch (S1) is closed or kept closed before the turn-off process of the semiconductor switch (T1). The auxiliary switch is connected in series with the capacitor (C1) and then in parallel with the load path of the semiconductor switch (T1). Alternatively, if the current intensity (IL) is not higher than the predefined current threshold, the auxiliary switch (S1) is opened or kept open before the turn-off process of the semiconductor switch (T1).

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