Circuit board, semiconductor module, and semiconductor system

Abstract

The invention provides a circuit board, a semiconductor module and a semiconductor system. A circuit board includes: an insulating layer configured to have a first surface and a second surface opposite to each other; a first terminal on the first surface of the insulating layer and configured to include a first signal terminal and a second signal terminal; and a first floating pattern embedded in the insulating layer, configured to have a region overlapping each of the first signal terminal and the second signal terminal, and electrically disconnected from the first signal terminal and the second signal terminal.

Description

Technical Field

[0001] This disclosure relates to circuit boards, semiconductor modules, and semiconductor systems. Background Technology

[0002] In memory modules, mutual inductance between signal terminals can cause far-end crosstalk (FEXT), which impairs signal integrity (SI) and interferes with high-speed operation. Therefore, methods to improve far-end crosstalk (FEXT) noise are being investigated to enhance the signal integrity (SI) of memory modules. Summary of the Invention

[0003] Some aspects of this disclosure provide circuit boards, semiconductor modules, and semiconductor systems capable of improving far-end crosstalk (FEXT) noise between signal terminals.

[0004] Some aspects of this disclosure relate to a circuit board comprising: an insulating layer configured to have a first surface and a second surface opposite to each other; a plurality of first terminals located on the first surface of the insulating layer and configured to include a first signal terminal and a second signal terminal; and a first floating pattern embedded in the insulating layer configured to have a region overlapping the first signal terminal and a region overlapping the second signal terminal, and electrically disconnected from the first signal terminal and the second signal terminal.

[0005] Some aspects of this disclosure relate to a semiconductor module comprising: a circuit board; and one or more semiconductor packages located on the circuit board, wherein the circuit board includes: an insulating layer configured to have a first surface and a second surface opposite to each other; a plurality of first terminals located on the first surface of the insulating layer and configured to include a first signal terminal and a second signal terminal; and a first floating pattern embedded in the insulating layer, configured to have a region overlapping the first signal terminal and a region overlapping the second signal terminal, and electrically disconnected from the first signal terminal and the second signal terminal, the plurality of first terminals being sequentially arranged along a first direction in an edge region of the circuit board.

[0006] Some aspects of this disclosure relate to a semiconductor system comprising: a motherboard; a connector located on the motherboard; and a semiconductor module coupled to the connector and configured to include a circuit board and one or more semiconductor packages located on the circuit board, wherein the circuit board includes: an insulating layer configured to have a first surface and a second surface opposite to each other; a plurality of terminals located on the first surface of the insulating layer and configured to include a first signal terminal and a second signal terminal; and a floating pattern embedded in the insulating layer configured to have regions overlapping with the first signal terminal and regions overlapping with the second signal terminal, and electrically disconnected from the first signal terminal and the second signal terminal, the plurality of terminals being arranged in an edge region of the circuit board and configured to be inserted into the connector. Attached Figure Description

[0007] Figure 1 This is a perspective view of an example semiconductor system.

[0008] Figure 2 This is a cross-sectional view of an example semiconductor module.

[0009] Figure 3 This is a partial top view of an example of a semiconductor module.

[0010] Figure 4 This is a partial perspective view of an example of a circuit board.

[0011] Figure 5 This is a partial plan view of an example of a circuit board.

[0012] Figure 6 This is a partial cross-sectional view of an example of a circuit board.

[0013] Figure 7 This shows a partial layout of an example circuit board used for semiconductor module design.

[0014] Figure 8 Show Figure 7 Example of the connection path for the signal terminals.

[0015] Figure 9 This is a partial perspective view of an example of a circuit board.

[0016] Figure 10 This is a partial plan view of an example of a circuit board.

[0017] Figure 11 This is a partial layout of an example circuit board used for semiconductor module design.

[0018] Figure 12 This is a partial perspective view of an example of a circuit board.

[0019] Figure 13 This is a partial cross-sectional view of an example of a circuit board.

[0020] Figure 14 This is a partial perspective view of the circuit board based on Comparative Example 1.

[0021] Figure 15 The comparison of far-end crosstalk (FEXT) noise between signal terminals is shown in Comparative Example 1 without a floating pattern and in an example including a floating pattern.

[0022] Figure 16 As shown in Figure 4 The simulation results show the mutual capacitance between signal terminals in the circuit board as a function of the width of the floating pattern.

[0023] Figure 17 Shown in such Figure 9 The simulation results show the mutual capacitance between signal terminals in the circuit board as a function of the width of the floating pattern.

[0024] Figure 18 Shown in such Figure 12 The simulation results show the mutual capacitance between signal terminals on the circuit board.

[0025] Figure 19 This is a perspective view showing a partial layout of the circuit board according to Comparative Example 2.

[0026] Figure 20 This is a perspective view showing a partial layout of the circuit board according to Example 1.

[0027] Figure 21 This is a perspective view showing a partial layout of the circuit board according to Example 2.

[0028] Figure 22 and Figure 23 This is an example eye diagram of a circuit board.

[0029] Figures 24 to 27 This shows the area of ​​the semiconductor module where floating patterns can be applied. Detailed Implementation

[0030] The present disclosure will be described more fully below with reference to the accompanying drawings, in which various examples are shown. It will be understood that the described examples may be modified in various ways without departing from the spirit or scope of the present disclosure.

[0031] Throughout the specification, the same reference numerals denote the same or similar parts.

[0032] Furthermore, since the dimensions and thicknesses of the constituent components shown in the accompanying drawings are arbitrarily given for better understanding and ease of description, this disclosure is not limited to the dimensions and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc., are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are exaggerated for better understanding and ease of description.

[0033] Throughout this specification and the following claims, when an element is described as being “connected” to another element, the element may be “directly connected” to the other element or “indirectly connected” to the other element via a third element. In a similar sense, this includes both “physical connection” and “electrical connection”.

[0034] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or there may be an intervening element. Conversely, when an element is referred to as being "directly on" another element, there is no intervening element. Furthermore, in the specification, the terms "on" or "above" indicate that it is located on or below the object portion, and do not necessarily indicate that it is located on the upper side of the object portion based on the direction of gravity.

[0035] Furthermore, unless explicitly stated otherwise, the words “including” and variations such as “contains” or “comprising” will be understood to imply inclusion of the described elements but not exclusion of any other elements.

[0036] Furthermore, throughout the specification, the phrase "in a plan view" refers to the view of a portion of the object from above, while the phrase "in a sectional view" refers to the view of a section taken from one side by vertically cutting the portion of the object.

[0037] Furthermore, throughout this specification, serial numbers such as "first," "second," etc., are used to distinguish a component from other components that are the same as or similar to it, and are not necessarily intended to refer to a specific component. Therefore, a component referred to as "first component" in a particular section of this specification may be referred to as "second component" in other sections of this specification.

[0038] Furthermore, throughout the specification, singular references to certain elements include references to multiple such elements, unless explicitly stated otherwise.

[0039] Figure 1 A perspective view of a semiconductor system is shown. The semiconductor system 1 includes a motherboard 30, a connector 20 located on the motherboard 30, and a semiconductor module 10 connected to the connector 20.

[0040] The motherboard 30 can connect the main components mounted thereon to each other and can provide interfaces between the main components and peripheral devices. The motherboard 30 may be referred to as a motherboard, hostboard, system board, etc. In addition to the semiconductor module 10, other components such as CPU, GPU, coprocessor, chipset, peripheral component interconnect (PCI) and power connectors can be further mounted on the motherboard 30.

[0041] A connector 20 for mounting the semiconductor module 10 can be located on the motherboard 30. The connector 20 can support the semiconductor module 10 and provide an electrical connection between the semiconductor module 10 and the motherboard 30. The connector 20 can have a slot 20S into which the semiconductor module 10 is accommodated by inserting a first end of the semiconductor module 10 into the slot 20S, with a first terminal 121 located on this first end. Pins electrically connected to the first terminal 121 can be located on the inner surface of the slot 20S of the connector 20. The pins can be located at positions corresponding to the first terminal 121 to contact the first terminal 121.

[0042] Semiconductor module 10 may include a memory module. The memory module may include at least one of the following: dual in-line memory module (DIMM), small outline dual in-line memory module (SODIMM), unbuffered dual in-line memory module (UDIMM), register-enabled dual in-line memory module (RDIMM), low load dual in-line memory module (LRDIMM), hypercloud dual in-line memory module (HDIMM), non-volatile DIMM (NVDIMM), fully buffered dual in-line memory module (FB-DIMM), CXL memory module (CMM), multilevel buffered DIMM (MRDIMM), and low power compressed additional memory module (LPCAMM).

[0043] The semiconductor module 10, which can be applied to a semiconductor system 1 according to the present disclosure, will be described in more detail below. Figure 2 A cross-sectional view of a semiconductor module (e.g., semiconductor module 10) is shown. Figure 3 A partial top plan view of a semiconductor module (e.g., semiconductor module 10) is shown.

[0044] Semiconductor module 10 may include circuit board 100 and one or more semiconductor packages 200 disposed on circuit board 100. To clearly illustrate the main components, Figure 3 Only some areas of the semiconductor package 200 of the semiconductor module 10 are shown.

[0045] The circuit board 100 may include an insulating layer 110 having a first surface 111 and a second surface 112 opposite to each other, a first terminal 121 and a pad 123 located on the first surface 111 of the insulating layer 110, and one or more floating patterns 131 embedded in the insulating layer 110.

[0046] Multiple internal wiring layers WL1, WL2, and WL3 may be located within insulating layer 110, which insulates the internal wiring layers WL1, WL2, and WL3 from each other. Insulating layer 110 may include multiple sub-insulating layers, the number of which is not particularly limited and can vary depending on the number of internal wiring layers WL1, WL2, and WL3. When insulating layer 110 is formed to include multiple sub-insulating layers, the multiple sub-insulating layers may have boundaries with each other or may not have boundaries visible to the naked eye. Insulating materials may be used for insulating layer 110, such as polyimide (PI), epoxy resin, FR-4, FR-2, photoimageable dielectric (PID) materials, etc.

[0047] Internal wiring layers WL1, WL2, and WL3 are electrically connected to each other via pathways. Alternatively, internal wiring layers WL1, WL2, and WL3 may be electrically connected to the first terminal 121 and the pad 123. Internal wiring layers WL1, WL2, and WL3 can perform various functions according to the design and may include signal patterns, power patterns, ground patterns, etc. The number of internal wiring layers WL1, WL2, and WL3 is not limited to the number shown in the figures and can be implemented in various ways. Conductive materials can be used as the materials for internal wiring layers WL1, WL2, and WL3. For example, aluminum (Al), copper (Cu), gold (Au), platinum (Pt), silver (Ag), tin (Sn), chromium (Cr), palladium (Pd), or alloys of two or more of these can be used.

[0048] The first terminal 121 may be arranged in the Y direction along an edge region of the circuit board 100 on the first surface 111 of the insulating layer 110. The first terminal 121 may be configured to protrude from the first surface 111 of the insulating layer 110, at least a portion of the first terminal 121 may be embedded in the insulating layer 110, and the upper surface of the first terminal 121 may be exposed through the first surface 111 of the insulating layer 110. The first terminals 121 may be spaced apart by a predetermined distance along the Y direction. The first terminal 121 may be accommodated in the connector 20 to provide an electrical connection between the semiconductor module 10 and the connector 20. The first terminal 121 may be referred to as a gold finger, edge connector, connector pin, terminal block, etc. The length of the first terminal 121 in the X direction may be longer than its length in the Y direction.

[0049] As the material used for the first terminal 121, a material with high conductivity and excellent chemical stability, such as gold (Au), can be used. However, the material of the first terminal 121 is not limited to gold, and other conductive materials can be used as the material of the first terminal 121.

[0050] The first terminal 121 may include a signal terminal 121S and a ground terminal 121G. The signal terminal 121S may be electrically connected to circuitry of the circuit board 100 that performs signal transmission functions, and the ground terminal 121G may be electrically connected to circuitry of the circuit board 100 that performs grounding functions. The signal terminal 121S and the ground terminal 121G may be arranged alternately in the Y direction along an edge region of the circuit board 100 or in an edge region of the circuit board 100. For example, the ground terminal 121G may be located between two adjacent signal terminals 121S.

[0051] The pad 123 may be located on the first surface 111 of the insulating layer 110 to electrically connect the circuit board 100 to the semiconductor package 200. A conductive material may be used as the material for the pad 123, and for example, aluminum (Al), copper (Cu), gold (Au), platinum (Pt), silver (Ag), tin (Sn), chromium (Cr), palladium (Pd), or an alloy of two or more of these may be used.

[0052] In some implementations, a passivation layer is disposed on a first surface 111 of the insulating layer 110, and the first terminal 121 and the pad 123 may be exposed on or by the upper surface of the passivation layer.

[0053] like Figures 2 to 3 As shown, the circuit board 100 includes one or more floating patterns 131 to compensate for mutual capacitance between two or more signal terminals 121S. The floating patterns 131 may be embedded in the insulating layer 110 and may have areas overlapping with the signal terminals 121S to provide compensation for mutual capacitance. In this disclosure, "overlap" means overlap in the Z direction, for example, when viewed in a plan view.

[0054] The number of floating patterns 131 included in the circuit board 100 can vary depending on the implementation. In some implementations, all signal terminals 121S included in the circuit board 100 have areas overlapping with the floating patterns 131. For example, as Figure 3 As shown, the circuit board 100 may include a plurality of floating patterns 131, each floating pattern 131 may have an area overlapping with an adjacent signal terminal 121S among the signal terminals 121S. In some implementations, some signal terminals 121S have an area overlapping with the floating pattern 131, and some signal terminals 121S do not have an area overlapping with the floating pattern 131. (Refer to...) Figures 4 to 6 Additional description of floating pattern 131 is provided.

[0055] Multiple semiconductor packages 200 may be arranged on the circuit board 100. For example, semiconductor packages 200 may be arranged on the circuit board 100 and spaced apart from each other in the Y direction. However, the number of semiconductor packages 200 located on the circuit board 100 is not particularly limited, and in some implementations, only a single semiconductor package 200 is located on the circuit board 100.

[0056] Each semiconductor package 200 may be spaced apart from the first terminal 121 of the circuit board 100 in the X direction.

[0057] Each semiconductor package 200 can be mounted on the circuit board 100 via a conductive bump B1. The conductive bump B1 can be located between the semiconductor package 200 and the pad 123 of the circuit board 100. The conductive bump B1 can be formed of a conductive material (e.g., solder balls).

[0058] Semiconductor package 200 may include substrate 210, semiconductor chip 220 located on substrate 210, and molding material 230 for molding semiconductor chip 220.

[0059] The substrate 210 may be a multilayer substrate including multiple insulating layers and multiple wiring layers. Pads may be located on the upper and lower surfaces of the substrate 210 to electrically connect the substrate 210 to other components. In addition, passivation layers may be located on the upper and lower surfaces of the substrate 210, and the pads of the substrate 210 may be exposed by the passivation layers.

[0060] In some implementations (e.g., when semiconductor module 10 includes a memory module), semiconductor chip 220 includes a memory chip. The memory chip may include one or more of dynamic random access memory (DRAM) chips, static random access memory (SRAM) chips, flash memory chips, high bandwidth memory (HBM) chips, read-only memory (ROM) chips, and magnetic random access memory (MRAM) chips.

[0061] The molding material 230 can be used to physically and chemically protect the semiconductor chip 220. The molding material 230 can be made of an insulating material such as an epoxy molding compound (EMC). Compression molding, transfer molding, and other methods can be used to form the molding material 230.

[0062] In the following text, reference will be made to Figures 4 to 6 Describe the layout of the floating pattern 131 and its adjacent components.

[0063] Figure 4 , Figure 5 and Figure 6 Partial perspective view, partial plan view and partial sectional view of a circuit board (such as circuit board 100) are shown respectively.

[0064] Figure 6 Showing the cut along I-I' Figure 5 The view.

[0065] To clearly illustrate certain components, it is assumed that the insulating layer 110 is transparent in each figure. Furthermore, in the following description, among the signal terminals 121S, the signal terminals overlapping the floating pattern 131 are respectively referred to as the first signal terminal 121S1 and the second signal terminal 121S2, and among the ground terminals 121G, the ground terminal 121G disposed between the first signal terminal 121S1 and the second signal terminal 121S2 is referred to as the first ground terminal 121G1.

[0066] According to some embodiments, far-end crosstalk is reduced by introducing a floating pattern 131 that is not electrically connected to some or any components within the circuit board 100 (e.g., electrically disconnected from some or all other components of the circuit board 100) and generating appropriate mutual capacitance between adjacent signal terminals.

[0067] The floating pattern 131 has an area overlapping with the first signal terminal 121S1 and an area overlapping with the second signal terminal 121S2. For example, the floating pattern 131 may be located below the lower surface of the first signal terminal 121S1 and the lower surface of the second signal terminal 121S2 to have an area overlapping with them. The first signal terminal 121S1 and the second signal terminal 121S2 may be adjacent signal terminals 121S. In some implementations, the floating pattern 131 has an area overlapping with additional signal terminals besides the first signal terminal 121S1 and the second signal terminal 121S2.

[0068] The floating pattern 131 can extend from the first signal terminal 121S1 to the second signal terminal 121S2 in the Y direction. The length of the floating pattern 131 in the Y direction can be longer than its length in the X direction (length in the width direction).

[0069] The first signal terminal 121S1 and the second signal terminal 121S2 are spaced apart in the Y direction, and the first ground terminal 121G1 may be located between them. Therefore, the first ground terminal 121G1 located between the first signal terminal 121S1 and the second signal terminal 121S2 may also have an area overlapping with the floating pattern 131.

[0070] Reference Figure 6 The first side surface ss3 of the opposing side surfaces ss3 and ss4 of the floating pattern 131 facing the Y direction can overlap (e.g., align) with the side surface ss1 of the opposing side surfaces of the first signal terminal 121S1 facing the Y direction that is furthest from the second signal terminal 121S2, or can be further outward in the Y direction (towards) Figure 6 (Left side) Arranged. Similarly, the second side surface ss4 of the opposing side surfaces ss3 and ss4 facing the Y direction of the floating pattern 131 can overlap (e.g., align) with the side surface ss2 of the opposing side surfaces facing the Y direction of the second signal terminal 121S2 that is furthest from the first signal terminal 121S1, or can be further outward in the Y direction (towards) Figure 6 (Right side of the image). In some implementations, the high target level of mutual capacitance between the floating pattern 131 and the signal terminal 121S is achieved by a structure in which the floating pattern 131 overlaps with the entire area of ​​each of the first signal terminal 121S1 and the second signal terminal 121S2 in a cross-sectional view, for example, completely spanning the extension of each of the first signal terminal 121S1 and the second signal terminal 121S2 in the Y direction.

[0071] The floating pattern 131 can be connected to the wiring of the circuit board 100 (e.g., Figure 2 The internal wiring layers (WL1, WL2, and WL3) are electrically disconnected. For example, the floating pattern 131 may not be electrically connected to any conductors on the circuit board 100. For example, the floating pattern 131 may be electrically disconnected from the signal terminals 121S and ground terminals 121G of the circuit board 100. Because the floating pattern 131 is electrically disconnected from other components, the outer surface of the floating pattern 131 may be covered with an insulating layer 110. The outer surface of the floating pattern 131 includes all of the upper surface, the lower surface, and the side surfaces connecting the upper and lower surfaces. Because the floating pattern 131 is electrically disconnected from the conductors of the circuit board 100, the floating pattern 131 may not affect existing conductors and may generate mutual capacitance between the signal terminals 121S without being associated with the increased time and / or cost required for more drastic design changes.

[0072] The width w3 of the floating pattern 131 can be equal to or narrower than the width w1 of the first signal terminal 121S1 and the width w2 of the second signal terminal 121S2. In this specification, the width of a component is defined as its length in the X direction. For example, if the width w1 of the first signal terminal 121S1 and the width w2 of the second signal terminal 121S2 are approximately 1.85 mm according to standard specifications, then the width w3 of the floating pattern 131 can be at most approximately 1.85 mm, for example, 1.85 mm or less. Because the width w3 of the floating pattern 131 is equal to or narrower than each of the width w1 of the first signal terminal 121S1 and the width w2 of the second signal terminal 121S2, wiring space can be prevented from being restricted by the floating pattern 131.

[0073] Reference Figure 16As can be seen, as the width w3 (or W) of the floating pattern 131 increases, the mutual capacitance Cm between the first signal terminal 121S1 and the second signal terminal 121S2 increases. When the width w3 of the floating pattern 131 is formed to be equal to each of the width w1 of the first signal terminal 121S1 and the width w2 of the second signal terminal 121S2, the mutual capacitance between the first signal terminal 121S1 and the second signal terminal 121S2 can be maximized without limiting the wiring space.

[0074] Reference Figure 2 The circuit board 100 may include a plurality of internal wiring layers WL1, WL2, and WL3 embedded in an insulating layer 110. A floating pattern 131 may be located at the same level as the internal wiring layer WL1 (hereinafter referred to as the uppermost internal wiring layer) closest to the first terminal 121 among the internal wiring layers WL1, WL2, and WL3. Therefore, there may be no internal wiring layer between the level L1 where the first terminal 121 is located and the level L2 where the floating pattern 131 is located. In this disclosure, "level" refers to the level in the Z direction, and in the figures, the level is indicated based on the lower surface of each component. Since the floating pattern 131 is located at the same level as the uppermost internal wiring layer WL1 among the internal wiring layers WL1, WL2, and WL3, mutual capacitance can be maximized by minimizing the distance between the floating pattern 131 and the first terminal 121. The internal wiring layers WL1, WL2, and WL3 embedded in the insulating layer 110 can be spaced apart from the floating pattern 131 in the X direction in the plan view and can not overlap with the floating pattern 131. Sufficient wiring space can be ensured by forming the floating pattern 131 at the edge portion of the circuit board 100 to space it apart from the internal wiring layers WL1, WL2, and WL3.

[0075] However, the floating pattern 131 is not limited to being designed to maximize the mutual capacitance between the signal terminals 121S, and the mutual capacitance to be generated between the signal terminals 121S can vary depending on the implementation. The level of the floating pattern 131 can be appropriately adjusted according to the target mutual capacitance value to be generated between the signal terminals 121S. For example, the floating pattern 131 can be located at the same level as the wiring layer (e.g., internal wiring layer WL2) among the internal wiring layers WL1, WL2, and WL3, excluding the uppermost internal wiring layer WL1. Furthermore, the shape and size of the floating pattern 131, the area overlapping with the signal terminals 121S, the distance between the signal terminals 121S, etc., can also be appropriately determined according to the mutual capacitance value to be generated between the signal terminals 121S.

[0076] The conductive material can be used as the material for the floating pattern 131, for example, aluminum (Al), copper (Cu), gold (Au), platinum (Pt), silver (Ag), tin (Sn), chromium (Cr), palladium (Pd), or alloys of two or more of these. The material of the floating pattern 131 can be the same as the material of the internal wiring layers WL1, WL2, and WL3 embedded in the insulating layer 110. The floating pattern 131 and the internal wiring layers WL1, WL2, and WL3 can be formed by the same process, thereby simplifying the process.

[0077] The first signal terminal 121S1 and the second signal terminal 121S2 can be connected to the first signal wire 122S1 and the second signal wire 122S2, respectively. The first signal terminal 121S1 can be connected to the first signal wire 122S1 and other components connected thereto to form a path for transmitting a first signal, and the second signal terminal 121S2 can be connected to the second signal wire 122S2 and other components connected thereto to form a path for transmitting a second signal.

[0078] The circuit board 100 may further include a ground plane 132G, which is located at the same horizontal level L2 as the floating pattern 131 and spaced apart from the floating pattern 131, and is electrically connected to the first ground terminal 121G1 via a path V. The ground plane 132G may be included in an inner wiring layer WL1 embedded in the insulating layer 110. For example, the ground plane 132G may be spaced apart from the floating pattern 131 in the X direction and may be a large-area pattern with a relatively large area. Since the first ground terminal 121G1 is electrically disconnected from the floating pattern 131, it will be understood that the ground plane 132G may also be electrically disconnected from the floating pattern 131.

[0079] Figure 7 This shows a partial layout of a circuit board used in semiconductor module design. Figure 8 Show Figure 7 Some connection paths for the signal terminals.

[0080] As described above, the first terminal 121 may include a signal terminal 121S and a ground terminal 121G, which may be arranged alternately in the Y direction along an edge region of the circuit board 100 or in an edge region of the circuit board 100. In this case, each floating pattern 131 may extend in the Y direction between adjacent signal terminals 121S to overlap with the adjacent signal terminal 121S and the ground terminal 121G located therebetween.

[0081] In some implementations, at least some of the signal terminals 121S overlap with multiple (e.g., two) of the floating patterns 131. The multiple floating patterns 131 overlapping a signal terminal 121S can generate mutual capacitance between the signal terminal 121S and each of the other signal terminals 121S located on the opposite side of the signal terminal 121S. Far-end crosstalk caused by signals transmitted from the opposite side of the signal terminal 121S can be reduced or effectively eliminated by generating mutual capacitance between the signal terminal 121S and each of the other signal terminals 121S located on its opposite side.

[0082] Floating patterns 131 adjacent to each other in the Y direction can be arranged to be offset from each other in the X direction in order to effectively arrange the floating patterns 131 overlapping with each signal terminal 121S and maximize the area of ​​overlap between the floating patterns 131 and the signal terminals 121S. For example, floating patterns 131 adjacent to each other in the Y direction can be arranged alternately at positions offset from each other in the X direction to form a zigzag shape.

[0083] Reference Figure 8 The first signal terminal 121S1 and the second signal terminal 121S2 can each be connected to other components of the circuit board 100 to form independent signal paths. For example, the first signal terminal 121S1 can be connected to the first signal wire 122S1 to form a path for transmitting a first signal, and the second signal terminal 121S2 can be connected to the second signal wire 122S2 to form a path for transmitting a second signal. To form signal paths, the first signal wire 122S1 and the second signal wire 122S2 can be electrically connected to signal wires located on other layers via circuits.

[0084] According to some implementations of this disclosure, by forming a floating pattern 131 that overlaps with the first signal terminal 121S1 and the second signal terminal 121S2 and is electrically disconnected from the wires of the circuit board 100 (e.g., electrically disconnected from the first signal terminal 121S1 and the second signal terminal 121S2 (including any wires connected thereto), the mutual capacitance between the signal terminals can be generated or increased without affecting the existing wires and without increasing the time and cost required for additional design changes.

[0085] Figure 9 and Figure 10 A partial perspective view and a partial plan view are shown, respectively, of another example of a circuit board. (Compared to...) Figures 4 to 6 Compared to the example, Figure 9 and Figure 10 The floating pattern 131 includes areas with different widths.

[0086] For example, such as Figure 9 and Figure 10As shown, the width w3c of the floating pattern 131 in the region overlapping with the first ground terminal 121G1 can be narrower than each of the width w3a of the floating pattern 131 in the region overlapping with the first signal terminal 121S1 and the width w3b of the floating pattern 131 in the region overlapping with the second signal terminal 121S2. The width w3a in the region overlapping with the first signal terminal 121S1 and the width w3b in the region overlapping with the second signal terminal 121S2 can be the same as or different from each other.

[0087] Reference Figure 17 As can be seen, under the condition that the widths w3a and w3b in the region overlapping with the first signal terminal 121S1 and the second signal terminal 121S2 are constant, as the width w3c of the region overlapping with the first ground terminal 121G1 narrows, the mutual capacitance between the first signal terminal 121S1 and the second signal terminal 121S2 increases.

[0088] When the width w3c of the floating pattern 131 is made narrow in the area overlapping with the first ground terminal 121G1, the mutual capacitance between the first signal terminal 121S1 and the second signal terminal 121S2 can be further increased by reducing the capacitance generated between the floating pattern 131 and the first ground terminal 121G1.

[0089] Figure 11 Showing the design based on Figure 9 and Figure 10 The partial layout of the circuit board configuration. (Compared to...) Figure 7 Compared to the circuit board shown, the width w3c of the floating pattern 131 in the region overlapping with the first ground terminal 121G1 can be narrower than each of the width w3a in the region overlapping with the first signal terminal 121S1 and the width w3b in the region overlapping with the second signal terminal 121S2.

[0090] Figure 12 and Figure 13 Partial perspective and partial sectional views are shown for another example of a circuit board. Figures 4 to 6 Compared to the example, Figure 12 and Figure 13 The circuit board 100 also includes a second terminal 151 located on the second surface 112 of the insulating layer 110 and an additional floating pattern 141 embedded in the insulating layer 110.

[0091] The second terminal 151 may be arranged in the Y direction on the second surface 112 of the insulating layer 110 along an edge region of the circuit board 100 or in an edge region of the circuit board 100. The second terminal 151 may be positioned to overlap with the first terminal 121.

[0092] Unless otherwise stated or suggested by the context, the description of the first terminal 121 can be applied equivalently to the description of the second terminal 151. For example, the second terminal 151 may include a signal terminal 151S and a ground terminal 151G, just like the first terminal 121, and the signal terminal 151S and the ground terminal 151G may be arranged alternately in the Y direction along an edge region of the circuit board 100 or in an edge region of the circuit board 100.

[0093] The signal terminals 151S of the second terminal 151 may each overlap with the ground terminal 121G of the first terminal 121, and the ground terminal 151G of the second terminal 151 may each overlap with the signal terminals 121S of the first terminal 121. However, their relative positions are not limited to this.

[0094] In the following description, among the signal terminals 151S, those overlapping with the second floating pattern 141 are referred to as the third signal terminal 151S1 and the fourth signal terminal 151S2, respectively. Among the ground terminals 151G, the ground terminal 151G located between the third signal terminal 151S1 and the fourth signal terminal 151S2 is referred to as the second ground terminal 151G1. Furthermore, in order to distinguish between the floating patterns 131 and 141 located on opposite sides of the insulating layer 110, the floating pattern 131 located near the first surface 111 of the insulating layer 110 (e.g., the surface closest to the first surface 111 of the insulating layer 110) is referred to as the first floating pattern 131, and the floating pattern 141 located near the second surface 112 of the insulating layer 110 (e.g., the surface closest to the second surface 112 of the insulating layer 110) is referred to as the second floating pattern 141.

[0095] The third signal terminal 151S1 and the fourth signal terminal 151S2 can be connected to the third signal wire 152S1 and the fourth signal wire 152S2, respectively. The third signal terminal 151S1 can be connected to the third signal wire 152S1 and other components connected thereto to form a path for transmitting the third signal, and the fourth signal terminal 151S2 can be connected to the fourth signal wire 152S2 and other components connected thereto to form a path for transmitting the fourth signal.

[0096] Unless otherwise stated or suggested by the context, the description of the first floating pattern 131 can be applied equivalently to the description of the second floating pattern 141. For example, the second floating pattern 141 may have an area overlapping with the third signal terminal 151S1 and an area overlapping with the fourth signal terminal 151S2, and may also have an area overlapping with the second ground terminal 151G1 located between the third signal terminal 151S1 and the fourth signal terminal 151S2. In addition, the second floating pattern 141 may be electrically disconnected from other conductors of the circuit board 100, including the third signal terminal 151S1 and the fourth signal terminal 151S2.

[0097] The second floating pattern 141 may be located at a horizontal level L3 between the first floating pattern 131 and the second terminal 151, thus being adjacent to the second terminal 151. For example, the second floating pattern 141 may be located at the same horizontal level as the inner wiring layer embedded in the insulating layer 110 closest to the second terminal 151. Therefore, there may be no inner wiring layer between the horizontal level L4 where the second terminal 151 is located and the horizontal level L3 where the second floating pattern 141 is located. The inner wiring layer may be present between the horizontal level L2 where the first floating pattern 131 is located and the horizontal level L3 where the second floating pattern 141 is located. It will be understood that other locations of the second floating pattern 141 are within the scope of this disclosure.

[0098] The circuit board 100 may also include one or more channels 160 embedded in the insulating layer 110 and electrically connecting the first floating pattern 131 and the second floating pattern 141. The channels 160 may extend integrally through the insulating layer 110 between a horizontal level L2 where the first floating pattern 131 is located and a horizontal level L3 where the second floating pattern 141 is located. The channels 160 may overlap with both the first floating pattern 131 and the second floating pattern 141. The number of channels 160 is not particularly limited and may be single or multiple. The shape of the channels 160 is also not particularly limited and may have cylindrical, conical (where the cross-sectional area narrows from one side to the other), hourglass, etc.

[0099] In a semiconductor module such as a dual in-line memory module (DIMM), the first floating pattern 131 and the second floating pattern 141 can generate mutual capacitance between signal electrodes located on opposite sides of the insulating layer 110 to effectively improve far-end crosstalk noise that may occur between multiple signal electrodes.

[0100] exist Figure 18 In the diagram, DQ00, DQ01, DQ02, and DQ03 represent the first signal terminal 121S1, the second signal terminal 121S2, the third signal terminal 151S1, and the fourth signal terminal 151S2, respectively. These are signal terminals used for transmitting and / or receiving data. (See reference...) Figure 18The simulation results confirm that mutual capacitance Cm is generated between every two of the first signal terminal 121S1, the second signal terminal 121S2, the third signal terminal 151S1, and the fourth signal terminal 151S2.

[0101] Figure 14 A partial perspective view of the circuit board according to Comparative Example 1 is shown. The circuit board according to Comparative Example 1 does not include the floating pattern 131 that overlaps with the signal terminals.

[0102] Figure 15 This illustrates a comparison of far-end crosstalk (FEXT) noise between signal terminals in Comparative Example 1, which does not include floating pattern 131, and in an example that includes floating pattern 131. (Refer to...) Figure 15 The simulation results show that the far-end crosstalk noise between signal terminals is significantly reduced from 44mV (without floating pattern 131) to 27mV (with floating pattern 131).

[0103] In addition, refer to Figure 16 As can be seen from the simulation results, the mutual capacitance between the first signal terminal 121S1 and the second signal terminal 121S2 is not significant (8.48 fF) in Comparative Example 1 without the floating pattern 131, but it is significant in the example with the floating pattern 131. Figure 4 In the case of the structure), it increases to approximately 240.58 fF. Therefore, it can be seen that the floating pattern 131 generates appropriate mutual capacitance between the signal terminals, thereby reducing far-end crosstalk noise between the signal terminals.

[0104] Figure 19 A perspective view is shown, illustrating a partial layout of the circuit board according to Comparative Example 2. Figure 20 A perspective view is shown, illustrating a partial layout of the circuit board according to Example 1. Figure 21 A perspective view is shown, illustrating a partial layout of the circuit board according to Example 2. Figure 22 and Figure 23 Eye diagrams of the circuit boards according to Comparative Example 2 and Examples 1 and 2 are shown.

[0105] Instead of a floating pattern, the circuit board of Comparative Example 2 includes an overlapping pattern 132S2. The overlapping pattern 132S2 is electrically connected to and positioned below the second signal conductor 122S2, and overlaps with the first signal conductor 122S1. Therefore, the overlapping pattern 132S2 is not electrically disconnected from both the first signal conductor 122S1 and the second signal conductor 122S2. The overlapping pattern 132S2 is formed at the same level as the floating pattern 131, for example, in the inner wiring layer closest to the first terminal 121 (located in…). Figure 6 (at level L2 in the middle).

[0106] The circuit boards according to Examples 1 and 2 include a floating pattern 131. The floating pattern 131 of Examples 1 and 2 is formed such that the width of the area overlapping with the first ground terminal 121G1 is narrower than the width of the area overlapping with the signal terminals 121S1 and 121S2.

[0107] In order to form an overlapping pattern 132S2 for generating mutual capacitance in the signal routing area, not only are changes to the routing design required, but there may also be a problem of limited routing space due to the presence of the overlapping pattern 132S2.

[0108] On the other hand, when the floating pattern 131 of this disclosure is introduced, sufficient mutual capacitance between the first signal terminal 121S1 and the second signal terminal 121S2 can be ensured, (in some implementations) without changing the wiring design of other components and without sacrificing sufficient wiring space. Furthermore, due to the increased wiring freedom, the signal transmission path of the first signal wire 122S1 and the second signal wire 122S2 can be further shortened, as in the case of Example 2 (…). Figure 21 ).

[0109] In addition, refer to Figure 22 and Figure 23 The simulation results show that, compared with Comparative Example 2, the circuit board including the floating pattern 131 exhibits increased eye width and eye height values, thus the floating pattern 131 can improve the signal integrity (SI) of the product.

[0110] Figure 24 Another example of the use of a floating pattern is shown. In this example, the floating pattern is present in another area of ​​the semiconductor module. In semiconductor module 10-1, the floating pattern 131 can be positioned to overlap with signal pads in the upper pads 123 of the circuit board 100. The floating pattern 131 can compensate for the mutual capacitance between the signal pads that overlap with the floating pattern 131. Figure 24 The floating pattern 131 may have the characteristics described throughout this disclosure for other floating patterns 131 (e.g., geometry, arrangement, connection and disconnection characteristics, etc.), unless otherwise stated or suggested by the context.

[0111] Figure 25 Another example of the use of a floating pattern is shown. In this example, the floating pattern is present in another area of ​​the semiconductor module. The semiconductor module 10-2 can be electrically connected to other components via conductive bumps B2 located on the lower surface of the circuit board 100. Specifically, the conductive bumps B2 can be located on the lower surface of a lower pad 191, which is located on the second surface 112 of the insulating layer 110. The conductive bumps B2 can be formed of a conductive material (e.g., solder balls).

[0112] In semiconductor module 10-2, floating pattern 131 can be positioned to overlap with signal pads in the lower pad 191 of the circuit board 100 connected to conductive bump B2. Floating pattern 131 can compensate for mutual capacitance between signal pads that overlap with floating pattern 131. Figure 25 The floating pattern 131 may have the characteristics (e.g., geometry, arrangement, connection and disconnection characteristics, etc.) described throughout this disclosure for other floating patterns 131, 141, unless otherwise stated or suggested by the context.

[0113] Figure 26 This illustrates another example of the use of floating patterns. In this example, the floating pattern exists in another area of ​​the semiconductor module. For example... Figure 26 As shown, the floating pattern 131 can be applied alternatively or additionally to the semiconductor package 200. In the semiconductor module 10-3, the substrate 210 of the semiconductor package 200 may include an upper pad 211 and a lower pad 212. The upper pad 211 can be electrically connected to the semiconductor chip 220 via a conductive bump B3, and the lower pad 212 can be electrically connected to the circuit board 100 via a conductive bump B1.

[0114] In semiconductor module 10-3, floating pattern 131 can be positioned to overlap with signal pads in the upper pads 211 of substrate 210 of semiconductor package 200. Floating pattern 131 can compensate for mutual capacitance between signal pads that overlap with floating pattern 131. Figure 26 The floating pattern 131 may have the characteristics described throughout this disclosure for other floating patterns 131 (e.g., geometry, arrangement, connection and disconnection characteristics, etc.), unless otherwise stated or suggested by the context.

[0115] Figure 27 Another example of the use of a floating pattern is shown. In this example, the floating pattern is present in another area of ​​the semiconductor module. Compared to semiconductor module 10-3, in semiconductor module 10-4, the floating pattern 131 can be positioned to overlap with the signal pads in the lower pads 212 of the substrate 210 of the semiconductor package 200. The floating pattern 131 can compensate for the mutual capacitance between the signal pads that overlap with the floating pattern 131. Figure 27 The floating pattern 131 may have the characteristics (e.g., geometry, arrangement, connection and disconnection characteristics, etc.) described throughout this disclosure for other floating patterns 131, 141, unless otherwise stated or suggested by the context.

[0116] Although this disclosure has been described in conjunction with certain examples, it will be understood that this disclosure is not limited to the disclosed examples, but rather is intended to cover various modifications and equivalent arrangements.

[0117] Although this disclosure contains numerous specific implementation details, these should not be construed as limiting the scope of the claims. Certain features described in the context of separate implementations (e.g., the presence / configuration of floating patterns) may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented separately in multiple implementations or in any suitable sub-combination. Furthermore, although features may be described above as functioning in certain combinations, in some cases, one or more features from a combination may be removed from that combination, and the combination may be for sub-combinations or variations thereof.

[0118] It will be understood that, unless there is a specific conflict, the examples of this disclosure are not independent of each other and can be implemented in combination with each other. For example, floating patterns described with reference to different examples in different regions / configurations can be included in the same semiconductor module. Therefore, implementations combining the examples of this disclosure should also be considered to be included within the scope of this disclosure.

[0119] This application claims priority and benefit to Korean Patent Application No. 10-2024-0069332, filed on May 28, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A circuit board, comprising: An insulating layer having a first surface and a second surface opposite to each other; A plurality of first terminals are located on the first surface of the insulating layer and include a first signal terminal and a second signal terminal; as well as A first floating pattern is embedded in the insulating layer, the first floating pattern including a first region overlapping the first signal terminal and a second region overlapping the second signal terminal. The first floating pattern is electrically disconnected from the first signal terminal and the second signal terminal.

2. The circuit board according to claim 1, wherein the plurality of first terminals are arranged sequentially along a first direction in the edge region of the circuit board.

3. The circuit board of claim 2, wherein the width of the first floating pattern in the second direction is equal to or narrower than the width of each of the first signal terminal and the second signal terminal in the second direction, wherein the second direction intersects the first direction.

4. The circuit board of claim 2, wherein the plurality of first terminals includes a ground terminal located between the first signal terminal and the second signal terminal, wherein the first floating pattern includes a third region overlapping the ground terminal.

5. The circuit board of claim 4, wherein the width of the first floating pattern in the third region in the second direction is narrower than each of the width of the first floating pattern in the first region in the second direction and the width of the first floating pattern in the second region in the second direction, wherein the second direction intersects the first direction.

6. The circuit board of claim 4, wherein the first floating pattern is electrically disconnected from the ground terminal.

7. The circuit board according to claim 4, further comprising: A ground plane is located at the same level as the first floating pattern and spaced apart from the first floating pattern, wherein the ground plane is electrically connected to the ground terminal.

8. The circuit board according to claim 1, further comprising: A plurality of second terminals are located on the second surface of the insulating layer and include a third signal terminal and a fourth signal terminal; and A second floating pattern is located horizontally between the first floating pattern and the plurality of second terminals, the second floating pattern being embedded in the insulating layer, wherein the second floating pattern comprises: The area overlapping with the third signal terminal, and The area overlapping with the fourth signal terminal, wherein the second floating pattern is electrically disconnected from the third and fourth signal terminals.

9. The circuit board of claim 8 further includes one or more channels embedded in the insulating layer, the one or more channels connecting the first floating pattern and the second floating pattern.

10. The circuit board of claim 1, wherein the circuit board includes a plurality of internal wiring layers embedded in the insulating layer. The first floating pattern is located at the same level as the inner wiring layer closest to the plurality of first terminals among the plurality of inner wiring layers.

11. The circuit board of claim 1, wherein the first signal terminal and the second signal terminal are included in a plurality of signal terminals, and the plurality of signal terminals are included in the plurality of first terminals. The first floating pattern is included in a plurality of floating patterns, and Each of the plurality of floating patterns is embedded in the insulating layer, including a corresponding area that overlaps with an adjacent signal terminal among the plurality of signal terminals, and is electrically disconnected from the plurality of signal terminals.

12. The circuit board of claim 1, wherein the outer surface of the first floating pattern is covered with the insulating layer.

13. A semiconductor module, comprising: Circuit board; and One or more semiconductor packages are located on the circuit board. The circuit board includes: An insulating layer having a first surface and a second surface opposite to each other; A plurality of first terminals, located on the first surface of the insulating layer, include a first signal terminal and a second signal terminal; and A first floating pattern is embedded in the insulating layer, the first floating pattern including a first region overlapping the first signal terminal and a second region overlapping the second signal terminal. Wherein the first floating pattern is electrically disconnected from the first signal terminal and the second signal terminal, and The plurality of first terminals are arranged sequentially along a first direction in the edge region of the circuit board.

14. The semiconductor module of claim 13, wherein the semiconductor module includes a memory module.

15. The semiconductor module of claim 13, wherein the width of the first floating pattern in the second direction is equal to or narrower than the width of each of the first signal terminal and the second signal terminal in the second direction, and wherein the second direction intersects the first direction.

16. The semiconductor module of claim 13, wherein the plurality of first terminals further includes a ground terminal located between the first signal terminal and the second signal terminal. The first floating pattern includes a third region overlapping the grounding terminal, and The width of the first floating pattern in the third region in the second direction is narrower than each of the width of the first floating pattern in the first region in the second direction and the width of the first floating pattern in the second region in the second direction, wherein the second direction intersects the first direction.

17. The semiconductor module of claim 16, wherein the first floating pattern is electrically disconnected from the ground terminal.

18. The semiconductor module according to claim 13, further comprising: A plurality of second terminals are located on the second surface of the insulating layer and include a third signal terminal and a fourth signal terminal; The second floating pattern is located horizontally between the first floating pattern and the plurality of second terminals and is embedded in the insulating layer. The second floating pattern includes an area overlapping the third signal terminal and an area overlapping the fourth signal terminal, wherein the second floating pattern is electrically disconnected from the third signal terminal and the fourth signal terminal; as well as One or more pathways are embedded in the insulating layer and connect the first floating pattern and the second floating pattern.

19. The semiconductor module of claim 13, wherein the circuit board includes a plurality of internal wiring layers embedded in the insulating layer, and The first floating pattern is located at the same level as the inner wiring layer that is closest to the plurality of first terminals among the plurality of inner wiring layers.

20. A semiconductor system, comprising: motherboard; Connector, located on the motherboard; as well as A semiconductor module, coupled to the connector, includes a circuit board and one or more semiconductor packages located on the circuit board, wherein the circuit board includes: An insulating layer having a first surface and a second surface opposite to each other; Multiple terminals, located on the first surface of the insulating layer and configured to include a first signal terminal and a second signal terminal; and A floating pattern is embedded in the insulating layer, wherein the floating pattern includes a first region overlapping the first signal terminal and a second region overlapping the second signal terminal. The floating pattern is electrically disconnected from the first signal terminal and the second signal terminal, and The plurality of terminals are arranged in the edge region of the circuit board and configured to be inserted into the connector.

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