Thin film transistor memory, method of manufacture and electronic device

Abstract

This application discloses a thin-film transistor (TFT) memory, its fabrication method, and an electronic device, belonging to the field of memory technology. The TFT memory includes: a substrate, an insulating layer, a charge trapping layer, a tunneling layer, an active layer, a source electrode, and a drain electrode. A target electrode is disposed on the side of the tunneling layer opposite to the charge trapping layer, and is electrically isolated from the active layer. The target electrode is located on one side of the channel region. The substrate serves as the gate electrode. During write or erase operations on the TFT memory, a voltage is applied to the gate electrode and the target electrode. The TFT memory constructs a four-terminal electrode control system by asymmetrically introducing the target electrode in the channel region. By applying a voltage to the target electrode and the gate electrode, the electric field between the active layer and the charge trapping layer is controlled, injecting a large number of holes into the charge trapping layer, effectively improving the erase efficiency.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of memory, and particularly relates to a thin film transistor memory, a preparation method and an electronic device. BACKGROUND

[0002] With the development of semiconductor storage technology towards high density and low power consumption, the metal oxide thin film transistor (TFT) based memory has become an important research direction of new memory devices due to its advantages such as wide band gap characteristics (3.0eV-4.5eV), low temperature process compatibility (less than 350℃), excellent storage window (more than 10V) and good durability (more than 10 4 cycles).

[0003] However, due to the lack of holes in the metal oxide, it is difficult to perform an erase operation after a write operation is performed on the memory device, and the data erase efficiency is low. SUMMARY

[0004] The present application aims to at least solve one of the technical problems existing in the prior art. To this end, the present application provides a thin film transistor memory, a preparation method and an electronic device, which can inject a large number of holes into the charge trapping layer, compensate for the lack of holes in the metal oxide, and effectively improve the erase efficiency.

[0005] In a first aspect, the present application provides a thin film transistor memory, comprising:

[0006] a substrate;

[0007] an insulating layer disposed on one side of the substrate;

[0008] a charge trapping layer disposed on a side of the insulating layer away from the substrate, the material of the charge trapping layer comprising a metal oxide;

[0009] a tunneling layer disposed on a side of the charge trapping layer away from the insulating layer;

[0010] an active layer disposed on a side of the tunneling layer away from the charge trapping layer, the material of the active layer comprising a metal oxide;

[0011] a source electrode and a drain electrode disposed on a side of the tunneling layer away from the charge trapping layer, the source electrode and the drain electrode being in electrical contact with the active layer, and a channel region being formed between the source electrode and the drain electrode;

[0012] a target electrode disposed on a side of the tunneling layer away from the charge trapping layer, the target electrode being electrically isolated from the active layer, and the target electrode being located on one side of the channel region;

[0013] The substrate is used as a gate electrode, and a voltage is applied to the gate electrode and the target electrode when the thin film transistor memory is subjected to a write operation or an erase operation.

[0014] According to the thin film transistor memory, the target electrode is introduced to construct a four-terminal electrode control system, the target electrode is located on one side of the channel region, i.e., asymmetrically integrated in the channel region, and a voltage is applied to the target electrode and the gate electrode to control the electric field force between the active layer and the charge trapping layer, so that a large number of holes are injected into the charge trapping layer, and the erase efficiency is effectively improved.

[0015] According to an embodiment of the present application, the distance between the target electrode and the drain electrode or the source electrode is a target distance.

[0016] The target distance is in a positive correlation with a voltage value of the voltage applied to the target electrode when the thin film transistor memory is subjected to an erase operation.

[0017] The target distance is in a positive correlation with a time length of the voltage applied to the target electrode when the thin film transistor memory is subjected to an erase operation.

[0018] According to an embodiment of the present application, the target distance is 200 µm-600 µm.

[0019] According to an embodiment of the present application, the material of the target electrode includes at least one of aluminum and molybdenum.

[0020] According to an embodiment of the present application, the thickness of the target electrode is 80 nm-120 nm.

[0021] According to an embodiment of the present application, the material of the tunneling layer includes at least one of aluminum oxide and hafnium dioxide, and / or the thickness of the tunneling layer is 3 nm-10 nm.

[0022] According to an embodiment of the present application, the metal oxide of the charge trapping layer includes at least one of zinc oxide, indium zinc oxide, indium gallium zinc oxide, and indium tungsten oxide, and the thickness of the charge trapping layer is 10 nm-15 nm.

[0023] And / or, the metal oxide of the active layer includes at least one of zinc oxide, indium zinc oxide, indium gallium zinc oxide, and indium tungsten oxide, and the thickness of the active layer is 30 nm-50 nm.

[0024] According to an embodiment of the present application, the substrate is N-type heavily doped silicon or P-type heavily doped silicon.

[0025] And / or, the material of the insulating layer includes at least one of silicon dioxide, aluminum oxide, hafnium dioxide, and hafnium nitride, and the thickness of the insulating layer is 100 nm-200 nm.

[0026] and / or, the material of the source electrode comprises at least one of aluminum and molybdenum, and the thickness of the source electrode is 50-100 nm;

[0027] and / or, the material of the drain electrode comprises at least one of aluminum and molybdenum, and the thickness of the drain electrode is 50-100 nm.

[0028] In a second aspect, the application provides a preparation method of a thin film transistor memory, comprising:

[0029] preparing an insulating layer on one side of a substrate by plasma enhanced chemical vapor deposition;

[0030] depositing a metal oxide by a radio frequency magnetron sputtering process to form a charge trapping layer on the side of the insulating layer away from the substrate;

[0031] forming a tunneling layer on the side of the charge trapping layer away from the insulating layer by atomic layer deposition;

[0032] depositing a metal oxide by a radio frequency magnetron sputtering process to form an active layer on the side of the tunneling layer away from the charge trapping layer;

[0033] depositing an electrode material by a radio frequency magnetron sputtering process to form a source electrode, a drain electrode and a target electrode on the side of the tunneling layer away from the charge trapping layer, the source electrode and the drain electrode are in electrical contact with the active layer, a channel region is formed between the source electrode and the drain electrode, the target electrode is electrically isolated from the active layer, and the target electrode is located on one side of the channel region;

[0034] wherein the substrate serves as a gate electrode, and when performing a write operation or an erase operation on the thin film transistor memory, a voltage is applied to the gate electrode and the target electrode.

[0035] According to the preparation method of the thin film transistor memory, the target electrode is introduced on one side of the channel region to construct a four-electrode regulation system, the electric field force between the active layer and the charge trapping layer is regulated by applying a voltage to the target electrode and the gate electrode, a large number of holes are injected into the charge trapping layer, the erase efficiency is effectively improved, the existing preparation process can be compatible, and the device preparation cost is reduced.

[0036] In a third aspect, the application provides an electronic device, comprising:

[0037] The thin film transistor memory as described in the first aspect above.

[0038] Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following description and drawings. BRIEF DESCRIPTION OF DRAWINGS

[0039] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0040] Figure 1 This is one of the structural schematic diagrams of the thin-film transistor memory provided in the embodiments of this application;

[0041] Figure 2 This is a second schematic diagram of the structure of the thin-film transistor memory provided in the embodiments of this application;

[0042] Figure 3 This is a schematic diagram of the transfer characteristic curve of the thin-film transistor memory provided in the embodiments of this application;

[0043] Figure 4 This is one of the schematic flowcharts of the fabrication method of the thin-film transistor memory provided in the embodiments of this application;

[0044] Figure 5 This is the second schematic flowchart of the method for fabricating a thin-film transistor memory provided in the embodiments of this application.

[0045] Figure label:

[0046] Substrate 110, insulating layer 120, charge trapping layer 130, tunneling layer 140, active layer 150, source electrode 161, drain electrode 162, target electrode 170. Detailed Implementation

[0047] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0048] Due to the physical characteristic of metal oxides having an intrinsic hole mobility that is too low (less than 1 cm² / V·s), memory devices in related technologies suffer from defects such as low carrier injection efficiency (less than 20%) and high erase voltage (greater than 20V) during erase operations, which seriously restricts the practical application of memory devices.

[0049] This application provides a thin-film transistor memory that can inject a large number of holes into the charge trapping layer 130 to compensate for the lack of holes in metal oxides, thereby effectively improving carrier injection efficiency, reducing erase voltage, and improving erase efficiency.

[0050] The following is for reference. Figures 1-5 This application describes a thin-film transistor memory, a method for fabricating a thin-film transistor memory, and an electronic device according to embodiments of the present application.

[0051] like Figure 1 As shown, the thin-film transistor memory includes a substrate 110, an insulating layer 120, a charge trapping layer 130, a tunneling layer 140, an active layer 150, a source electrode 161, a drain electrode 162, and a target electrode 170.

[0052] The substrate 110 serves as the gate of the thin-film transistor memory, and the substrate 110 can be a doped silicon substrate.

[0053] In some embodiments, the substrate 110 is N-type heavily doped silicon or P-type heavily doped silicon.

[0054] Silicon is doped by adding pentavalent elements such as phosphorus, arsenic, and antimony. These pentavalent elements have one more valence electron than silicon, and the doping will provide additional free electrons, making silicon an N-type semiconductor. When the doping concentration is high (exceeding a preset threshold), it is called heavily doped N-type silicon.

[0055] Adding trivalent elements, such as boron, aluminum, and gallium, to silicon for doping creates holes in the silicon lattice, making silicon a P-type semiconductor. When the doping concentration is high (exceeding a preset threshold), it is called heavily doped P-type silicon.

[0056] Understandably, the substrate 110 is the mechanical support base of the thin-film transistor memory, and the insulating layer 120, charge trapping layer 130, tunneling layer 140, active layer 150, source electrode 161, drain electrode 162 and target electrode 170 are constructed on the substrate 110.

[0057] The charge trapping layer 130 can trap and retain charges (electrons or holes) and is the storage film structure of a thin-film transistor memory. Injecting charges into the charge trapping layer 130 can change the transistor threshold voltage, and the magnitude of the threshold voltage represents the stored data.

[0058] In this embodiment, the material of the charge trapping layer 130 includes metal oxide, that is, the thin-film transistor memory is a metal oxide TFT-based memory.

[0059] In some embodiments, the metal oxide of the charge trapping layer 130 includes at least one of zinc oxide, indium zinc oxide, indium gallium zinc oxide, and indium tungsten oxide.

[0060] In practice, the charge trapping layer 130 may include one or more metal oxides selected from zinc oxide, indium zinc oxide, indium gallium zinc oxide, and indium tungsten oxide.

[0061] In some embodiments, the thickness of the charge trapping layer 130 is 10 nm to 15 nm.

[0062] For example, the thickness of the charge trapping layer 130 can be 10 nm, 11 nm, 12 nm, 13 nm, 14 nm or 15 nm.

[0063] In this embodiment, the insulating layer 120 is disposed on one side of the substrate 110, and the charge trapping layer 130 is disposed on the side of the insulating layer 120 away from the substrate 110. That is, the insulating layer 120 is located between the gate and the charge trapping layer 130. The insulating layer 120 can prevent charge from moving between the gate and the charge trapping layer 130, so that the charge trapped by the charge trapping layer 130 can be stored for a long time, thereby ensuring the non-volatility of data.

[0064] In some embodiments, the material of the insulating layer 120 includes at least one of silicon dioxide, aluminum oxide, hafnium dioxide, and hafnium nitride.

[0065] In actual implementation, the material of the insulating layer 120 may include one or more of silicon dioxide, aluminum oxide, hafnium dioxide and hafnium nitride. The insulating layer 120 may be a single-layer structure or a multi-layer stacked structure, such as a three-layer stacked structure of silicon dioxide-alumina-silicon dioxide-silicon dioxide.

[0066] In some embodiments, the thickness of the insulating layer 120 is 100nm-200nm.

[0067] For example, the thickness of the insulating layer 120 can be 100nm, 120nm, 150nm, 170nm, 180nm or 200nm.

[0068] It is understandable that the active layer 150 is a film layer structure that forms a conductive channel in a thin-film transistor memory. In a thin-film transistor memory, the current between the source 161 and the drain 162 can flow in the active layer 150. By adjusting the voltage applied to the gate, the conductivity state of the active layer 150 can be controlled.

[0069] The active layer 150 is made of metal oxide.

[0070] In some embodiments, the metal oxide of the active layer 150 includes at least one of zinc oxide, indium zinc oxide, indium gallium zinc oxide, and indium tungsten oxide.

[0071] In practice, the active layer 150 may include one or more metal oxides selected from zinc oxide, indium zinc oxide, indium gallium zinc oxide, and indium tungsten oxide.

[0072] In some embodiments, the thickness of the active layer 150 is 30nm-50nm.

[0073] For example, the thickness of the active layer 150 can be 30nm, 35nm, 40nm, 45nm or 50nm.

[0074] In this embodiment, the tunneling layer 140 is disposed on the side of the charge trapping layer 130 facing away from the insulating layer 120, and the active layer 150 is disposed on the side of the tunneling layer 140 facing away from the charge trapping layer 130. That is, the tunneling layer 140 is located between the active layer 150 and the charge trapping layer 130, allowing charges to enter or leave the charge trapping layer 130 through the tunneling layer 140 under certain operating conditions, thereby realizing the writing or erasing of thin-film transistor memory data.

[0075] In some embodiments, the material of the tunneling layer 140 includes at least one of alumina and hafnium dioxide.

[0076] In some embodiments, the thickness of the tunneling layer 140 is 3 nm to 10 nm.

[0077] For example, the thickness of the tunneling layer 140 can be 3 nm, 5 nm or 10 nm.

[0078] It should be noted that different thicknesses of the tunneling layer 140 will result in different erasure effects when performing an erase operation on a thin-film transistor memory.

[0079] In actual operation, when erasing a thin-film transistor memory, the thickness of the tunneling layer 140 is negatively correlated with the voltage value and duration applied to the thin-film transistor memory. For example, for a 10nm thick tunneling layer 140, a long-term, large-amplitude erase voltage is required. For a 3nm or 5nm thick tunneling layer 140, a short-term, small-amplitude erase voltage is sufficient to achieve complete erasure.

[0080] In this embodiment, source 161 and drain 162 are disposed on the side of tunneling layer 140 away from charge trapping layer 130, source 161 and drain 162 are electrically in contact with active layer 150, and a channel region is formed between source 161 and drain 162.

[0081] In some embodiments, the source electrode 161 is made of at least one of aluminum and molybdenum.

[0082] In some embodiments, the thickness of the source electrode 161 is 50nm-100nm.

[0083] For example, the thickness of the source 161 can be 50nm, 70nm, 80nm or 100nm.

[0084] In some embodiments, the material of the drain 162 includes at least one of aluminum and molybdenum.

[0085] In some embodiments, the thickness of the drain 162 is 50nm-100nm.

[0086] For example, the thickness of the drain 162 can be 50nm, 70nm, 80nm or 100nm.

[0087] In actual implementation, the source 161 and drain 162 can be located at opposite ends of the active layer 150. The source 161 and drain 162 form an ohmic contact with the active layer 150. In a thin-film transistor memory, the conductivity state of the channel region in the active layer 150 can be controlled by adjusting the gate voltage.

[0088] It should be noted that, in addition to the gate, source 161 and drain 162, the thin film transistor memory also has a target electrode 170. The target electrode 170 is disposed on the side of the tunneling layer 140 away from the charge trapping layer 130. The target electrode 170 can be located at the same level as the source 161 and drain 162.

[0089] In this embodiment, the target electrode 170 is electrically isolated from the active layer 150, and the target electrode 170 is located on one side of the channel region.

[0090] It should be noted that the target electrode 170 is located on one side of the channel region. A fourth terminal control electrode, in addition to the gate, source 161 and drain 162, is asymmetrically integrated in the channel region. Applying a forward bias voltage to the target electrode 170 can form a strong electric field at the interface between the electrode layer where the target electrode 170, source 161 and drain 162 are located and the charge trapping layer 130, inducing the Fowler-Nordheim (FN) tunneling effect and realizing the efficient injection of hole carriers in the charge trapping layer 130.

[0091] It is understandable that the holes injected into the charge trapping layer 130 will undergo a recombination dynamic process with the electrons trapped in the charge trapping layer 130. Through the diffusion-recombination coupling mechanism driven by the carrier concentration gradient, the potential of the storage node is reduced, the barrier reconstruction of the erase operation is completed, and the efficiency of the erase operation is improved.

[0092] In this embodiment, when performing a write or erase operation on the thin-film transistor memory, a voltage is applied to the gate and the target electrode 170.

[0093] In a thin-film transistor memory, a voltage is applied to the gate and target electrode 170, and the movement of charges in the thin-film transistor memory is controlled by the electric field. During a write operation, electrons are injected into the charge trapping layer 130 and captured by the charge trapping layer 130, which increases the transistor threshold voltage. During an erase operation, holes are injected into the charge trapping layer 130 and recombine with the electrons trapped in the charge trapping layer 130, which decreases the transistor threshold voltage. By modulating the threshold voltage through the charge storage state, data writing and operation are realized.

[0094] It should be noted that when performing write or erase operations, the greater the applied voltage amplitude, the shorter the time required to apply the voltage.

[0095] In related technologies, charge-capture memories based on metal oxides are limited by the lack of holes in metal oxides, making it difficult to erase data after a write operation. Extremely large voltage and optical assistance are required to completely erase data, resulting in low data erasure efficiency and limiting the practical application of the memory.

[0096] The inventors of this application have discovered that during a write operation, by applying a positive bias voltage to the gate, the majority carriers (i.e., electrons) in the active layer 150 tunnel through FN into the charge trapping layer 130 under the influence of an electric field, and are trapped by traps in the charge trapping layer 130. The write operation causes the device transfer characteristic curve to be positively biased. During an erase operation, by applying a negative bias voltage to the gate, the holes in the active layer 150 tunnel into the charge trapping layer 130 and recombine with the trapped electrons. The erase operation causes the device transfer characteristic curve to be negatively biased back to the initial state. The hole concentration in the active layer 150 directly affects the memory erase efficiency.

[0097] In this embodiment, in addition to the gate, source 161, and drain 162, a fourth terminal electrode, namely the target electrode 170, is introduced on one side of the channel region. The target electrode 170 is asymmetrically integrated in the channel region. By applying a voltage to the target electrode 170, a strong electric field is formed between the active layer 150 and the charge trapping layer 130, inducing the FN tunneling effect and injecting a large number of holes into the charge trapping layer 130. This compensates for the lack of holes in the metal oxide active film layer in related technologies. The holes injected into the charge trapping layer 130 recombine with the bound electrons, reducing the potential of the storage node and completing the barrier reconstruction for the erase operation. The device threshold voltage offset can be fully recovered, effectively improving the erase efficiency and constructing a high-performance thin-film transistor memory.

[0098] According to the thin-film transistor memory provided in the embodiments of this application, a four-terminal electrode control system is constructed by introducing a target electrode 170. The target electrode 170 is located on one side of the channel region, that is, it is asymmetrically integrated in the channel region. By applying a voltage to the target electrode 170 and the gate, the electric field force between the active layer 150 and the charge trapping layer 130 is controlled, and a large number of holes are injected into the charge trapping layer 130, which effectively improves the erasure efficiency.

[0099] In actual implementation, the target electrode 170 can be located on the side closer to the drain electrode 162 or on the side closer to the source electrode 161.

[0100] In some embodiments, the distance between the target electrode 170 and the drain electrode 162 or the source electrode 161 is the target distance.

[0101] Taking the target electrode 170 located on the side close to the drain electrode 162 as an example, such as Figure 2 As shown, the distance between the target electrode 170 and the drain electrode 162 is the target distance D1.

[0102] It should be noted that the size of the target spacing will affect the erasure effect during the erasure operation.

[0103] In this embodiment, the target spacing is positively correlated with the voltage value applied to the target electrode 170 during the erase operation of the thin-film transistor memory; the target spacing is positively correlated with the duration of the voltage applied to the target electrode 170 during the erase operation of the thin-film transistor memory.

[0104] When the target spacing is small, that is, when the target electrode 170 is close to the drain 162 or the source 161, applying a small voltage value to the target electrode 170 for a short time can restore the device threshold voltage to the initial state and complete the erasure operation.

[0105] When the target spacing is large, that is, when the distance between the target electrode 170 and the drain 162 or the source 161 is far, applying a large voltage value to the target electrode 170 for a long time can restore the device threshold voltage to the initial state and complete the erasure operation.

[0106] In some embodiments, the target spacing is 200µm-600µm.

[0107] For example, the target spacing D1 between the target electrode 170 and the drain electrode 162 can be 200µm, 400µm or 600µm.

[0108] In some embodiments, the material of the target electrode 170 includes at least one of aluminum and molybdenum.

[0109] In practice, the target electrode 170 can be made of the same electrode material as the source electrode 161 and the drain electrode 162. For example, the source electrode 161, the drain electrode 162 and the target electrode 170 are all made of aluminum.

[0110] In this embodiment, the material of the target electrode 170 includes at least one of aluminum and molybdenum, and the thin-film transistor memory is compatible with existing fabrication processes, which helps to reduce the cost of device fabrication.

[0111] In some embodiments, the thickness of the target electrode 170 is 80 nm to 120 nm.

[0112] For example, the thickness of the target electrode 170 can be 80 nm, 100 nm or 120 nm.

[0113] In this embodiment, by optimizing the device structure, a fourth electrode (i.e., target electrode 170) is introduced as an additional control terminal on the basis of the source, drain, and gate three-terminal TFT charge capture memory architecture, and a four-terminal electrode control system is constructed. Combined with the optimization of parameters such as target spacing and tunneling layer 140 thickness, the erasure efficiency of metal oxide-based thin film transistor memory is significantly improved while being fully compatible with existing fabrication processes.

[0114] The following is a specific example.

[0115] like Figure 3 As shown, a fourth terminal electrode is introduced on one side of the channel region. Initial represents the transfer characteristic curve of the thin-film transistor memory in the initial state, Programed represents the transfer characteristic curve of the thin-film transistor memory in the write state, and Erased represents the transfer characteristic curve of the thin-film transistor memory in the erase state. Under the operating conditions of low erase voltage and short pressure application time, the transfer characteristic curve can be negatively biased to the initial state.

[0116] In this embodiment, by applying a voltage to the target electrode 170, a strong electric field is formed between the active layer 150 and the charge trapping layer 130, inducing the FN tunneling effect and injecting a large number of holes into the charge trapping layer 130. By establishing a physical mechanism for enhancing the hole injection path, the tunneling recombination efficiency of the charge carriers stored in the charge trapping layer 130 is effectively improved, and the erasure speed is effectively increased.

[0117] This application also provides a method for fabricating a thin-film transistor memory.

[0118] like Figure 4 As shown, the fabrication method of the thin-film transistor memory includes steps 410, 420, 430, 440 and 450.

[0119] Step 410: Prepare an insulating layer 120 on one side of the substrate 110 by plasma-enhanced chemical vapor deposition.

[0120] Plasma-enhanced chemical vapor deposition (PECVD) combines chemical vapor deposition with plasma technology, enabling the production of high-quality thin films and precise control over film properties.

[0121] It is understandable that the substrate 110 serves as the gate of the thin-film transistor memory, and the substrate 110 can be a doped silicon substrate.

[0122] In some embodiments, the substrate 110 is N-type heavily doped silicon or P-type heavily doped silicon.

[0123] In some embodiments, the material of the insulating layer 120 includes at least one of silicon dioxide, aluminum oxide, hafnium dioxide, and hafnium nitride.

[0124] In this step, an insulating layer 120 can be prepared on one side of the substrate 110 by plasma-enhanced chemical vapor deposition of at least one of silicon dioxide, aluminum oxide, hafnium dioxide and hafnium nitride.

[0125] Step 420: Deposit metal oxide using radio frequency magnetron sputtering process to form a charge trapping layer 130 on the side of insulating layer 120 facing away from substrate 110.

[0126] Magnetron sputtering is a process that uses a high-frequency electric field and a static magnetic field in a vacuum environment to create plasma on the surface of a target. Then, ions bombard the target to release atoms or molecules, which are deposited at high speed onto the substrate surface to form a thin film. It features low deposition temperature, high film quality, and high uniformity.

[0127] In this step, a metal oxide is deposited by radio frequency magnetron sputtering to form a charge trapping layer 130 on the side of the insulating layer 120 facing away from the substrate 110.

[0128] In some embodiments, the metal oxide of the charge trapping layer 130 includes at least one of zinc oxide, indium zinc oxide, indium gallium zinc oxide, and indium tungsten oxide.

[0129] In some embodiments, the thickness of the charge trapping layer 130 is 10 nm to 15 nm.

[0130] Step 430: By atomic layer deposition, a tunneling layer 140 is formed on the side of the charge trapping layer 130 facing away from the insulating layer 120.

[0131] Atomic layer deposition (ALD) can deposit materials onto a substrate surface in the form of a single-atom film.

[0132] In this step, a high-dielectric material can be deposited by atomic layer deposition to form a tunneling layer 140 on the side of the charge trapping layer 130 facing away from the insulating layer 120.

[0133] High dielectric materials, also known as high-k materials, refer to insulating materials whose dielectric constant (k) is significantly higher than that of silicon dioxide.

[0134] In some embodiments, the material of the tunneling layer 140 includes at least one of alumina and hafnium dioxide.

[0135] Step 440: Deposit metal oxide using radio frequency magnetron sputtering process to form an active layer 150 on the side of the tunneling layer 140 facing away from the charge trapping layer 130.

[0136] In some embodiments, the metal oxide of the active layer 150 includes at least one of zinc oxide, indium zinc oxide, indium gallium zinc oxide, and indium tungsten oxide.

[0137] In some embodiments, the thickness of the active layer 150 is 30nm-50nm.

[0138] Step 450: Electrode material is deposited by radio frequency magnetron sputtering process to form source 161, drain 162 and target electrode 170 on the side of tunneling layer 140 opposite to charge trapping layer 130.

[0139] In this configuration, the source electrode 161 and the drain electrode 162 are electrically connected to the active layer 150, and a channel region is formed between the source electrode 161 and the drain electrode 162. The target electrode 170 is electrically isolated from the active layer 150 and is located on one side of the channel region.

[0140] In some embodiments, the source electrode 161 is made of at least one of aluminum and molybdenum.

[0141] In some embodiments, the thickness of the source electrode 161 is 50nm-100nm.

[0142] In some embodiments, the material of the drain 162 includes at least one of aluminum and molybdenum.

[0143] In some embodiments, the thickness of the drain 162 is 50nm-100nm.

[0144] In some embodiments, the material of the target electrode 170 includes at least one of aluminum and molybdenum.

[0145] In some embodiments, the thickness of the target electrode 170 is 80 nm to 120 nm.

[0146] In practice, the target electrode 170 can be fabricated using the same electrode material as the source electrode 161 and the drain electrode 162, which is compatible with existing fabrication processes and helps to reduce device fabrication costs.

[0147] In this embodiment, when performing a write or erase operation on the thin-film transistor memory, a voltage is applied to the gate and the target electrode 170.

[0148] In some embodiments, the distance between the target electrode 170 and the drain electrode 162 or the source electrode 161 is the target distance.

[0149] In this embodiment, the target spacing is positively correlated with the voltage value applied to the target electrode 170 during the erase operation of the thin-film transistor memory; the target spacing is positively correlated with the duration of the voltage applied to the target electrode 170 during the erase operation of the thin-film transistor memory.

[0150] In some embodiments, the target spacing is 200µm-600µm.

[0151] According to the method for fabricating a thin-film transistor memory provided in the embodiments of this application, a four-terminal electrode control system is constructed by introducing a target electrode 170 on one side of the channel region. By applying a voltage to the target electrode 170 and the gate, the electric field force between the active layer 150 and the charge trapping layer 130 is controlled, and a large number of holes are injected into the charge trapping layer 130, which effectively improves the erasure efficiency. It is compatible with existing fabrication processes and reduces the device fabrication cost.

[0152] The following is a specific example.

[0153] like Figure 5 As shown, using N-type heavily doped silicon as substrate 110, an insulating layer 120 is prepared on substrate 110 with a silicon dioxide layer 100 nm thick by PECVD.

[0154] Subsequently, using radio frequency magnetron sputtering, combined with patterning of the trapping layer mask, indium zinc oxide metal oxide was deposited to prepare a 10 nm thick charge trapping layer 130 on the insulating layer 120.

[0155] Then, using atomic layer deposition, a 5 nm thick layer of alumina is deposited as the tunneling layer 140.

[0156] The radio frequency magnetron sputtering process was used again, combined with an active mask for patterning, to deposit indium zinc oxide metal oxide to form a 30nm active layer 150.

[0157] Aluminum is deposited using radio frequency magnetron sputtering to prepare source electrode 161, drain electrode 162 and target electrode 170. The target spacing can be adjusted by using a mask. The thickness of source electrode 161, drain electrode 162 and target electrode 170 can be the same or different.

[0158] The fabricated device was annealed in a muffle furnace at 200°C in an air atmosphere for 10-20 minutes.

[0159] In this embodiment, a fourth control electrode, namely the target electrode 170, is introduced on the basis of the three-terminal structure of source 161, drain 162 and gate. By applying a bias voltage to the gate and the target electrode 170, a large number of holes can be injected into the charge trapping layer 130, which effectively improves the erasure efficiency of the device. Experiments show that, compared with the traditional three-terminal structure, after introducing the fourth control electrode, the device can be effectively erased by applying a low erasure voltage and a short pulse time.

[0160] This application also provides an electronic device.

[0161] The electronic device includes a thin-film transistor memory as described above.

[0162] The electronic device can be a terminal or other devices besides a terminal. For example, the electronic device can be a mobile phone, tablet computer, laptop computer, handheld computer, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), television (TV), ATM, or self-service machine, etc. The embodiments of this application do not specifically limit it.

[0163] According to the electronic device provided in the embodiments of this application, a four-terminal electrode control system is constructed by introducing a target electrode 170. The target electrode 170 is located on one side of the channel region, that is, it is asymmetrically integrated in the channel region. By applying a voltage to the target electrode 170 and the gate, the electric field force between the active layer 150 and the charge trapping layer 130 is controlled, and a large number of holes are injected into the charge trapping layer 130, which effectively improves the erasure efficiency.

[0164] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0165] In the description of this application, it should be understood that the terms "thickness", "upper", "lower", "front", "rear", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0166] In the description of this application, "first feature" and "second feature" may include one or more of the features.

[0167] In the description of this application, "multiple" means two or more.

[0168] In the description of this application, the first feature being "above" or "below" the second feature may include the first and second features being in direct contact, or the first and second features being in contact through another feature between them.

[0169] In the description of this application, the terms "above," "over," and "on top" for the first feature and the second feature include the first feature being directly above or diagonally above the second feature, or simply indicate that the first feature is at a higher horizontal level than the second feature.

[0170] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0171] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A thin-film transistor memory, characterized in that, include: Substrate; An insulating layer is disposed on one side of the substrate; A charge trapping layer is disposed on the side of the insulating layer opposite to the substrate, and the material of the charge trapping layer includes metal oxide; A tunneling layer is disposed on the side of the charge trapping layer opposite to the insulating layer; An active layer is disposed on the side of the tunneling layer opposite to the charge trapping layer, and the material of the active layer includes a metal oxide; The source and drain are disposed on the side of the tunneling layer opposite to the charge trapping layer, and the source and drain are electrically in contact with the active layer, forming a channel region between the source and drain; The target electrode is disposed on the side of the tunneling layer opposite to the charge trapping layer. The target electrode is electrically isolated from the active layer and is located on one side of the channel region. Wherein, the substrate serves as the gate, and when writing or erasing the thin-film transistor memory, a voltage is applied to the gate and the target electrode.

2. The thin-film transistor memory according to claim 1, characterized in that, The distance between the target electrode and the drain electrode or the source electrode is the target distance; The target spacing is positively correlated with the voltage value applied to the target electrode when the thin-film transistor memory is erased; The target spacing is positively correlated with the duration of voltage applied to the target electrode during the erase operation of the thin-film transistor memory.

3. The thin-film transistor memory according to claim 2, characterized in that, The target spacing is 200µm-600µm.

4. The thin-film transistor memory according to claim 1, characterized in that, The target electrode is made of at least one of aluminum and molybdenum.

5. The thin-film transistor memory according to claim 1, characterized in that, The thickness of the target electrode is 80nm-120nm.

6. The thin-film transistor memory according to claim 1, characterized in that, The material of the tunneling layer includes at least one of alumina and hafnium dioxide, and / or the thickness of the tunneling layer is 3nm-10nm.

7. The thin-film transistor memory according to any one of claims 1-6, characterized in that, The metal oxide of the charge trapping layer includes at least one of zinc oxide, indium zinc oxide, indium gallium zinc oxide, and indium tungsten oxide, and the thickness of the charge trapping layer is 10 nm-15 nm; And / or, the metal oxide of the active layer includes at least one of zinc oxide, indium zinc oxide, indium gallium zinc oxide, and indium tungsten oxide, and the thickness of the active layer is 30nm-50nm.

8. The thin-film transistor memory according to any one of claims 1-6, characterized in that, The substrate is N-type heavily doped silicon or P-type heavily doped silicon; And / or, the material of the insulating layer includes at least one of silicon dioxide, aluminum oxide, hafnium dioxide and hafnium nitride, and the thickness of the insulating layer is 100nm-200nm; And / or, the source electrode is made of at least one of aluminum and molybdenum, and the thickness of the source electrode is 50 nm to 100 nm; And / or, the material of the drain electrode includes at least one of aluminum and molybdenum, and the thickness of the drain electrode is 50nm-100nm.

9. A method for fabricating a thin-film transistor memory, characterized in that, include: An insulating layer is prepared on one side of the substrate by plasma-enhanced chemical vapor deposition; A charge trapping layer is formed on the side of the insulating layer away from the substrate by depositing metal oxides using a radio frequency magnetron sputtering process. A tunneling layer is formed on the side of the charge trapping layer opposite to the insulating layer by atomic layer deposition; An active layer is formed on the side of the tunneling layer opposite to the charge trapping layer by depositing metal oxide using a radio frequency magnetron sputtering process. Electrode material is deposited using a radio frequency magnetron sputtering process to form a source, drain, and target electrode on the side of the tunneling layer opposite to the charge trapping layer. The source and drain are electrically in contact with the active layer, and a channel region is formed between the source and drain. The target electrode is electrically isolated from the active layer and is located on one side of the channel region. Wherein, the substrate serves as the gate, and when writing or erasing the thin-film transistor memory, a voltage is applied to the gate and the target electrode.

10. An electronic device, characterized in that, include: The thin-film transistor memory as described in any one of claims 1-8.

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