Row decoder and row address scheme in memory system

Abstract

Numerous examples of a row address decoding scheme are disclosed. In one example, a memory system includes: m banks of non-volatile memory cells, the m banks each including n or less sectors, and the sectors each including p rows; and a row decoder for receiving a row address comprising r bits and for (i) identifying a row using the least significant t bits of the r bits, (ii) identifying a memory bank using the next u least significant bits, and (iii) identifying a sector using the next v least significant bits, where m < = 2u, n < = 2v, and p < = 2t.

Description

[0001] Priority Statement

[0002] This application claims priority to U.S. Patent Application No. 18 / 206,488, filed June 6, 2023, entitled “Row Decoder and Row Address Scheme in a Memory System”, and U.S. Provisional Patent Application No. 63 / 457,751, filed April 6, 2023, entitled “Row Address Decoding Scheme for Memory Banks Comprising Any Number of Sectors”. Technical Field

[0003] Numerous examples of row address decoding schemes are disclosed, which uniquely identify each row in a memory system by the bank, sector, and row within the sector. Background Technology

[0004] Prior art includes non-volatile memories. For example, U.S. Patent 5,029,130 ​​(“130 Patent”), incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, which is a type of flash memory cell. Such a memory cell 110 is shown in FIG. 1. Each memory cell 110 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source and drain regions. A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and is formed over a portion of the source region 14. A word line terminal 22 (which is typically coupled to a word line) has a first portion disposed over and insulated from (and controlling the conductivity of) a second portion of the channel region 18, and a second portion extending upward and located over the floating gate 20. The floating gate 20 and the word line terminal 22 are insulated from the substrate 12 by a gate oxide. A bit line 24 is coupled to the drain region 16.

[0005] The memory cell 110 is erased by applying a high positive voltage to the word line terminal 22 (where electrons are removed from the floating gate), which causes electrons on the floating gate 20 to tunnel from the floating gate 20 to the word line terminal 22 through the intermediate insulator via the Fowler-Nordheim (FN) tunnel.

[0006] The memory cell 110 is programmed via source-side injection (SSI) using hot electrons (where electrons are placed on the floating gate) by applying a positive voltage to both the word line terminal 22 and the source region 14. The electron flow will proceed from the drain region 16 to the source region 14. As the electrons reach the gap between the word line terminal 22 and the floating gate 20, they accelerate and become heated. Due to electrostatic attraction from the floating gate 20, some of the heated electrons will be injected onto the floating gate 20 through the gate oxide.

[0007] Memory cell 110 is read by applying a positive read voltage to drain region 16 and word line terminal 22 (which turns on the portion of channel region 18 below the word line terminal). If floating gate 20 is positively charged (i.e., electrons are erased), the portion of channel region 18 below floating gate 20 is also turned on, and current flows through channel region 18, which is sensed as erased or "1". If floating gate 20 is negatively charged (i.e., programmed electronically), the portion of channel region below floating gate 20 is mostly or completely turned off, and current does not flow (or very little current) through channel region 18, which is sensed as programmed or "0".

[0008] Table 1 depicts the typical voltage and current ranges that can be applied to the terminals of memory cell 110 to perform read, erase, and program operations:

[0009] Table 1: Operation of Flash Memory Cell 110 in Figure 1

[0010] WL BL SL Read 2V-3V 0.6V-2V 0V erase Approximately 11V-13V 0V 0V programming 1V-2V 10.5μA-3μA 9V-10V

[0011] Other split-gate memory cell configurations, as other types of flash memory cells, are available in the prior art. For example, Figure 2 depicts a four-gate memory cell 210 including a source region 14, a drain region 16, a floating gate 20 over a first portion of a channel region 18, a select gate 22 (typically coupled to the word line WL) over a second portion of the channel region 18, a control gate 28 over the floating gate 20, and an erase gate 30 over the source region 14. This configuration is described in U.S. Patent 6,747,210, which is incorporated herein by reference for all purposes. Here, all gates except the floating gate 20 are non-floating gates, meaning they are electrically connected to or can be electrically connected to a voltage source. Programming is performed by heated electrons from the channel region 18 that inject themselves into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0012] Table 2 depicts the typical voltage and current ranges that can be applied to the terminals of memory cell 210 to perform read, erase, and program operations:

[0013] Table 2: Operation of Flash Memory Cell 210 in Figure 2

[0014] WL / SG BL CG EG SL Read 1.0V-2V 0.6V-2V 0V-2.6V 0V-2.6V 0V erase -0.5V / 0V 0V 0V / -8V 8V-12V 0V programming 1V 0.1μA-1μA 8V-11V 4.5V-9V 4.5V-5V

[0015] Figure 3 depicts a tri-gate memory cell 310, which is another type of split-gate flash memory cell. Memory cell 310 is identical to memory cell 210 in Figure 2, except that memory cell 310 does not have a separate control gate. Except for the absence of a control gate bias, erase operations (thus erasing via an erase gate) and read operations are similar to those in Figure 2. Programming operations are also performed without a control gate bias, and therefore, a higher voltage is applied to the source line during programming operations to compensate for the lack of control gate bias.

[0016] Table 3 depicts the typical voltage and current ranges that can be applied to the terminals of memory cell 310 to perform read, erase, and program operations:

[0017] Table 3: Operation of flash memory cell 310 in Figure 3

[0018] WL / SG BL EG SL Read 0.7V-2.2V 0.6V-2V 0V-2.6V 0V erase -0.5V / 0V 0V 11.5V 0V programming 1V 0.21μA-3μA 4.5V 7V-9V

[0019] Figure 4 depicts a stacked-gate memory cell 410, which is another type of flash memory cell. Memory cell 410 is similar to memory cell 110 of Figure 1, except that the floating gate 20 extends over the entire channel region 18 and the control gate 22 (which will be coupled to the word line here) extends over the floating gate 20 and is separated by an insulating layer (not shown). Erasing is performed by electron tunneling from the FG to the substrate via the FN, and programming is performed by channel hot electron (CHE) injection in the region between the channel 18 and the drain region 16, by electron flow from the source region 14 towards the drain region 16, and by a read operation similar to that used for a read operation of memory cell 110 with a higher control gate voltage.

[0020] Table 4 depicts the typical voltage range that can be applied to the terminals of memory cell 410 and substrate 12 to perform read, erase, and program operations:

[0021] Table 4: Operation of Flash Memory Cell 410 in Figure 4

[0022] CG BL SL substrate Read 2V-5V 0.6V-2V 0V 0V erase -8V to -10V / 0V FLT FLT 8V-10V / 15V-20V programming 8V-12V 3V-5V 0V 0V

[0023] The methods and apparatus described herein can be applied to other non-volatile memory technologies, such as, but not limited to, FINFET split-gate flash or stacked-gate flash memory, NAND flash memory, SONOS (silicon-oxide-nitride-oxide-silicon with charge trapped in nitride), MONOS (metal-oxide-nitride-oxide-silicon with metal charge trapped in nitride), ReRAM (resistive RAM), PCM (phase-change memory), MRAM (magnetic RAM), FeRAM (ferroelectric RAM), CT (charge-trapping) memory, CN (carbon nanotube) memory, OTP (two-level or multi-level one-time programmable) and CeRAM (associative electron RAM).

[0024] Non-volatile memory cells are arranged in an array comprising rows and columns of non-volatile memory cells. In a simple configuration, a single physical array contains all the non-volatile memory cells of the memory system and extends together with a logical array presented to components outside the memory system, such as a CPU utilizing the memory system. In a more complex configuration, multiple physical arrays are used, and these physical arrays contain the non-volatile memory cells of the memory system. In this case, the logical array can be mapped to multiple physical arrays.

[0025] In another configuration, multiple memory banks are used, and these memory banks contain non-volatile memory cells of the memory system. The memory banks can comprise a single physical array or multiple physical arrays. By partitioning logical arrays among different memory banks instead of using a single physical array, the overall system speed can be improved, overall memory system leakage can be reduced to enhance the margin of read or program operations (because read or program operations will be less affected by memory cell leakage), and parasitic capacitance can be reduced. The disadvantage is the need for additional address decoding, as a portion of the address will be allocated to identify the memory bank used for the operation.

[0026] Figure 5 illustrates a prior art memory system 500. The memory system 500 includes a logic array 550 formed by memory banks 501, 502, 503, and 504. In one example, the logic array 550 can store 8 Mb of data. In this example, memory banks 501, 502, 503, and 504 each store 2 Mb of data and include 512 rows and 4096 bit lines.

[0027] Referring to Figure 6, prior art memory banks 501, 502, 503, and 504 may include sectors. In this example, memory banks 501, 502, 503, and 504 include N+1 sectors referred to as sector 0, sector 1, ..., sector (N-1), and sector N, respectively. Each sector comprises two or more consecutive rows of memory cells within the memory bank.

[0028] Figure 7 depicts a prior art memory system 700. The memory system 700 includes a logic array 750 formed by memory banks 701, 702, 703, and 704. The memory system 700 also includes: column multiplexers 705, 706, 707, and 708; a sense amplifier and column driver 709 and a sense amplifier and column driver 710; high-voltage (HV) decoders and latches 712, 713, 714, and 715; and row decoders 711 and 712. Memory banks 701, 702, 703, and 704 form a logic array of non-volatile memory cells arranged in rows and columns. Column multiplexer 705 operates on columns of memory bank 701, column multiplexer 706 operates on columns of memory bank 702, column multiplexer 707 operates on columns of memory bank 703, and column multiplexer 708 operates on columns of memory bank 704. Row decoder 711 operates on rows of memory banks 701 and 702, and row decoder 712 operates on rows of memory banks 703 and 704. Sensing amplifier and column driver 709 perform sensing operations on outputs received from column multiplexers 705 and 707 during read operations (i.e., reading "1" or "0" stored in memory cells), and control the current applied to the columns of memory banks 701 and 703 through column multiplexers 705 and 707 during programming operations. Sensing amplifier and column driver 710 perform sensing operations on outputs received from column multiplexers 706 and 708 during read operations, and control the current applied to the columns of memory banks 702 and 704 through column multiplexers 706 and 708 during programming operations. HV decoders and latches 712, 713, 714 and 715, for example, provide high voltages to the rows of memory banks 701, 702, 703 and 704, respectively, during programming or erasing operations.

[0029] In existing systems, multiple rows in a logic array 750 are allocated to each memory bank 701, 702, 703, and 704, where the number of rows is a power of 2 (i.e., 2^n), where n is an integer and the number of address bits required to decode any particular row in the memory bank. For example, if the logic array can store 32 Mb, the logic array 750 might comprise 8192 rows × 4096 columns (where other memory banks, not shown, are used besides memory banks 701, 702, 703, and 704) that can be divided into 16 memory banks of 512 rows × 4096 bit lines each, where 512 = 2^n. 9And n = 9. In this example, the row address will require 13 address bits XA[12:0], while the bank address will require 4 of those bits, such as XA[12:9] (indicating bits 12, 11, 10, and 9 within the 13 address bits, where the bit positions span from bit position 12 to bit position 0), to distinguish 16 different banks. Here, the total number of rows is 512 * 16 = 8192 = 2 13 Storage units 701, 702, 703, and 704 may optionally include sectors.

[0030] In a simpler example involving 16 rows, the 16 rows can be divided among the four memory banks according to the addressing scheme shown in Table 5:

[0031] Table 5: Storage allocation for 16 rows

[0032] XA[3] XA[2] XA[1] XA[0] OK# Storage# 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 2 0 0 0 1 1 3 0 0 1 0 0 4 1 0 1 0 1 5 1 0 1 1 0 6 1 0 1 1 1 7 1 1 0 0 0 8 2 1 0 0 1 9 2 1 0 1 0 10 2 1 0 1 1 11 2 1 1 0 0 12 3 1 1 0 1 13 3 1 1 1 0 14 3 1 1 1 1 15 3

[0033] In the example in Table 5, because the number of rows in each memory bank is a power of 2 (i.e., 2^32), n Therefore, the two most significant bits (MSB) XA[3] and XA[2] in the row address can be used as memory bank identifiers, where XA[3:2] = 00 indicates memory bank 0, XA[3:2] = 01 indicates memory bank 1, XA[3:2] = 10 indicates memory bank 2, and XA[3:2] = 11 indicates memory bank 3. In this way, the row address can be decoded very quickly to identify the appropriate memory bank for read, program, or erase operations. If the memory bank contains sectors formed by two rows per sector, XA[1] ​​can be used to identify a particular memory bank, and XA[0] can be used to identify a row within a particular sector. However, this scheme will not work if the sectors are formed by different numbers of rows (such as three rows), or if the memory bank contains different numbers of sectors.

[0034] If the number of rows allocated to the storage body is not a power of 2 (i.e., 2... n If the total number of rows is not equal to 2, this method will not work because in that case, the memory identifier will not correspond neatly to a certain number of bits in the row address. Additionally, if the total number of rows is not equal to 2... r (where r is the number of row address bits), for example, if r = 9, but the total number of rows is 510 instead of 512 (i.e., 2), 9If this is not the case, this method will not work. For example, in the example in Table 5, if each memory bank were instead assigned 6 rows, the addressing scheme shown in Table 5 would not be able to uniquely identify each memory bank and row. Furthermore, it is desirable for any address decoding scheme to keep the rows of a sector within the same memory bank, as sectors consist of physically contiguous rows, which adds to the challenge. For example, a sector might have a multiple of 2 rows because two consecutive rows share one or more of the erase gate line and the control gate line.

[0035] Table 6 illustrates an example of allocating 36 rows among four banks. It is noteworthy that 36 is not a power of 2. In this example, banks 0 and 1 each have 10 rows, and banks 2 and 3 each have 8 rows. Using this scheme, existing row decoding schemes would be insufficient. Therefore, existing systems might use combinational logic to identify the bank for a specific row using the 4 or 5 most significant bits in the row address. For example, bank 3 could be indicated by XA[5:2] =

[0111] OR

[1100] , bank 2 by XA[5:2] =

[0101] OR

[0110] , bank 1 by XA[5:1] =

[00101] OR XA[5:2] =

[0011] OR

[0100] , and bank 0 by XA[5:1] =

[0000] OR

[0001] OR

[00100] . The combinational logic required to perform this decoding function will be complex and will require a large amount of die space.

[0036] Table 6: Storage allocation for 36 rows

[0037] XA[5] XA[4] XA[3] XA[2] XA[1] XA[0] OK# Storage# 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 2 0 0 0 0 0 1 1 3 0 0 0 0 1 0 0 4 0 0 0 0 1 0 1 5 0 0 0 0 1 1 0 6 0 0 0 0 1 1 1 7 0 0 0 1 0 0 0 8 0 0 0 1 0 0 1 9 0 0 0 1 0 1 0 10 1 0 0 1 0 1 1 11 1 0 0 1 1 0 0 12 1 0 0 1 1 0 1 13 1 0 0 1 1 1 0 14 1 0 0 1 1 1 1 15 1 0 1 0 0 0 0 16 1 0 1 0 0 0 1 17 1 0 1 0 0 1 0 18 1 0 1 0 0 1 1 19 1 0 1 0 1 0 0 20 2 0 1 0 1 0 1 21 2 0 1 0 1 1 0 22 2 0 1 0 1 1 1 23 2 0 1 1 0 0 0 24 2 0 1 1 0 0 1 25 2 0 1 1 0 1 0 26 2 0 1 1 0 1 1 27 2 0 1 1 1 0 0 28 3 0 1 1 1 0 1 29 3 0 1 1 1 1 0 30 3 0 1 1 1 1 1 31 3 1 0 0 0 0 0 32 3 1 0 0 0 0 1 33 3 1 0 0 0 1 0 34 3 1 0 0 0 1 1 35 3

[0038] If the memory bank contains sectors formed by two rows per sector, then XA[1] ​​can be used to identify a particular memory bank, and XA[0] can be used to identify a row within a particular sector. However, this scheme will not work if the sector is formed by a different number of rows (such as three rows), and it will also not work if the memory bank contains a different number of sectors.

[0039] A new address decoding scheme is needed, which can handle cases where the number of rows assigned to the memory bank is not a power of 2, and which keeps the rows of the sector in the same memory bank. Summary of the Invention

[0040] Numerous examples of row address decoding schemes are disclosed, which uniquely identify each row in a memory system by the bank, sector, and rows within the sector. The row addressing schemes described herein can handle cases where the number of sectors is odd or even, where the bank contains an odd or even number of sectors, and where the total number of rows in the bank is a power of 2 or not. Attached Figure Description

[0041] Figure 1 depicts a split-gate flash memory cell of the prior art.

[0042] Figure 2 depicts another prior art split-gate flash memory cell.

[0043] Figure 3 depicts another prior art split-gate flash memory cell.

[0044] Figure 4 depicts a stacked gate flash memory cell of the prior art.

[0045] Figure 5 depicts a memory system comprising a logic array stored in multiple memory banks.

[0046] Figure 6 depicts the components of the memory system in Figure 5.

[0047] Figure 7 depicts a memory bank comprising multiple sectors.

[0048] Figure 8 A memory system comprising multiple memory banks is described.

[0049] Figure 9 Another memory system comprising multiple memory banks is described.

[0050] Figure 10 The address decoding scheme is described.

[0051] Figure 11 Another address decoding method is described. Detailed Implementation

[0052] In the example described herein, the row address includes multiple bits, wherein the first set of bits is used to identify the memory bank, the second set of bits is used to identify the sectors within the memory bank, and the third set of bits is used to identify the rows within the sectors. However, unlike the prior art, the addressing scheme described herein can handle cases where the number of sectors is odd or even, where the memory bank contains an odd or even number of sectors, and where the total number of rows in the memory bank is a power of 2 or not a power of 2.

[0053] Figure 8An example memory system is depicted, wherein one or more banks comprise an even number of sectors, one or more banks comprise an odd number of sectors, banks contain varying numbers of sectors, and the memory system comprises a total number of rows that are not powers of 2. In this example, there are 4 banks and 18 sectors, where each sector contains 2 rows. Here, banks 801 and 803 are each allocated 5 sectors, and banks 802 and 804 are each allocated 4 sectors. Since each sector has 2 rows, the least significant bit XA[0] will be used to decode the rows within each sector. That is, since the sector contains two rows, XA[0] = 0 will indicate one row, and XA[0] = 1 will indicate the other row.

[0054] The memory system 800 includes a logic array 850 formed by memory banks 801, 802, 803, and 804. The memory system 800 also includes: column multiplexers 805, 806, 807, and 808; sense amplifiers and column drivers 809 and 810; row decoders 811, 812, 813, and 814; and high-voltage decoders and latches 815, 816, 817, 818, 819, and 820. Memory banks 801, 802, 803, and 804 each comprise an array of non-volatile memory cells arranged in rows and columns. The non-volatile memory cells may be split-gate flash memory cells such as memory cells 110, 210, and 310 in Figures 1, 2, and 3, respectively, or stacked-gate flash memory cells such as memory cell 410 in Figure 4. Memory bank 801 includes sectors 0, 1, 2, 3, and 4; memory bank 802 includes sectors 10, 11, 12, and 13; memory bank 803 includes sectors 5, 6, 7, 8, and 9; and memory bank 804 includes sectors 14, 15, 16, and 17. Figure 8 In this context, the sector number is a global sector number, which means that it is a unique number that identifies a sector among all sectors in all memory.

[0055] Column multiplexer 805 operates on columns of memory bank 801, column multiplexer 806 operates on columns of memory bank 802, column multiplexer 807 operates on columns of memory bank 803, and column multiplexer 808 operates on columns of memory bank 804.

[0056] Line decoder 811 operates on the rows of memory bank 801 corresponding to sectors 0, 1, 2, and 3, and on the rows of memory bank 802 corresponding to sectors 10, 11, 12, and 13; line decoder 813 operates on the row of memory bank 801 corresponding to sector 4; line decoder 812 operates on the rows of memory bank 803 corresponding to sectors 5, 6, 7, and 8, and on the rows of memory bank 804 corresponding to sectors 14, 15, 16, and 17; and line decoder 814 operates on the row of memory bank 803 corresponding to sector 9.

[0057] The sense amplifier and column driver 809 performs a sensing operation on the outputs received from column multiplexers 805 and 807 during a read operation, and controls the current applied to the columns of memory banks 801 and 803 through column multiplexers 805 and 807 during a programming operation. The sense amplifier and column driver 810 performs a sensing operation on the outputs received from column multiplexers 806 and 808 during a read operation, and controls the current applied to the columns of memory banks 802 and 804 through column multiplexers 806 and 808 during a programming operation.

[0058] HV decoder and latch 815 provide high voltage to the rows of memory bank 801 corresponding to sectors 0, 1, 2, and 3 (e.g., for programming or erasing operations); HV decoder and latch 816 provide high voltage to the rows of memory bank 802 corresponding to sectors 10, 11, 12, and 13; HV decoder and latch 817 provide high voltage to the rows of memory bank 803 corresponding to sectors 5, 6, 7, and 8; HV decoder and latch 818 provide high voltage to the rows of memory bank 804 corresponding to sectors 14, 15, 16, and 17; HV decoder and latch 819 provide high voltage to the row of memory bank 801 corresponding to sector 4; and HV decoder and latch 820 provide high voltage to the row of memory bank 803 corresponding to sector 9.

[0059] Table 7 describes the... Figure 8 The example shows the memory allocation schemes implemented by the line decoders 811, 812, 813, and 814.

[0060] Table 7: Storage allocation for 36 rows

[0061]

[0062] In the example in Table 7, XA[2:1] is used to identify the bank, XA[5:3] is used to identify the sector within the bank (where each sector within the bank is also assigned a global sector number, which is the sector number across all banks), and XA[0] is used to identify the row within the sector. It is worth noting that no additional combinational logic is required to identify the bank from the row address; this decoding is performed by row decoders 811, 812, 813, and 814.

[0063] Figure 9 An example memory system is depicted, wherein one or more banks comprise an even number of sectors, one or more banks comprise an odd number of sectors, banks contain varying numbers of sectors, and the memory system comprises a total number of rows that are not powers of 2. In this example, there are 4 banks and 17 sectors, where each sector comprises 2 rows. Here, bank 901 is allocated 5 sectors, and banks 902, 903, and 904 are each allocated 4 sectors. Because each sector has 2 rows, the least significant bit XA[0] is used to decode the rows within each sector. That is, because a sector contains two rows, XA[0] = 0 will indicate one row, and XA[0] = 1 will indicate the other row. It is desirable that the sense amplifier and column driver 909 and the sense amplifier and column driver 910 have balanced top and bottom bit lines. Therefore, if the top bank (such as bank 901) contains 5 sectors, it is desirable that the bottom bank (such as bank 903) also contains 5 sectors. Because memory bank 901 contains 5 sectors and memory bank 903 contains 4 sectors, a dummy sector 921 is added to memory bank 903. The dummy sector 921 is not used to store data.

[0064] The memory system 900 includes a logic array 950 formed by memory banks 901, 902, 903, and 904. The memory system 900 also includes: column multiplexers 905, 906, 907, and 908; a sense amplifier and column driver 909 and a sense amplifier and column driver 910; row decoders 911, 912, 913, and 914; and high-voltage decoders and latches 915, 916, 917, 918, 919, and 920. Memory banks 901, 902, 903, and 904 each comprise an array of non-volatile memory cells arranged in rows and columns. The non-volatile memory cells may be split-gate flash memory cells such as memory cells 110, 210, and 310 in Figures 1, 2, and 3, respectively, or stacked-gate flash memory cells such as memory cell 410 in Figure 4. Storage bank 901 includes sectors 0, 1, 2, 3 and 4; storage bank 902 includes sectors 9, 10, 11 and 12; storage bank 903 includes sectors 5, 6, 7, 8 and dummy sector 921; and storage bank 904 includes sectors 13, 14, 15 and 16.

[0065] Column multiplexer 905 operates on columns of memory bank 901, column multiplexer 906 operates on columns of memory bank 902, column multiplexer 907 operates on columns of memory bank 903, and column multiplexer 908 operates on columns of memory bank 904.

[0066] Line decoder 911 operates on the rows corresponding to sectors 0, 1, 2, and 3 of memory bank 901 and on the rows corresponding to sectors 9, 10, 11, and 12 of memory bank 902; line decoder 913 operates on the row corresponding to sector 4 of memory bank 901; and line decoder 912 operates on the rows corresponding to sectors 5, 6, 7, and 8 of memory bank 903 and on the rows corresponding to sectors 13, 14, 15, and 16 of memory bank 904. Line decoder 914 corresponds to the row corresponding to dummy sector 921 of memory bank 903. Line decoder 914 is optional and included to allow the possibility that dummy sector 921 can be converted into a normal sector for storing and retrieving data.

[0067] The sense amplifier and column driver 909 perform a sensing operation on the outputs received from column multiplexers 905 and 907 during a read operation, and control the current applied to the columns of memory banks 901 and 903 through column multiplexers 905 and 907 during a programming operation. The sense amplifier and column driver 910 perform a sensing operation on the outputs received from column multiplexers 906 and 908 during a read operation, and control the current applied to the columns of memory banks 902 and 904 through column multiplexers 906 and 908 during a programming operation.

[0068] HV decoder and latch 915 provide a high voltage to the rows of memory bank 901 corresponding to sectors 0, 1, 2, and 3 (e.g., for programming or erasing operations); HV decoder and latch 916 provide a high voltage to the rows of memory bank 902 corresponding to sectors 9, 10, 11, and 12; HV decoder and latch 917 provide a high voltage to the rows of memory bank 903 corresponding to sectors 5, 6, 7, and 8; HV decoder and latch 918 provide a high voltage to the rows of memory bank 904 corresponding to sectors 13, 14, 15, and 16; and HV decoder and latch 919 provide a high voltage to the row of memory bank 901 corresponding to sector 4. HV decoder and latch 920 corresponds to the row of memory bank 903 corresponding to dummy sector 921. HV decoder and latch 920 are optional and included to allow the possibility that dummy sector 921 can be converted into a normal sector for storing and retrieving data. Figure 9 In this context, the sector number is a global sector number, which means that it is a unique number that identifies a sector among all sectors in all memory.

[0069] Table 8 depicts the memory allocation scheme implemented by the row decoders 911, 912, 913 and 914 used in this example.

[0070] Table 8: Storage allocation for 34 rows

[0071]

[0072] In this example, XA[2:1] is used to identify the bank, XA[5:3] is used to identify the sector within the bank (where each sector within the bank is also assigned a global sector number, which is the sector number across all banks), and XA[0] is used to identify the row within the sector. It is worth noting that no additional combinational logic is needed to identify the bank from the row address; this decoding is performed by row decoders 911, 912, 913, and 914.

[0073] Figure 10 An address decoding scheme 1000 implemented by a line decoder 1002 is described. In one example, Figure 8 The line decoders 811, 813, 813 and 814 in the middle and Figure 9 Line decoders 911, 912, 913, and 914 in the code conform to address decoding scheme 1000 and are instantiations of line decoder 1002. Therefore, line decoder 1002 can be used as... Figure 8 The line decoders 811, 812, 813, and 814 in the memory system 800 and as Figure 9 The row decoders 911, 912, 913, and 914 operate within this. Row address 1001 comprises r bits and is provided to row decoder 1002 (as indicated, this row decoder is...). Figure 8 The line decoders 811, 813, 813 and 814 in the middle and Figure 9 Examples of row decoders 911, 912, 913 and 914 in the example), and row decoder 1002 sets various control signals corresponding to the sectors, memory banks and rows identified by row address 1001.

[0074] According to address decoding scheme 1000, the t least significant bits in row address 1001 identify the row within a sector, the u next least significant bits in row address 1001 identify the bank within the memory system, and the v next least significant bits in row address 1001 identify the sector within the bank, where t + u + v ≤ r (e.g., one or more of the r bits can be used for another purpose). Generally, if the system comprises m banks of non-volatile memory cells, each bank comprising n or fewer sectors, and each sector comprising p rows, then t, u, and v are chosen to satisfy the following conditions:

[0075] m≤2 u

[0076] n≤2 v

[0077] p≤2 t

[0078] For example, if m = 4, n = 5, and p = 2 (as in...) Figure 8 As in the example in Table 7), then u = 2, v = 3, and t = 1. This is reasonable because 4 banks of memory can be identified by 2 bits (00, 01, 10, and 11), 5 sectors can be identified by 3 bits (e.g., 000, 001, 010, 011, and 100), and 2 rows can be identified by 1 bit (0 and 1).

[0079] Address decoding scheme 1000 is effective for configurations that are not feasible in existing systems, such as configurations where n*p is not a power of 2, where n is an odd number, where the memory contains a different number of sectors, and where the total number of rows is not a power of 2.

[0080] Figure 11 Depicting what can be used Figure 10 The address decoding method 1100 executed by the row decoder 1002 is as follows: The first operation is that the row decoder 1002 receives a row address consisting of r bits (1101). The second operation is that the row decoder uses the least significant t bits of the r bits to identify rows within p rows of non-volatile memory cells in a logical array formed by m memory banks, uses the next u least significant bits of the r bits to identify memory banks within the m memory banks, and uses the next v least significant bits to identify sectors within n sectors of the memory banks, where m ≤ 2. u n≤2 v And p≤2 t (1102).

[0081] It should be noted that, as used herein, the terms "above" and "on" both encompass "directly on" (without intermediate material, components, or spaces between) and "indirectly on" (with intermediate material, components, or spaces between). Similarly, the term "adjacent" includes "directly adjacent" (without intermediate material, components, or spaces between) and "indirectly adjacent" (with intermediate material, components, or spaces between), "mounted to" includes "directly mounted to" (without intermediate material, components, or spaces between) and "indirectly mounted to" (with intermediate material, components, or spaces between), and "electrically coupled to" includes "directly electrically coupled to" (without intermediate material or components electrically connecting the components together) and "indirectly electrically coupled to" (with intermediate material or components electrically connecting the components together). For example, forming a component "above the substrate" can include forming a component directly on the substrate without intermediate material / components between, and forming a component indirectly on the substrate with one or more intermediate materials / components between.

Claims

1. A memory system, comprising: The non-volatile memory cell comprises m memory banks, each of which includes n or fewer sectors, and each sector includes p rows; as well as A row decoder is configured to receive a row address comprising r bits and to (i) identify the row using the least significant t bits of the r bits, (ii) identify the memory bank using the next u least significant bits, and (iii) identify the sector using the next v least significant bits, where m ≤ 2. u n≤2 v And p≤2 t .

2. The memory system according to claim 1, wherein n*p is not a power of 2.

3. The memory system according to claim 1, wherein n is an odd number.

4. The memory system of claim 1, wherein the non-volatile memory cell comprises a split-gate flash memory cell.

5. The memory system of claim 1, wherein the non-volatile memory cell comprises a stacked gate flash memory cell.

6. The memory system of claim 1, wherein the number of sectors in the memory bank is even.

7. The memory system of claim 1, wherein the number of sectors in the memory bank is odd.

8. The memory system of claim 1, wherein the number of sectors in one memory bank is different from the number of sectors in the other memory bank.

9. The memory system of claim 1, wherein the total number of rows in the memory system is not equal to 2. r .

10. A method comprising: The row address, consisting of r bits, is received by the row decoder. as well as The row decoder uses the least significant t bits of the r bits to identify rows within p rows of non-volatile memory cells in a logical array formed by m memory banks, uses the next u least significant bits of the r bits to identify memory banks within the m memory banks, and uses the next v least significant bits to identify sectors within n sectors of the memory banks, where m ≤ 2. u n≤2 v And p≤2 t .

11. The method of claim 10, wherein n*p is not a power of 2.

12. The method of claim 10, wherein n is an odd number.

13. The method of claim 10, wherein the non-volatile memory cell comprises a split-gate flash memory cell.

14. The method of claim 10, wherein the non-volatile memory cell comprises a stacked gate flash memory cell.

15. The method of claim 10, wherein the number of sectors in the memory is even.

16. The method of claim 10, wherein the number of sectors in the memory is odd.

17. The method of claim 10, wherein the number of sectors in one of the memory banks is different from the number of sectors in the other memory bank.

18. The method of claim 10, wherein the total number of rows is not equal to 2. r .

19. A memory system comprising: The non-volatile memory cell comprises m memory banks, each of which includes n or fewer sectors, and each sector includes p rows; as well as A row decoder, which is used to receive a row address including r bits and to use the r bits to identify the row; The total number of rows in the m storage units is not a power of 2.

20. The system of claim 19, wherein at least two of the m memory banks comprise different numbers of sectors.

21. The system of claim 19, wherein the row decoder uses a subset of the r bits to identify one of the m memory banks.

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