Integrated circuit test information integration analysis system and method

Abstract

The invention relates to the technical field of circuit test data processing, in particular to an integrated circuit test information integration analysis system and method. The method comprises the following steps: constructing an integrated circuit excitation test strategy; analyzing the gradient value of the leakage current of the standard integrated circuit along with the change of the temperature, the grid voltage and the leakage voltage through an integrated circuit excitation test strategy to obtain the response gradient characteristic data of the standard circuit; executing an excitation test on the to-be-tested integrated circuit through the integrated circuit excitation test strategy, and judging the defect time constant type of the to-be-tested integrated circuit; based on the standard circuit response gradient characteristic data and the defect time constant type, reconstructing a leakage path potential fluctuation map; metastable state fault point processing is carried out according to the electric leakage path electric potential fluctuation graph, and then information integration is carried out according to circuit electric leakage dominant component data. According to the invention, accurate identification and fault metastable state processing of a leakage physical area in an integrated circuit are realized, and integrated analysis and feedback of test information are completed.

Description

Technical Field

[0001] This invention relates to the field of circuit test data processing technology, and in particular to an integrated circuit test information integration and analysis system and method. Background Technology

[0002] In integrated circuits, leakage current generation mechanisms are complex and diverse, including but not limited to PN junction tunneling leakage, gate leakage, channel hot carrier effect, dielectric breakdown, and defect-induced leakage. Among these, defect-induced leakage paths are particularly critical because such leakage often manifests as intermittent or metastable faults, exhibiting strong concealment and uncertainty. The location, type, and dynamic behavior of defects under an electric field produce the so-called "defect-induced barrier modulation effect," where changes in the band structure around the defect create a specific potential distribution, thereby affecting the transport characteristics of electrons or holes. However, existing testing systems typically use DC bias or simple AC signals to measure leakage current. This method cannot distinguish between different leakage mechanisms and easily mixes various leakage phenomena in the measurement. Secondly, traditional testing methods lack the ability to deeply analyze the potential distribution characteristics of leakage paths, often treating leakage current as a single parameter. This fails to accurately capture the dynamic changes of the defect-induced barrier modulation effect and ignores the intrinsic relationship between barrier height changes and current characteristics in the leakage path, leading to an inability to accurately identify the dominant leakage path. Summary of the Invention

[0003] Based on this, the present invention provides an integrated circuit test information integration and analysis system and method to solve at least one of the above-mentioned technical problems.

[0004] To achieve the above objectives, an integrated circuit test information integration and analysis method includes the following steps: Step S1: Construct an integrated circuit excitation test strategy; perform ideal circuit benchmark tests on a standard integrated circuit using the integrated circuit excitation test strategy to generate ideal circuit response data; analyze the gradient values ​​of leakage current with temperature, gate voltage and leakage voltage based on the ideal circuit response data to obtain standard circuit response gradient characteristic data; Step S2: Perform stimulus testing on the integrated circuit under test using the integrated circuit stimulus test strategy, and then evaluate the circuit leakage current dominant component data; analyze the dominant temperature-sensitive leakage behavior based on the circuit leakage current dominant component data, and determine the defect time constant type of the integrated circuit under test; Step S3: Calculate the defect-induced barrier height change data based on the standard circuit response gradient characteristic data and the defect time constant type; reconstruct the leakage path potential fluctuation spectrum based on the defect-induced barrier height change data; Step S4: Based on the leakage path potential fluctuation map, intelligently identify the dominant physical location of leakage in the integrated circuit under test, and obtain leakage physical area identification data; Step S5: Perform metastable fault point processing based on the leakage physical area identification data, and then integrate the information based on the circuit leakage dominant component data to feed back to the terminal equipment.

[0005] Preferably, the present invention also provides an integrated circuit test information integration and analysis system, which executes the integrated circuit test information integration and analysis method described above. The integrated circuit test information integration and analysis system includes: The benchmark feature acquisition module is used to construct integrated circuit excitation test strategies; to perform ideal circuit benchmark tests on standard integrated circuits using integrated circuit excitation test strategies, and to generate ideal circuit response data; and to analyze the gradient values ​​of leakage current with temperature, gate voltage and leakage voltage changes based on the ideal circuit response data, so as to obtain standard circuit response gradient feature data. The leakage current characteristic diagnostic module is used to perform stimulation tests on the integrated circuit under test using integrated circuit stimulation test strategies, and then evaluate the dominant leakage current component data of the circuit; based on the dominant leakage current component data of the circuit, it analyzes the dominant temperature-sensitive leakage current behavior and determines the defect time constant type of the integrated circuit under test; The potential spectrum reconstruction module is used to calculate the defect-induced barrier height change data based on standard circuit response gradient characteristic data and defect time constant type; and to reconstruct the leakage path potential fluctuation spectrum based on the defect-induced barrier height change data. The leakage area location module is used to intelligently identify the dominant physical location of leakage in the integrated circuit under test based on the potential fluctuation map of the leakage path, and obtain leakage physical area identification data. The fault integration and feedback module is used to process metastable fault points based on the leakage physical area identification data, and then integrate the information based on the circuit leakage dominant component data to feed it back to the terminal equipment.

[0006] This invention establishes an ideal circuit benchmark testing and gradient feature data analysis framework, achieving precise classification and identification of leakage mechanisms, effectively overcoming the limitations of traditional testing systems that measure multiple leakage phenomena together. The system can intelligently distinguish between different physical mechanisms such as PN junction tunneling leakage, gate leakage, and hot carrier effects, enabling targeted diagnosis and analysis. It innovatively introduces a defect time constant type determination mechanism, accurately capturing the dynamic activation process of defects through temperature-sensitive leakage behavior analysis, allowing for the quantitative characterization of previously unobservable time-varying characteristics. This dynamic analysis method enables the system to effectively handle the detection challenges of metastable faults, significantly improving the accuracy of intermittent defect identification. Particularly noteworthy is the innovative quantitative calculation of defect-induced barrier height changes, filling the technical gap in traditional testing methods that treat leakage current as a single parameter. By correlating the differences between standard circuit response characteristics and measured data, it can accurately extract the barrier modulation characteristics of defects under different electric field conditions, thereby revealing the physical nature of leakage. More significantly, the system can reconstruct the potential fluctuation spectrum of the leakage path based on the calculation results, intuitively presenting the changes in the band structure around the defect. This visualizes the abstract electron transport barrier, greatly enhancing the understanding of the intrinsic relationship between the change in barrier height and current characteristics in the leakage path. It accurately identifies the dominant physical location of the leakage, achieving a mapping transformation from electrical characteristics to physical regions, significantly shortening fault location time and improving repair efficiency. Compared to the blind search or experience-based judgment of traditional methods, this system improves the location accuracy by orders of magnitude, especially effective for tiny defects in deep submicron devices. Through the intelligent integration and feedback mechanism of the dominant component data of circuit leakage, the system can continuously optimize the testing strategy to adapt to the characteristic requirements of different types of integrated circuits. Therefore, the integrated circuit test information integration and analysis method of the present invention obtains standard circuit response data by constructing a three-dimensional excitation test strategy of temperature-gate voltage-drain voltage, and extracts key gradient feature data using numerical differentiation processing; it innovatively adopts an iterative linear decomposition algorithm to identify the dominant leakage component, and determines the defect time constant type by the ratio of peak current to steady-state current; it combines Arrhenius transform analysis to analyze the difference between measured activation energy and ideal activation energy to calculate the defect-induced barrier height change; it accurately locates the spatial position of the defect by the ratio of fast and slow pulse response time constants, and reconstructs the complete leakage path potential fluctuation spectrum by Gaussian distribution processing; it performs preliminary judgment of gate control correlation based on barrier height modulation coefficient, achieves fine classification of weak gate control paths by body bias suppression ratio, and identifies strong gate control path types by interface state influence deviation; finally, it achieves accurate identification of leakage physical regions and fault metastability processing, and completes the integration, analysis and feedback of integrated circuit test information. Attached Figure Description

[0007] Figure 1 This is a flowchart illustrating the steps of the integrated circuit test information integration and analysis method of the present invention; The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0008] The technical method of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0009] Furthermore, the accompanying drawings are merely illustrative of the invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor methods and / or microcontroller methods.

[0010] It should be understood that although the terms "first," "second," etc., may be used herein to describe various units, these units should not be limited by these terms. These terms are used merely to distinguish one unit from another. For example, without departing from the scope of the exemplary embodiments, a first unit may be referred to as a second unit, and similarly, a second unit may be referred to as a first unit. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0011] To achieve the above objectives, please refer to Figure 1 This invention provides a method for integrating and analyzing integrated circuit test information, comprising the following steps: Step S1: Construct an integrated circuit excitation test strategy; perform ideal circuit benchmark tests on a standard integrated circuit using the integrated circuit excitation test strategy to generate ideal circuit response data; analyze the gradient values ​​of leakage current with temperature, gate voltage and leakage voltage based on the ideal circuit response data to obtain standard circuit response gradient characteristic data; Step S2: Perform stimulus testing on the integrated circuit under test using the integrated circuit stimulus test strategy, and then evaluate the circuit leakage current dominant component data; analyze the dominant temperature-sensitive leakage behavior based on the circuit leakage current dominant component data, and determine the defect time constant type of the integrated circuit under test; Step S3: Calculate the defect-induced barrier height change data based on the standard circuit response gradient characteristic data and the defect time constant type; reconstruct the leakage path potential fluctuation spectrum based on the defect-induced barrier height change data; Step S4: Based on the leakage path potential fluctuation map, intelligently identify the dominant physical location of leakage in the integrated circuit under test, and obtain leakage physical area identification data; Step S5: Perform metastable fault point processing based on the leakage physical area identification data, and then integrate the information based on the circuit leakage dominant component data to feed back to the terminal equipment.

[0012] In this embodiment of the invention, the integrated circuit test information integration and analysis method includes the following steps: Step S1: Construct an integrated circuit excitation test strategy; perform ideal circuit benchmark tests on a standard integrated circuit using the integrated circuit excitation test strategy to generate ideal circuit response data; analyze the gradient values ​​of leakage current with temperature, gate voltage and leakage voltage based on the ideal circuit response data to obtain standard circuit response gradient characteristic data; In this embodiment of the invention, structural regions of a standard integrated circuit are identified using a high-resolution optical microscope and an electron beam scanning microscope to precisely locate the high-density SRAM region, the analog front-end region, and the independent transistor region. Subsequently, a precisely controlled voltage sequence is applied to the standard integrated circuit using a semiconductor parameter analyzer and a test probe card, including a gate voltage scan with a step size of 10 mV from -1 volt to 2 volts and a drain voltage scan with a step size of 50 mV from 0 volt to 2 volts. Simultaneously, a high-precision thermal control platform is used to perform temperature scans within the range of -40°C to 150°C, at 5°C intervals. After stabilization at each temperature point, a complete gate voltage and drain voltage scan matrix is ​​executed, and drain current data is acquired. Based on the acquired three-dimensional response data, four key gradient features are calculated using a numerical differential processor: the gate voltage transconductance is calculated using the central difference method; the slope factor is extracted in the subthreshold region; the exponential growth factor is obtained by performing a logarithmic transformation on the drain voltage-related data and then differentiating it piecewise; and the high and low temperature activation energy factors are obtained by performing an Arrhenius transformation on the temperature-related data and then differentiating it piecewise. These four gradient features are combined to form the standard circuit response gradient feature data.

[0013] Step S2: Perform stimulus testing on the integrated circuit under test using the integrated circuit stimulus test strategy, and then evaluate the circuit leakage current dominant component data; analyze the dominant temperature-sensitive leakage behavior based on the circuit leakage current dominant component data, and determine the defect time constant type of the integrated circuit under test; In this embodiment of the invention, a complete voltage and temperature matrix is ​​applied to the integrated circuit under test according to the excitation test strategy established in step S1, and the leakage current data acquisition accuracy reaches the 100 picoampere level. The same gradient analysis as in step S1 is performed on the acquired circuit under test response data to extract the circuit under test response gradient feature data. The similarity between the feature under test and each feature vector in the standard feature database is calculated using a cosine similarity algorithm to generate a response similarity score list. Subsequently, an iterative linear decomposition method is used to determine the contribution weight of each standard feature vector to the feature under test: firstly, the feature vector with the highest similarity is identified as the first dominant component, and its weighted contribution is subtracted from the feature under test. Similarity calculation and component identification are repeatedly performed on the remaining feature vectors until the magnitude of the remaining vector is less than a preset threshold of 0.1. The contribution weights of each dominant component are summarized to generate circuit leakage current dominant component data. Based on this data, temperature dependence characteristics are analyzed to determine key test temperature points. At these temperature points, a standard pulse (amplitude 0.25 volts, width 10 microseconds) is applied to the gate of the circuit under test. The leakage current response is monitored, the ratio of peak value to steady-state current is extracted, and the defect time constant type is determined to be either a slow-state trap defect or a fast-state interface defect by comparing it with a preset threshold of 2.5.

[0014] Step S3: Calculate the defect-induced barrier height change data based on the standard circuit response gradient characteristic data and the defect time constant type; reconstruct the leakage path potential fluctuation spectrum based on the defect-induced barrier height change data; In this embodiment of the invention, the original transient leakage current curve data is transformed using logarithmic coordinates, with the horizontal axis representing the reciprocal of temperature and the vertical axis representing the natural logarithm of leakage current, to construct an Arrhenius plot. An adaptive piecewise fitting algorithm is applied to the data points on the plot, typically dividing them into three segments: a low-temperature region (-40°C to 25°C), a medium-temperature region (25°C to 85°C), and a high-temperature region (85°C to 150°C). Each segment is linearly fitted using the least squares method. Based on the defect type determined in step S2, the slope of the target temperature region is selected: the medium-temperature slope is selected for slow-state trap defects, and the low-temperature slope is selected for fast-state interface defects. The selected slope is multiplied by the Boltzmann constant to calculate the measured defect activation energy value, which is then subtracted from the ideal device activation energy baseline value to obtain the defect-induced barrier height change data. Subsequently, the potential spatial distribution is analyzed using a pulse testing system: a fast pulse (rise time 1 nanosecond) and a slow pulse (rise time 1 microsecond) are applied to the circuit under test, and the time required for the leakage current to reach 90% of its steady state is measured, and the time constant ratio is calculated. The depth of the defect is determined based on the time constant ratio (threshold 2.5). A channel location coordinate axis is established to determine the center of the potential barrier depression. Discrete potential distribution coordinate points are generated through Gaussian distribution processing. Finally, cubic Hermite interpolation is applied to connect these points to reconstruct a complete leakage path potential fluctuation spectrum.

[0015] Step S4: Based on the leakage path potential fluctuation map, intelligently identify the dominant physical location of leakage in the integrated circuit under test, and obtain leakage physical area identification data; In this embodiment of the invention, key features are extracted from the potential fluctuation spectrum of the leakage path: the lowest barrier valley value V_min and its location are identified by an extreme value detection algorithm, and the average barrier height value V_avg of the middle 80% region of the channel is calculated by the compound Simpson integral method. The difference between the two is divided by the thermal voltage (approximately 25.8 mV) to obtain the barrier height modulation coefficient M. Based on the comparison of this coefficient value with the threshold of 1.5, the leakage path is initially divided into gate-controlled weakly correlated paths and gate-controlled strongly correlated paths. For gate-controlled weakly correlated paths, the system measures the leakage current under zero-body bias (0 volts) and reverse body bias (-1 volt) conditions, calculates the body bias suppression ratio (BSR), and further subdivides the weakly gate-controlled path into gate-induced drain leakage path, junction leakage path, or isolation region defect path by comparing it with the thresholds of 3.0 and 15.0. For gate-controlled strongly correlated paths, the system calculates the theoretical leakage suppression ratio based on process parameters, compares it with the measured value to obtain the interface state influence deviation, and marks the path as a channel interface path when the deviation is less than 50% of the threshold. Finally, based on the path classification results and valley location information, the system determines the leakage physical region as the interface between the shallow trench isolation area and the active area or the gate oxide layer area, and further subdivides it into the source end, the center or the vicinity of the drain end, generating leakage physical region identification data.

[0016] Step S5: Perform metastable fault point processing based on the leakage physical area identification data, and then integrate the information based on the circuit leakage dominant component data to feed back to the terminal equipment.

[0017] In this embodiment of the invention, leakage physical region identification data is read to determine the fault location and type. For shallow trench isolation region faults, the system applies an optimal reverse body bias through a body bias regulator, with the bias value dynamically calculated based on the body bias suppression ratio measured in step S2. For gate oxide layer faults, the system fine-tunes the gate voltage through a gate bias controller, with the offset set based on the defect-induced barrier height obtained in step S3. The repair parameters are applied for at least 100 milliseconds to ensure complete circuit stability. Subsequently, the system reads the dominant leakage component data, extracts components with a contribution weight exceeding 10%, and cross-validates them with the physical region identification data to ensure consistency in their physical interpretation. The system converts the processed comprehensive information into a standard format data packet, containing five core fields: fault type identifier, physical location description, contribution weight percentage, confidence score, and repair parameters. The data packet is transmitted to the terminal device via a high-speed serial interface at a transmission rate of 115200 baud, with a complete transmission time of no more than 50 milliseconds. Upon receiving the data, the terminal device automatically parses and displays an intuitive fault analysis report, including a leakage path diagram and repair suggestions.

[0018] Preferably, step S1, which involves performing ideal circuit benchmark testing on a standard integrated circuit using an integrated circuit excitation test strategy, includes: The test structure regions of a standard integrated circuit are identified to obtain the circuit reference test structure; the test structure regions include the high-density SRAM region, the analog front-end region, and the independent transistor region of the integrated circuit. Based on the circuit benchmark test structure, a standard electrical excitation sequence is generated by applying a gate voltage scan from -1 V to 2 V with a step size of 10 mV and a drain voltage scan from 0 V to 2 V with a step size of 50 mV to a standard integrated circuit through a test probe card. A standard integrated circuit is placed on a precisely temperature-controlled thermal fixture. A temperature scan sequence is set from -40°C to 150°C with a step size of 5°C. After each temperature point stabilizes, gate voltage and drain voltage scans are performed based on a standard electrical excitation sequence to obtain the integrated circuit excitation test strategy. Based on the integrated circuit excitation test strategy, an excitation scan is performed on a standard integrated circuit, and leakage current values ​​are collected simultaneously; Ideal circuit response data is generated by associating the leakage current value with the corresponding test condition data; the test condition data includes gate voltage, leakage voltage, and temperature value.

[0019] In this embodiment of the invention, the identification of the test structure region is performed using a silicon wafer probing instrument. First, a standard integrated circuit sample is placed on the probing stage, and a high-resolution optical microscope is used to locate specific areas on the integrated circuit. For high-density SRAM areas, alignment technology between circuit layout markers and physical markers on the actual wafer is used to ensure precise positioning of each memory cell array. The identification of the analog front-end area uses an infrared thermal imager combined with a circuit layout file for marking, identifying the analog signal processing circuitry. Individual transistor regions are microscopically located using an electron beam scanning microscope, achieving nanometer-level positioning accuracy. After region identification, test coordinate points are marked on the wafer map, generating a test structure coordinate file.

[0020] The standard electrical excitation sequence is generated using a semiconductor parameter analyzer. The test probe card is precisely positioned to the target area according to the test structure coordinate file. The contact pressure between the probe and the test pad is controlled at 20 ± 2 g / L to ensure stable contact without damaging the pad. The gate voltage scan starts at -1 volt and increases in increments of 10 mV to 2 volts, for a total of 300 test points; the drain voltage scan starts at 0 volt and increases in increments of 50 mV to 2 volts, for a total of 40 test points. The semiconductor parameter analyzer uses a four-terminal measurement method to eliminate the influence of contact resistance. The accuracy of the gate and drain voltage scans is better than ±0.01%, and the current measurement range is from 1 nanoamp to 100 mA with a resolution of 0.1 nanoamp. The test sequence is executed by the parameter analyzer controller, with the settling time for each voltage point set to 100 microseconds and the sampling time set to 10 microseconds.

[0021] Temperature scanning tests were performed using a high-precision thermal control testing platform. A standard integrated circuit sample was placed at the center of the thermal fixture, and thermal grease was used to ensure full contact between the sample and the fixture surface, with a thermal conductivity of not less than 1.5 W / m·Kelvin. The thermal fixture employed a bidirectional temperature control system combining semiconductor cooling and resistance heating, with a temperature control accuracy of ±0.1 degrees Celsius. The temperature scan started at -40 degrees Celsius and increased in 5-degree Celsius increments to 150 degrees Celsius, totaling 39 temperature points. At each temperature point, the sample temperature was monitored in real time using a platinum resistance temperature sensor. After the temperature stabilized at ±0.05 degrees Celsius for 30 seconds, the system automatically executed the gate voltage and drain voltage scan sequence. After the electrical tests at each temperature point were completed, the system automatically increased the temperature to the next point, with the temperature change rate controlled at 3 degrees Celsius / minute to ensure the sample was not damaged by thermal stress.

[0022] Excitation scan execution and data acquisition are completed using an integrated circuit test system. The test system includes a high-precision source meter unit, achieving a leakage current measurement accuracy of ±0.05% +10 picoamps, with a measurement range from 1 picoamp to 1 amp. Measurements at each test point employ an integral sampling method with an integration time of 100 milliseconds in medium-speed mode to filter out external interference and noise. During test data acquisition, the system maintains the stability of the gate and leakage voltages, with voltage fluctuations not exceeding ±0.01% of the set values. To eliminate the influence of internal bias in the measuring instruments, the system performs zero-point calibration before each round of testing. During current measurement, the test system uses four-wire measurement technology to eliminate the influence of wire resistance, and employs shielded test cables to reduce environmental electromagnetic interference, ensuring that the measured leakage current value accurately reflects the device characteristics.

[0023] The raw test data file is read, the leakage current value of each test point is extracted, and a correlation is established with the corresponding test conditions (gate voltage, leakage voltage, temperature). For each set of test conditions, the statistical average and standard deviation are calculated, and outlier data points exceeding three times the standard deviation of the average are removed. The ideal circuit response data is stored in a three-dimensional matrix structure. The first dimension represents the gate voltage change (300 points), the second dimension represents the leakage voltage change (40 points), and the third dimension represents the temperature change (39 points). The matrix element value is the leakage current value under the corresponding test condition. The complete matrix is ​​interpolated to fill in the missing data points due to test anomalies. The interpolation algorithm uses cubic spline interpolation to ensure the continuity and smoothness of the interpolated points with the surrounding measured points.

[0024] Preferably, step S1, analyzing the gradient values ​​of leakage current as a function of temperature, gate voltage, and leakage voltage based on ideal circuit response data, includes: By taking the first derivative of the leakage current versus gate voltage data in the ideal circuit response data, the gate voltage transconductance variation curve is obtained. The slope of the subthreshold region is calculated based on the gate voltage transconductance variation curve, and the subthreshold slope factor is generated. The leakage current as a function of leakage voltage in the ideal circuit response data is logarithmically transformed and then differentiated to generate the leakage voltage exponential growth factor. The temperature activation energy factor is generated by performing an Arrhenius transform on the leakage current variation with temperature data in the ideal circuit response data and then taking the derivative. The subthreshold slope factor, leakage pressure exponential growth factor, and temperature activation energy factor are combined to form standard circuit response gradient characteristic data.

[0025] In this embodiment of the invention, the gate voltage-transconductance variation curve is generated by processing the leakage current-gate voltage dataset in the ideal circuit response data using a numerical differentiation method. Specifically, a one-dimensional dataset of leakage current versus gate voltage variation under fixed leakage voltage values ​​(typically 0.05 volts) and fixed temperature (25 degrees Celsius) conditions is first extracted from the ideal circuit response data matrix. The central difference method is applied to this dataset to calculate the first derivative, with the central difference window width set to 5 times the gate voltage step size (i.e., 50 millivolts) to smooth out noise during the differentiation process. For each voltage point Vi in the gate voltage scan sequence, the transconductance value at point Vi is calculated, i.e., the derivative of the leakage current with respect to the gate voltage. After the calculation, all gate voltage points and their corresponding transconductance values ​​are paired to form a gate voltage-transconductance variation curve.

[0026] The maximum transconductance value Gm_max is identified on the gate voltage-transconductance curve. Then, a search is performed to the left for points where the transconductance value is less than 1 / 10 of the maximum value, defining the upper boundary of the subthreshold region. The search continues to the left until a point where the transconductance value is less than 10 nanoamps / volt, defining the lower boundary of the subthreshold region. Within the defined subthreshold region, a logarithmic transformation is performed on the leakage current data, and the least squares method is used to fit a linear relationship between the transformed data and the gate voltage. By calculating the slope of this linear relationship, the subthreshold swing factor is obtained. This value represents the voltage change required for each order of magnitude change in the gate voltage, expressed in millivolts per decade. The subthreshold slope factor is the reciprocal of the subthreshold swing factor.

[0027] Data sets of leakage current versus leakage voltage under fixed gate voltage (typically the threshold voltage plus 0.1 volts) and fixed temperature (25 degrees Celsius) conditions are extracted from ideal circuit response data. The leakage current data undergoes a natural logarithmic transformation, converting it to a relationship between ln(Id) and Vd. The transformed data is then smoothed using a weighted moving average method, with a smoothing window size three times the leakage voltage step size (i.e., 150 mV). The smoothed curves are then calculated using a point-to-point numerical differentiation method at each leakage voltage point, employing a five-point difference formula to improve accuracy. The obtained derivative data is divided into intervals to identify regions where the derivative is stable within the device saturation region. The average value of the derivative within these regions is calculated; this average value is the leakage voltage exponential growth factor λ, which characterizes the exponential growth rate of leakage current with increasing leakage voltage, expressed in negative volts.

[0028] Data sets of leakage current variations with temperature under fixed gate voltage (typically the threshold voltage) and fixed drain voltage (typically 0.5 volts) conditions are extracted from ideal circuit response data. Temperature values ​​T are converted to 1 / kT (k is the Boltzmann constant, 1.38 × 10⁻²³ joules / Kelvin), and leakage current values ​​Id are converted to ln(Id), constructing a graph of ln(Id) versus 1 / kT. A piecewise linear fitting method is applied to the converted data, dividing the temperature range into two intervals: a low-temperature region (-40°C to 25°C) and a high-temperature region (25°C to 150°C), and linear fitting is performed for each interval. The slope of the line is determined using the least squares method for each interval; the slope for the low-temperature region is denoted as Ea_low, and the slope for the high-temperature region is denoted as Ea_high. These two slope values ​​are the activation energy factors for the corresponding temperature intervals, expressed in electron volts (eV), reflecting the thermal activation characteristics of leakage current at low and high temperatures, respectively, ultimately generating temperature activation energy characteristic parameters.

[0029] A feature data structure is constructed, comprising four core parameters: subthreshold slope factor SS, drain voltage exponential growth factor λ, low-temperature activation energy factor Ea_low, and high-temperature activation energy factor Ea_high. To improve the effectiveness of the feature data, each parameter is normalized by subtracting the pre-statistical average value from each parameter value and dividing by the standard deviation. For different transistor sizes, a size correction coefficient is introduced, multiplying the feature parameters by the corresponding correction coefficient to eliminate the influence of device size differences. After parameter processing, the four normalized parameters are encapsulated into a feature vector according to a predefined data structure, and supplemented with test condition information (including temperature range, gate voltage range, and drain voltage range) and device type identifier, ultimately generating standard circuit response gradient feature data.

[0030] Preferably, in step S2, the integrated circuit under test is subjected to a test using an integrated circuit test strategy, and then the circuit leakage current dominant component data is evaluated, including: The integrated circuit test strategy is used to perform stimulus tests on the integrated circuit under test and collect the response data of the circuit under test. Gradient feature analysis is performed on the response data of the circuit under test to obtain the gradient feature data of the circuit under test response; Calculate the cosine similarity of each feature in the response gradient feature data of the circuit under test and the response gradient feature data of the standard circuit to obtain a list of response similarity scores; Linear decomposition calculation is performed based on the response similarity score list to determine the contribution weight of each feature vector in the response gradient feature data of the standard circuit to the response gradient feature data of the circuit under test, and thus obtain the leakage current component contribution weight data. The weight values ​​in the leakage current component contribution weight data are normalized to generate the circuit leakage current dominant component data.

[0031] In this embodiment of the invention, the integrated circuit sample under test is fixed in a test socket, and the contact resistance between the test probe and the circuit test point is controlled within 0.5 ohms. The test system applies a precise voltage sequence to the sample according to the integrated circuit excitation test strategy: gate voltage from -1 volt to 2 volts in 10 millivolt steps; drain voltage from 0 volt to 2 volts in 50 millivolt steps. The test temperature is set from -40 degrees Celsius to 150 degrees Celsius in 5-degree intervals. Under each test condition, the current acquisition sensitivity of the test system is set to 100 picoamperes, the sampling rate is 10 kHz, 100 samples are collected at each test point, and the average value is calculated to eliminate the influence of random noise. All test data are acquired through a 16-bit analog-to-digital converter and stored as a three-dimensional data matrix. The matrix dimensions are the number of gate voltage points × the number of drain voltage points × the number of temperature points, and the matrix element values ​​are the leakage current values ​​under the corresponding conditions, constituting complete response data of the circuit under test.

[0032] The gradient analysis process for the circuit under test response data is identical to that in step S1: Under fixed drain voltage and temperature conditions, the drain current-gate voltage data is differentiated using the central difference method to generate the gate voltage transconductance curve; in the subthreshold region, the least squares method is applied to fit the logarithmically transformed drain current-gate voltage relationship to calculate the subthreshold slope factor; under fixed gate voltage and temperature conditions, the drain current-drain voltage data is differentiated after a logarithmic transformation to generate the drain voltage exponential growth factor; under fixed gate voltage and drain voltage conditions, the drain current-temperature data is subjected to an Arrhenius transform followed by piecewise linear fitting to generate the temperature activation energy factors for the low-temperature and high-temperature regions. During feature extraction, a smoothing filter is used for each differential operation, with a filter window width of 5 data points and Gaussian distribution of filter coefficients to ensure the accuracy of gradient calculation. Finally, the four extracted feature parameters are combined to form the gradient feature data vector of the circuit under test response.

[0033] The response gradient feature data vector of the circuit under test is compared with each feature vector in the standard circuit response gradient feature database. Each feature vector contains four components: subthreshold slope factor, leakage voltage exponential growth factor, low-temperature activation energy factor, and high-temperature activation energy factor. For the test feature vector A and the standard feature vector B, the dot product of the two vectors is calculated and divided by the product of their magnitudes to obtain the cosine similarity value. During the cosine similarity calculation, different weights are assigned to each component: the subthreshold slope factor has a weight of 0.3, the leakage voltage exponential growth factor has a weight of 0.2, the low-temperature activation energy factor has a weight of 0.2, and the high-temperature activation energy factor has a weight of 0.3. The weight allocation is determined based on the degree of influence of each parameter on the leakage characteristics. The cosine similarity between each feature vector in the standard circuit response gradient feature database and the test feature vector is calculated, generating a response similarity score list, which is sorted in descending order of similarity value.

[0034] The gradient feature vector of the circuit under test is represented as a linear combination of the gradient feature vectors of the standard circuit response. The contribution weight of each standard feature vector is determined by solving a system of linear equations. Specifically, a standard feature matrix X is constructed, with the number of rows equal to the number of standard feature vectors and the number of columns equal to the number of feature components (4). The feature vector to be tested, Y, is constructed. The non-negative least squares method is used to solve the weight vector W in the equation XW=Y, with the constraint that the weight values ​​are non-negative and their sum is 1. The solution process uses the alternating projection method, with an upper limit of 1000 iterations and a convergence threshold of 10^-6. To improve the solution accuracy, the top 10 standard feature vectors in the similarity score list are used in the linear decomposition calculation, while standard feature vectors with a similarity lower than 0.5 are ignored. The calculated weight vector W represents the contribution weight data of the leakage current component, indicating the degree of contribution of each standard leakage current feature to the leakage current characteristics of the circuit under test.

[0035] The weight values ​​in the leakage current component contribution weight data are filtered, retaining only components with contribution weights greater than 0.05, and setting weight values ​​less than 0.05 to 0 to eliminate interference from minor contribution components. The filtered weight values ​​are then normalized, and the percentage of each retained component's weight relative to the total weight is calculated. After normalization, the leakage mechanism label corresponding to each standard feature vector is associated with its normalized weight value to generate a data structure for the dominant leakage current component. This data structure includes three fields: leakage mechanism identifier, normalized contribution weight value, and contribution confidence score. The confidence score is calculated by multiplying the original similarity score by the weight value.

[0036] Of particular importance, based on the response similarity score list, linear decomposition calculations are performed to determine the contribution weights of each feature vector in the standard circuit response gradient feature data to the response gradient feature data of the circuit under test, including: The feature vector corresponding to the highest score in the response similarity score list is taken as the first dominant component to obtain the first dominant component identification data. The residual feature vector is obtained by subtracting the first dominant component identifier data and its contribution weight from the gradient feature data of the circuit under test response. The similarity calculation and dominant component identification are repeatedly performed on the residual feature vectors until the magnitude of the residual feature vectors is less than a preset threshold, thus obtaining the dominant component sequence; The contribution weights of each component in the dominant component sequence are summarized to generate the contribution weight of the leakage current component.

[0037] In this embodiment of the invention, the response similarity score list is sorted from high to low according to the cosine similarity value, and the feature vector with the highest similarity is extracted as the first dominant component. The sorting process uses a fast sorting algorithm with a time complexity of O(nlogn), where n is the number of standard feature vectors. After determining the first dominant component, the complete information of the feature vector is extracted from the standard circuit response gradient feature database, including four feature component values ​​(subthreshold slope factor, leakage voltage exponential growth factor, low temperature activation energy factor, and high temperature activation energy factor) and their corresponding leakage mechanism identifiers. The projection coefficient is calculated between the extracted feature vector and the response gradient feature vector of the circuit under test. This coefficient is the square of the magnitude of the first dominant component vector divided by the dot product of the two vectors. This projection coefficient is the contribution weight of the first dominant component. The first dominant component identifier data includes the feature vector value, the leakage mechanism identifier, and the contribution weight value.

[0038] The first dominant component's eigenvector is scaled according to its contribution weight to obtain a weighted eigenvector. During scaling, each eigenvalue of the first dominant component is multiplied by its contribution weight to obtain the actual contribution of that component to the characteristics of the circuit under test. Then, the weighted eigenvector is subtracted from the circuit under test's response gradient eigenvector, performing a vector subtraction operation. The subtraction operation is performed in a four-dimensional feature space, calculating the residual values ​​of the four components: subthreshold slope factor, leakage voltage exponential growth factor, low-temperature activation energy factor, and high-temperature activation energy factor. High-precision floating-point arithmetic is used during subtraction, retaining six decimal places to ensure calculation accuracy. After calculation, the residual eigenvector is normalized, adjusting the vector magnitude to unit length for subsequent similarity calculations. The final residual eigenvector represents the characteristics of the circuit under test that have not yet been explained by the first dominant component.

[0039] A residual vector magnitude threshold of 0.1 is set. This threshold, determined through statistical analysis of the standard sample set, represents the noise level in the feature space. For the current residual feature vector, the cosine similarity with each feature vector in the standard circuit response gradient feature database is recalculated, generating a new response similarity score list. The feature vector with the highest similarity is extracted from the updated score list as the next dominant component, its contribution weight is calculated, and this dominant component information is added to the dominant component sequence. The vector subtraction operation is repeated, subtracting the weighted contribution of the newly identified dominant component from the current residual feature vector to obtain a new residual feature vector. The magnitude of the new residual feature vector is calculated. If the magnitude is greater than the preset threshold of 0.1, the iteration process continues; if the magnitude is less than or equal to the preset threshold, the iteration terminates. In practical applications, to prevent infinite loops, the maximum number of iterations is set to 5, meaning a maximum of 5 dominant components can be identified.

[0040] Create an empty contribution weight dictionary with the key being the leakage mechanism identifier and the value initialized to zero. Iterate through each dominant component in the dominant component sequence, extracting its leakage mechanism identifier and contribution weight value. If the leakage mechanism identifier already exists in the contribution weight dictionary, add the current contribution weight value to the corresponding value in the dictionary; otherwise, create a new entry in the dictionary with the key being the current leakage mechanism identifier and the value being the current contribution weight value. During the accumulation process, apply a decay coefficient to recurring leakage mechanisms. The decay coefficient is set to a power of 0.9, where the power is the order of occurrence of the mechanism in the dominant component sequence minus one, to reduce the influence weight of subsequently identified components. After summarization, normalize all values ​​in the contribution weight dictionary to ensure that the sum of all weight values ​​is 1. Finally, convert the dictionary into a structured data format to generate leakage component contribution weight data containing leakage mechanism identifiers and corresponding contribution weight values.

[0041] Preferably, step S2, which involves analyzing the dominant temperature-sensitive leakage behavior based on the dominant component data of circuit leakage and determining the defect time constant type of the integrated circuit under test, includes: Temperature dependence was assessed based on the dominant component data of circuit leakage current, and dominant temperature-sensitive leakage current behavior was analyzed to obtain dominant component leakage current-temperature point data. The ambient temperature was adjusted based on the leakage current-temperature point data of the dominant component, and a voltage pulse with an amplitude of 0.25 V and a pulse width of 10 microseconds was applied to the gate of the integrated circuit under test. The drain current was monitored simultaneously to obtain the original transient leakage current curve data. The transient peak current data is obtained by extracting the current value 1 nanosecond after the pulse rise edge ends based on the original transient leakage current curve data. The current value at 1 microsecond before the end of the pulse is extracted from the original transient leakage current curve data to obtain transient steady-state current data; The ratio of the fast and slow leakage current components is calculated based on the transient peak current data and the transient steady-state current data. The test is performed based on the ratio of the fast and slow leakage components. If the ratio is greater than a preset threshold, it is determined that there is a slow-state trap defect in the leakage path of the integrated circuit under test. Otherwise, it is determined to be a fast-state interface defect, and the defect time constant type is obtained.

[0042] In this embodiment of the invention, the three leakage components with the highest contribution weights are extracted from the dominant leakage component data. For each dominant leakage component, its complete temperature-dependent characteristic curve is extracted from the standard circuit response database. Based on the extracted temperature characteristic curve, the sensitivity coefficient of leakage current to temperature change within the temperature range of -40°C to 150°C is calculated. This coefficient is obtained by calculating the average of the leakage current change rate between adjacent temperature points. Subsequently, the range with the largest temperature sensitivity coefficient is identified as the key temperature range dominating temperature-sensitive leakage behavior. The system extracts the leakage current data points of the dominant leakage components within the key temperature range, forming dominant component leakage-temperature point data, which includes 5 key temperature points and their corresponding standardized leakage current values. The temperature point selection algorithm is based on the principle of equal leakage current change rate, ensuring that the selected temperature points can reflect the characteristics of leakage current changing with temperature to the greatest extent.

[0043] The integrated circuit under test (ICD) is fixed on a temperature-controlled test fixture made of copper with a gold-plated surface and a thermal conductivity greater than 380 W / m·Kelvin. Based on the dominant component leakage current-temperature point data, a test temperature sequence is set with a temperature control accuracy of ±0.1°C. The test system uses bidirectional temperature control technology combining semiconductor cooling elements and precision heating wires, controlling the temperature change rate at 2°C / min to avoid thermal shock damage to the sample. After each temperature point stabilizes (temperature fluctuation less than ±0.05°C for 30 seconds), a pulse generator applies a standard pulse signal to the gate of the ICD. The pulse amplitude is precisely controlled at 0.25 volts ±1 millivolt, the pulse rise and fall times are both 1 nanosecond, the pulse width is 10 microseconds, and the repetition frequency is 10 kHz. Simultaneously, the drain current is monitored in real time at a sampling rate of 1 gigahertz, with a dynamic range from 1 nanoamp to 10 milliamps and an acquisition accuracy of ±0.1%, obtaining the raw transient leakage current curve data.

[0044] The original transient leakage current curve data is time-referenced to ensure that the 50% level point of the pulse rising edge is used as the time zero point. Then, a precision timing trigger is used to initiate sampling precisely 1 nanosecond after the pulse rising edge ends, with a sampling window width set to 100 picoseconds. To improve data accuracy, the system repeats the pulse test 100 times at each temperature point, collecting 100 sets of transient leakage current curve data. The current value is extracted at the target time (1 nanosecond after the rising edge) for each set of data, and outliers are removed using median filtering. Specifically, the highest and lowest 10% of data points are excluded, and the average value of the remaining data points is calculated. The average peak current at each temperature point is integrated into a transient peak current dataset, which includes both temperature and corresponding peak current values, reflecting the temperature characteristics of the rapid response component of the leakage current.

[0045] For the original transient leakage current curve data, the time window is located to 1 microsecond before the end of the pulse, at which point the leakage current has basically reached its steady-state value. An integral sampling method is used, with 50 points uniformly sampled within a 200 nanosecond time window before and after the target time, with an 8-nanosecond interval between sampling points. A weighted average is calculated on the 50 sampled data points, with a weight of 1 at the center point, linearly decreasing to 0.5 towards both sides to eliminate the influence of random noise. Similarly, 100 pulse tests are repeated at each temperature point to obtain 100 sets of steady-state current data. The singular value decomposition (SVD) algorithm is applied to denoise the data, retaining the first three principal components, and reconstructing a smooth steady-state current value. The steady-state current values ​​at each temperature point are integrated into a transient steady-state current dataset, containing both temperature value and corresponding steady-state current value, reflecting the temperature characteristics of the slow response component of the leakage current.

[0046] Transient peak current data and transient steady-state current data are matched one-to-one at temperature points to form paired datasets. For each temperature point data pair, the ratio of peak current to steady-state current is calculated to obtain the original ratio data. To eliminate the influence of the circuit's intrinsic current, the baseline current value is subtracted from the peak current and steady-state current. The baseline current value is determined by the average current in the 5 microseconds before the measurement pulse is applied. After correction, the ratio of peak current to steady-state current is recalculated to obtain corrected ratio data. Cubic spline interpolation is applied to the corrected ratio data at each temperature point to generate a continuous ratio-temperature curve. The ratio data for key temperature points (-40°C, 25°C, 85°C, 125°C) are extracted from the curve. Finally, the weighted average of these key temperature point ratios is calculated, with weights assigned as 25°C (0.4), 85°C (0.3), 125°C (0.2), and -40°C (0.1), to obtain the final leakage current fast and slow component ratio data.

[0047] The system reads the ratio of the fast to slow leakage components and compares it with a preset threshold. The preset threshold is 2.5, obtained through statistical analysis of a large number of integrated circuit samples with known defect types. Specifically, it calculates the average of the fast to slow leakage component ratios for 100 known slow-state trap defect samples and 100 known fast-state interface defect samples, and takes the arithmetic mean of the two as the judgment threshold. When the ratio of the fast to slow leakage components of the integrated circuit under test is greater than 2.5, it is determined that there is a slow-state trap defect in its leakage path; when the ratio is less than or equal to 2.5, it is determined to be a fast-state interface defect. The judgment result is stored as defect time constant type data, containing three fields: defect type identifier, ratio data, and judgment confidence level. The judgment confidence level is calculated by the distance between the ratio and the threshold; the greater the distance, the higher the confidence level. The calculation formula is: Confidence Level = |Ratio - Threshold| / Threshold × 100%, with a maximum value limited to 100%.

[0048] Preferably, step S3, which calculates the defect-induced barrier height change data based on standard circuit response gradient characteristic data and defect time constant type, includes: Logarithmic coordinate transformation is performed on the original transient leakage current curve data, and the absolute temperature reciprocal and leakage current logarithm corresponding to each temperature point are calculated to generate leakage current logarithm-temperature reciprocal data. Multi-segment linear fitting was performed on the leakage current logarithm-temperature reciprocal data, and the slope of each segment was calculated to obtain the segmented activation energy spectrum; The target activation energy slope is determined based on the type of defect time constant. If it is a slow-state trap defect, the slope of the medium-temperature region is selected from the segmented activation energy spectrum; if it is a fast-state interface defect, the slope of the low-temperature region is selected to obtain the target activation energy slope. The medium-temperature region is the temperature range above 25°C, and the low-temperature region is the temperature range below 25°C. The measured defect activation energy value is calculated by multiplying the target activation energy slope by the preset Boltzmann constant. The activation energy of the ideal device in the standard circuit response gradient feature data is extracted as a benchmark, and the measured defect activation energy value is subtracted to generate defect-induced barrier height change data.

[0049] In this embodiment of the invention, steady-state leakage current values ​​at each temperature point are extracted from the original transient leakage current curve data to form temperature-current data pairs. The temperature values ​​are expressed in Kelvin units. The formula for converting Celsius to Kelvin is T_K = T_C + 273.15, where T_K is Kelvin and T_C is Celsius. For each temperature point, its reciprocal 1 / T_K is calculated, with the unit being the reciprocal of Kelvin. Simultaneously, the natural logarithm of the leakage current value I_D at each temperature point is taken to obtain the ln(I_D) value. The calculated 1 / T_K is used as the abscissa, and ln(I_D) as the ordinate to construct a data point set in the Arrhenius coordinate system. During data processing, a 64-bit floating-point calculation engine is used to ensure that the numerical calculation accuracy reaches the order of 10^-15. For abnormal data points (deviations from adjacent points exceeding 3 times the standard deviation) that occur during the measurement process, cubic spline interpolation is used for correction to ensure the continuity and smoothness of the data point distribution.

[0050] Data smoothing was performed on the logarithm of leakage current minus the reciprocal of temperature using a Savitzky-Gorley filter with a window width of 7 data points and a polynomial order of 3 to reduce the impact of random noise. Subsequently, an adaptive piecewise algorithm was applied to divide the data points. This algorithm sets the segment boundaries based on the rate of change of the slope of the data points. Specifically, it calculates the linear fitting slope of five adjacent points, marking a segment boundary when the slope change exceeds 20%. For data in the temperature range of -40°C to 150°C, it is typically divided into three segments: a low-temperature region (-40°C to 25°C), a medium-temperature region (25°C to 85°C), and a high-temperature region (85°C to 150°C). A least-squares method was applied to perform linear fitting for each segment, with the fitting equation being ln(I_D) = a × (1 / T_K) + b, where a is the slope and b is the intercept. During the fitting process, the weight of each data point is inversely proportional to its measurement uncertainty, ensuring that high-quality data points contribute more to the fitting results. Finally, the slope values ​​a_low, a_mid, and a_high of the three data segments were obtained, which constitute the segmented activation energy spectrum.

[0051] The system reads the defect time constant type data to determine the defect type of the integrated circuit under test. The judgment logic is based on the correspondence between defect type and temperature range: when the defect time constant type is a slow-state trap defect, the system extracts the slope value a_mid of the mid-temperature region (25°C to 85°C) from the segmented activation energy spectrum as the target activation energy slope; when the defect time constant type is a fast-state interface defect, the system extracts the slope value a_low of the low-temperature region (-40°C to 25°C) as the target activation energy slope. The selection is based on semiconductor physics theory, where slow-state trap defects mainly exhibit significant temperature dependence in the mid-temperature region, while fast-state interface defects are more pronounced in the low-temperature region. In actual execution, the system simultaneously checks the correlation coefficient R² of the data fitting in the selected region. When the R² value is lower than 0.95, the system issues a data quality warning and expands the fitting interval to adjacent temperature points until the R² value meets the requirement or the interval is expanded to its limit.

[0052] The target activation energy slope value is converted from a pure numerical value on the Arrhenius diagram to energy units. During the conversion, the Boltzmann constant k_B is multiplied, with a value of 8.617 × 10^-5 eV / Kelvin. The calculation formula is E_a = -k_B × a_target, where E_a is the measured defect activation energy value in eV, and a_target is the target activation energy slope (a negative value). The negative sign is introduced because in the Arrhenius diagram, leakage current decreases with the reciprocal increase of temperature, resulting in a negative slope, while activation energy is physically defined as positive. The calculation process uses a high-precision scientific computing library, maintaining at least 6 significant digits. For slow-state trap defects, the typical measured activation energy range is 0.3 to 0.6 eV; for fast-state interface defects, the typical range is 0.1 to 0.3 eV. The system compares the calculated activation energy value with the typical range. When the deviation from the typical range exceeds 50%, the outlier check procedure is triggered to re-verify the data processing flow.

[0053] The system extracts the ideal device activation energy reference value E_a_ref, which is made of the same process and structure as the integrated circuit under test, from the standard circuit response gradient characteristic database. The ideal device activation energy reference value is obtained by performing the same testing and analysis process on 10 defect-free samples and calculating their average activation energy, which represents the intrinsic activation energy of the defect-free device. For an N-channel MOSFET, the typical ideal activation energy reference value is approximately 0.7 eV; for a P-channel MOSFET, this value is approximately 0.6 eV. The measured defect activation energy value E_a is subtracted from the ideal device activation energy reference value E_a_ref to obtain the defect-induced barrier height change ΔE, calculated as ΔE = E_a_ref - E_a, in eV. A positive ΔE value indicates that the defect causes a decrease in the barrier, while a negative value indicates an increase in the barrier. The system associates the calculated ΔE value with defect type information to generate a complete defect-induced barrier height change data structure, containing three fields: defect type, barrier change amount, and device identification information.

[0054] Preferably, the reconstruction of the leakage path potential fluctuation spectrum based on the defect-induced barrier height change data in step S3 includes: Identify the steady-state value of leakage current based on the original transient leakage current curve data; A fast pulse voltage with a rise time of 1 nanosecond is applied to the gate of the integrated circuit under test, and the time required for the leakage current response to reach 90% of the steady-state value of the leakage current is measured to obtain the fast pulse response time constant. A slow pulse voltage with a rising edge of 1 microsecond is applied to the gate of the same device in the integrated circuit under test, and the time required for the leakage current response to reach 90% of the steady-state value of the leakage current is measured to obtain the slow pulse response time constant. Calculate the ratio of the fast impulse response time constant to the slow impulse response time constant to obtain the impulse response time constant ratio; Based on the pulse response time constant ratio, the relative spatial position of the defect in the channel direction of the integrated circuit under test is inferred, and the potential distribution is processed according to the defect-induced barrier height change data to obtain discrete potential distribution coordinate points. By connecting the coordinate points of the discrete potential distribution with a smooth curve, the potential fluctuation spectrum of the leakage path can be reconstructed.

[0055] In this embodiment of the invention, the current-time series after pulse application is extracted from the original transient leakage current curve data, with a sampling interval of 1 nanosecond and a total duration of 20 microseconds. A sliding window averaging filter is applied to preprocess the data, with the window width set to 100 nanoseconds to eliminate high-frequency noise. Then, the rate of change of current is calculated, which is the difference between current values ​​at adjacent time points divided by the time interval. When the rate of change of current at 50 consecutive sampling points is less than the steady-state determination threshold (set as 0.1% of the peak current per microsecond), the leakage current is determined to have reached a steady state. To improve the accuracy of identification, the system also calculates the standard deviation of the current value within the next microsecond. When the standard deviation is less than 0.5% of the average value, steady state is further confirmed. After the steady-state interval is determined, the average value of 500 sampling points within that interval is taken as the steady-state value of the leakage current, I_steady, which will be used for subsequent time constant calculations. For cases with high noise, the least squares exponential fitting method is used to predict the limiting steady-state value.

[0056] A high-precision pulse generator was used to apply a standard fast pulse to the gate of the integrated circuit under test. The pulse amplitude was 0.25 volts, the rise time was precisely controlled within 1 nanosecond ± 50 picoseconds, and the pulse width was 50 microseconds to ensure sufficient length for observing the complete response process. The gate voltage was monitored using a high-bandwidth (10 GHz) oscilloscope to ensure that the actual applied pulse met the set requirements. The drain current was converted into a voltage signal by a transimpedance amplifier and then acquired by a 16-bit high-speed data acquisition card with a sampling rate set to 1 GHz to ensure the capture of fast transient processes. The system recorded the complete drain current response curve from the rise of the pulse and determined the time point t_90 when the drain current reached 90% of the steady-state value using a threshold detection method. Specifically, the current threshold I_threshold = I_start + 0.9 × (I_steady - I_start) at the 90% position between the initial current I_start and the steady-state current I_steady was calculated, and then the time point when the current first exceeded this threshold was located on the response curve. The time difference between this time point and the completion of the pulse rise is the fast pulse response time constant τ_fast.

[0057] The slow pulse response time constant was measured using the same test platform but with different pulse settings. After completing the fast pulse test, the system switched to slow pulse mode, applying a slow pulse voltage to the identical device in the integrated circuit under test. The amplitude of the slow pulse was also 0.25 volts, but the rise time was set to 1 microsecond ± 50 nanoseconds, and the pulse width was 100 microseconds. Due to the longer response time, the system reduced the sampling rate to 100 MHz but extended the acquisition window to 200 microseconds to ensure complete capture of the response process. The acquisition and processing method of the leakage current response curve was the same as that of the fast pulse test, but a Gaussian filter was used for signal smoothing to address the slow response characteristics, with the filter standard deviation set to 200 nanoseconds. The threshold detection method was also used to determine the time point when the leakage current reached 90% of the steady-state value. I_threshold = I_start + 0.9 × (I_steady - I_start) was calculated, and the time difference between the first time the threshold was exceeded on the response curve and the completion time of the pulse rise edge was the slow pulse response time constant τ_slow. Set a 30-second recovery time between the two tests to ensure that the device is fully restored to its initial state.

[0058] The system reads the measurement results of the fast pulse response time constant τ_fast and the slow pulse response time constant τ_slow, and directly calculates their ratio R_τ = τ_slow / τ_fast. Floating-point arithmetic is used in the calculation, retaining four significant digits. To ensure the reliability of the calculation results, the system repeats the fast pulse and slow pulse tests 10 times each, obtaining 10 sets of time constant ratios. The maximum and minimum values ​​are then removed, and the average of the remaining 8 sets of data is calculated as the final pulse response time constant ratio R_τ. This ratio typically falls within the range of 1.0 to 5.0, where a value closer to 1.0 indicates the defect location is closer to the drain end, and a larger value indicates the defect location is closer to the source end. The system quantifies and classifies the ratio results, dividing the range of 1.0 to 5.0 into 10 equal intervals, each interval corresponding to a relative position interval in the channel.

[0059] The relative position x_defect of the defect in the channel direction is inferred based on the impulse response time constant ratio R_τ. The inference uses a lookup table method, determining the defect location based on a pre-established table of time constant ratios and locations. This table is established through finite element simulations of the time response characteristics of numerous defects at different locations, covering the entire channel from the source (x=0) to the drain (x=L, where L is the channel length). After determining the defect location, the system creates 11 uniformly distributed sampling points in the channel direction, including the source, drain, and 9 points within the channel. For the defect-free case, the potential distribution follows the classical drift-diffusion model, exhibiting a smooth change. At the defect location x_defect, the potential value is corrected based on the defect-induced barrier height change data ΔE. Specifically, the original potential value is subtracted from ΔE (unit: electron volts), and the value decays towards both sides according to a Gaussian distribution, with the decay width parameter σ set to 5% of the channel length. The corrected value yields a set of discrete potential distribution coordinates containing the source, drain, and 9 points in the channel.

[0060] Discrete potential distribution coordinates are imported into a two-dimensional coordinate system, where the horizontal axis represents the normalized distance from the source to the drain (0 to 1), and the vertical axis represents the potential value (unit: electron volts). To generate a continuous and smooth potential distribution curve, the system uses cubic Hermitian interpolation to process the discrete point data. Hermitian interpolation considers not only point value matching but also derivative matching, generating a smooth C1 continuous curve that better reflects the actual physical process. In the interpolation calculation, the derivative boundary conditions at the source and drain points are determined based on the drift-diffusion equation. The resolution of the interpolated curve is set to 0.1% of the channel length, i.e., generating 1000 interpolation points along the normalized channel length. To enhance the visual effect of potential fluctuations, the system uses gradient color scales to plot the curve, with high potential areas displayed in red and low potential areas displayed in blue. Markers are added at defect locations, and the ideal potential distribution curve under defect-free conditions is indicated by dashed lines as a reference.

[0061] Of particular importance is the inference of the relative spatial location of defects in the channel direction of the integrated circuit under test based on the pulse response time constant ratio, and the processing of potential distribution based on the defect-induced barrier height variation data, including: The pulse response time constant ratio is judged by a preset pulse response time threshold. If it is greater than the preset pulse response time threshold, the defect is determined to be located in a shallow trench isolator in the integrated circuit far from the channel interface; otherwise, it is determined to be located in the oxide layer in the integrated circuit under test near the channel interface, thus obtaining the defect depth region judgment data. Based on the defect depth region determination data, a one-dimensional physical coordinate axis from the source to the drain is established for the transistor channel direction of the integrated circuit under test, and the channel position coordinate axis is obtained. Based on the defect depth region determination data, the barrier reduction in the defect-induced barrier height change data is located to the center region of the channel position coordinate axis or the edge region near the drain electrode to obtain the center position of the barrier depression. The defect activation energy spectrum distribution width is extracted from the original transient leakage current curve data to obtain the potential fluctuation width parameter; Based on the center position of the barrier depression and the width of the potential fluctuation, Gaussian potential distribution processing is performed on the channel position coordinate axis to generate discrete potential distribution coordinate points.

[0062] In this embodiment of the invention, a pulse response time threshold of 2.5 is set. This threshold is determined through statistical analysis of 100 defect samples at known locations. Specifically, the pulse response time constant ratio is measured for 50 shallow trench insulator (STI) defect samples and 50 gate oxide defect samples. The average of the two sets of data is calculated, and the midpoint is taken as the judgment threshold. The system reads the calculated pulse response time constant ratio R_τ and compares it with the preset threshold of 2.5. When R_τ is greater than 2.5, the system determines that the defect is located in a shallow trench insulator far from the channel interface; when R_τ is less than or equal to 2.5, the system determines that the defect is located in the oxide layer near the channel interface. The judgment result includes three fields: defect type identifier (STI or Gate-Ox), pulse response time constant ratio, and judgment confidence level. The confidence level is calculated as |R_τ-2.5| / 2.5×100%, with a maximum limit of 100%. The system stores the judgment result as defect depth region judgment data.

[0063] The transistor channel length L is extracted based on the process information of the integrated circuit under test (ICD), typically ranging from 45 nm to 14 nm, depending on the process node. The origin of the coordinate axis is set at the source (x=0), and the endpoint is set at the drain (x=L). The coordinate axis is linearly and uniformly distributed, with 101 sampling points set along the entire channel length at a sampling interval of L / 100. Each sampling point is assigned a normalized coordinate value, from 0 to 1, representing the positional proportion relative to the total channel length. The system simultaneously establishes a mapping relationship between physical coordinates and normalized coordinates, with physical coordinates in nanometers and normalized coordinates being dimensionless. For devices with different channel lengths, the system achieves standardized comparison through this mapping relationship. The coordinate axis information is stored as structured data, containing four fields: physical length, number of sampling points, physical coordinate array, and normalized coordinate array, constituting a complete channel position coordinate axis definition.

[0064] The system reads the defect depth region determination data to determine the defect location type. For shallow trench insulator (STI) defects, the system sets the center of the barrier depression in the center region of the channel location coordinate axis, corresponding to a normalized coordinate value x_center = 0.5 ± 0.05. For gate oxide (Gate-Ox) defects, the system sets the center of the barrier depression in the edge region near the drain, corresponding to a normalized coordinate value x_center = 0.8 ± 0.05. The precise value of the location setting is determined through a subdivision mapping of the impulse response time constant ratio R_τ: for STI defects, x_center = 0.5 - 0.1 × (R_τ - 2.5) / 2.5 (when R_τ > 2.5); for Gate-Ox defects, x_center = 0.8 - 0.3 × (2.5 - R_τ) / 2.5 (when R_τ ≤ 2.5). The system correlates the defect-induced barrier height change data ΔE with the determined barrier depression center location x_center to form barrier depression location data.

[0065] A Fourier transform is performed on the raw transient leakage current curve data to convert the time-domain response into frequency-domain characteristics. For the raw data with a duration of 50 microseconds and a sampling rate of 1 gigahertz, the system applies the Fast Fourier Transform (FFT) algorithm, using a Hanning window to reduce spectral leakage. In the frequency domain, the system locates the dominant frequency component f_main and its full width at half maximum (FWHM) value Δf. According to measurement theory, the time-domain width is inversely proportional to the frequency-domain width. The system calculates the time constant distribution width σ_t using the relationship σ_t = 0.44 / Δf. The time constant distribution width is then converted into a spatial distribution width σ_x = v_carrier × σ_t using the carrier velocity v_carrier (typically 1 × 10^5 m / s). After normalization, the potential fluctuation width parameter w = σ_x / L is obtained, where L is the channel length and w is a dimensionless parameter with a typical value range of 0.05 to 0.25.

[0066] A basic potential distribution is established on the channel location coordinate axis, following a linear drift model, exhibiting a linear variation from the source (0 volts) to the drain (V_d volts). Subsequently, a Gaussian-shaped barrier perturbation is superimposed at the center of the barrier depression, x_center. The perturbation amplitude is the defect-induced barrier height change ΔE, and the direction is a decrease in potential (negative value). The Gaussian distribution function is expressed as: ΔV(x) = -ΔE × exp[-(x - x_center)² / (2 × w²)], where x is the normalized channel location, ΔV(x) is the potential perturbation value at location x, and w is the potential fluctuation width parameter. The system calculates the potential perturbation value at 101 sampling points and superimposes it onto the basic potential distribution to obtain the perturbed complete potential distribution. To enhance the accuracy of the results, the system densifies the sampling points near the center of the barrier depression, inserting an additional 50 uniformly distributed points within the range of x_center ± 2w. The final result is a set of discrete potential distribution coordinate points containing 151 points, each point containing two data items: location coordinates and the corresponding potential value.

[0067] Preferably, step S4 includes the following steps: Step S41: Identify the lowest potential barrier valley value based on the potential fluctuation spectrum of the leakage path; Step S42: Extract the average barrier height value based on the leakage path potential fluctuation spectrum; Step S43: Calculate the barrier height modulation coefficient based on the lowest barrier valley value and the average barrier height value; Step S44: Based on the barrier height modulation coefficient, intelligent gate control path classification is performed to obtain weak gate control path classification data and strong gate control path classification data respectively; Step S45: Identify the dominant physical location of leakage current in the integrated circuit under test based on the weak gate control path classification data and the strong gate control path classification data, and obtain leakage current physical area identification data.

[0068] In this embodiment of the invention, the potential fluctuation spectrum data of the leakage path is preprocessed, and a five-point median filtering algorithm is applied to eliminate data noise. The filtering window width is 5% of the channel length. Then, a local minimum search is performed, with a search window set on the entire channel position coordinate axis. The window width is 10% of the channel length, and the window sliding step size is 20% of the window width. For each window position, the system calculates the minimum potential value and its location within the window and compares it with the results of neighboring windows. When the minimum value of a certain window is less than the minimum value of the adjacent window, the point is marked as a candidate local minimum. The system performs a secondary judgment on all candidate points, requiring that the values ​​within 10 sampling points to the left and right of the candidate point are all greater than the candidate point value, in order to eliminate false minimums. Among all local minimums after the above double verification, the point with the lowest potential value is selected as the final lowest barrier valley value, and its position coordinates x_min and potential value V_min are recorded.

[0069] Determine the effective integration interval, remove the 10% regions near the source and drain, and only consider the 80% region in the middle of the channel (i.e., the normalized coordinates range from 0.1 to 0.9). This selection is based on experimental observations that the potential changes at both ends of the source and drain are mainly affected by the electrode effect and do not represent the intrinsic barrier characteristics inside the channel. Within the effective interval, the system numerically integrates the potential distribution function using the composite Simpson's integration method, dividing the interval into 100 sub-intervals equally. A quadratic polynomial is used to approximate the potential distribution function within each sub-interval, and then the definite integral value is calculated. The sum of the integrals is divided by the length of the integration interval (0.8) to obtain the average barrier height value V_avg. 64-bit floating-point numbers are used in the calculation process to ensure the calculation accuracy reaches the order of 10^-12. To verify the reasonableness of the calculation results, the system also calculates the arithmetic mean of all sampling points within the effective interval, and the difference between the results of the two methods should be less than 1%, otherwise a data anomaly warning is triggered.

[0070] Read the obtained minimum barrier valley value V_min and the average barrier height value V_avg, and calculate the difference between them ΔV = V_avg - V_min. This value represents the amplitude of the potential fluctuation. To make the results comparable, the system normalizes the difference ΔV by dividing it by the thermal voltage V_T (V_T = kT / q, where k is the Boltzmann constant, T is the absolute temperature, and q is the electron charge). At room temperature (300 Kelvin), V_T is approximately 25.8 mV. After normalization, the dimensionless barrier height modulation coefficient M = ΔV / V_T is obtained. The physical meaning of this coefficient is the ease for thermally excited carriers to cross the barrier. A larger M value indicates a more significant barrier modulation effect. The system conducts a validity check on the calculated M value, and the normal range is from 1 to 20. When it exceeds this range, the system issues a warning and rechecks the input data.

[0071] Set the classification threshold of the barrier height modulation coefficient M_th = 7.5, which is determined through statistical analysis of 100 known types of leakage circuit paths. The specific method is to measure the barrier height modulation coefficients of 50 known weak gate control paths and 50 known strong gate control paths, plot the distribution histograms of the two groups of data, and find the intersection point of the two distributions as the optimal classification threshold. The system reads the calculated barrier height modulation coefficient M and compares it with the preset threshold M_th. When M < M_th, the system classifies this leakage circuit path as a weak gate control path, characterized by a weak ability of the gate voltage to modulate the barrier; when M ≥ M_th, the system classifies this leakage circuit path as a strong gate control path, characterized by a strong ability of the gate voltage to modulate the barrier. The system also calculates the classification confidence, with the formula conf = |M - M_th| / M_th × 100%, and the maximum limit is 100%. The classification result and the confidence are combined into path classification data.

[0072] The system reads path classification data to determine the leakage path type. For weak gate control path classification data, the system identifies the dominant physical location of leakage as the interface between the shallow trench isolation region (STI) and the active region, a region where the gate electric field is difficult to modulate effectively. For strong gate control path classification data, the system identifies the dominant physical location of leakage as the gate oxide (Gate-Ox) region, which is directly controlled by the gate electric field. The system further combines the location information x_min of the lowest barrier valley value to precisely locate the physical location: when x_min < 0.3, it is identified as near the source; when 0.3 ≤ x_min ≤ 0.7, it is identified as the central region of the channel; when x_min > 0.7, it is identified as near the drain. The path type and location information are combined into structured data, including three fields: region type identifier (STI or Gate-Ox), relative location descriptor (source / central / drain), and confidence level, forming complete leakage physical region identification data.

[0073] Preferably, the intelligent gate control path classification based on the barrier height modulation coefficient in step S44 includes: When the barrier height modulation coefficient is greater than 1.5, it is determined to be a gate-controlled weakly correlated path; when the barrier height modulation coefficient is less than or equal to 1.5, it is determined to be a gate-controlled strongly correlated path. Based on the gate-controlled weak correlation path, the reference leakage current of the integrated circuit under test is measured under the condition that the body electrode is 0 V, and the zero-body bias leakage current data is obtained. Apply a reverse bias voltage of -1 V to the body electrode of the transistor in the integrated circuit under test, measure the leakage current at this time, and obtain the reverse body bias leakage current data. The body bias rejection ratio is calculated based on the zero-body bias leakage current data and the reverse-body bias leakage current data. Weak gate control path classification is performed on the body bias suppression ratio data by using a preset leakage range determination threshold to obtain weak gate control path classification data. The weak gate control path classification data includes gate-induced drain leakage path, junction leakage path, and isolation region defect path. Theoretical leakage current suppression ratio data is calculated based on the gate control strong correlation path through the process parameters of the integrated circuit under test; The deviation data of interface state influence is obtained by calculating the difference between the body bias suppression ratio data and the theoretical leakage current suppression ratio data. When the deviation of the interface state influence data is less than the preset interface state influence threshold, it is marked as a channel interface path and used as strong gate control path classification data.

[0074] In this embodiment of the invention, a classification threshold M_th = 1.5 for the barrier height modulation coefficient is set. This threshold is determined through statistical analysis of 200 standard samples. Specifically, the barrier height modulation coefficients of 100 known strongly correlated gate-controlled paths and 100 known weakly correlated gate-controlled paths are measured. The probability density distributions of the two sets of data are plotted, and the intersection of the two distributions is determined as the classification threshold. The system reads the calculated barrier height modulation coefficient M and compares it with the preset threshold of 1.5. When M > 1.5, the system classifies the leakage path as a weakly correlated gate-controlled path, indicating that the gate voltage has a weak modulation capability of the barrier height. When M ≤ 1.5, the system classifies the leakage path as a strongly correlated gate-controlled path, indicating that the gate voltage has a strong modulation capability of the barrier height. The classification result is stored as a preliminary path classification identifier, containing two fields: a path type identifier and a modulation coefficient value.

[0075] The integrated circuit under test (ICD) is fixed on the test fixture, and electrical connections are established with the body electrode, source, drain, and gate of the circuit using a probe card. The body electrode voltage is set to a precise 0 volt ± 0.5 mV, the source is grounded (0 volt), the drain is applied with a voltage of 0.8 volt ± 1 mV, and the gate voltage is set to the off-state voltage (0 volt for NMOS, VDD for PMOS). The current acquisition sensitivity of the measurement system is set to 1 picoampere, and 10 acquisitions are taken and averaged to eliminate random noise. During the measurement, the temperature is controlled at 25°C ± 0.1°C, and the relative humidity is controlled at 40% ± 5% to avoid environmental factors affecting measurement accuracy. The system records the drain current value under steady-state conditions, which is the zero-body bias drain current data I_leak0. The measurement time lasts for at least 1 second to ensure stable current readings with fluctuations less than 0.5% of the reading.

[0076] After completing the zero-body bias measurement, the system maintains the source grounded, drain voltage 0.8 volts, and gate off-state voltage unchanged, adjusting only the body electrode voltage to -1 volt ± 1 millivolt. For N-type transistors, the negative body bias creates a reverse bias, enhancing the depletion region width of the PN junction; for P-type transistors, the positive body bias creates a reverse bias, producing a similar effect. After setting the reverse body bias voltage, the system waits 100 milliseconds for the circuit to stabilize, then executes the same current acquisition procedure as the zero-body bias measurement, maintaining consistent sampling times, temperature, and humidity control conditions. The system records the drain current value under stable conditions, which is the reverse body bias leakage current data I_leak1. This current value is typically less than the leakage current under zero body bias, reflecting the effect of body bias on leakage current suppression.

[0077] The system reads the acquired zero-body bias leakage current data I_leak0 and reverse-body bias leakage current data I_leak1, and calculates their ratio BSR = I_leak0 / I_leak1. This value is the body bias suppression ratio. The calculation uses double-precision floating-point arithmetic, retaining four significant digits. To ensure the validity of the calculation result, the system checks whether I_leak1 is greater than the minimum detection limit of the measurement system (usually 10 picoamps). If it is less than this value, I_leak1 is set to 10 picoamps to avoid an excessively large ratio. Simultaneously, if I_leak0 is less than 100 picoamps, the system marks this calculation result as low confidence and requires further verification. The BSR value typically ranges from 1.0 to 100; a larger value indicates a more significant effect of body bias on leakage current suppression. The system stores the calculated BSR value as body bias suppression ratio data, serving as a key parameter for path classification.

[0078] Two classification thresholds were set: BSR_1 = 3.0 and BSR_2 = 15.0. These thresholds were determined by analyzing 300 known leakage current samples. Specifically, the BSR value distributions of different leakage current paths were plotted, and the boundary values ​​of each type of distribution were identified. For samples initially classified as gate-controlled weakly correlated paths, the system read their body bias suppression ratio (BSR) for further classification: when BSR < 3.0, it was classified as a gate-induced drain leakage path (GIDL), characterized by surface generation enhanced by the gate electric field; when 3.0 ≤ BSR < 15.0, it was classified as a junction leakage path (JL), characterized by reverse leakage current in the PN junction; when BSR ≥ 15.0, it was classified as an isolation defect path (STI), characterized by defect conductivity in the shallow trench isolation structure. The classification results include two fields: a path type identifier (GIDL, JL, or STI) and a BSR value, constituting the weakly gate-controlled path classification data.

[0079] Key parameters are extracted from the process parameter database of the integrated circuit under test: channel doping concentration N_A (typically 1×10^18 / cm³), gate oxide thickness t_ox (typically 1.2 nm), junction depth x_j (typically 50 nm), and substrate doping concentration N_sub (typically 5×10^17 / cm³). Based on these parameters, the system applies a semiconductor physics model to calculate the theoretical leakage current suppression ratio (BSR_theo). The calculation process considers two main mechanisms: the dependence of the PN junction reverse current on the body bias and the sensitivity of the subthreshold leakage current to the body effect. Specifically, a simplified exponential model is used: BSR_theo = exp(|V_body|×q / (n×k×T)), where V_body is the body bias (1 volt), q is the electron charge, k is the Boltzmann constant, T is the absolute temperature, and n is the subthreshold swing factor (typically 1.3 to 1.5). The calculation results are stored as theoretical leakage current suppression ratio data.

[0080] The system reads the calculated body bias suppression ratio (BSR) and theoretical leakage current suppression ratio (BSR_theo), and calculates the relative deviation between them: D_int = |BSR - BSR_theo| / BSR_theo × 100%. This value represents the deviation of the interface state influence, expressed as a percentage. Floating-point arithmetic is used in the calculation, with two decimal places retained. Under normal circumstances, due to the presence of interface states, the actual measured BSR value is usually lower than the theoretical value, with a deviation ranging from 10% to 200%. A larger deviation indicates a more significant impact of the interface states on leakage characteristics. The system verifies the validity of the calculation results. If BSR is greater than BSR_theo, a warning is issued prompting a check of the measurement data or theoretical model parameters. The calculated deviation data serves as a quantitative indicator of the degree of interface state influence.

[0081] A threshold for interface state influence, D_th, is set to 50%. This threshold is determined by analyzing the statistical characteristics of 100 known channel interface defect samples. Specifically, the deviation distribution of interface state influence for these samples is calculated, and the median of the distribution is used as the judgment threshold. The system reads the calculated deviation data of interface state influence, D_int, and compares it with the preset threshold, D_th. When D_int < 50%, the system marks the leakage path as a channel interface path (CI), indicating that the leakage mainly originates from defect states at the gate oxide-semiconductor interface. When D_int ≥ 50%, the system marks the path as another type of strongly gated path, requiring further analysis in conjunction with other parameters. The marking result includes two fields: a path type identifier (CI or Other) and a deviation value, constituting the strongly gated path classification data.

[0082] Therefore, the embodiments should be considered as exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of the equivalents of the application are intended to be included within the invention.

[0083] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features of the invention herein.

Claims

1. A method for integrating and analyzing integrated circuit test information, characterized in that, Includes the following steps: Step S1: Construct an integrated circuit stimulus test strategy; An ideal circuit benchmark test is performed on a standard integrated circuit using an integrated circuit excitation test strategy to generate ideal circuit response data. Based on the ideal circuit response data, the gradient values ​​of leakage current as a function of temperature, gate voltage, and leakage voltage are analyzed to obtain the gradient characteristic data of the standard circuit response. Step S2: Perform stimulus testing on the integrated circuit under test using the integrated circuit stimulus test strategy, and then evaluate the circuit leakage current dominant component data; analyze the dominant temperature-sensitive leakage behavior based on the circuit leakage current dominant component data, and determine the defect time constant type of the integrated circuit under test; Step S3: Calculate the defect-induced barrier height change data based on the standard circuit response gradient characteristic data and the defect time constant type; Reconstruct the potential fluctuation spectrum of the leakage path based on the defect-induced barrier height change data; Step S4: Based on the leakage path potential fluctuation map, intelligently identify the dominant physical location of leakage in the integrated circuit under test, and obtain leakage physical area identification data; Step S5: Perform metastable fault point processing based on the leakage physical area identification data, and then integrate the information based on the circuit leakage dominant component data to feed back to the terminal equipment.

2. The integrated circuit test information integration and analysis method according to claim 1, characterized in that, Step S1, which involves performing ideal circuit benchmark tests on a standard integrated circuit using an integrated circuit stimulus test strategy, includes: The test structure regions of a standard integrated circuit are identified to obtain the circuit reference test structure; the test structure regions include the high-density SRAM region, the analog front-end region, and the independent transistor region of the integrated circuit. Based on the circuit benchmark test structure, a standard electrical excitation sequence is generated by applying a gate voltage scan from -1 V to 2 V with a step size of 10 mV and a drain voltage scan from 0 V to 2 V with a step size of 50 mV to a standard integrated circuit through a test probe card. A standard integrated circuit is placed on a precisely temperature-controlled thermal fixture. A temperature scan sequence is set from -40°C to 150°C with a step size of 5°C. After each temperature point stabilizes, gate voltage and drain voltage are scanned based on a standard electrical excitation sequence to obtain the integrated circuit excitation test strategy. Based on the integrated circuit excitation test strategy, an excitation scan is performed on a standard integrated circuit, and leakage current values ​​are collected simultaneously; Ideal circuit response data is generated by associating the leakage current value with the corresponding test condition data; the test condition data includes gate voltage, leakage voltage, and temperature value.

3. The integrated circuit test information integration and analysis method according to claim 1, characterized in that, Step S1 involves analyzing the gradient values ​​of leakage current as a function of temperature, gate voltage, and leakage voltage based on ideal circuit response data. By taking the first derivative of the leakage current versus gate voltage data in the ideal circuit response data, the gate voltage transconductance variation curve is obtained. The slope of the subthreshold region is calculated based on the gate voltage transconductance variation curve, and the subthreshold slope factor is generated. The leakage current as a function of leakage voltage in the ideal circuit response data is logarithmically transformed and then differentiated to generate the leakage voltage exponential growth factor. The temperature activation energy factor is generated by performing an Arrhenius transform on the leakage current variation with temperature data in the ideal circuit response data and then taking the derivative. The subthreshold slope factor, leakage voltage exponential growth factor, and temperature activation energy factor are combined to form standard circuit response gradient characteristic data.

4. The integrated circuit test information integration and analysis method according to claim 1, characterized in that, In step S2, the integrated circuit under test is subjected to a test using an integrated circuit test strategy, and then the circuit leakage current dominant component data is evaluated, including: The integrated circuit test strategy is used to perform stimulus tests on the integrated circuit under test and collect the response data of the circuit under test. Gradient feature analysis is performed on the response data of the circuit under test to obtain the gradient feature data of the circuit under test response; Calculate the cosine similarity of each feature in the response gradient feature data of the circuit under test and the response gradient feature data of the standard circuit to obtain a list of response similarity scores; Linear decomposition calculation is performed based on the response similarity score list to determine the contribution weight of each feature vector in the response gradient feature data of the standard circuit to the response gradient feature data of the circuit under test, and thus obtain the leakage current component contribution weight data. The weight values ​​in the leakage current component contribution weight data are normalized to generate the circuit leakage current dominant component data.

5. The integrated circuit test information integration and analysis method according to claim 1, characterized in that, In step S2, the dominant temperature-sensitive leakage behavior is analyzed based on the circuit leakage dominant component data, and the defect time constant type of the integrated circuit under test is determined, including: Temperature dependence was assessed based on the dominant component data of circuit leakage current, and dominant temperature-sensitive leakage current behavior was analyzed to obtain dominant component leakage current-temperature point data. The ambient temperature was adjusted based on the leakage current-temperature point data of the dominant component, and a voltage pulse with an amplitude of 0.25 V and a pulse width of 10 microseconds was applied to the gate of the integrated circuit under test. The drain current was monitored simultaneously to obtain the original transient leakage current curve data. The transient peak current data is obtained by extracting the current value 1 nanosecond after the pulse rise edge ends based on the original transient leakage current curve data. The transient steady-state current data is obtained by extracting the current value 1 microsecond before the end of the pulse based on the original transient leakage current curve data. The ratio of the fast and slow leakage current components is calculated based on the transient peak current data and the transient steady-state current data. The test is performed based on the ratio of the fast and slow leakage components. If the ratio is greater than a preset threshold, it is determined that there is a slow-state trap defect in the leakage path of the integrated circuit under test. Otherwise, it is determined to be a fast-state interface defect, and the defect time constant type is obtained.

6. The integrated circuit test information integration and analysis method according to claim 5, characterized in that, Step S3, which calculates the defect-induced barrier height variation data based on standard circuit response gradient characteristic data and defect time constant type, includes: Logarithmic coordinate transformation is performed on the original transient leakage current curve data, and the absolute temperature reciprocal and leakage current logarithm corresponding to each temperature point are calculated to generate leakage current logarithm-temperature reciprocal data. Multi-segment linear fitting was performed on the leakage current logarithm-temperature reciprocal data, and the slope of each segment was calculated to obtain the segmented activation energy spectrum; The target activation energy slope is determined based on the type of defect time constant. If it is a slow-state trap defect, the slope of the medium-temperature region is selected from the segmented activation energy spectrum; if it is a fast-state interface defect, the slope of the low-temperature region is selected to obtain the target activation energy slope. The medium-temperature region is the temperature range above 25°C, and the low-temperature region is the temperature range below 25°C. The measured defect activation energy value is calculated by multiplying the target activation energy slope by the preset Boltzmann constant. The activation energy of the ideal device in the standard circuit response gradient feature data is extracted as a benchmark, and the measured defect activation energy value is subtracted to generate defect-induced barrier height change data.

7. The integrated circuit test information integration and analysis method according to claim 6, characterized in that, Step S3, which involves reconstructing the leakage path potential fluctuation map based on the defect-induced barrier height change data, includes: Identify the steady-state value of leakage current based on the original transient leakage current curve data; A fast pulse voltage with a rise time of 1 nanosecond is applied to the gate of the integrated circuit under test, and the time required for the leakage current response to reach 90% of the steady-state value of the leakage current is measured to obtain the fast pulse response time constant. A slow pulse voltage with a rising edge of 1 microsecond is applied to the gate of the same device in the integrated circuit under test, and the time required for the leakage current response to reach 90% of the steady-state value of the leakage current is measured to obtain the slow pulse response time constant. Calculate the ratio of the fast impulse response time constant to the slow impulse response time constant to obtain the impulse response time constant ratio; Based on the pulse response time constant ratio, the relative spatial position of the defect in the channel direction of the integrated circuit under test is inferred, and the potential distribution is processed according to the defect-induced barrier height change data to obtain discrete potential distribution coordinate points. By connecting the coordinate points of the discrete potential distribution with a smooth curve, the potential fluctuation spectrum of the leakage path can be reconstructed.

8. The integrated circuit test information integration and analysis method according to claim 1, characterized in that, Step S4 includes the following steps: Step S41: Identify the lowest potential barrier valley value based on the leakage path potential fluctuation spectrum; Step S42: Extract the average barrier height value based on the leakage path potential fluctuation spectrum; Step S43: Calculate the barrier height modulation coefficient based on the lowest barrier valley value and the average barrier height value; Step S44: Based on the barrier height modulation coefficient, intelligent gate control path classification is performed to obtain weak gate control path classification data and strong gate control path classification data respectively; Step S45: Identify the dominant physical location of leakage current in the integrated circuit under test based on the weak gate control path classification data and the strong gate control path classification data, and obtain leakage current physical area identification data.

9. The integrated circuit test information integration and analysis method according to claim 1, characterized in that, Step S44, which classifies the intelligent gate control path based on the barrier height modulation coefficient, includes: When the barrier height modulation coefficient is greater than 1.5, it is determined to be a gate-controlled weakly correlated path; when the barrier height modulation coefficient is less than or equal to 1.5, it is determined to be a gate-controlled strongly correlated path. Based on the gate-controlled weak correlation path, the reference leakage current of the integrated circuit under test is measured under the condition that the body electrode is 0 V, and the zero-body bias leakage current data is obtained. Apply a reverse bias voltage of -1 V to the body electrode of the transistor in the integrated circuit under test, measure the leakage current at this time, and obtain the reverse body bias leakage current data. The body bias rejection ratio is calculated based on the zero-body bias leakage current data and the reverse-body bias leakage current data. Weak gate control path classification is performed on the body bias suppression ratio data by using a preset leakage range determination threshold to obtain weak gate control path classification data. The weak gate control path classification data includes gate-induced drain leakage path, junction leakage path, and isolation region defect path. Theoretical leakage current suppression ratio data is calculated based on the gate control strong correlation path through the process parameters of the integrated circuit under test; The deviation data of interface state influence is obtained by calculating the difference between the body bias suppression ratio data and the theoretical leakage current suppression ratio data. When the deviation of the interface state influence data is less than the preset interface state influence threshold, it is marked as a channel interface path and used as strong gate control path classification data.

10. An integrated circuit test information integration and analysis system, characterized in that, The integrated circuit test information integration and analysis system, used to perform the integrated circuit test information integration and analysis method as described in claim 1, comprises: The benchmark feature acquisition module is used to construct integrated circuit excitation test strategies; to perform ideal circuit benchmark tests on standard integrated circuits using integrated circuit excitation test strategies, and to generate ideal circuit response data; and to analyze the gradient values ​​of leakage current with temperature, gate voltage and leakage voltage changes based on the ideal circuit response data, so as to obtain standard circuit response gradient feature data. The leakage current characteristic diagnostic module is used to perform stimulation tests on the integrated circuit under test using integrated circuit stimulation test strategies, and then evaluate the dominant leakage current component data of the circuit; based on the dominant leakage current component data of the circuit, it analyzes the dominant temperature-sensitive leakage current behavior and determines the defect time constant type of the integrated circuit under test; The potential spectrum reconstruction module is used to calculate the defect-induced barrier height change data based on standard circuit response gradient characteristic data and defect time constant type; and to reconstruct the leakage path potential fluctuation spectrum based on the defect-induced barrier height change data. The leakage area location module is used to intelligently identify the dominant physical location of leakage in the integrated circuit under test based on the potential fluctuation map of the leakage path, and obtain leakage physical area identification data. The fault integration and feedback module is used to process metastable fault points based on the leakage physical area identification data, and then integrate the information based on the circuit leakage dominant component data to feed it back to the terminal equipment.

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