ECC storage circuit with self-adaptive reliability

Abstract

The invention discloses an ECC storage circuit with self-adaptive reliability, and belongs to the technical field of digital integrated circuits, the ECC storage circuit with self-adaptive reliability comprises a control module, an ECC coding module, a storage module, an ECC decoding module and a multiplexer, the control module divides a storage area of the storage module according to a bus input address, and the ECC coding module is connected with the multiplexer; the control module is connected with the storage module, so that the storage module comprises at least two storage areas with different bit widths, each storage area has a corresponding storage address, and the control module is used for providing the storage addresses for the storage module and configuring storage contents by using the corresponding storage areas, so that various data storage modes are realized. By providing the storage circuit with the ECC function, the storage space can be adaptively adjusted according to requirements, and different requirements for reliability and real-time performance are met.

Description

Technical Field

[0001] This invention relates to the field of digital integrated circuit technology, and in particular to an adaptive reliability ECC memory circuit. Background Technology

[0002] In recent years, with the transformation of new energy technologies and the automotive industry, the demand for new energy vehicles has increased, leading to a surge in demand for automotive electronic products. The core challenge of automotive electronic products lies in the ever-increasing requirements for reliability, thus driving a continuous increase in the demand for high-reliability chips.

[0003] In chip reliability assessment, the reliability requirements of memory are the main focus. Common methods to improve reliability include: (1) process-level improvements; (2) design technology improvements, optimizing at the algorithm and circuit structure levels. Process improvement cycles are very long and require a lot of manpower and money. The core difficulty is that the time and money spent on each process improvement may far exceed the benefits of the product itself. From a commercial perspective, it is very difficult to carry out process improvements specifically for a single product requirement.

[0004] In the field of design, the background is to improve reliability through design methods under existing process conditions. Commonly used techniques include: (1) Redundant data storage: Adding redundant row and column storage to the memory, updating address decoding during chip testing, and eliminating erroneous addresses. (2) Check code methods: For memory, the most common method is to use data verification, with CRC and ECC technologies being the most common. CRC can only detect errors. Unlike CRC, ECC can correct erroneous bits.

[0005] ECC, short for Error Correction Codes, is an error checking and correction algorithm. Its core lies in storing verification information and correcting errors upon reading. It is widely used in existing products. The number of bits that ECC can correct is positively correlated with the number of redundant bits. Commonly used Hamming code algorithms for ECC can generally correct single-bit errors and check for two-bit errors. While ECC circuits offer significant performance advantages, their substantial area overhead presents the following design challenges:

[0006] First, the contradiction between ECC area overhead and product cost.

[0007] like Figure 1The basic implementation structure of ECC technology is as follows: During data writing, the ECC encoding circuit calculates ECC check data, which is then stored in memory along with the data. During data reading, both the data and check data are read out simultaneously, and the ECC decoding circuit performs data comparison and error correction. Commonly used SoC chips can be classified into different types based on the number of data bits: 4-bit, 8-bit, 16-bit, 32-bit, and 64-bit. The more data bits, the larger the amount of data the MCU can process, and the stronger its performance.

[0008] The memory bit width is often higher than the bus bit width because the memory speed is often slower than digital circuits. To improve chip performance, the memory bit width is set to several times the bus bit width to improve memory read efficiency. For example, the processor and bus are 32-bit, and the memory bit width is set to 128-bit. The different bit widths of memory and bus cause contradictions in ECC calculation: based on bus calculation, 32 bits are grouped together, and 128 bits require 28-bit ECC; based on memory calculation, 128 bits require 9-bit ECC. (1) From a reliability perspective, 32-bit ECC is better, which can realize 4-bit correction / 8-bit detection of 128-bit data, while 128-bit ECC can only realize 1-bit correction and 2-bit detection at most; (2) From a cost perspective, 128-bit ECC has a smaller area and only requires an increase of 7% capacity, while 32-bit ECC requires an increase of 21.9% capacity.

[0009] Second, the contradiction between reliability requirements and the timing of R&D and market launch.

[0010] While 32-bit ECC offers higher reliability, ECC itself relies heavily on process analysis, and its bit depth is related to the probability of process failure. Typically, product design and market launch take several years. Waiting entirely for the process to mature before starting the design process risks missing out on market opportunities, while choosing a mature process often leads to difficulties in negotiating prices and a lack of profit. This means that once a product design is complete, it inevitably faces the challenge of growing alongside the manufacturing process.

[0011] The requirements for ECC correction vary at different product stages. (1) Early stage of product: The supporting process is not yet complete and still needs adjustment. However, the product has the potential to seize the market and cannot wait for process improvement before investing. At this time, the memory failure rate cannot be met by using 128-bit ECC, so 32-bit ECC is used to solve the problem through a higher correction method. (2) Mature stage of product: The supporting process is complete, and 128-bit correction method can be used at this time.

[0012] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0013] The purpose of this invention is to provide an adaptive reliability ECC memory circuit to resolve the contradiction between ECC area overhead and product cost, and the contradiction between reliability requirements and the timing of research and development and market launch.

[0014] To address the aforementioned technical problems, this invention provides an adaptive reliability ECC storage circuit, comprising a control module, an ECC encoding module, a storage module, an ECC decoding module, and a multiplexer. The control module divides the storage area of ​​the storage module according to the bus input address, so that the storage module contains at least two storage areas with different bit widths, each storage area having a corresponding storage address. The control module configures the storage content using the corresponding storage area by providing the storage address to the storage module, thereby realizing multiple data storage modes.

[0015] During a write operation, the control module receives and concatenates the input data, which is then transmitted to the ECC encoding module. The ECC encoding module obtains the input data from the control module, configures the encoding according to the data storage mode, and then transmits the encoding result to the storage module for storage. During a read operation, the storage module outputs the data to be decoded to the ECC decoding module for decoding. The ECC decoding module then outputs the decoded data to the multiplexer for selection and output.

[0016] Preferably, the storage module includes a first storage area with a bit width of 64 bits and a second storage area with a bit width of 73 bits. The first storage area corresponds to a first storage address, and the second storage area corresponds to a second storage address. By using one or two storage areas, three data storage modes can be implemented: standard 128-bit mode, enhanced 64-bit mode, and enhanced 32-bit mode.

[0017] Preferably, in the standard 128-bit mode, the high 64 bits and low 64 bits of the encoding result received by the storage module are stored in the first storage area and the second storage area respectively, 128-bit ECC information is calculated and stored in the second storage area, at which time the first storage address is equal to the second storage address.

[0018] Preferably, in the enhanced 64-bit mode, the written data 0 to 7 are stored in the 0 to 7 address bits of the first storage area, and the first layer of ECC operation is performed: the corresponding 64-bit ECC information is calculated based on the written data and stored in bits 9 to 72 of address 0 in the second storage area; the second layer of ECC operation is performed: the check data is calculated based on the 64-bit ECC information and stored in bits 0 to 8 of address 0; and so on to calculate and store the remaining data.

[0019] Preferably, in the enhanced 32-bit mode, the written data 0 and data 1 are stored in the first storage area address 0, the written data 2 and data 3 are stored in the first storage area address 1, and so on; the first layer ECC operation is performed: the 56-bit ECC32 information corresponding to data 0 to 7 is calculated and stored in the 9 to 72-bit area of ​​the second storage area address 0, and the extra 8 bits can be padded with 0 or 1; the second layer ECC operation is performed to calculate the check data of the 56-bit ECC32 information and store it in the second storage area address 0; the remaining data is calculated and stored in the same way.

[0020] Preferably, the ECC encoding module includes a first bit mapping unit, a second bit mapping unit, and an ECC encoding unit. The first bit mapping unit obtains input data from the control module, arranges the data according to the data storage mode and the input configuration signal, and inputs it to the ECC encoding unit for calculation. The calculation result is output to the second bit mapping unit for arrangement and input as the encoding result into the storage module.

[0021] Preferably, the ECC encoding unit includes a first adaptive XOR gate combination and a 64-bit XOR gate encoding combination. The first adaptive XOR gate combination contains multiple XOR arrays, and the XOR arrays are combined using multiple two-input XOR methods. The 64-bit XOR gate encoding combination receives the output results of the first adaptive XOR gate combination in the enhanced 64-bit mode and the enhanced 32-bit mode, performs standard ECC 64-bit encoding calculation, and sends the calculation result to the second bit mapping unit.

[0022] Preferably, the number of XOR arrays in the first adaptive XOR gate combination is set based on the number of calculations used, and the XOR arrays in the first adaptive XOR gate combination are cascaded with a second multiplexer to achieve the corresponding data storage mode. The second multiplexer transmits the calculation result to the second bit mapping unit.

[0023] Preferably, the ECC decoding module includes a third bit mapping unit, a fourth bit mapping unit, and an ECC decoding unit. The third bit mapping unit obtains the data to be decoded from the storage module, arranges the data according to the data storage mode, inputs it into the ECC decoding unit for calculation, outputs the decoding result to the fourth bit mapping unit for arrangement, and outputs it to the multiplexer.

[0024] Preferably, the ECC decoding unit includes a second adaptive XOR gate combination and a 64-bit XOR gate decoding combination. The second adaptive XOR gate combination adopts the same structure as the first adaptive XOR gate combination. The 64-bit XOR gate decoding combination is used to perform standard ECC 64-bit decoding operations and inputs the correction data into the second adaptive XOR gate combination. The second adaptive XOR gate combination merges and corrects the read data and the correction data, and then outputs it to the fourth bit mapping unit.

[0025] In the adaptive reliability ECC storage circuit provided by this invention, the storage space can be adaptively adjusted according to requirements to meet different reliability and real-time requirements. The circuit provided by this invention can be organized in a stepped manner with dynamic ECC changes according to different application conditions. Based on the ECC enhancement direction, three or more data storage modes can be realized through at least two storage regions with different bit widths. According to the data reliability requirements, the corresponding data is reconstructed into a suitable ECC algorithm, improving data space utilization and enhancing product robustness. Taking 32-bit data as an example, setting up a storage region with a bit width of 64 bits and a storage region with a bit width of 73 bits, the dual-layer enhanced ECC storage circuit corrects 2 bit failures for every 32-bit and 64-bit data. The dual-layer ECC enhancement mode proposed by this invention can make the ECC data calculated from the 32-bit and 64-bit storage modes more reliable. For the case of 1 ECC bit error + 1 data bit error, the data can be corrected after ECC bit correction, thereby realizing the correction function of 2 bit failures.

[0026] This invention also enables tiered ECC partitioning to meet the reliability requirements of products under different application conditions, thereby improving product robustness. Based on different requirements, the storage circuit is organized in a tiered manner with dynamically changeable ECC, and the data storage mode is set according to the ECC reinforcement direction. Using a tiered ECC organization, combined with the application, corresponding data blocks can be reconstructed into appropriate ECC algorithms according to data reliability requirements, improving data space utilization. By combining the standard ECC mode and the dual-layer ECC reinforcement mode, it is possible to reliably repair 1 bit, 2 bits, and 4 bits of data per 128 bits, respectively, thus achieving tiered data reliability protection. Attached Figure Description

[0027] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0028] Figure 1 This is a schematic diagram of existing ECC application scenarios;

[0029] Figure 2 This is a system architecture diagram of an embodiment of the present invention;

[0030] Figure 3 This is a block diagram of a storage module according to an embodiment of the present invention;

[0031] Figure 4 This is a schematic diagram of the ECC encoding module structure according to an embodiment of the present invention;

[0032] Figure 5 This is a schematic diagram of the ECC decoding module structure according to an embodiment of the present invention. Detailed Implementation

[0033] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0034] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; the term “at least two” is generally used to mean “two or more”; furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first," "second," and "third" may explicitly or implicitly include one or at least two of those features. The term "proximal" typically refers to the end closer to the operator, and the term "distal" typically refers to the end closer to the patient. "One end" and "the other end," as well as "proximal" and "distal," generally refer to two corresponding parts, including not only endpoints. The terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can be fixed connections, detachable connections, or integral connections; they can be mechanical connections or electrical connections; they can be direct connections or indirect connections through an intermediate medium; they can be internal connections between two elements or interactions between two elements. Furthermore, as used in this invention, the placement of one element on another element generally only indicates a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of another element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0035] The inventors discovered through research that, for example Figure 1 The existing ECC circuit architecture shown, when writing data from the AHB bus (e.g., writing 32-bit data), uses an ECC encoder to calculate ECC checksum data, which is then stored in memory along with the data. For example, 32-bit data and 7-bit ECC information are written to SRAM. When reading data, both the data and checksum data are read simultaneously, and an ECC decoder performs data comparison and error correction. This places certain demands on memory area, but increasing memory area obviously increases product cost. Furthermore, the ECC correction requirements vary at different stages of the product development process, and redesigning the system would present a series of challenges.

[0036] Based on this, the core idea of ​​the present invention is to provide a storage circuit with ECC function that can adaptively adjust the storage space according to requirements to meet different reliability and real-time requirements.

[0037] For details, please refer to Figures 2-5 This is a schematic diagram of an embodiment of the present invention. Figure 2 As shown, an adaptive reliability ECC storage circuit includes a controller, an ECC encoder, a storage module, an ECC decoder, and a multiplexer (MUX). The controller divides the storage area of ​​the storage module Storage according to the bus input address HADR, so that the storage module Storage contains at least two storage areas with different bit widths. Each storage area has a corresponding storage address. The controller provides storage addresses to the storage module Storage and configures the storage content using the corresponding storage area to realize multiple data storage modes.

[0038] During a write operation, the Controller receives and concatenates the input data, which is then transmitted to the ECC Encoder. The ECC Encoder obtains the input data from the Controller, configures the encoding according to the data storage mode, and then transmits the encoded result to the Storage module for storage. During a read operation, the Storage module outputs the data to be decoded to the ECC Decoder for decoding. The ECC Decoder then outputs the decoded data to the MUX multiplexer for selection and output.

[0039] like Figure 2 The overall circuit structure comprises five modules: a controller, an ECC encoder (ECCEncoder), a storage module, an ECC decoder, and a multiplexer (MUX). The controller handles the concatenation, readback, and storage address calculation of the 32-bit input data (HWDATA), and configures the modules under different modes. The multiplexer (MUX) selects the output based on the input address (HADR). The circuit provided by this invention can dynamically adjust the ECC settings in a stepped manner according to different application conditions. Based on the ECC enhancement direction, it can achieve three or more data storage modes through at least two storage regions with different bit widths. According to data reliability requirements, it can reconstruct the corresponding data into a suitable ECC algorithm, improving data space utilization and enhancing product robustness.

[0040] It should be noted that the technical solution provided in this invention is described based on 32-bit data. Extending it to other data bit widths, such as 64 bits, can be achieved by modifying the controller and multiplexer. This is basic industry knowledge and will not be elaborated upon here. The following will describe in detail, using 32-bit data as an example, the Storage module consisting of a first storage area (Data) and a second storage area (Data_ECC), as well as the corresponding three data storage modes: standard 128-bit mode, enhanced 64-bit mode, and enhanced 32-bit mode.

[0041] The Controller module handles the concatenation and readback of 32-bit input data HWDATA, operations on the first storage address CA0 and the second storage address CA1, read and write operations based on the read / write control signal HWRITE, and configuration of each module under different data storage modes. The MUX multiplexer performs a 32-bit selection on the read 128-bit data Q based on the bus input address HADR and transmits it to the read port HRDATA. This invention proposes an enhanced dual-layer ECC circuit that can operate in three different reliability data storage modes: standard 128-bit, enhanced 64-bit, and enhanced 32-bit. In the enhanced 64-bit and enhanced 32-bit modes, the number of recoverable data bits increases progressively, thus improving the reliability level progressively.

[0042] Specifically, the Storage module contains a first storage area Data with a bit width of 64 bits and a second storage area Data_ECC with a bit width of 73 bits. The first storage area Data corresponds to the first storage address CA0, and the second storage area Data_ECC corresponds to the second storage address CA1. Three data storage modes are implemented using one or two storage areas: standard 128-bit, enhanced 64-bit, and enhanced 32-bit. The Storage module receives the control signal CTRL from the Controller module, the first storage address CA0 and the second storage address CA1, and the encoded results 64-bit CD0 and 73-bit CD1 output by the ECC Encoder module.

[0043] Storage module structure as follows Figure 3 As shown, it consists of two storage areas: the first storage area (Data) and the second storage area (Data_ECC), with bit widths of 64 bits and 73 bits respectively. As shown in the table, the corresponding storage content is adjusted according to different configuration signals (CFG). Figure 3 In this context, CA0 and CA1 represent the addresses of two storage regions, and data allocation is performed based on different configuration signals (CFG). It can be understood that the storage regions within the Storage module are divided into multiple storage regions via the bus input address HADR, and each region is configured with independent ECC (Electronic Code Correction) via the configuration signal CFG. Under different CFG configurations, data is encoded according to different ECC configurations. The first storage address CA0 and the second storage address CA1 in the Storage module are organized into different modes, and the addresses of the first storage address CA0 and the second storage address CA1 are mapped by the Controller module based on the HADR.

[0044] In standard 128-bit mode, the high 64 bits and low 64 bits of the encoding result received by the Storage module are stored in the first storage area CA0 and the second storage area CA1, respectively. 128 bits of ECC information are calculated and stored in the second storage area Data_ECC. At this time, the first storage address CA0 is equal to the second storage address CA1. The bus input address HADR is automatically mapped to the stored first storage address CA0 and second storage address CA1.

[0045] Referring to Table 1 below, the 128-bit mode is used for stable product production. Data uses the standard ECC algorithm, with the high 64 bits and low 64 bits stored in the first storage area (Data) and the second storage area (Data_ECC), respectively. The 128-bit ECC information is stored in the second storage area (Data_ECC). At this time, storage area CA0 equals CA1.

[0046] Specifically, in the enhanced 64-bit mode, the written data 0 to 7 are stored in the 0 to 7 address bits of the first storage area Data, and the first layer of ECC operation is performed: the corresponding 64-bit ECC information is calculated based on the written data and stored in bits 9 to 72 of address 0 of the second storage area Data_ECC; the second layer of ECC operation is performed: the check data is calculated based on the 64-bit ECC information and stored in bits 0 to 8 of address 0; and so on to calculate and store the remaining data.

[0047] The enhanced 64-bit mode employs an enhanced dual-layer ECC circuit. For example, as shown in Table 1, data 0 through 7 are stored at addresses 0 through 7 in the first storage area, Data. The first layer of ECC: the 64-bit ECC information ECC640 through ECC647, calculated based on the written data 0 through 7, is stored in bits 9 through 72 at address 0 in the second storage area, Data_ECC. The second layer of ECC: the ECC64 checksum data, calculated based on ECC640 through ECC64, is stored in bits 0 through 8 at address 0. The remaining data is calculated and stored in the same manner.

[0048] Specifically, in enhanced 32-bit mode, data 0 and data 1 are stored in the first storage area Data address 0, data 2 and data 3 are stored in the first storage area Data address 1, and so on. The first layer of ECC operation is performed: the 56-bit ECC32 information corresponding to data 0-7 is calculated and stored in the 9-72 bit area of ​​the second storage area Data_ECC address 0. The extra 8 bits can be padded with 0s or 1s. The second layer of ECC operation is performed: the check data of the 56-bit ECC32 information is calculated and stored in the second storage area Data_ECC address 0. The remaining data is calculated and stored in the same manner.

[0049] The enhanced 32-bit mode is similar to the 64-bit mode, employing an enhanced two-layer ECC algorithm. For example, as shown in Table 1, 32-bit data 0 and data 1 are stored in the first storage area at address 0, data 2 and data 3 are stored in the first storage area at address 1, and so on. The 56 bits of ECC32 data corresponding to data 0 to 7 are stored in the 9th to 72nd bit area of ​​the second storage area at address 0. The extra 8 bits can be padded with 0s or 1s without affecting the ECC decoding circuit's processing result in this mode. Through the second-layer ECC operation, the corresponding ECC64 code is also stored in the second storage area at address 0. The remaining data is calculated and stored in the same way.

[0050] Table 1 below also provides the data bit width. For example, the annotation [63:0] after CD0 / CQ indicates that its bit width is 64. Figure 2 and Figure 3 The same principle applies to China.

[0051] Table 1 Data Organization in Storage Areas

[0052]

[0053]

[0054] The dual-layer ECC enhancement mode proposed in this invention can improve the reliability of ECC data calculated in 32-bit and 64-bit storage modes. For cases of 1 bit ECC error + 1 bit data error, data correction can be completed after ECC bit correction, thus achieving a 2-bit failure correction function. Depending on different requirements, the storage circuit is organized in a stepped manner with dynamically changing ECC, and based on the ECC enhancement direction, it is divided into three ECC modes: standard 128-bit, enhanced 64-bit, and enhanced 32-bit. Using a stepped ECC organization, it can be combined with applications to reconstruct corresponding data blocks into appropriate ECC algorithms according to data reliability requirements, improving data space utilization. Combining the standard ECC mode and the dual-layer ECC enhancement mode, it is possible to reliably repair 1 bit, 2 bits, and 4 bits of data per 128 bits, respectively, thereby achieving stepped data reliability protection.

[0055] The ECC encoding module ECC Encoder includes a first bit mapping unit Bit Mapping Mux-1, a second bit mapping unit Bit Mapping Mux-2, and an ECC encoding unit. The first bit mapping unit obtains input data D from the control module Controller, arranges the data according to the data storage mode and the input configuration signal CFG, and inputs it to the ECC encoding unit for calculation. The calculation result is output to the second bit mapping unit Bit Mapping Mux-2 for arrangement and is input to the storage module Storage as the encoding result CD0, CD1.

[0056] The ECC encoding unit includes a first adaptive XOR gate combination Adapt-ECC-1 and a 64-bit XOR gate encoding combination ECC64_ENC. The first adaptive XOR gate combination Adapt-ECC-1 contains multiple XOR arrays, and the XOR arrays are combined using multiple two-input XOR methods. The 64-bit XOR gate encoding combination ECC64_ENC receives the output results of the first adaptive XOR gate combination Adapt-ECC-1 in the enhanced 64-bit mode and the enhanced 32-bit mode, performs standard ECC64-bit encoding calculation, and sends the calculation result to the second bit mapping unit BitMapping Mux-2.

[0057] The number of XOR arrays in the first adaptive XOR gate combination Adapt-ECC-1 is set based on the number of calculations used. The XOR arrays in the first adaptive XOR gate combination Adapt-ECC-1 are cascaded with the corresponding data storage modes using the second multiplexer MUX-2. The second multiplexer MUX-2 passes the calculation results to the second bitmapping unit BitMapping Mux-2.

[0058] like Figure 4 As shown, the ECC encoding module consists of four units: two bit mapping units (BitMapping Mux-1 and BitMapping Mux-2, also referred to as BMM1 and BMM2) and two ECC encoding units composed of XOR arrays (Adapt-ECC-1, the first adaptive XOR gate combination, and ECC64_ENC, the 64-bit ECC XOR gate combination).

[0059] The first mapping unit BMM1 obtains data from the control module Controller. Based on the mode configuration, it arranges the data using Table 1, arranging the 128-bit data. Depending on the different data storage modes (128 / 64 / 32 bits), the corresponding XOR array is input. The XOR array in the first adaptive XOR gate combination Adapt-ECC-1 uses multiple two-input XOR combinations, with the number of XOR arrays determined based on the number of XOR gates used in different calculations. The XOR arrays are cascaded through the second multiplexer MUX-2 to achieve different mode structures.

[0060] Taking the calculation of P1 code in phase coding as an example, a single calculation in 128-bit mode requires 67 XOR gates, two calculations in enhanced 64-bit mode require 70 XOR gates, and four calculations in enhanced 32-bit mode require 72 XOR gates. A total of four XOR arrays are used, each containing 18 XOR gates. In enhanced 32-bit mode, the second multiplexer MUX-2 transmits the corresponding data from the first mapping unit BMM1 to the XOR gates for calculation. In enhanced 64-bit or 128-bit mode, the second multiplexer MUX-2 transmits the data from the first mapping unit BMM1, or the results from other XOR arrays, forming a cascade of XOR gates. In enhanced 64-bit mode, the XOR arrays are cascaded in pairs; in 128-bit mode, all four arrays are cascaded. The XOR cluster data path can be switched via the second multiplexer MUX-2 according to the configuration signal CFG. The calculated P1 code is arranged through the second bit mapping unit BMM2 and transmitted to the storage module Storage as input data CD0 and CD1. ECC64_ENC implements standard ECC64-bit calculation. In enhanced 64-bit mode, the calculation result is ECC32*, or in enhanced 32-bit mode, the calculation result is ECC34*. After being input into a 64-bit ECC XOR gate and combined with ECC64_ENC for calculation, it is transmitted to the corresponding input data port of the storage module Storage through the second bit mapping unit BMM2. The second bit mapping unit BMM2 also receives data output from the first bit mapping unit BMM1 for data arrangement.

[0061] Even better, in 128-bit mode, the 64-bit ECC XOR gate combination ECC64_ENC does not work, and low-power processing can be carried out through conventional design methods, such as power-off, to reduce overall power consumption.

[0062] Based on the aforementioned ECC Encoder module, a corresponding ECC Decoder module is provided. The ECC Decoder module includes a third bit mapping unit (BitMapping Mux-3), a fourth bit mapping unit (BitMapping Mux-4), and an ECC decoding unit. The third bit mapping unit (BitMapping Mux-3) obtains the data to be decoded (CQ0, CQ1) from the storage module (Storage), arranges the data according to the data storage mode, and inputs it into the ECC Decoder unit for calculation. The decoding result is then output to the fourth bit mapping unit (BitMapping Mux-4) for arrangement and finally output to the multiplexer (MUX).

[0063] In one embodiment, the ECC decoding unit includes a second adaptive XOR gate combination Adapt-ECC-2 and a 64-bit XOR gate decoding combination ECC64_DEC. The second adaptive XOR gate combination Adapt-ECC-2 adopts the same structure as the first adaptive XOR gate combination Adapt-ECC-1. The 64-bit XOR gate decoding combination is used to perform standard ECC64-bit decoding operations and inputs the ECC64 correction data into the second adaptive XOR gate combination Adapt-ECC-2. The second adaptive XOR gate combination Adapt-ECC-2 merges and corrects the read data and the ECC64 correction data, and then outputs it to the fourth bit mapping unit Bit Mapping Mux-4.

[0064] like Figure 5 As shown, the ECC decoding module, ECC Encoder, consists of four units: two bit mapping units (BitMapping Mux-3 and BitMapping Mux-4, hereinafter referred to as BMM3 and BMM4) and two ECC decoding units composed of XOR arrays (Adapt-ECC-2 and ECC64_DEC, a 64-bit XOR gate decoding combination). The structure of Adapt-ECC-2 is the same as that of Adapt-ECC-1 in the ECC encoding unit. ECC64_DEC internally uses an XOR array to perform standard ECC64 bit decoding operations and inputs the corrected ECC64 data into Adapt-ECC-2. In enhanced 32-bit or enhanced 64-bit mode, Adapt-ECC-2 merges the read data with the corrected ECC64 data and outputs it to the fourth bit mapping unit, BMM4. Similarly, in 128-bit mode, the 64-bit XOR gate decoding combination ECC64_DEC does not work, and low-power processing can be achieved through conventional design methods.

[0065] The adaptive reliability ECC storage circuit of the present invention includes a control module, a storage module, an ECC encoding module, an ECC decoding module, and a multiplexer basic component. Based on configuration, it can simultaneously encode, store, and decode one standard 128-bit ECC data, one enhanced 64-bit ECC data, and two enhanced 32-bit ECC data. Based on mode definition, 32-bit and 64-bit data are stored separately from their corresponding ECC data, while multiple ECC data and their corresponding calculated 64-bit ECC checksums are stored together. For a single 64-bit or 32-bit data, recovery can be achieved for one ECC code error and one data error. The storage module includes two memories with different data widths: one 64-bit and the other 73-bit. In 128-bit mode, the 64-bit memory stores the high 64 bits of the data at each address, and the 73-bit memory stores the low 64 bits and the corresponding ECC information for each 128-bit data at each address. In 64-bit mode, the 64-bit memory stores one data entry at each address, and the 73-bit memory stores the ECC information for eight data entries at each address, along with the corresponding ECC checksum. In 32-bit mode, the 64-bit memory stores two 32-bit data entries at each address, and the 73-bit memory stores the ECC information for eight data entries at each address, along with the corresponding ECC checksum. The memory addresses are controlled by the controller, calculated based on the input address, and generate different write or read addresses for the two memories based on the operating mode. The adaptive XOR gate combination design used in the ECC encoding and decoding modules is based on different numbers of two-input XOR gate groups. The corresponding number is set based on the XOR gates used for different check bits, and the input data is switched through a multiplexer by using the number of XOR gates in different modes.

[0066] The technical effects of this invention include:

[0067] A dual-layer enhanced ECC circuit corrects two-bit errors for every 32-bit and 64-bit data. The dual-layer ECC enhancement mode proposed in this invention improves the reliability of ECC data calculated in 32-bit and 64-bit storage modes. In the case of a 1-bit ECC error plus a 1-bit data error, data correction can be achieved after ECC bit correction, thus realizing the correction function for two-bit errors.

[0068] Tiered ECC classification matches the reliability requirements of products under different application conditions, improving product robustness. Based on different requirements, the storage circuit is organized in a tiered manner with dynamically adjustable ECC, and according to the ECC reinforcement direction, it is divided into three ECC modes: standard 128-bit, reinforced 64-bit, and reinforced 32-bit. Using a tiered ECC organization, corresponding data blocks can be reconstructed into appropriate ECC algorithms according to application and data reliability requirements, improving data space utilization. Combining the standard ECC mode and the dual-layer ECC reinforcement mode, it is possible to reliably repair 1 bit, 2 bits, and 4 bits of data for every 128 bits of data, respectively, thus achieving tiered data reliability protection.

[0069] Furthermore, this invention is an IP circuit, applicable to both chip-level and IP-level designs. Based on different configurations of address and data bit widths, various memory capacities can be expanded, and storage areas can be implemented using standard memory modules such as flash memory and SRAM. The design includes 128-bit, 64-bit, and 32-bit modes, which can be tailored to specific applications. It can be implemented using industry-standard digital design methods, based on commercial standard cell libraries and conventional digital design software.

[0070] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. An adaptive reliability ECC memory circuit, characterized in that, It includes a control module, an ECC encoding module, a storage module, an ECC decoding module, and a multiplexer. The control module divides the storage area of ​​the storage module according to the bus input address, so that the storage module contains at least two storage areas with different bit widths. Each storage area has a corresponding storage address. The control module provides the storage address to the storage module and configures the storage content using the corresponding storage area to realize multiple data storage modes. During a write operation, the control module receives and concatenates the input data, which is then transmitted to the ECC encoding module. The ECC encoding module obtains the input data from the control module, configures the encoding according to the data storage mode, and then transmits the encoding result to the storage module for storage. During a read operation, the storage module outputs the data to be decoded to the ECC decoding module for decoding. The ECC decoding module then outputs the decoded data to the multiplexer for selection and output.

2. The adaptive reliability ECC memory circuit according to claim 1, characterized in that, The storage module contains a first storage area with a bit width of 64 bits and a second storage area with a bit width of 73 bits. The first storage area corresponds to a first storage address, and the second storage area corresponds to a second storage address. By using one or two storage areas, three data storage modes can be implemented: standard 128-bit mode, enhanced 64-bit mode, and enhanced 32-bit mode.

3. The adaptive reliability ECC memory circuit according to claim 2, characterized in that, In standard 128-bit mode, the high 64 bits and low 64 bits of the encoding result received by the storage module are stored in the first storage area and the second storage area respectively. 128-bit ECC information is calculated and stored in the second storage area. At this time, the first storage address is equal to the second storage address.

4. The adaptive reliability ECC memory circuit according to claim 2, characterized in that, In the enhanced 64-bit mode, the written data 0 to 7 are stored in the 0 to 7 address bits of the first storage area, and the first layer of ECC operation is performed: the corresponding 64-bit ECC information is calculated based on the written data and stored in bits 9 to 72 of address 0 in the second storage area; the second layer of ECC operation is performed: the check data is calculated based on the 64-bit ECC information and stored in bits 0 to 8 of address 0; and so on to calculate and store the remaining data.

5. The adaptive reliability ECC memory circuit according to claim 2, characterized in that, In enhanced 32-bit mode, data 0 and data 1 are stored in address 0 of the first storage area, data 2 and data 3 are stored in address 1 of the first storage area, and so on. The first layer of ECC operation is performed: the 56-bit ECC32 information corresponding to data 0-7 is calculated and stored in the 9-72 bit area of ​​address 0 of the second storage area. The extra 8 bits can be padded with 0s or 1s. The second layer of ECC operation is performed: the check data of the 56-bit ECC32 information is calculated and stored in address 0 of the second storage area. The remaining data is calculated and stored in the same manner.

6. The adaptive reliability ECC memory circuit according to claim 2, characterized in that, The ECC encoding module includes a first bit mapping unit, a second bit mapping unit, and an ECC encoding unit. The first bit mapping unit obtains input data from the control module, arranges the data according to the data storage mode and the input configuration signal, and inputs it to the ECC encoding unit for calculation. The calculation result is output to the second bit mapping unit for arrangement and is input to the storage module as the encoding result.

7. The adaptive reliability ECC memory circuit according to claim 6, characterized in that, The ECC encoding unit includes a first adaptive XOR gate combination and a 64-bit XOR gate encoding combination. The first adaptive XOR gate combination contains multiple XOR arrays, and the XOR arrays are combined using multiple two-input XOR methods. The 64-bit XOR gate encoding combination receives the output results of the first adaptive XOR gate combination in the enhanced 64-bit mode and the enhanced 32-bit mode, performs standard ECC 64-bit encoding calculation, and sends the calculation result to the second bit mapping unit.

8. The adaptive reliability ECC memory circuit according to claim 7, characterized in that, The number of XOR arrays in the first adaptive XOR gate combination is set based on the number of calculations used. The XOR arrays in the first adaptive XOR gate combination are cascaded to achieve the corresponding data storage mode using a second multiplexer. The second multiplexer transmits the calculation result to the second bit mapping unit.

9. The adaptive reliability ECC memory circuit according to any one of claims 7-8, characterized in that, The ECC decoding module includes a third bit mapping unit, a fourth bit mapping unit, and an ECC decoding unit. The third bit mapping unit obtains the data to be decoded from the storage module, arranges the data according to the data storage mode, inputs it into the ECC decoding unit for calculation, outputs the decoding result to the fourth bit mapping unit for arrangement, and outputs it to the multiplexer.

10. The adaptive reliability ECC memory circuit according to claim 9, characterized in that, The ECC decoding unit includes a second adaptive XOR gate combination and a 64-bit XOR gate decoding combination. The second adaptive XOR gate combination adopts the same structure as the first adaptive XOR gate combination. The 64-bit XOR gate decoding combination is used to perform standard ECC 64-bit decoding operations and inputs the correction data into the second adaptive XOR gate combination. The second adaptive XOR gate combination merges and corrects the read data and the correction data, and then outputs it to the fourth bit mapping unit.

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