A data acquisition method across cache lines, electronic equipment and storage medium

Abstract

The present application relates to the technical field of chip design, in particular to a cross cache line data acquisition method, electronic equipment and storage medium, which obtains the maximum unit total amount M corresponding to the current subtask belonging to the graphics rendering command; reads and splices the data corresponding to the (M-1) subunits continuous at the end of the first cache line address range and the data corresponding to the (M-1) subunits continuous at the beginning of the second cache line address range, obtains the continuous data covering the complete access range of the current subtask and stores it in the preset buffer; according to the starting address of the current subtask and the first target number of the first target subunit falling in the first cache line, the target data is extracted from the buffer, and the target data is used as the input of the distribution operation, which reduces the logical complexity and the calculation complexity.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip design, in particular to a data acquisition method across cache lines, an electronic device and a storage medium. BACKGROUND

[0002] In application scenarios such as graphics processing, artificial intelligence inference, and high-performance computing, data access patterns are becoming increasingly complex. For example, in sub-drawing calls (subdraw) in graphics rendering or tensor slice access tasks in neural networks, the data required by these tasks may start from the high-bit region of the first cache line and extend to the low-bit region of the second cache line, resulting in the need to read data segments from two consecutive cache lines and splice them to complete the acquisition of complete data. In the traditional data reading mechanism, the system usually adopts a "request-response" mode: whenever a task initiates an access request, the memory management unit generates a read request according to the cache line to which the access address belongs. When the data spans two cache lines, the system independently, sequentially, or in parallel initiates read operations to the two cache lines, and after both pieces of data are returned, the data distribution unit splices and delivers them. In order to avoid repeated reading of memory data, the system can implement non-repetitive reading of cache line data, and during data distribution, the corresponding data needs to be extracted from the already retrieved cache line.

[0003] The traditional data extraction method is to find and calculate the data taken out of the previous cache line by the recorded position, then calculate how much data needs to be retrieved in total according to the data length, then calculate and retrieve the remaining data from the next cache line, and assemble a complete data, and finally extract the real data for distribution from the complete data during distribution. Although this method can acquire data across cache lines, the logic of data extraction is complex, the calculation is large, and it requires a large amount of hardware resources. Therefore, there is an urgent need for a data acquisition method with simple logic and small calculation. SUMMARY

[0004] To solve the above technical problems, the technical solution adopted by the present application is as follows: a data acquisition method across cache lines, the method comprising the following steps:

[0005] S100, acquiring the total amount of sub-units of each sub-task in the current sub-task belonging to the graphics rendering command, and taking the maximum value in the total amount of sub-units of all sub-tasks as the maximum unit total amount M.

[0006] S200, acquiring the first cache line and the second cache line spanned by the current sub-task.

[0007] S300, reading the data corresponding to the (M-1) sub-units continuously at the end of the address range of the first cache line as the low-bit target data segment.

[0008] S400, reading, from the second cache line, data corresponding to (M-1) sub-units continuous at the start of the address range as high target data segments.

[0009] S500, splicing the low target data segments and the high target data segments to obtain continuous data covering the complete access range of the current sub-task and storing the continuous data in a preset buffer.

[0010] S600, obtaining the start address of the current sub-task and a first target number of the first target sub-unit in which the current sub-task falls in the first cache line, extracting target data from the buffer according to the start address and the first target number of the first target sub-unit, and taking the target data as an input of a distribution operation.

[0011] In addition, the application further provides a non-transitory computer readable storage medium, wherein at least one instruction or at least one program is stored in the storage medium, and the at least one instruction or the at least one program is loaded and executed by a processor to implement the above method.

[0012] In addition, the application further provides an electronic device comprising a processor and the above non-transitory computer readable storage medium.

[0013] The application has at least the following beneficial effects:

[0014] The method provided by the application converts the complex data extraction problem across the cache line boundary into reading and splicing the data corresponding to (M-1) sub-units at the end of the first cache line and the data corresponding to (M-1) sub-units continuous at the start of the second cache line, obtaining continuous data covering the complete access range of the current sub-task and storing the continuous data in a preset buffer, and then extracting target data from the buffer, which only needs to generate two fixed address range readings and splicing, greatly simplifies the address generation logic, reduces the variable length processing, makes the control logic more direct and easier to implement, and pre-splices the data in the buffer to form a continuous data block, so that the target data only needs to be extracted from the buffer, without the need for real-time assembly, thereby reducing the operation delay. The method converts the complex data extraction problem across the cache line into a simple and predictable operation, directly reduces the logic complexity, and makes the hardware implementation simpler and easier to verify. In this process, only one simple subtraction is needed to pre-splice the data in the buffer and calculate the first target number to extract the data from the buffer, avoiding the multiple dynamic calculations and complex segment length calculations in the traditional method, and greatly reducing the calculation amount. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to make the technical solutions in the embodiments of the present application clearer, the accompanying drawings needed in the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description only represent some of the embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of the accompanying drawings.

[0016] Figure 1 A flow chart of a data acquisition method across cache lines is provided in the embodiments of the present application. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments only represent some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort on the basis of the present application should fall into the protection scope of the present application.

[0018] Unless otherwise defined, all the technical and scientific terms used in the embodiments of the present application have the same meanings as commonly understood by those skilled in the art.

[0019] Please refer to FIG. 1, which shows a data acquisition method across cache lines, and the method comprises the following steps:

[0020] S100, the total amount of sub-units of each sub-task in the current sub-task belonging to a graphic rendering command is acquired, and the maximum value in the total amount of sub-units of all sub-tasks is taken as the maximum unit total amount M.

[0021] In the graphic rendering, GPU scheduling or parallel computing, a large drawing command (Draw Call) is split into multiple fine-grained sub-tasks, such as subdraw. Each subdraw is an independently schedulable and executable rendering unit, which may involve vertex data, index, texture, shader parameter, etc.

[0022] In an embodiment, each type of drawing command corresponds to a maximum unit total amount. It should be noted that each type of drawing command includes multiple sub-tasks, and the length attribute of each sub-task may be different. And the size of each sub-unit is fixed. Therefore, after analyzing a graphic command package to obtain the type and length attribute value of all sub-tasks included therein, the maximum length attribute value is obtained, and the maximum unit total amount is obtained according to the maximum length attribute value and the size of the sub-unit.

[0023] It should be noted that the amount of data carried in the plurality of sub-tasks included in one graphics rendering command can be different, and if a buffer is allocated for each sub-task, it will cause memory fragmentation and large allocation overhead. Therefore, the basic unit allocated by the graphics rendering command is uniformly allocated a fixed size buffer according to M corresponding to the value of the maximum length attribute in one graphics rendering command, and all tasks reuse the buffer, without the need to allocate a buffer for each sub-task, avoiding frequent memory operations, significantly reducing the risk of fragmentation; At the same time, it avoids the allocation overhead of each sub-task start, and improves the system response speed.

[0024] S200, obtaining a first cache line and a second cache line crossed by a current sub-task.

[0025] The cache line is a basic unit of CPU or GPU cache. When CPU or GPU needs to read data from main memory or video memory, it will not read a single byte or word alone, but read in the unit of the entire cache line.

[0026] In an embodiment, the first cache line and the second cache line are data saved in two cache blocks recorded in the order of read request sending in the issued list, and if the data accessed by the current task is all reused or to be retrieved from the cache line retrieved by the previous read request, the read request of the current task is not sent.

[0027] S300, from the first cache line, reading data corresponding to (M-1) sub-units at the end of the address range as a low target data segment.

[0028] As an example, the size of each cache line is 64 bytes, and the size of each sub-unit is 4 bytes by default, so each cache line is divided into 16 sub-units, and the number of 16 sub-units starts from 0 to 15. Assuming that the address starts from 0, the addresses 0~3 correspond to sub-unit 0, 4~7 correspond to sub-unit 1, and so on.

[0029] It should be noted that the total amount of sub-units to be read is M, and the data to be read spans the cache line, so the data must be in the last (M-1) sub-units of the first cache line. Although two cache lines need to be accessed, this method purposefully reads (M-1) sub-units, which can reduce the total memory access times or transaction numbers through one batch read operation compared with the traditional method. Reduce the load of memory bus or interconnection, reduce power consumption, and improve bandwidth utilization.

[0030] S400, from the second cache line, reading data corresponding to (M-1) sub-units at the beginning of the address range as a high target data segment.

[0031] It should be noted that since the current subtask spans two cache lines, part of the data is at the end of the first cache line and part of the data is at the beginning of the second cache line. Therefore, the other part of the data required by the current subtask is read directly from the beginning of the second cache line.

[0032] wherein the total number of subunits in a cache line is determined. According to the first number, it can be determined how many subunits are included from the first number to the end of the current cache line. According to the second number, it can be determined how many subunits are included from the 0th number of the current cache line to the second number. The sum of the two subunits is M.

[0033] Similarly, the data must also be in the (M-1) subunits at the beginning of the second cache line. This method explicitly reads data from two consecutive cache lines, which can ensure one-time and sequential access to the two key cache lines, reduce the possibility of random access or multiple cross-border access, and significantly reduce cache misses, thereby reducing memory access delay and improving overall performance.

[0034] In an embodiment, S300 and S400 are executed in parallel. It should be noted that the operations of reading the data at the end of the first cache line and the data at the beginning of the second cache line are physically independent, and the two read requests can be initiated in parallel, which can hide part of the memory access delay and further improve the throughput.

[0035] S500, splicing the low-bit target data segment and the high-bit target data segment to obtain continuous data covering the complete access range of the current subtask and storing it in a predetermined buffer. The formation of the buffer can make subsequent data reading more efficient.

[0036] In an embodiment, S500 further comprises: the (M-1) subunits at the end of the first cache line in the buffer are re-assigned with consecutive numbers starting from 0; wherein the subunit with the smallest original number is assigned with the new number 0, and the subsequent subunits are sequentially incremented in number. Wherein, the new number re-assigned to the first target subunit is equal to the sequential position of the target subunit in the M-1 subunits minus one.

[0037] In an embodiment, the new number re-assigned to the first target subunit satisfies: T´=T-(N-M+2), wherein T´ is the new number re-assigned to the first target subunit, T is the first number, and N is the maximum number in the first cache line.

[0038] In one embodiment, the buffer in S500 is a hardware pre-allocated storage space that can be reused by all tasks in the current graphics rendering command. Frequent memory operations are avoided, and the risk of fragmentation is significantly reduced. At the same time, the allocation overhead of each sub-task start is avoided, and the system response speed is improved.

[0039] S600, obtaining the starting address of the current sub-task and the first target number of the first target sub-unit in which the current sub-task falls within the first cache line to which the current sub-task belongs, extracting target data from the buffer according to the starting address and the first target number of the first target sub-unit, and taking the target data as the input of the distribution operation.

[0040] In one embodiment, the starting address of the data accessed by the current sub-task is an absolute address.

[0041] In one embodiment, the step of obtaining the first number comprises: mapping the starting address of the current sub-task to the first cache line to which the current sub-task belongs; calculating the byte offset of the starting address relative to the starting address of the first cache line; determining the sub-unit number in which the starting address falls according to the byte offset and the size of the sub-unit; and taking the sub-unit number as the first number. Specifically, the integer part of the quotient obtained by dividing the offset of the starting address relative to the starting address of the cache line by the size of the sub-unit is the number of the sub-unit.

[0042] In one embodiment, the step of obtaining the first target number of the first target sub-unit in the first cache line to which the first target sub-unit belongs in S100 comprises: obtaining the configured first target number through the positioning entry configured in the position queue, the positioning entry further comprising a reuse state flag; wherein, if the data accessed by the current task is all or part of the cache line retrieved or to be retrieved by the previous read request, the reuse state is valid; otherwise, the reuse state is invalid.

[0043] Therefore, the first number can be directly obtained from the positioning entry.

[0044] The method provided by the application converts the complex data extraction problem across the cache line boundary into reading and splicing the data at the end of the first line and the beginning of the second line. This is much simpler than the complex branch logic that needs to dynamically judge and handle various boundary conditions in the traditional method, directly reduces the logic complexity, and makes the hardware implementation simpler and easier to verify, reducing potential bugs. Since the access mode is relatively fixed, that is, the data of the last (M-1) sub-units and the data of the first (M-1) sub-units are read, the execution time and resource consumption are more predictable than the traditional method that relies on complex dynamic logic.

[0045] In one embodiment, S600 further comprises the step of extracting the target data:

[0046] S610, obtaining a new number of the first target subunit re-assigned in the buffer.

[0047] S620, determining a target start address of the first target subunit in the splicing buffer according to the new number of the first target subunit and the subunit size. As an example, the subunit size is 4 bytes, and the new number is 3, and it is indicated that the start address of the new number 3, i.e., the target start address, is a position with an offset of 12 bytes in the buffer.

[0048] S630, calculating an internal byte offset of a start address of a current subtask relative to the target start address.

[0049] S640, reading a continuous data segment from the buffer based on the internal byte offset and a data length required by the current subtask.

[0050] S650, taking the data segment as distribution data of the current subtask.

[0051] Through the method, data calculation amount can be reduced, and data extraction efficiency can be improved.

[0052] In summary, the embodiment of the present application provides a data acquisition method across cache lines, which acquires a maximum unit total amount M corresponding to a graphic drawing command to which a current subtask belongs, and then reads and splices data corresponding to (M-1) subunits continuously at the end of a first cache line and data corresponding to (M-1) subunits continuously at the start of a second cache line, to obtain continuous data covering a complete access range of the current subtask and store the continuous data in a preset buffer. Compared with a traditional method, the method not only reduces logical complexity, but also further reduces calculation amount and releases more hardware resources.

[0053] The embodiment of the present application also provides a non-transitory computer readable storage medium, which can be arranged in an electronic device to save at least one instruction or at least one program related to a method in the method embodiment, and the at least one instruction or the at least one program is loaded and executed by the processor to realize the method provided by the above embodiment.

[0054] The embodiment of the present application also provides an electronic device, which comprises a processor and the aforementioned non-transitory computer readable storage medium.

[0055] The embodiment of the present application also provides a computer program product, which comprises program code, and when the program product runs on an electronic device, the program code is used to make the electronic device execute steps in the method according to various exemplary embodiments of the present application described in the specification.

[0056] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above-mentioned division of each functional unit and module is exemplified, and in actual application, the above-mentioned functions can be completed by different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the above-described functions.

[0057] Although some specific embodiments of the present application have been described in detail by way of example with reference to the accompanying drawings, it is to be understood that the examples are for illustration only and are not intended to limit the scope of the present application. Those skilled in the art will appreciate that various modifications can be made to the embodiments without departing from the scope and spirit of the present application. The scope of the present application is defined by the appended claims.

Claims

1. A method for retrieving data across cache lines, characterized in that, The method includes the following steps: S100: Obtain the total number of sub-units for each sub-task in the graphics drawing command to which the current sub-task belongs, and take the maximum value among the total number of sub-units of all sub-tasks as the maximum total number of units M. S200, retrieve the first and second cache lines spanned by the current subtask; S300: Read the data corresponding to the last M-1 consecutive sub-units of the address range from the first cache line and use them as the low-order target data segment; S400: Read the data corresponding to the M-1 consecutive sub-units at the beginning of the address range from the second cache line and use them as the high-order target data segment; S500, the low-order target data segment and the high-order target data segment are spliced ​​together to obtain continuous data covering the complete access range of the current subtask and stored in a preset buffer. S600: Obtain the starting address of the current subtask and the first target number of the first target subunit it falls into within its first cache line; extract target data from the buffer according to the starting address and the first target number of the first target subunit; and use the target data as input for the distribution operation.

2. The method according to claim 1, characterized in that, S600 also includes a target data extraction step: S610, Obtain the new number that the first target sub-unit has been reassigned in the buffer; S620, determine the target starting address of the first target sub-unit in the splicing buffer according to the new number and sub-unit size of the first target sub-unit; S630, calculate the internal byte offset of the starting address of the current subtask relative to the target starting address; S640, based on the internal byte offset and the data length required by the current subtask, read a continuous data segment from the buffer; S650, the data segment is used as the distribution data for the current subtask.

3. The method according to claim 2, characterized in that, S500 further includes: the M-1 consecutive sub-units at the end of the first cache line in the buffer are reassigned with consecutive numbers starting from 0; wherein the sub-unit with the smallest original number is assigned the new number 0, and the subsequent sub-units are numbered sequentially. Wherein, the new number reassigned to the first target subunit in the buffer is equal to the sequential position of the target subunit in the M-1 subunits minus one.

4. The method according to claim 2, characterized in that, The new number reassigned to the first target sub-unit in the buffer satisfies: T´=T-(N-M+2), where T´ is the new number assigned to the first target sub-unit, T is the first number, and N is the maximum number in the first cache line; The steps for obtaining the first number are as follows: mapping the starting address of the current subtask to its corresponding first cache line; calculating the byte offset of the starting address relative to the starting address of the first cache line; determining the sub-unit number to which the starting address falls based on the byte offset and the sub-unit size; and using the sub-unit number as the first number.

5. The method according to claim 1, characterized in that, S100 also includes: a maximum total number of cells for each type of drawing command.

6. The method according to claim 1, characterized in that, The step of obtaining the first target number in the first target subunit of S600 within its first cache line includes: obtaining the configured first target number through the location entry of the location queue, wherein the location entry also includes a reuse status flag; wherein, if all or part of the data accessed by the current task is in the cache line retrieved or to be retrieved by the previous read request, the reuse status is valid; otherwise, it is invalid.

7. The method according to claim 6, characterized in that, The first cache line and the second cache line are the data stored in the two cache blocks recorded in the order of the read requests in the issued list. If the data accessed by the current task reuses all the cache lines retrieved or to be retrieved by the previous read request, then no read request is issued for the current task.

8. The method according to claim 1, characterized in that, The buffer in S500 is a hardware-pre-allocated storage space that can be reused by all tasks in the current graphics drawing command.

9. A non-transitory computer-readable storage medium, wherein the storage medium stores at least one instruction or at least one program segment, characterized in that, The at least one instruction or the at least one program segment is loaded and executed by the processor to implement the method as described in any one of claims 1-8.

10. An electronic device, characterized in that, Includes a processor and the non-transitory computer-readable storage medium as described in claim 9.

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