Switching tube driving circuit and electrolytic water hydrogen production system

Abstract

The application discloses a switch tube driving circuit and a water electrolysis hydrogen production system. The switch tube driving circuit comprises a first sampling branch, a second sampling branch, a voltage generation branch, a first comparison branch, a controller and a logic control branch. The first sampling branch outputs a first sampling voltage based on an output current. The second sampling branch outputs a second sampling voltage based on an output voltage. The voltage generation branch generates a reference voltage based on a voltage of a first power supply when the output current is less than or equal to an upper limit value, and generates the reference voltage based on the sampling voltage when the output current is greater than the upper limit value. The first comparison branch outputs a first driving signal based on the reference voltage and a first triangular carrier signal. The controller outputs a second driving signal. The logic control branch outputs a third driving signal according to the first driving signal and the second driving signal. In this way, the response speed can be improved, the risk of overcurrent and overvoltage impact on the electrolytic cell module can be reduced, and the service life of the electrolytic cell module can be prolonged.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a switching transistor drive circuit and an electrolytic water hydrogen production system. Background Technology

[0002] AEM (Anion Exchange Membrane) water electrolysis hydrogen production technology combines the low cost of alkaline water electrolysis hydrogen production technology with the high efficiency of proton exchange membrane water electrolysis hydrogen production technology, making it possible to achieve high-efficiency and low-cost green hydrogen energy production.

[0003] Currently, in AEM water electrolysis hydrogen production stack systems, the electrolyzers are typically designed as series-connected electrolyzer modules. This involves encapsulating a fixed number of membrane electrodes (MEAs) into a single module, and then connecting multiple electrolyzer modules in series within the AEM water electrolysis hydrogen production stack system. The electrolyzer modules are usually powered by a voltage conversion circuit, such as a DC-DC converter. The voltage conversion circuit is typically designed using software strategies to achieve constant current and voltage regulation control.

[0004] However, due to the inherent delay characteristics of software control, in the AEM water electrolysis hydrogen production system, if a single module fails among multiple series-connected electrolyzer modules, the software-implemented constant current and voltage regulation control loop cannot achieve real-time transient constant current and voltage regulation control. As a result, the membrane electrodes in the series-connected electrolyzer modules will be subjected to overcurrent and overvoltage impacts, which will not only shorten the life of the electrolyzer modules, but may even directly damage the membrane electrodes inside the electrolyzer modules. Summary of the Invention

[0005] This application provides a switching transistor drive circuit and an electrolytic water hydrogen production system, which can improve the response speed, reduce the risk of overcurrent and overvoltage impacts on the electrolyzer module, and thus extend the service life of the electrolyzer module.

[0006] In a first aspect, embodiments of this application provide a switching transistor driving circuit for driving a first switching transistor in a voltage conversion circuit. The switching transistor driving circuit includes: a first sampling branch electrically connected to the voltage conversion circuit and configured to output a first sampled voltage based on the output current of the voltage conversion circuit; a second sampling branch electrically connected to the voltage conversion circuit and configured to output a second sampled voltage based on the output voltage of the voltage conversion circuit; a voltage generation branch electrically connected to the first sampling branch and a first power supply, configured to generate a reference voltage based on the voltage of the first power supply when the output current is less than or equal to an upper limit of the output current of the voltage conversion circuit, and configured to generate a reference voltage based on the first sampled voltage when the output current is greater than the upper limit; and a first comparison branch electrically connected to the voltage generation branch, receiving a first triangular carrier signal, and configured to... The first comparison result between the reference voltage and the voltage of the first triangular carrier signal outputs a first drive signal; the controller, electrically connected to the second sampling branch, is configured to perform PI regulation on the difference between the second sampled voltage and the preset voltage to generate a voltage regulation signal, and to perform pulse width modulation operation on the voltage regulation signal and the second triangular carrier signal to output a second drive signal, wherein the waveforms of the first triangular carrier signal and the second triangular carrier signal are the same; the logic control branch, electrically connected to the controller, the first comparison branch and the first switch, is configured to output a third drive signal based on the logic operation result of the first drive signal and the second drive signal to drive the first switch, wherein the third drive signal is consistent with the second drive signal when the output current is less than or equal to the upper limit value, and the third drive signal is consistent with the first drive signal when the output current is greater than the upper limit value.

[0007] In one or more embodiments, the first sampling branch is further configured to differentially sample the output current to output a first sampled voltage.

[0008] In one or more embodiments, the first sampling branch includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor, and a first operational amplifier; the first resistor and the second resistor are connected in series between the positive terminal of the differential sampling signal of the output current and ground, the connection point between the first resistor and the second resistor is electrically connected to the non-inverting input terminal of the first operational amplifier, the first capacitor and the second resistor are connected in parallel, the third resistor and the fourth resistor are connected in series between the negative terminal of the differential sampling signal of the output current and the output terminal of the first operational amplifier, the connection point between the third resistor and the fourth resistor is electrically connected to the inverting input terminal of the first operational amplifier, the second capacitor and the fourth resistor are connected in parallel, and the fifth resistor is electrically connected between the output terminal of the first operational amplifier and the voltage generation branch.

[0009] In one or more embodiments, the voltage generation branch includes a first unidirectional conductive unit and a second unidirectional conductive unit; the first unidirectional conductive unit is electrically connected to a first sampling branch, and the second unidirectional conductive unit is electrically connected to a first power supply; the voltage generation branch is specifically configured such that: when the output current is greater than the upper limit of the output current of the voltage conversion circuit, the first unidirectional conductive unit is turned on and the second unidirectional conductive unit is turned off, so as to generate a reference voltage based on the first sampling voltage; when the output current is less than or equal to the upper limit, the first unidirectional conductive unit is turned off and the second unidirectional conductive unit is turned on, so as to generate a reference voltage based on the voltage of the first power supply.

[0010] In one or more embodiments, the first unidirectional conductive unit is a first diode, the second unidirectional conductive unit is a second diode, and the voltage generation branch further includes a sixth resistor and a seventh resistor; the anode of the first diode is electrically connected to the first sampling branch, the cathode of the first diode is electrically connected to the first end of the sixth resistor and the cathode of the second diode, the anode of the second diode is electrically connected to the first power supply through the seventh resistor, and the second end of the sixth resistor is grounded.

[0011] In one or more embodiments, the first comparison branch includes an eighth resistor, a ninth resistor, a tenth resistor, and a first comparator; the first end of the eighth resistor is electrically connected to the voltage generation branch, the second end of the eighth resistor is electrically connected to the inverting input of the first comparator, the first end of the ninth resistor receives a first triangular carrier signal, the second end of the ninth resistor is electrically connected to the non-inverting input of the first comparator, the output of the first comparator is electrically connected to the first end of the tenth resistor and the logic control branch, and the second end of the tenth resistor is electrically connected to the first power supply.

[0012] In one or more embodiments, the logic control branch includes an eleventh resistor, a twelfth resistor, a thirteenth resistor, a third capacitor, and a first AND gate; the eleventh resistor and the third capacitor are connected in series between the first comparison branch and ground, the connection point between the eleventh resistor and the third capacitor is electrically connected to the first input terminal of the first AND gate, the twelfth resistor and the thirteenth resistor are connected in series between the controller and ground, the connection point between the twelfth resistor and the thirteenth resistor is electrically connected to the second input terminal of the first AND gate, and the output terminal of the first AND gate is electrically connected to the first switching transistor.

[0013] In one or more embodiments, the switch driving circuit further includes: a signal generation circuit, electrically connected to the controller and the first comparison branch respectively, configured to generate a first triangular carrier signal according to the first square wave signal output by the controller, wherein a triangular waveform is generated in each half cycle of the first square wave signal, and multiple triangular waveforms constitute the first triangular carrier signal.

[0014] Secondly, embodiments of this application provide a water electrolysis hydrogen production system, including an input power supply, a voltage conversion circuit, N electrolyzer modules, and a switch driving circuit as described above, wherein N is a positive integer; the N electrolyzer modules are connected in series, the voltage conversion circuit is electrically connected between the input power supply and the electrolyzer modules, and the switch driving circuit is electrically connected to a first switch in the voltage conversion circuit; the switch driving circuit is configured to drive the first switch to turn on or off, so that the voltage conversion circuit generates a voltage to supply power to the electrolyzer modules based on the voltage of the input power supply.

[0015] In one or more embodiments, the water electrolysis hydrogen production system further includes N switching circuits, each of which is electrically connected to an electrolyzer module; the switching circuits are configured to short-circuit the electrolyzer module in the event of an overvoltage or undervoltage fault, wherein, after at least one electrolyzer module is short-circuited, the switching transistor drive circuit adjusts the duty cycle of the output third drive signal so that the output current of the voltage conversion circuit is less than or equal to the upper limit value.

[0016] The beneficial effects of this application are as follows: The switching transistor driving circuit of this application embodiment includes a first sampling branch, a second sampling branch, a voltage generation branch, a first comparison branch, a controller, and a logic control branch. The first sampling branch outputs a first sampled voltage based on the output current of the voltage conversion circuit. The second sampling branch outputs a second sampled voltage based on the output voltage of the voltage conversion circuit. The controller performs PI regulation on the difference between the second sampled voltage and a preset voltage to generate a voltage adjustment signal, and performs pulse width modulation operation on the voltage adjustment signal and a second triangular carrier signal to output a second driving signal. The first comparison branch outputs a first driving signal based on a first comparison result of the reference voltage and the voltage of the first triangular carrier signal. When the output current of the voltage conversion circuit is less than or equal to its upper limit, the voltage generation branch generates a reference voltage based on the voltage of the first power supply. The logic control branch outputs a third drive signal, consistent with the second drive signal, based on the logical operation result of the first and second drive signals. In this case, the third drive signal drives the first switching transistor to adjust the load voltage so that the second sampled voltage equals the preset voltage, which helps reduce the risk of overvoltage surges to the load. When the load is an electrolytic cell module, this reduces the risk of overvoltage surges to the electrolytic cell module. Conversely, when the output current of the voltage conversion circuit is greater than its upper limit, the voltage generation branch generates a reference voltage based on the first sampled voltage. The logic control branch outputs a third drive signal, consistent with the first drive signal, based on the logical operation result of the first and second drive signals. In this case, the third drive signal drives the first switching transistor to adjust the output current of the voltage conversion circuit to reduce it back to less than or equal to the upper limit, which helps reduce the risk of overcurrent surges to the load. When the load is an electrolytic cell module, this reduces the risk of overcurrent surges to the electrolytic cell module. In addition, hardware is used to adjust the output current of the voltage conversion circuit, which has a faster response speed and effectively reduces the risk of overcurrent impact on the electrolytic cell module, thereby extending the service life of the load. When the load is an electrolytic cell module, the service life of the electrolytic cell module is extended. Attached Figure Description

[0017] One or more embodiments are illustrated by way of example with reference to the accompanying drawings, which are not intended to limit the embodiments, and elements having the same reference numerals in the drawings are designated as similar elements.

[0018] Figure 1 This is a schematic diagram of the switching transistor driving circuit provided in the embodiments of this application. Figure 1 ;

[0019] Figure 2 This is a schematic diagram of the circuit structure of the voltage conversion circuit provided in the embodiments of this application;

[0020] Figure 3 This is a schematic diagram of the switching transistor driving circuit provided in the embodiments of this application. Figure 2 ;

[0021] Figure 4 This is a schematic diagram of the circuit structure of the first sampling branch, voltage generation branch, first comparison branch, and logic control branch provided in the embodiments of this application;

[0022] Figure 5 This is a schematic diagram of the signals in the switching transistor drive circuit provided in the embodiments of this application. Figure 1 ;

[0023] Figure 6 This is a schematic diagram of the signals in the switching transistor drive circuit provided in the embodiments of this application. Figure 2 ;

[0024] Figure 7 This is a schematic diagram of the circuit structure of the second sampling branch provided in the embodiments of this application;

[0025] Figure 8 This is a schematic diagram of the switching transistor driving circuit provided in the embodiments of this application. Figure 3 ;

[0026] Figure 9 This is a schematic diagram of the signal generation circuit provided in the embodiments of this application. Figure 1 ;

[0027] Figure 10 This is a schematic diagram of each signal in the signal generation circuit provided in the embodiments of this application;

[0028] Figure 11 This is a schematic diagram of the signal generation circuit provided in the embodiments of this application. Figure 2 ;

[0029] Figure 12 This is a schematic diagram of the water electrolysis hydrogen production system provided in the embodiments of this application. Figure 1 ;

[0030] Figure 13 This is a schematic diagram of the water electrolysis hydrogen production system provided in the embodiments of this application. Figure 2 ;

[0031] Figure 14 This is a schematic diagram of the switching circuit provided in the embodiments of this application. Figure 1 ;

[0032] Figure 15 This is a schematic diagram of the switching circuit provided in the embodiments of this application. Figure 2 ;

[0033] Figure 16This is a schematic diagram of the circuit structure of the second comparison branch, the third comparison branch, the fourth comparison branch, the logic operation branch, and the reset branch provided in the embodiments of this application;

[0034] Figure 17 This is provided by the embodiments of this application. Figure 16 Schematic diagram of each signal in the circuit structure shown Figure 1 ;

[0035] Figure 18 This is provided by the embodiments of this application. Figure 16 Schematic diagram of each signal in the circuit structure shown Figure 2 ;

[0036] Figure 19 This is provided by the embodiments of this application. Figure 16 Schematic diagram of each signal in the circuit structure shown Figure 3 ;

[0037] Figure 20 This is a schematic diagram of the switch branch provided in the embodiments of this application. Figure 1 ;

[0038] Figure 21 This is a schematic diagram of the switch branch provided in the embodiments of this application. Figure 2 ;

[0039] Figure 22 This is a schematic diagram of the switch branch provided in the embodiments of this application. Figure 3 ;

[0040] Figure 23 This is provided by the embodiments of this application. Figure 22 The diagram shows the signals in the circuit structure shown. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and thoroughly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0042] It should be noted that when an element is described as "connected" to another element, it can be directly connected to the other element, or there can be one or more intermediate elements between them.

[0043] Furthermore, the technical features involved in the various embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0044] Please refer to Figure 1 , Figure 1This is a schematic diagram of the block diagram of the switching transistor driving circuit provided in an embodiment of this application. Figure 1 As shown, the switching transistor drive circuit 100 is used to drive the first switching transistor Q1 in the voltage conversion circuit 200 so that the voltage conversion circuit 200 supplies power to the load.

[0045] The voltage conversion circuit 200 is used to convert electrical energy of one voltage level to another voltage level to meet the power supply requirements of the load. In a specific embodiment, the voltage conversion circuit 200 is a DC-DC converter, such as a buck converter. Figure 2 An exemplary circuit structure for a voltage conversion circuit 200 is shown. For example... Figure 2 As shown, the voltage conversion circuit 200 includes a first switching transistor Q1, capacitors CA1 and CA2, resistor RA1, diodes DA1 and DA2, and inductor Lr. Capacitor CA1 is electrically connected between the positive terminal DC_IN+ of the input power supply and ground GND. The drain of the first switching transistor Q1 is electrically connected to the positive terminal DC_IN+ of the input power supply. The gate of the first switching transistor Q1 receives a fourth driving signal GH. The fourth driving signal GH is the signal output by the driver chip after the third driving signal P3 output by the switching transistor driver circuit 100 is input to the driver chip. The fourth driving signal GH is the same as the third driving signal P3, but its driving capability is stronger. Signal HS is a reference ground relative to the fourth driving signal GH. Resistor RA1 is electrically connected between the gate and source of the first switching transistor Q1. Both the anodes of diodes DA1 and DA2 are grounded to GND. The cathode of diode DA1 is electrically connected to the cathode of diode DA2 and the source of the first switching transistor Q1. The first terminal of inductor Lr is electrically connected to the source of the first switching transistor Q1, and the second terminal of inductor Lr is electrically connected to the first terminal of capacitor CA2. The first terminal of capacitor CA2 is the positive terminal DC_OUT+ of the output power supply, and the second terminal of capacitor CA2 is grounded to GND. The second terminal of capacitor CA2 is the negative terminal DC_OUT- of the output power supply. The output power supply is electrically connected to the load to supply power to the load. The first switching transistor Q1 is controlled by the fourth drive signal GH (which can also be understood as being controlled by the third drive signal P3) to turn on or off, thereby reducing the voltage of the input power supply and outputting the power supply to power the load.

[0046] Please return to the reference. Figure 1 The switching transistor drive circuit 100 includes a first sampling branch 10, a second sampling branch 20, a voltage generation branch 30, a first comparison branch 40, a controller 50, and a logic control branch 60.

[0047] The first sampling branch 10 is electrically connected to the voltage conversion circuit 200, the second sampling branch 20 is electrically connected to the voltage conversion circuit 200, the voltage generation branch 30 is electrically connected to the first sampling branch 10 and the first power supply VC1, the first comparison branch 40 is electrically connected to the voltage generation branch 30, the controller 50 is electrically connected to the second sampling branch 20, and the logic control branch 60 is electrically connected to the controller 50, the first comparison branch 40, and the first switching transistor Q1.

[0048] Specifically, the first sampling branch 10 is configured to output a first sampling voltage SV1 based on the output current of the voltage conversion circuit 200. The second sampling branch 20 is configured to output a second sampling voltage SV2 based on the output voltage of the voltage conversion circuit 200. The voltage generation branch 30 is configured to generate a reference voltage VREF based on the voltage of the first power supply VC1 when the output current is less than or equal to the upper limit of the output current of the voltage conversion circuit 200, and is configured to generate a reference voltage VREF based on the first sampling voltage SV1 when the output current is greater than the upper limit. The first comparison branch 40 receives a first triangular carrier signal S1 and is configured to output a first drive signal P1 based on a first comparison result between the reference voltage VREF and the voltage of the first triangular carrier signal S1. The controller 50 is configured to perform PI regulation on the difference between the second sampling voltage SV2 and a preset voltage to generate a voltage regulation signal, and to perform pulse width modulation operation on the voltage regulation signal and the second triangular carrier signal (denoted as S2) to output a second drive signal P2, wherein the waveforms of the first triangular carrier signal S1 and the second triangular carrier signal S2 are the same. The specific implementation process of pulse width modulation (PWM) operation on the voltage regulation signal and the second triangular carrier signal S2 is as follows: the voltage regulation signal (i.e., the modulation wave) and the second triangular carrier signal S2 are compared in real time. When the voltage of the modulation wave is greater than the voltage of the second triangular carrier signal S2, the comparison result is high level; when the voltage of the modulation wave is less than or equal to the voltage of the second triangular carrier signal S2, the comparison result is low level. Thus, a continuous analog signal (i.e., the modulation wave) is converted into a discrete, variable-width square wave signal, i.e., a PWM signal. The logic control branch 60 is configured to output a third drive signal P3 based on the logic operation result of the first drive signal P1 and the second drive signal P2 to drive the first switch Q1. When the output current is less than or equal to the upper limit value, the third drive signal P3 is consistent with the second drive signal P2; when the output current is greater than the upper limit value, the third drive signal P3 is consistent with the first drive signal P1.

[0049] In practical applications, when the output current of the voltage conversion circuit 200 is less than or equal to the upper limit, the voltage generation branch 30 generates a reference voltage VREF based on the voltage of the first power supply VC1. Since the reference voltage VREF remains unchanged, the first drive signal P1 remains unchanged. The third drive signal P3 output by the logic control branch 60 is consistent with the second drive signal P2. At this time, the first switching transistor Q1 is driven by the third drive signal P3 to adjust the load voltage so that the second sampled voltage equals the preset voltage. Therefore, a preset voltage can be set based on the voltage required to supply power to the load (denoted as the target voltage). Through the above-mentioned automatic voltage adjustment process, the load voltage can be made to the target voltage, which also helps to reduce the risk of overvoltage surges to the load. When the load is an electrolytic cell module, the risk of overvoltage surges to the electrolytic cell module can be reduced. It can be understood that the process by which the controller 50 outputs the second drive signal P2 based on the second sampled voltage SV2 and the preset voltage is the execution of a voltage loop, with the goal of adjusting the load voltage to make the second sampled voltage equal to the preset voltage, thereby making the load voltage the target voltage.

[0050] When the output current of the voltage conversion circuit 200 exceeds the upper limit, the voltage generation branch 30 generates a reference voltage VREF based on the first sampling voltage SV1. At this time, the reference voltage VREF increases with the increase of the first sampling voltage SV1. The third drive signal P3 output by the logic control branch 60 is consistent with the first drive signal P1. Since the reference voltage VREF increases with the increase of the first sampling voltage SV1, the third drive signal P3 drives the first switching transistor Q1 to reduce the output current of the adjustable voltage conversion circuit 200 until the output current of the voltage conversion circuit 200 decreases to be less than or equal to the upper limit again. This reduces the risk of overcurrent surges to the load. When the load is an electrolytic cell module, it also reduces the risk of overcurrent surges to the electrolytic cell module. Furthermore, in this embodiment, hardware implementation is used to adjust the output current of the voltage conversion circuit 200, which provides a faster response speed, effectively reducing the risk of overcurrent surges to the load and thus extending the service life of the load. When the load is an electrolytic cell module, this extends the service life of the electrolytic cell module.

[0051] In one specific embodiment, when the output current of the voltage conversion circuit 200 is less than or equal to the upper limit value, the first drive signal P1 remains unchanged. Simultaneously, the duty cycle of the second drive signal P2 output by the controller 50 is less than the duty cycle of the first drive signal P1. The logic control branch 60 outputs a third drive signal P3 based on the logical AND result of the first drive signal P1 and the second drive signal P2, so that the third drive signal P3 is consistent with the second drive signal P2. When the output current of the voltage conversion circuit 200 is greater than the upper limit value, the second drive signal P2 remains unchanged. Simultaneously, the duty cycle of the first drive signal P1 is less than the duty cycle of the second drive signal P2. In this case, the logic control branch 60 outputs a third drive signal P3 based on the logical AND result of the first drive signal P1 and the second drive signal P2, so that the third drive signal P3 is consistent with the first drive signal P1.

[0052] In some embodiments, the first sampling branch 10 is further configured to differentially sample the output current to output a first sampling voltage SV1. This helps to improve measurement accuracy and suppress common-mode interference (such as power supply noise, electromagnetic interference, etc.).

[0053] In some embodiments, such as Figure 3 As shown, the voltage generation branch 30 includes a first unidirectional conductive unit 31 and a second unidirectional conductive unit 32. The first unidirectional conductive unit 31 is electrically connected to the first sampling branch 10 and the first comparison branch 40, and the second unidirectional conductive unit 32 is electrically connected to the first power supply VC1 and the first comparison branch 40.

[0054] The voltage generation branch 30 is specifically configured such that: when the output current is greater than the upper limit value, the first unidirectional conductive unit 31 is turned on and the second unidirectional conductive unit 32 is turned off, so as to generate a reference voltage VREF based on the first sampling voltage SV1; when the output current is less than or equal to the upper limit value, the first unidirectional conductive unit 31 is turned off and the second unidirectional conductive unit 32 is turned on, so as to generate a reference voltage VREF based on the voltage of the first power supply VC1.

[0055] Please refer to Figure 4 , Figure 4 This is a schematic diagram of the circuit structure of the first sampling branch 10, voltage generation branch 30, first comparison branch 40, and logic control branch 60 in the switch driving circuit 100 provided in the embodiments of this application. Figure 4 As shown, the first sampling branch 10 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first capacitor C1, a second capacitor C2, and a first operational amplifier U1.

[0056] The first resistor R1 and the second resistor R2 are connected in series between the positive terminal I_D+ of the differential sampling signal of the output current and ground GND. The connection point between the first resistor R1 and the second resistor R2 is electrically connected to the non-inverting input terminal of the first operational amplifier U1. The first capacitor C1 is connected in parallel with the second resistor R2. The third resistor R3 and the fourth resistor R4 are connected in series between the negative terminal I_D- of the differential sampling signal of the output current and the output terminal of the first operational amplifier U1. The connection point between the third resistor R3 and the fourth resistor R4 is electrically connected to the inverting input terminal of the first operational amplifier U1. The second capacitor C2 is connected in parallel with the fourth resistor R4. The fifth resistor R5 is electrically connected between the output terminal of the first operational amplifier U1 and the voltage generation branch 30.

[0057] The first sampling branch 10 uses a high-speed operational amplifier (i.e., the first operational amplifier U1) to construct a differential sampling circuit, which is used to sample the output current of the voltage conversion circuit 200 and output the first sampling voltage SV1. The magnitude of the first sampling voltage SV1 can be changed by changing the ratio of the first resistor R1, the third resistor R3, and the fourth resistor R4.

[0058] In some embodiments, the first unidirectional conductive unit 31 is a first diode D1, the second unidirectional conductive unit 32 is a second diode D2, and the voltage generation branch 30 further includes a sixth resistor R6 and a seventh resistor R7.

[0059] The anode of the first diode D1 is electrically connected to the first sampling branch 10. The cathode of the first diode D1 is electrically connected to the first end of the sixth resistor R6 and the cathode of the second diode D2. The anode of the second diode D2 is electrically connected to the first power supply VC1 through the seventh resistor R7. The second end of the sixth resistor R6 is grounded to GND.

[0060] When the first diode D1 is forward-biased and the second diode D2 is reverse-biased, the reference voltage VREF = SV1 - VD1, where VD1 is the forward voltage drop of the first diode D1. When the second diode D2 is forward-biased and the first diode D1 is reverse-biased, the first power supply VC1 forms the reference voltage VREF after being divided by the seventh resistor R7, the second diode D2, and the sixth resistor R6. Then, VREF = R6 × (VC1 - VD2) / (R7 + R6), where VD2 is the forward voltage drop of the second diode D2.

[0061] In some embodiments, the first comparison branch 40 includes an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, and a first comparator U2.

[0062] The first end of the eighth resistor R8 is electrically connected to the voltage generation branch 30, the second end of the eighth resistor R8 is electrically connected to the inverting input of the first comparator U2, the first end of the ninth resistor R9 receives the first triangular carrier signal S1, the second end of the ninth resistor R9 is electrically connected to the non-inverting input of the first comparator U2, the output of the first comparator U2 is electrically connected to the first end of the tenth resistor R10 and the logic control branch 60, and the second end of the tenth resistor R10 is electrically connected to the first power supply VC1.

[0063] The reference voltage VREF is compared with the first triangular carrier signal S1, and a high-frequency drive signal (i.e., the first drive signal P1) is obtained at the output of the first comparator U2. Furthermore, the duty cycle of the first drive signal P1 decreases as the reference voltage VREF increases.

[0064] In some embodiments, the logic control branch 60 includes an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a third capacitor C3, and a first AND gate AN1.

[0065] The eleventh resistor R11 and the third capacitor C3 are connected in series between the first comparator branch 40 and ground GND. The connection point between the eleventh resistor R11 and the third capacitor C3 is electrically connected to the first input terminal of the first AND gate AN1. The twelfth resistor R12 and the thirteenth resistor R13 are connected in series between the controller and ground GND. The left end of the twelfth resistor R12 receives the second drive signal P2. The connection point between the twelfth resistor R12 and the thirteenth resistor R13 is electrically connected to the second input terminal of the first AND gate AN1. The output terminal of the first AND gate AN1 is electrically connected to the first switch Q1 through a driver chip (not shown in the figure). The output terminal of the first AND gate AN1 outputs the third drive signal P3.

[0066] Specifically, the first driving signal P1 is connected to the first input terminal of the first AND gate AN1 via a current-limiting resistor (i.e., the eleventh resistor R11), and the second driving signal P2 is connected to the second input terminal of the first AND gate AN1 via a current-limiting resistor (i.e., the twelfth resistor R12). Simultaneously, since the waveforms of the first triangular carrier signal S1 and the second triangular carrier signal S2 are identical, they are of the same frequency, amplitude, and phase. Therefore, the first driving signal P1 and the second driving signal P2 have the same center point during their conduction period and also the same center point during their turn-off period. Consequently, the third driving signal P3 output by the first AND gate AN1 is consistent with the signal with the shorter conduction time among the two high-frequency signals, the first driving signal P1 and the second driving signal P2.

[0067] The following are Figure 4 The working process of the circuit structure shown is explained. Specifically, Figure 4The circuit structure shown can be divided into two modes of operation, with the specific operating states as follows:

[0068] Mode 1: When the output current of voltage conversion circuit 200 is less than or equal to the upper limit, the second diode D2 is forward-biased and the first diode D1 is reverse-biased. Therefore, R6×(VC1-VD2) / (R7+R6)≥SV1-VD1, VREF=R6×(VC1-VD2) / (R7+R6). Since the output current of voltage conversion circuit 200 is less than or equal to the upper limit, the switching transistor drive circuit 100 operates in voltage regulation mode. That is, the output voltage of voltage conversion circuit 200 changes with the load's operating state. Of course, when the load remains constant, the output voltage of voltage conversion circuit 200 also remains constant, i.e., it is a constant voltage. The schematic diagram of each signal in the switching transistor drive circuit 100 at this time is as follows: Figure 5 As shown, the output of the first comparator U2 receives a high-frequency drive signal with a constant duty cycle (i.e., the first drive signal P1). Because the conduction time of the first drive signal P1 is longer than that of the second drive signal P2, the third drive signal P3 output by the first AND gate AN1 is consistent with the second drive signal P2. Wherein, Figure 5 In the vertical direction, from top to bottom, are the first triangular carrier signal S1, the reference voltage VREF, the first sampling voltage SV1, the first driving signal P1, the second driving signal P2, and the third driving signal P3.

[0069] Mode 2: When the output current of the voltage conversion circuit 200 exceeds the upper limit, the second diode D2 is reverse-biased and the first diode D1 is forward-biased. Therefore, R6×(VC1-VD2) / (R7+R6)<SV1-VD1, and VREF=SV1-VD1. At this time, the schematic diagram of each signal in the switching transistor drive circuit 100 is as follows... Figure 6 As shown, the duty cycle of the first drive signal P1 decreases as VREF increases, and the third drive signal P3 output by the first AND gate AN1 remains consistent with the first drive signal P1. Because the duty cycle of the third drive signal P3 decreases, the conduction duty cycle of the first switching transistor Q1 decreases, causing the output voltage of the voltage conversion circuit 200 to decrease, thereby reducing its output current. When the output current of the voltage conversion circuit 200 decreases to the current limiting value, the switching transistor drive circuit 100 returns to mode 1 and repeats these two modes cyclically, thus achieving the voltage regulation and current limiting function. In this process, Figure 6 In the vertical direction, from top to bottom, are the first triangular carrier signal S1, the first sampling voltage SV1, the reference voltage VREF, the first driving signal P1, the second driving signal P2, and the third driving signal P3.

[0070] Furthermore, since the response speed of the switching transistor drive circuit 100 proposed in this embodiment far exceeds the regulation speed of the software current loop, when the load is an electrolytic cell module and when an electrolytic cell module failure occurs, the switching transistor drive circuit 100 possesses a highly sensitive transient constant current and voltage regulation function. This effectively solves the problem of overcurrent and overvoltage surges on the electrolytic cell membrane electrodes caused by the inherent delay characteristics of the software-implemented constant current and voltage regulation control loop, thereby maximizing the service life of the electrolytic cell module.

[0071] Please refer to Figure 7 , Figure 7 An exemplary circuit structure for the second sampling branch 20 is shown. For example... Figure 7 As shown, the second sampling branch 20 includes a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, and a second operational amplifier U3.

[0072] Among them, the fourteenth resistor R14 and the fifteenth resistor R15 are connected in series between the positive terminal V_D+ of the differential sampling signal of the load voltage and ground GND. The connection point between the fourteenth resistor R14 and the fifteenth resistor R15 is electrically connected to the non-inverting input terminal of the second operational amplifier U3. The fourth capacitor C4 is connected in parallel with the fifteenth resistor R15. The sixteenth resistor R16 and the seventeenth resistor R17 are connected in series between the negative terminal V_D- of the differential sampling signal of the load voltage and the output terminal of the second operational amplifier U3. The connection point between the sixteenth resistor R16 and the seventeenth resistor R17 is electrically connected to the inverting input terminal of the second operational amplifier U3. The fifth capacitor C5 is connected in parallel with the seventeenth resistor R17. The sixth capacitor C6 is electrically connected between the output terminal of the second operational amplifier U3 and ground GND. The output terminal of the second operational amplifier U3 is electrically connected to the controller 50 to output the second sampling voltage SV2 to the controller 50.

[0073] The second sampling branch 20 uses a high-speed operational amplifier (i.e., the second operational amplifier U3) to construct a differential sampling circuit for sampling the load voltage and outputting a second sampling voltage SV2. The magnitude of the second sampling voltage SV2 can be changed by altering the ratio of the fourteenth resistor R14, the sixteenth resistor R16, and the seventeenth resistor R17.

[0074] In some embodiments, such as Figure 8 As shown, the switching transistor drive circuit 100 also includes a signal generation circuit 70.

[0075] The signal generation circuit 70 is electrically connected to the controller 50 and the first comparison branch 40 respectively. The signal generation circuit 70 is configured to generate a first triangular carrier signal S1 based on the first square wave signal SW1 output by the controller 50. A triangular waveform is generated in each half cycle of the first square wave signal SW1, and multiple triangular waveforms form the first triangular carrier signal S1.

[0076] In some embodiments, such as Figure 9 As shown, the signal generation circuit 70 includes a square wave generating branch 71, a triangular wave generating branch 72, a signal following branch 73, and an inverting branch 74.

[0077] Among them, the square wave generating branch 71 is electrically connected to the controller 50, the triangular wave generating branch 72 is electrically connected to the square wave generating branch 71, the signal following branch 73 is electrically connected to the triangular wave generating branch 72, and the inverting branch 74 is electrically connected to both the triangular wave generating branch 72 and the signal following branch 73.

[0078] Specifically, the square wave generating branch 71 is configured to input the first square wave signal SW1 output by the controller 50, and output a second square wave signal SW2 based on the first square wave signal SW1. The positive voltage corresponding to the second square wave signal SW2 is greater than the positive voltage corresponding to the first square wave signal SW1, the negative voltage corresponding to the second square wave signal SW2 is less than the negative voltage corresponding to the first square wave signal SW1, and the negative voltage corresponding to the second square wave signal SW2 is less than zero. The waveforms of the first square wave signal SW1 and the second square wave signal SW2 are shown below. Figure 10 As shown. The triangular wave generating branch 72 is configured to generate a triangular wave signal S3 based on the second square wave signal SW2, wherein when the second square wave signal SW2 corresponds to a positive voltage, the voltage of the triangular wave signal S3 increases from the negative voltage corresponding to the second square wave signal SW2 to the positive voltage corresponding to the second square wave signal SW2 (e.g., ...). Figure 10 The waveform diagram shown is from time T3 to time T5. When the second square wave signal SW2 corresponds to a negative voltage, the voltage of the triangular wave signal S3 decreases from the positive voltage corresponding to the second square wave signal SW2 to the negative voltage corresponding to the second square wave signal SW2 (e.g., Figure 10 The waveform diagram shown is for the period from time T1 to time T3. The signal follower branch 73 is configured to generate a first discontinuous triangular wave signal S4 based on the triangular wave signal S3, wherein the first discontinuous triangular wave signal S4 is equal to the triangular wave signal S3 when the voltage of the triangular wave signal S3 is greater than or equal to zero (e.g., ...). Figure 10 The waveforms shown are from time T1 to time T2, and from time T4 to time T5. When the voltage of the triangular wave signal S3 is less than zero, the first discontinuous triangular wave signal S4 is zero (as shown). Figure 10The waveform diagram shown is for the period from time T2 to time T4. The inverting branch 74 is configured to generate a first triangular carrier signal S1 by superimposing the inverted result of the triangular wave signal S3 with the first discontinuous triangular wave signal S4. The inverted result of the triangular wave signal S3 is the second discontinuous triangular wave signal (denoted as S5). The second discontinuous triangular wave signal S5 is zero when the voltage of the triangular wave signal S3 is greater than or equal to zero (e.g., ...). Figure 10 The waveforms shown are from time T1 to time T2, and from time T4 to time T5. When the voltage of the triangular wave signal S3 is less than zero, the second discontinuous triangular wave signal S5 is equal to the inverted signal of the triangular wave signal S3 (e.g., Figure 10 The waveform diagram shown is for the period from time T2 to time T4. Figure 10 In the vertical direction, from top to bottom, the signals are: second triangular carrier signal S2, first square wave signal SW1, second square wave signal SW2, triangular wave signal S3, first discontinuous triangular wave signal S4, second discontinuous triangular wave signal S5, and first triangular carrier signal S1.

[0079] Please refer to Figure 11 , Figure 11 An exemplary circuit structure for a signal generation circuit is shown. For example... Figure 11 As shown, the square wave generating branch 71 includes the eighteenth resistor R18, the nineteenth resistor R19, the twentieth resistor R20, and the second comparator U4.

[0080] Among them, the first end of the eighteenth resistor R18 is used to input the first square wave signal SW1, the second end of the eighteenth resistor R18 is electrically connected to the non-inverting input of the second comparator U4, the nineteenth resistor R19 is electrically connected between the second power supply VC2 and the inverting input of the second comparator U4, the twentieth resistor R20 is electrically connected between the first power supply VC1 and the output of the second comparator U4, and the output of the second comparator U4 is electrically connected to the triangular wave generating branch 72.

[0081] Specifically, in controller 50, the frequency of its internal triangular carrier signal (i.e., the second triangular carrier signal S2) is set to fr1, and the level of the signal output by controller 50 is flipped at the peak point of the second triangular carrier signal S2 to obtain a first square wave signal SW1 with a frequency of fr2, and fr1 = 2fr2. Since the square wave signal requires two flips (i.e., switching from high level to low level and then from low level to high level) to complete one cycle, while the triangular carrier signal only provides two flip opportunities every two cycles, the frequency fr2 of the first square wave signal SW1 is half the frequency fr1 of the triangular carrier signal, i.e., fr1 = 2fr2.

[0082] The first square wave signal SW1 is input to the non-inverting input of the second comparator U4 through a current-limiting resistor (i.e., the eighteenth resistor R18). The second power supply VC2 is input to the inverting input of the second comparator U4 through a nineteenth resistor R19. The second comparator U4 is powered by a dual power supply consisting of the first power supply VC1 and a negative first power supply VC1 (i.e., -VC1). When the first square wave signal SW1 is high, the voltage at the non-inverting input of the second comparator U4 is higher than the voltage at its inverting input, and the output of the second comparator U4 is pulled up to the voltage of the first power supply VC1 through a pull-up current-limiting resistor (i.e., the twentieth resistor R20). When the first square wave signal SW1 is low, the voltage at the non-inverting input of the second comparator U4 is lower than the voltage at its inverting input, and the output of the second comparator U4 is pulled down to -VC1, thus obtaining a second square wave signal SW2 with a frequency of fr2, a maximum value of VC1, and a minimum value of -VC1.

[0083] In some embodiments, the triangular wave generating branch 72 includes a twenty-second resistor R22, a twenty-first resistor R21, a twenty-third resistor R23, a seventh capacitor C7, and a third operational amplifier U5.

[0084] Among them, the twenty-second resistor R22 is electrically connected between the square wave generating branch 71 and the inverting input terminal of the third operational amplifier U5, the twenty-first resistor R21 is electrically connected between the non-inverting input terminal of the third operational amplifier U5 and ground GND, the twenty-third resistor R23 is electrically connected between the inverting input terminal and the output terminal of the third operational amplifier U5, the seventh capacitor C7 is connected in parallel with the twenty-third resistor R23, and the output terminal of the third operational amplifier U5 is electrically connected to the signal following branch 73 and the inverting branch 74 respectively.

[0085] Specifically, the second square wave signal SW2 is input into the triangular wave generating branch 72. The third operational amplifier U5 is powered by a dual power supply of VC1 and -VC1. Therefore, by setting the values ​​of the twenty-second resistor R22, the twenty-first resistor R21, the twenty-third resistor R23 and the seventh capacitor C7 in the triangular wave generating branch 72, a triangular wave signal S3 with a frequency of fr2 can be obtained.

[0086] In some embodiments, the signal follower branch 73 includes a twenty-fourth resistor R24, a twenty-fifth resistor R25, and a fourth operational amplifier U6.

[0087] Among them, the twenty-fourth resistor R24 ​​is electrically connected between the triangular wave generating branch 72 and the non-inverting input terminal of the fourth operational amplifier U6, the twenty-fifth resistor R25 is electrically connected between the inverting input terminal and the output terminal of the fourth operational amplifier U6, and the output terminal of the fourth operational amplifier U6 is electrically connected to the inverting branch 74.

[0088] Specifically, the first discontinuous triangular wave signal S4 is obtained from the input signal follower branch 73 of the triangular wave signal S3. Since the fourth operational amplifier U6 is powered by the single power supply of the first power supply VC1, when the triangular wave signal S3 is less than zero, the first discontinuous triangular wave signal S4 is equal to zero; when the triangular wave signal S3 is greater than or equal to zero, the first discontinuous triangular wave signal S4 = S3, and thus the first discontinuous triangular wave signal S4 is obtained.

[0089] In some embodiments, the inverting branch 74 includes a twenty-sixth resistor R26, a twenty-seventh resistor R27, a twenty-eighth resistor R28, and a fifth operational amplifier U7.

[0090] Among them, the twenty-sixth resistor R26 is electrically connected between the signal follower branch 73 and the non-inverting input terminal of the fifth operational amplifier U7, the twenty-seventh resistor R27 is electrically connected between the triangular wave generating branch 72 and the inverting input terminal of the fifth operational amplifier U7, the twenty-eighth resistor R28 is electrically connected between the inverting input terminal and the output terminal of the fifth operational amplifier U7, and the output terminal of the fifth operational amplifier U7 outputs the first triangular carrier signal S1.

[0091] Specifically, the triangular wave signal S3 is input to the inverting input port of the fifth operational amplifier U7 via a current-limiting resistor (i.e., the twenty-seventh resistor R27), and the first discontinuous triangular wave signal S4 is input to the non-inverting input port of the fifth operational amplifier U7 via a current-limiting resistor (i.e., the twenty-sixth resistor R26). This results in a first triangular carrier signal S1 at the output of the fifth operational amplifier U7. Because the fifth operational amplifier U7 is powered by a single power supply VC1, it can only output signals greater than zero. Therefore, when the triangular wave signal S3 is greater than or equal to zero, the output signal of the triangular wave signal S3 after passing through the inverting branch 74 is zero; when the triangular wave signal S3 is less than zero, the output signal of the triangular wave signal S3 after passing through the inverting branch 74 will be the second discontinuous triangular wave signal S5. Meanwhile, when the first discontinuous triangular wave signal S4 is greater than zero, the output of the first discontinuous triangular wave signal S4 after passing through the inverting branch 74 will be a discontinuous triangular wave signal with a frequency of fr2 and a dead time of 1 / 2fr2; when the first discontinuous triangular wave signal S4 is equal to zero, the output signal of the first discontinuous triangular wave signal S4 after passing through the inverting branch 74 will be zero. Because the first discontinuous triangular wave signal S4 is greater than zero when the triangular wave signal S3 is greater than zero, and the first discontinuous triangular wave signal S4 is equal to zero when the triangular wave signal S3 is less than zero, the output of the inverting branch 74 will obtain a continuous triangular wave signal with a frequency of 2fr2 (i.e., the first triangular carrier signal S1). Furthermore, the first triangular carrier signal S1 and the second triangular carrier signal S2 have the same frequency, the same amplitude, and the same phase.

[0092] Please refer to Figure 12 , Figure 12 This is a schematic diagram of the composition of the water electrolysis hydrogen production system provided in the embodiments of this application. Figure 12As shown, the water electrolysis hydrogen production system 1000 includes an input power supply VIN, a voltage conversion circuit 200, N electrolyzer modules EM, and a switching transistor drive circuit 100 as described in any embodiment of this application, where N is a positive integer. Each electrolyzer module is formed by encapsulating an electrolyzer with a fixed number of membrane electrodes connected in series.

[0093] In this circuit, N electrolytic cell modules EM are connected in series. A voltage conversion circuit 200 is electrically connected between the input power supply VIN and the electrolytic cell modules EM. A switch drive circuit 100 is electrically connected to the first switch Q1 in the voltage conversion circuit 200. The switch drive circuit 100 is configured to drive the first switch Q1 to turn on or off, so that the voltage conversion circuit 200 generates a voltage to supply power to the electrolytic cell modules EM based on the voltage of the input power supply VIN.

[0094] In some embodiments, such as Figure 13 As shown, the water electrolysis hydrogen production system 1000 also includes N switching circuits 400, each of which is electrically connected to an electrolyzer module EM.

[0095] The switching circuit 400 is configured to short-circuit the electrolytic cell module EM when an overvoltage or undervoltage fault occurs. After at least one electrolytic cell module EM is short-circuited, the switching tube drive circuit 100 adjusts the duty cycle of the output third drive signal P3 so that the output current of the voltage conversion circuit 200 is less than or equal to the upper limit value.

[0096] Figure 14 A block diagram of a switching circuit 400 is shown. For example... Figure 14 As shown, the switching circuit 400 includes a second comparison branch 401, a third comparison branch 402, a fourth comparison branch 403, a logic operation branch 404, and a switching branch 405.

[0097] Specifically, the second comparison branch 401 is electrically connected to the second sampling branch 20, the third comparison branch 402 is electrically connected to the second sampling branch 20, the fourth comparison branch 403 is electrically connected to the second sampling branch 20, the logic operation branch 404 is electrically connected to the second comparison branch 401, the third comparison branch 402 and the fourth comparison branch 403 respectively, and the switch branch 405 is electrically connected to the electrolytic cell module EM and the voltage conversion circuit 200.

[0098] Specifically, the second comparison branch 401 is configured to output a second comparison result between the second sampled voltage SV2 and the first voltage threshold VH, wherein the second comparison result is a first level signal when the second sampled voltage SV2 is greater than the first voltage threshold VH, and a second level signal when the second sampled voltage SV2 is less than or equal to the first voltage threshold VH. The third comparison branch 402 is configured to output a third comparison result between the second sampled voltage SV2 and the second voltage threshold VL, wherein the third comparison result is a second level signal when the second sampled voltage SV2 is greater than or equal to the second voltage threshold VL, and a first level signal when the second sampled voltage SV2 is less than the second voltage threshold VL, wherein the second voltage threshold VL is less than the first voltage threshold VH. The fourth comparison branch 403 is configured to output a fourth comparison result between the second sampled voltage SV2 and the second voltage threshold VL, and to maintain the fourth comparison result as a first level signal when it is a first level signal, wherein the fourth comparison result is a first level signal when the second sampled voltage SV2 is greater than the second voltage threshold VL, and a second level signal when the second sampled voltage SV2 is less than or equal to the second voltage threshold VL. The logic operation branch 404 is configured to perform logic operations based on the second comparison result, the third comparison result, and the fourth comparison result to output a switch signal. The switch signal is a second-level signal when the fourth comparison result is a second-level signal and / or when both the second and third comparison results are second-level signals. The switch signal is a first-level signal when the fourth comparison result is a first-level signal and at least one of the second and third comparison results is a first-level signal. The switch branch 405 is configured to be in a first conducting state in response to the switch signal being a first-level signal to short-circuit the electrolytic cell module EM, and to be in a second conducting state in response to the switch signal being a second-level signal to connect the electrolytic cell module EM to the voltage conversion circuit 200 and the current path of the N electrolytic cell modules EM.

[0099] Therefore, the first voltage threshold VH can be set as the overvoltage threshold, meaning that when the second sampled voltage SV2 is greater than the first voltage threshold VH, it is determined that the voltage of the electrolytic cell module EM has experienced an overvoltage fault; and the second voltage threshold VL can be set as the undervoltage threshold, meaning that when the second sampled voltage SV2 is less than the second voltage threshold VL, it is determined that the voltage of the electrolytic cell module EM has experienced an undervoltage fault. Then, when the electrolytic cell module EM experiences an overvoltage fault, the second comparison result is a first-level signal, the third comparison result is a second-level signal, and the fourth comparison result is a first-level signal. At this time, if the fourth comparison result is a first-level signal and at least one of the second and third comparison results is a first-level signal, the switch signal is a first-level signal, the switch branch 405 is in the first conducting state, and the electrolytic cell module EM is short-circuited. When an undervoltage fault occurs in the electrolyzer module EM, the second comparison result is a second-level signal, the third comparison result is a first-level signal, and the fourth comparison result is a first-level signal (this is because under normal conditions, when the second sampling voltage SV2 is greater than the second voltage threshold VL, the fourth comparison result is a first-level signal; when the fourth comparison result is a first-level signal, the fourth comparison branch 403 maintains the fourth comparison result as a first-level signal). At this time, the fourth comparison result is a first-level signal, and at least one of the second and third comparison results is a first-level signal. The switch signal is a first-level signal, the switch branch 405 is in the first conducting state, and the electrolyzer module EM is short-circuited. In summary, this achieves the goal of short-circuiting the electrolyzer module EM when it experiences overvoltage or undervoltage overload, while other electrolyzer modules EM that have not experienced faults can operate normally. The water electrolysis hydrogen production system 1000 does not need to be shut down, thus maintaining high operating efficiency. Subsequently, if the voltage of the electrolytic cell module EM returns to normal, then the second voltage threshold VL ≤ the second sampling voltage SV2 ≤ the first voltage threshold VH, the second comparison result is a second level signal, the third comparison result is a second level signal, and the fourth comparison result is a first level signal. At this time, if the fourth comparison result is a second level signal and / or the second comparison result and the third comparison result are both second level signals, the switch signal is a second level signal, the switch branch 405 is in the second conduction state, and the electrolytic cell module EM can be reconnected to the voltage conversion circuit 200 and the current path of the N electrolytic cell modules EM.

[0100] In some embodiments, such as Figure 15 As shown, the switching circuit 400 also includes a reset branch 406.

[0101] The reset branch 406 is electrically connected to both the second comparison branch 401 and the third comparison branch 402. During operation, the reset branch 406 resets both the second and third comparison results to a second-level signal. Consequently, the switch signal becomes a second-level signal, and the switch branch 405 is in a second conducting state, no longer short-circuiting any electrolytic cell module EM.

[0102] In some embodiments, such as Figure 16 As shown, the second comparison branch 401 includes a third diode D3, a fourth diode D4, a twenty-ninth resistor R29, a thirtieth resistor R30, a thirty-first resistor R31, a thirty-second resistor R32, a thirty-third resistor R33, a seventh capacitor C7, and a third comparator U8.

[0103] In this circuit, the anode of the third diode D3 is electrically connected to the second sampling branch 20 to input the second sampling voltage SV2. The cathode of the third diode D3 is electrically connected to the non-inverting input of the third comparator U8 through the twenty-ninth resistor R29. The first terminal of the thirty-first resistor R31 is connected to the first voltage threshold VH. The second terminal of the thirty-first resistor R31 is electrically connected to the inverting input of the third comparator U8. The thirty-third resistor R33 is electrically connected between the non-inverting input of the third comparator U8 and ground GND. The seventh capacitor C7 is electrically connected between the inverting input of the third comparator U8 and ground GND. The thirtieth resistor R30 is electrically connected between the non-inverting input of the third comparator U8 and the cathode of the fourth diode D4. The anode of the fourth diode D4 is electrically connected to the output of the third comparator U8. The thirty-second resistor R32 is electrically connected between the first power supply VC1 and the output of the third comparator U8. The output of the third comparator U8 is electrically connected to the logic operation branch 404 to output the signal OVP_n to the logic operation branch 404.

[0104] In some embodiments, the third comparison branch 402 includes a fifth diode D5, a sixth diode D6, a thirty-fourth resistor R34, a thirty-fifth resistor R35, a thirty-sixth resistor R36, a thirty-seventh resistor R37, a thirty-eighth resistor R38, an eighth capacitor C8, and a fourth comparator U9.

[0105] In this circuit, the anode of the fifth diode D5 is electrically connected to the second sampling branch 20 to input the second sampling voltage SV2. The cathode of the fifth diode D5 is electrically connected to the inverting input of the fourth comparator U9 through the thirty-sixth resistor R36. The first terminal of the thirty-fourth resistor R34 inputs the second voltage threshold VL, and the second terminal of the thirty-fourth resistor R34 is electrically connected to the non-inverting input of the fourth comparator U9. The thirty-seventh resistor R37 is electrically connected between the inverting input of the fourth comparator U9 and ground GND. The eighth capacitor C8 is electrically connected between the non-inverting input of the fourth comparator U9 and ground GND. The thirty-fifth resistor R35 is electrically connected between the non-inverting input of the fourth comparator U9 and the cathode of the sixth diode D6. The anode of the sixth diode D6 is electrically connected to the output of the fourth comparator U9. The thirty-eighth resistor R38 is electrically connected between the first power supply VC1 and the output of the fourth comparator U9. The output of the fourth comparator U9 is electrically connected to the logic operation branch 404 to output the signal LVP_n to the logic operation branch 404.

[0106] In some embodiments, the fourth comparison branch 403 includes a seventh diode D7, a thirty-ninth resistor R39, a fortieth resistor R40, a forty-first resistor R41, a forty-second resistor R42, a forty-third resistor R43, a ninth capacitor C9, and a fifth comparator U10.

[0107] Specifically, the first end of the 40th resistor R40 is electrically connected to the second sampling branch 20 to input the second sampling voltage SV2, and the second end of the 40th resistor R40 is electrically connected to the non-inverting input of the fifth comparator U10. The first end of the 39th resistor R39 is used to input the second voltage threshold VL, and the second end of the 39th resistor R39 is electrically connected to the inverting input of the fifth comparator U10. The 41st resistor R41 is electrically connected between the non-inverting input of the fifth comparator U10 and ground GND. The 9th capacitor C9 is electrically connected between the inverting input of the fifth comparator U10 and ground GND. The 42nd resistor R42 is electrically connected between the non-inverting input of the fifth comparator U10 and the cathode of the seventh diode D7, and the anode of the seventh diode D7 is electrically connected to the output of the fifth comparator U10. The 43rd resistor R43 is electrically connected between the first power supply VC1 and the output of the fifth comparator U10. The output of the fifth comparator U10 is electrically connected to the logic operation branch 404 to output the signal EN_n to the logic operation branch 404.

[0108] In some embodiments, the logic operation branch 404 includes an eighth diode D8, a ninth diode D9, a forty-fourth resistor R44, a forty-fifth resistor R45, a forty-sixth resistor R46, a forty-seventh resistor R47, and a second AND gate AN2.

[0109] In this circuit, the anode of the eighth diode D8 is electrically connected to the second comparator branch 401, the cathode of the eighth diode D8 is electrically connected to the cathode of the ninth diode D9 and the first terminal of the forty-fourth resistor R44, the anode of the ninth diode D9 is electrically connected to the third comparator branch 402, the second terminal of the forty-fourth resistor R44 is electrically connected to the first terminal of the forty-fifth resistor R45 and the first input terminal of the second AND gate AN2, the first terminal of the forty-sixth resistor R46 is electrically connected to the fourth comparator branch 403, the second terminal of the forty-sixth resistor R46 is electrically connected to the first terminal of the forty-seventh resistor R47 and the second input terminal of the second AND gate AN2, the second terminals of the forty-fifth resistor R45 and the forty-seventh resistor R47 are both grounded to GND, and the output terminal of the second AND gate AN2 is electrically connected to the switch branch 405 to output the signal SW_n to the switch branch 405.

[0110] In some embodiments, the reset branch 406 includes a tactile switch K1, a forty-eighth resistor R48, a forty-ninth resistor R49, a fiftieth resistor R50, a tenth diode D10, and an eleventh diode D11.

[0111] In this circuit, the first terminal of the tactile switch K1 is electrically connected to the first power supply VC1. The second terminal of the tactile switch K1 is electrically connected to the anode of the tenth diode D10, the first terminal of the forty-ninth resistor R49, and the anode of the eleventh diode D11. The cathode of the tenth diode D10 is electrically connected to the second comparator branch 401 through the forty-eighth resistor R48. The second terminal of the forty-ninth resistor R49 is grounded to GND. The cathode of the eleventh diode D11 is electrically connected to the third comparator branch 402 through the fiftieth resistor R50.

[0112] In this embodiment, because the output of the third comparator U8 is connected to the input of the eighth diode D8, and the output of the fourth comparator U9 is connected to the input of the ninth diode D9, and the outputs of the eighth diode D8 and the ninth diode D9 are connected and then connected to the first input of the second AND gate AN2 via a current-limiting resistor (i.e., the forty-fourth resistor R44), the signal at the first input of the second AND gate AN2 is consistent with the high-level signal of either signal OVP_n or signal LVP_n. The output of the fifth comparator U10 is connected to the second input of the second AND gate AN2 via a current-limiting resistor (i.e., the forty-sixth resistor R46). Therefore, as long as at least one of the following two conditions is met: Condition 1: Both signals OVP_n and LVP_n are low-level signals; Condition 2: Signal EN_n is a low-level signal, the signal SW_n output by the second AND gate AN2 will also be a low-level signal. The following two conditions must be met simultaneously: Condition 1: At least one of the signals OVP_n and LVP_n is a high-level signal; Condition 2: If the signal EN_n is a high-level signal, the signal SW_n output by the second AND gate AN2 is also a high-level signal.

[0113] Secondly, when signal OVP_n is high, it pulls the level of the non-inverting input of the third comparator U8 high through a voltage divider formed by the fourth diode D4, the thirtieth resistor R30, and the thirty-third resistor R33, keeping it consistently higher than the level at the inverting input. This causes the third comparator U8 to enter a latched state, maintaining its output signal OVP_n at a high level. Similarly, when signal LVP_n is high, it pulls the level of the non-inverting input of the fourth comparator U9 high through the sixth diode D6 and the thirty-fifth resistor R35, keeping it consistently higher than the level at the inverting input. This causes the fourth comparator U9 to enter a latched state, maintaining its output signal LVP_n at a high level. When the signal EN_n is high, it will pull the level of the non-inverting input of the fifth comparator U10 high through the seventh diode D7 and the forty-second resistor R42, making it always higher than the level of the inverting input of the fifth comparator U10. This will cause the fifth comparator U10 to enter the latch-up state, keeping its output signal EN_n at a high level.

[0114] The following will combine Figures 17 to 19 The signal pairs shown Figure 16 The working principle of the circuit structure shown will be explained. Figure 16 Taking the forward voltage drop of each diode (such as the third diode D3) as an example, VD is the forward voltage drop.

[0115] like Figure 17As shown, at time T11, the electrolytic cell module EN starts up, and the current flowing through the electrodes of the electrolytic cell module EN gradually increases from zero. The membrane electrode voltage of the electrolytic cell module EN also gradually increases from zero, thus the second sampling voltage SV2 gradually increases. During the period from time T11 to time T12, SV2-VD < VL and SV2-VD < VH. Therefore, the voltages at the non-inverting inputs of the third comparator U8 and the fifth comparator U10 are lower than the voltages at the inverting inputs, while the voltage at the non-inverting input of the fourth comparator U9 is higher than the voltage at the inverting input. Therefore, the third comparator U8 and the fifth comparator U10 output a low level, and the fourth comparator U9 outputs a high level; that is, signals OVP_n and EN_n are low, and signal LVP_n is high. At this time, the second AND gate AN2 outputs a low level, meaning signal SW_n is low. After time T12, the membrane electrode voltage continues to increase, and the second sampling voltage SV2 continues to increase, with VL < SV2 - VD < VH. Therefore, the voltages at the non-inverting inputs of the third comparator U8 and the fourth comparator U9 are lower than the voltages at the inverting inputs, while the voltage at the non-inverting input of the fifth comparator U10 is higher than the voltage at the inverting input. Consequently, the signals OVP_n and LVP_n output by the third comparator U8 and the fourth comparator U9 are low, and the signal EN_n output by the fifth comparator U10 is high. At this time, the second AND gate AN2 outputs a low level, i.e., the signal SW_n is low. Wherein, in Figure 17 In the vertical direction from top to bottom, the components are: first power supply VC1, voltage VSW1 at the second terminal of tactile switch K1, first voltage threshold VH, second sampling voltage SV2, second voltage threshold VL, signal EN_n, signal LVP_n, signal OVP_n, and signal SW_n.

[0116] like Figure 18As shown, at time T24, the membrane electrode voltage of the electrolytic cell module EN suddenly experiences a low-voltage abnormality fault, i.e., SV2-VD<VL. At this time, the voltage at the non-inverting input of the third comparator U8 is lower than the voltage at the inverting input, and the signal OVP_n output by the third comparator U8 remains at a low level. The voltage at the non-inverting input of the fourth comparator U9 is higher than the voltage at the inverting input, and the signal LVP_n output by the fourth comparator U9 flips to a high level. Secondly, since the signal EN_n output by the fifth comparator U10 is at a high level at time T22, when the signal EN_n is at a high level, the signal EN_n will pull the level of the non-inverting input of the fifth comparator U10 high through the seventh diode D7 and the forty-second resistor R42, making it always higher than the level of the inverting input of the fifth comparator U10, thereby causing the fifth comparator U10 to enter a latching state, so that its output signal EN_n remains a high level signal. Therefore, the signal SW_n output by the second AND gate AN2 flips from low to high, completing the switching signal of the drive switch branch 405 from low (i.e., the second level signal) to high (i.e., the first level signal). After the low-voltage fault is cleared, at time T25, the tactile switch K1 is pressed. The first power supply VC1, through the eleventh diode D11 and the fiftieth resistor R50 of the tactile switch K1, pulls the level of the inverting input terminal of the fourth comparator U9 high, making it higher than the level of the non-inverting input terminal of the fourth comparator U9. The signal LVP_n output by the fourth comparator U9 instantly flips to low. At this time, the signal OVP_n output by the third comparator U8 remains low. Then, the signal SW_n output by the second AND gate AN2 instantly flips from high to low, completing the reset action. Figure 18 In the vertical direction from top to bottom, the components are: first power supply VC1, voltage VSW1 at the second terminal of tactile switch K1, first voltage threshold VH, second sampling voltage SV2, second voltage threshold VL, signal EN_n, signal LVP_n, signal OVP_n, and signal SW_n.

[0117] like Figure 19As shown, at time T34, the membrane electrode voltage of the electrolytic cell module EN suddenly experiences an overvoltage fault, i.e., SV2-VD>VH. At this time, the voltage at the non-inverting input of the third comparator U8 is higher than the voltage at the inverting input, and the signal OVP_n output by the third comparator U8 instantly flips to a high level. The voltage at the non-inverting input of the fourth comparator U9 remains lower than the voltage at the inverting input, and the signal LVP_n output by the fourth comparator U9 remains at a low level. At the same time, the signal EN_n output by the fifth comparator U10 is at a high level, so the signal SW_n output by the second AND gate AN2 flips from a low level to a high level, completing the switching signal of the drive switch branch 405 from a low level (i.e., the second level signal) to a high level (i.e., the first level signal). After the high-voltage fault is cleared, at time T35, pressing the tactile switch K1 causes the first power supply VC1 to pull the level of the inverting input of the third comparator U8 high, making it higher than the level of the non-inverting input of the third comparator U8, after passing through the tactile switch K1, the tenth diode D10, and the forty-eighth resistor R48. The signal OVP_n output by the third comparator U8 then momentarily flips to a low level. At this time, the signal OVP_n output by the third comparator U8 remains low, and then the signal SW_n output by the second AND gate AN2 momentarily flips from a high level to a low level, completing the reset action. In this process... Figure 19 In the vertical direction from top to bottom, the components are: first power supply VC1, voltage VSW1 at the second terminal of tactile switch K1, first voltage threshold VH, second sampling voltage SV2, second voltage threshold VL, signal EN_n, signal LVP_n, signal OVP_n, and signal SW_n.

[0118] In some embodiments, such as Figure 20 As shown, the switch branch 405 includes a first switch unit 4051, a second switch unit 4052, and a third switch unit 4053.

[0119] The second switch unit 4052, the electrolytic cell module EM and the third switch unit 4053 are connected in series and are located on the current path of the voltage conversion circuit 200 and the N electrolytic cell modules EM. The circuit in which the second switch unit 4052, the electrolytic cell module EM and the third switch unit 4053 are connected in series is connected in parallel with the first switch unit 4051.

[0120] The switch branch 405 is configured such that, in response to a first level signal, the first switch unit 4051 is turned on, and the second switch unit 4052 and the third switch unit 4053 are turned off, so as to short-circuit the electrolytic cell module EM; in response to a second level signal, the first switch unit 4051 is turned off, and the second switch unit 4052 and the third switch unit 4053 are turned on, so as to connect the electrolytic cell module EM to the voltage conversion circuit 200 and the current path of the N electrolytic cell modules EM.

[0121] In some embodiments, such as Figure 21 As shown, the switch branch 405 also includes a drive unit 4054. The drive unit 4054 is electrically connected to the first switch unit 4051, the second switch unit 4052 and the third switch unit 4053 respectively.

[0122] The drive unit 4054 is configured to output a fifth drive signal to the first switch unit 4051, a sixth drive signal to the second switch unit 4052, and a seventh drive signal to the third switch unit 4053 based on the switch signal. Specifically, when the switch signal is a first level signal, the fifth drive signal drives the first switch unit 4051 to turn on, the sixth drive signal drives the second switch unit 4052 to turn off, and the seventh drive signal drives the third switch unit 4053 to turn off; when the switch signal is a second level signal, the fifth drive signal drives the first switch unit 4051 to turn off, the sixth drive signal drives the second switch unit 4052 to turn on, and the seventh drive signal drives the third switch unit 4053 to turn on.

[0123] Figure 22 An exemplary circuit structure for switch branch 405 is shown. Figure 22 As shown, the first switching unit 4051 includes a fifty-first resistor R51, a second switching transistor Q2, and a third switching transistor Q3.

[0124] Among them, the fifty-first resistor R51 is electrically connected between the first terminal of the second switch Q2 and the first ground GND1. The first terminal of the second switch Q2 is electrically connected to the first terminal of the third switch Q3 and the driving unit 4054 respectively. The second terminals of the second switch Q2 and the second terminals of the third switch Q3 are both electrically connected to the first ground GND1. The third terminal of the second switch Q2 is electrically connected to the second switching unit 4052. The third terminal of the third switch Q3 is electrically connected to the third switching unit 4053.

[0125] In some embodiments, the second switching unit 4052 includes a fifty-second resistor R52, a fourth switching transistor Q4, and a fifth switching transistor Q5.

[0126] The third terminal of the fourth switch Q4 is electrically connected to the first switch unit 4051. The first terminal of the fourth switch Q4 is electrically connected to the first terminal of the fifth switch Q5 and the drive unit 4054. The fifty-second resistor R52 is electrically connected between the first terminal of the fourth switch Q4 and the second ground GND2. The second terminals of the fourth switch Q4 and the fifth switch Q5 are both electrically connected to the second ground GND2. The third terminal of the fifth switch Q5 is electrically connected to the electrolytic cell module EM.

[0127] In some embodiments, the third switching unit 4053 includes a fifty-third resistor R53, a sixth switching transistor Q6, and a seventh switching transistor Q7.

[0128] The third terminal of the sixth switch Q6 is electrically connected to the electrolytic cell module EM. The first terminal of the sixth switch Q6 is electrically connected to the first terminal of the seventh switch Q7 and the drive unit 4054. The fifty-third resistor R53 is electrically connected between the first terminal of the sixth switch Q6 and the third ground GND3. The second terminals of the sixth switch Q6 and the seventh switch Q7 are both electrically connected to the third ground GND3. The third terminal of the seventh switch Q7 is electrically connected to the first switch unit 4051.

[0129] Among them, the fourth switch Q4, the fifth switch Q5, the electrolytic cell module EM, the sixth switch Q6 and the seventh switch Q7 are connected in series and are located on the current path between the voltage conversion circuit 200 and the N electrolytic cell modules EM.

[0130] In some embodiments, the driving unit 4054 includes the following resistors: the 54th resistor R54, the 55th resistor R55, the 56th resistor R56, the 57th resistor R57, the 58th resistor R58, the 59th resistor R59, the 60th resistor R60, the 61st resistor R61, the 62nd resistor R62, the 63rd resistor R63, the 64th resistor R64, the 65th resistor R65, the 66th resistor R66, the 67th resistor R67, the 68th resistor R68, the 69th resistor R69, and the 70th resistor R60. Resistor R70, seventy-first resistor R71, seventy-second resistor R72, seventy-third resistor R73, seventy-fourth resistor R74, seventy-fifth resistor R75, eighth switch Q8, ninth switch Q9, tenth switch Q10, eleventh switch Q11, twelfth switch Q12, first optocoupler UA1, second optocoupler UA2, third optocoupler UA3, tenth capacitor C10, eleventh capacitor C11, twelfth capacitor C12, twelfth diode D12, thirteenth diode D13, and fourteenth diode D14.

[0131] Specifically, the first terminal of the 54th resistor R54 receives the switch signal; the second terminal of the 54th resistor R54 is electrically connected to the first terminal of the 55th resistor R55 and the first terminal of the 8th switch Q8; the third terminal of the 8th switch Q8 is electrically connected to the first terminal of the 9th switch Q9, the first terminal of the 56th resistor R56, and the first terminal of the 57th resistor R57; the second terminals of the 55th resistor R55, the 8th switch Q8, the 57th resistor R57, and the 9th switch Q9 are all grounded (GND); the second terminals of the 56th resistor R56, the first terminals of the 58th resistor R58, and the 59th resistor R59 are all electrically connected to the first power supply VC1; and the third terminal of the 9th switch Q9 is connected to the second terminal of the 58th resistor R58 and the first optocoupler. The first terminal of the input of UA1 is electrically connected, the second terminal of the fifty-ninth resistor R59 is electrically connected to the second terminal of the input of the first optocoupler UA1, the first terminal of the output of the first optocoupler UA1 and the first terminal of the tenth capacitor C10 are both electrically connected to the third power supply VC3, the second terminal of the output of the first optocoupler UA1 and the second terminal of the tenth capacitor C10 are both electrically connected to the second ground GND2, the third terminal of the output of the first optocoupler UA1 is electrically connected to the cathode of the twelfth diode D12 and the first terminal of the sixtieth resistor R60, the anode of the twelfth diode D12 is electrically connected to the first terminal of the sixty-first resistor R61, and the second terminal of the sixty-first resistor R60 is electrically connected to the second terminal of the sixty-first resistor R61 and the second switching unit 4052, so as to output the sixth drive signal P6 to the second switching unit 4052.

[0132] The first terminal of the sixty-second resistor R62 receives the switch signal. The second terminal of the sixty-second resistor R62 is electrically connected to the first terminal of the sixty-third resistor R63 and the first terminal of the tenth switch transistor Q10. The second terminals of both the sixty-third resistor R63 and the tenth switch transistor Q10 are grounded (GND). The third terminal of the tenth switch transistor Q10 is electrically connected to the first terminal of the sixty-fourth resistor R64 and the first terminal of the input of the second optocoupler UA2. The second terminals of the sixty-fourth resistor R64 and the sixty-fifth resistor R65 are both electrically connected to the first power supply VC1. The second terminal of the sixty-fifth resistor R65 is electrically connected to the second terminal of the input of the second optocoupler UA2. The first terminal of the output of the second optocoupler UA2 and the first terminal of the eleventh capacitor C11 are both electrically connected to the third power supply. The second terminal of the output of the second optocoupler UA2 and the second terminal of the eleventh capacitor C11 are both electrically connected to the first ground GND1. The third terminal of the output of the second optocoupler UA2 is electrically connected to the cathode of the thirteenth diode D13 and the first terminal of the sixty-sixth resistor R66, respectively. The anode of the thirteenth diode D13 is electrically connected to the first terminal of the sixty-seventh resistor R67, respectively. The second terminal of the sixty-seventh resistor R67 is electrically connected to the second terminal of the sixty-sixth resistor R66 and the first switching unit 4051, so as to output the fifth drive signal P5 to the first switching unit 4051.

[0133] The first terminal of the 68th resistor R68 receives a switch signal. The second terminal of the 68th resistor R68 is electrically connected to the first terminal of the 69th resistor R69 and the first terminal of the 11th switch Q11. The third terminal of the 11th switch Q11 is electrically connected to the first terminal of the 12th switch Q12, the first terminal of the 70th resistor R70, and the first terminal of the 71st resistor R71. The second terminals of the 69th resistor R69, the 11th switch Q11, the 71st resistor R71, and the 12th switch Q12 are all grounded (GND). The second terminals of the 70th resistor R70, the first terminals of the 72nd resistor R72, and the first terminals of the 73rd resistor R73 are all electrically connected to the first power supply VC1. The third terminal of the 12th switch Q12 is electrically connected to the second terminal of the 72nd resistor R72 and the first terminal of the 73rd resistor R73. The first terminal of the input of the third optocoupler UA3 is electrically connected, the second terminal of the seventy-third resistor R73 is electrically connected to the second terminal of the input of the third optocoupler UA3, the first terminal of the output of the third optocoupler UA3 and the first terminal of the twelfth capacitor C12 are both electrically connected to the third power supply VC3, the second terminal of the output of the third optocoupler UA3 and the second terminal of the twelfth capacitor C12 are both electrically connected to the third ground GND3, the third terminal of the third optocoupler UA3 is electrically connected to the cathode of the fourteenth diode D14 and the first terminal of the seventy-fourth resistor R74, the anode of the fourteenth diode D14 is electrically connected to the first terminal of the seventy-fifth resistor R75, and the second terminal of the seventy-fifth resistor R75 is electrically connected to the second terminal of the seventy-fourth resistor R74 and the third switching unit 4053, so as to output the seventh drive signal P7 to the third switching unit 4053.

[0134] The following is Figure 23 The signals shown are used as examples. Figure 22 The principle of the circuit structure shown is explained. Specifically, in... Figure 23 In the middle, from bottom to top in the vertical direction, they are the switch signal SW_n, the sixth drive signal P6, the seventh drive signal P7, and the fifth drive signal P5.

[0135] Specifically, when the switching signal SW_n flips from high to low, the base voltages of the eighth switch Q8 and the eleventh switch Q11 are pulled down by pull-down resistors (resistors R55 (55) and R69 (69) respectively), causing their base-emitter voltage (the voltage difference between the base and emitter) to fall below the turn-on threshold voltage, thus turning off the eighth switch Q8 and the eleventh switch Q11. The first power supply VC1 pulls up the base voltage of the ninth switch Q9 through voltage divider resistors (resistors R56 (56) and R57 (57) respectively), and the first power supply VC1 also pulls up the base voltage of the twelfth switch Q12 through voltage divider resistors (resistors R70 (70) and R71 (71) respectively), causing its base-emitter voltage to exceed the turn-on threshold voltage, thus turning on the ninth switch Q9 and the twelfth switch Q12. After the ninth switch Q9 and the twelfth switch Q12 are turned on, the first power supply VC1 forms a circuit through the fifty-ninth resistor R59, the LED of the first optocoupler UA1, and the ninth switch Q9 to ground GND. The LED of the first optocoupler UA1 emits light, and the third terminal of the first optocoupler UA1 outputs a high level (i.e., the sixth drive signal P6 is high). Figure 23 At time T42, the sixth drive signal P6 switches to a high level, driving the fourth switch Q4 and the fifth switch Q5 to conduct through the sixtieth resistor R60; the first power supply VC1 forms a circuit with ground GND through the seventy-third resistor R73, the LED of the third optocoupler UA3, and the twelfth switch Q12. The LED of the third optocoupler UA3 emits light, and the third terminal of the output of the third optocoupler UA3 outputs a high level (i.e., the seventh drive signal P7 is high, such as...). Figure 23 At time T42, the seventh drive signal P7 switches to a high level, driving the sixth switch Q6 and the seventh switch Q7 to conduct through the seventy-fourth resistor R74. Simultaneously, the base voltage of the tenth switch Q10 is pulled low through the pull-down resistor (i.e., the sixty-third resistor R63), causing its base-emitter voltage to fall below the conduction threshold voltage, thus turning off the tenth switch Q10. The first power supply VC1 pulls up the voltage at the second terminal of the input of the second optocoupler UA2 through the pull-up resistor (i.e., the sixty-fourth resistor R64), causing the LED of the second optocoupler UA2 to be reverse-biased and cut off. The second optocoupler UA2 outputs a low-level signal (i.e., the fifth drive signal P5 is low, such as...). Figure 23 At time T42, the fifth drive signal P5 switches to a low level. This low-level signal, through the sixty-sixth resistor R66, pulls down the gate voltages of the second switch Q2 and the third switch Q3, making them lower than the turn-on voltage of the MOSFET, thus turning off the second switch Q2 and the third switch Q3. In this way, the electrolytic cell module EM is connected to the voltage conversion circuit 200 and the current path of the N electrolytic cell modules EM.

[0136] When the switching signal SW_n flips from low to high, the drive signal SW_n, through resistors R54 (54), R62 (62), and R68 (68), pulls up the base voltages of the eighth switch Q8, tenth switch Q10, and eleventh switch Q11, respectively, making their base-emitter voltages higher than the transistor's turn-on threshold voltage. This turns on the eighth switch Q8, tenth switch Q10, and eleventh switch Q11. After the eighth switch Q8 and eleventh switch Q11 are turned on, the base voltages of the ninth switch Q9 and twelfth switch Q12 are pulled down through the eighth switch Q8 and eleventh switch Q11, respectively, making them lower than the transistor's turn-on threshold voltage. This turns off the ninth switch Q9 and twelfth switch Q12. After the ninth switch Q9 and the twelfth switch Q12 are turned off, the first power supply VC1 pulls up the voltage at the second terminal of the input of the first optocoupler UA1 and the third optocoupler UA3 through the fifty-eighth resistor R58 and the seventy-second resistor R72, respectively. This causes the LEDs of the first optocoupler UA1 and the third optocoupler UA3 to be reverse-biased and cut off. The third terminal of the output of the first optocoupler UA1 and the third optocoupler UA3 outputs a low-level signal (corresponding to the sixth drive signal P6 and the seventh drive signal P7 being low-level signals, such as...). Figure 23 At time T41, the sixth drive signal P6 and the seventh drive signal P7 switch to low level. Therefore, the sixth drive signal P6 turns off the fourth switch Q4 and the fifth switch Q5, and the seventh drive signal P7 turns off the sixth switch Q6 and the seventh switch Q7. Simultaneously, after the tenth switch Q10 turns on, the first power supply VC1 forms a circuit through the sixty-fifth resistor R65, the LED of the second optocoupler UA2, and the tenth switch Q10 to ground GND. The LED of the second optocoupler UA2 illuminates, and the third terminal of the second optocoupler UA2 outputs a high level. This high-level signal pulls up the gate voltage of the second switch Q2 and the third switch Q3 through the sixty-sixth resistor R66, making it higher than the turn-on voltage of the MOSFET, thus turning on the second switch Q2 and the third switch Q3. In this way, the faulty electrolytic cell module EM is short-circuited, effectively kicking the faulty electrolytic cell module EM out of the voltage conversion circuit 200 and the current path of the N electrolytic cell modules EM.

[0137] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

[0138] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, and the steps can be implemented in any order. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A switching transistor driving circuit, characterized in that, For driving a first switching transistor in a voltage conversion circuit, the switching transistor driving circuit includes: The first sampling branch is electrically connected to the voltage conversion circuit and is configured to output a first sampling voltage based on the output current of the voltage conversion circuit. The second sampling branch is electrically connected to the voltage conversion circuit and is configured to output a second sampling voltage based on the output voltage of the voltage conversion circuit. A voltage generation branch, electrically connected to the first sampling branch and the first power supply respectively, is configured to generate a reference voltage based on the voltage of the first power supply when the output current is less than or equal to the upper limit of the output current of the voltage conversion circuit, and is configured to generate the reference voltage based on the first sampling voltage when the output current is greater than the upper limit. The first comparison branch is electrically connected to the voltage generation branch, receives a first triangular carrier signal, and is configured to output a first drive signal based on a first comparison result between the reference voltage and the voltage of the first triangular carrier signal. The controller, electrically connected to the second sampling branch, is configured to perform PI regulation on the difference between the second sampled voltage and a preset voltage to generate a voltage regulation signal, and to perform pulse width modulation operation on the voltage regulation signal and the second triangular carrier signal to output a second drive signal, wherein the waveforms of the first triangular carrier signal and the second triangular carrier signal are the same. A logic control branch, electrically connected to the controller, the first comparison branch, and the first switch, is configured to output a third drive signal based on the logical operation result of the first drive signal and the second drive signal to drive the first switch. The third drive signal is consistent with the second drive signal when the output current is less than or equal to the upper limit value, and the third drive signal is consistent with the first drive signal when the output current is greater than the upper limit value.

2. The switching transistor driving circuit according to claim 1, characterized in that, The first sampling branch is also configured to differentially sample the output current to output the first sampled voltage.

3. The switching transistor driving circuit according to claim 2, characterized in that, The first sampling branch includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor, and a first operational amplifier; The first resistor and the second resistor are connected in series between the positive terminal of the differential sampling signal of the output current and ground. The connection point between the first resistor and the second resistor is electrically connected to the non-inverting input terminal of the first operational amplifier. The first capacitor is connected in parallel with the second resistor. The third resistor and the fourth resistor are connected in series between the negative terminal of the differential sampling signal of the output current and the output terminal of the first operational amplifier. The connection point between the third resistor and the fourth resistor is electrically connected to the inverting input terminal of the first operational amplifier. The second capacitor is connected in parallel with the fourth resistor. The fifth resistor is electrically connected between the output terminal of the first operational amplifier and the voltage generation branch.

4. The switching transistor driving circuit according to claim 1, characterized in that, The voltage generation branch includes a first unidirectional conductive unit and a second unidirectional conductive unit; The first unidirectional conductive unit is electrically connected to the first sampling branch, and the second unidirectional conductive unit is electrically connected to the first power supply. The voltage generation branch is specifically configured such that when the output current is greater than the upper limit of the output current of the voltage conversion circuit, the first unidirectional conductive unit is turned on and the second unidirectional conductive unit is turned off, so as to generate the reference voltage based on the first sampled voltage. When the output current is less than or equal to the upper limit value, the first unidirectional conductive unit is turned off and the second unidirectional conductive unit is turned on to generate a reference voltage based on the voltage of the first power supply.

5. The switching transistor driving circuit according to claim 4, characterized in that, The first unidirectional conductive unit is a first diode, the second unidirectional conductive unit is a second diode, and the voltage generation branch further includes a sixth resistor and a seventh resistor; The anode of the first diode is electrically connected to the first sampling branch, the cathode of the first diode is electrically connected to the first end of the sixth resistor and the cathode of the second diode, the anode of the second diode is electrically connected to the first power supply through the seventh resistor, and the second end of the sixth resistor is grounded.

6. The switching transistor driving circuit according to claim 1, characterized in that, The first comparison branch includes an eighth resistor, a ninth resistor, a tenth resistor, and a first comparator; The first end of the eighth resistor is electrically connected to the voltage generation branch, the second end of the eighth resistor is electrically connected to the inverting input of the first comparator, the first end of the ninth resistor receives the first triangular carrier signal, the second end of the ninth resistor is electrically connected to the non-inverting input of the first comparator, the output of the first comparator is electrically connected to the first end of the tenth resistor and the logic control branch, and the second end of the tenth resistor is electrically connected to the first power supply.

7. The switching transistor driving circuit according to claim 1, characterized in that, The logic control branch includes an eleventh resistor, a twelfth resistor, a thirteenth resistor, a third capacitor, and a first AND gate; The eleventh resistor and the third capacitor are connected in series between the first comparison branch and ground. The connection point between the eleventh resistor and the third capacitor is electrically connected to the first input terminal of the first AND gate. The twelfth resistor and the thirteenth resistor are connected in series between the controller and ground. The connection point between the twelfth resistor and the thirteenth resistor is electrically connected to the second input terminal of the first AND gate. The output terminal of the first AND gate is electrically connected to the first switching transistor.

8. The switching transistor drive circuit according to any one of claims 1-7, characterized in that, The switching transistor drive circuit also includes: The signal generation circuit is electrically connected to the controller and the first comparison branch, respectively, and is configured to generate the first triangular carrier signal based on the first square wave signal output by the controller, wherein a triangular waveform is generated in each half cycle of the first square wave signal, and multiple triangular waveforms constitute the first triangular carrier signal.

9. A water electrolysis hydrogen production system, characterized in that, It includes an input power supply, a voltage conversion circuit, N electrolytic cell modules, and a switching transistor drive circuit as described in any one of claims 1-8, wherein N is a positive integer; N electrolytic cell modules are connected in series, the voltage conversion circuit is electrically connected between the input power supply and the electrolytic cell module, and the switching transistor drive circuit is electrically connected to the first switching transistor in the voltage conversion circuit. The switching transistor driving circuit is configured to drive the first switching transistor to turn on or off, so that the voltage conversion circuit generates a voltage to power the electrolytic cell module based on the voltage of the input power supply.

10. The water electrolysis hydrogen production system according to claim 9, characterized in that, It also includes N switching circuits, each of which is electrically connected to an electrolytic cell module; The switching circuit is configured to short-circuit the electrolytic cell module when an overvoltage or undervoltage fault occurs, wherein, after at least one electrolytic cell module is short-circuited, the switching transistor drive circuit adjusts the duty cycle of the output third drive signal so that the output current of the voltage conversion circuit is less than or equal to the upper limit value.

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