Error code testing device for multi-rate switching and working method thereof

Abstract

The application provides a multi-rate switching error code testing device and a working method thereof. The error code testing device comprises a control terminal, a control module, a signal generating unit and a signal receiving unit. The control terminal is used for receiving a multi-rate switching test configuration command of a user, encapsulating the multi-rate switching test configuration command as a control command and issuing the control command to the control module. The control module is used for receiving the control command issued by the control terminal, scheduling the signal generating unit and the signal receiving unit to execute an operation corresponding to the control command. The signal generating unit is used for preloading a test signal pattern parameter matched with a current target rate from a multi-rate parameter library according to the control command, generating a test signal according to the test signal pattern parameter and sending the test signal to a device under test. The signal receiving unit is used for receiving an output signal output by the device under test according to the test signal, and performing error code statistics on the output signal. The error code testing device can improve test efficiency.

Description

Technical Field

[0001] This invention relates to the field of communication testing technology, specifically to a multi-rate switching bit error rate testing device, and also to a method for operating the multi-rate switching bit error rate testing device. Background Technology

[0002] Existing bit error rate (BER) testing devices for high-speed communication equipment (such as optical modules and network switches) can achieve basic BER measurement functions, but due to limitations in design concepts and technical architecture, they still have significant technical shortcomings in multi-rate, fast-switching testing scenarios, specifically in the following aspects:

[0003] 1. Fixed-rate design, unable to adapt to dynamic needs in multiple scenarios. Traditional bit error rate testers (BERTs) employ a fixed-rate design in both hardware and software architecture. Hardware interfaces and circuits are fixed: the rate capabilities of core components (such as DAC / ADC, SerDes chips) at the transmitting and receiving ends are fixed through physical packaging or hardware programming, and cannot be extended to other rates through software configuration. To test devices at different rates, dedicated hardware modules must be replaced (e.g., replacing with a higher-bandwidth SerDes board), resulting in extremely low device utilization. Alternatively, different rate configuration files are programmed through hardware or factory presets, supporting only a few rates specified at the factory. For emerging or non-standard rates (such as custom 30G / 75G test rates), hardware circuits must be redesigned and firmware code modified, making dynamic parameter loading through software adaptation impossible. In R&D testing, engineers typically need to prepare multiple BERTs for devices under test at different rates, or frequently change hardware modules on a single device, leading to time-consuming test environment setup (each change requires rewiring and calibration), severely impacting multi-task testing efficiency.

[0004] 2. The rate switching process is complex and lengthy, making dynamic and seamless testing difficult. Even though some devices claim to support multiple rates, their parameter configuration and initialization processes are cumbersome and cannot meet the dynamic switching requirements of high-speed testing scenarios. After switching rates, the PRBS code pattern, equalizer coefficients, etc., must be manually set, and each item must be confirmed through the host computer software. Some devices also require a link training process (such as the transmitter sending a training sequence and the receiver automatically adjusting the equalizer), which takes up to tens of seconds, during which effective testing cannot be performed.

[0005] Therefore, a more optimized multi-rate switching error testing method needs to be considered. Summary of the Invention

[0006] The primary objective of this invention is to provide a multi-rate switching bit error rate testing device that can improve testing efficiency.

[0007] The second object of the present application is to provide a working method of the error code testing device which can improve testing efficiency.

[0008] In order to achieve the above-mentioned first object, the present application provides a multi-rate switching error code testing device, which comprises a control terminal, a control module, a signal generating unit and a signal receiving unit; the control terminal is used for receiving a multi-rate switching testing configuration command of a user, encapsulating the multi-rate switching testing configuration command as a control command and issuing the control command to the control module; the control module is used for receiving the control command issued by the control terminal, scheduling the signal generating unit and the signal receiving unit to execute the operation corresponding to the control command; the signal generating unit is used for preloading a test signal pattern parameter matched with a current target rate from a multi-rate parameter library according to the control command, generating a test signal according to the test signal pattern parameter and sending the test signal to a device under test; and the signal receiving unit is used for receiving an output signal output by the device under test according to the test signal, and performing error code statistics on the output signal.

[0009] As can be seen from the above scheme, in the multi-rate switching error code testing device of the present application, the multi-rate switching testing configuration command is set, so that the multi-rate testing sequence can be triggered by one key, the multi-rate continuous seamless testing is realized, and the function of fast switching is realized. Meanwhile, the signal generating unit preloads the test signal pattern parameter matched with the current target rate from the multi-rate parameter library, so that the parameter configuration and calibration are not required to be manually intervened, the testing efficiency is improved, and the testing period of batch devices or multi-rate scenes is greatly shortened.

[0010] In a further scheme, the error code testing device further comprises a clock generating unit, which is used for receiving the current target rate sent by the control module and outputting a corresponding clock signal to the signal generating unit and the signal receiving unit according to the current target rate.

[0011] As can be seen from this, the clock generating unit directly receives the current target rate issued by the control module, generates the clock signal matched with the rate in real time, and synchronously outputs the same clock signal to the signal generating unit and the signal receiving unit, so as to ensure that the test signal generation and the output signal receiving are based on the same time reference, and the clock synchronization accuracy of the sending end and the receiving end is ensured.

[0012] In a further scheme, the clock generating unit generates the clock signal by using a digital phase-locked loop.

[0013] As can be seen from this, the clock generating unit uses the digital phase-locked loop, so that after receiving the rate switching instruction, the digital phase-locked loop can be used to quickly adjust the frequency division ratio and the control voltage of a voltage-controlled oscillator (VCO), so as to realize the smooth switching of the clock frequency.

[0014] In a further scheme, after the signal receiving unit receives the output signal output by the device under test according to the test signal, the signal receiving unit performs equalization processing on the output signal by using the preloaded equalizer coefficient corresponding to the current target rate.

[0015] Therefore, by preloading the equalizer coefficients matched with the current target rate, the signal receiving unit can achieve targeted compensation, and the transmission characteristics of signals of different rates are significantly different. The pre-stored equalizer coefficients are calibrated and optimized, and the typical channel distortion at the current rate can be accurately compensated. Compared with real-time adaptive equalization, the preloaded coefficients can make the equalizer immediately enter a stable working state after rate switching, avoiding signal misjudgment caused by the convergence process.

[0016] In a further scheme, when the signal receiving unit performs error code statistics on the output signal, the signal receiving unit also performs signal state monitoring on the output signal.

[0017] Therefore, by monitoring the signal state of the output signal, real-time early warning capability can be achieved. The control terminal can pre-set the normal threshold range of each state parameter, and the signal receiving unit can compare the monitoring data with the threshold in real time. If the parameter is out of limit, the control module will immediately feed back to the control terminal, and the control terminal can intervene in time according to the early warning information to avoid invalid test.

[0018] In a further scheme, when the signal receiving unit performs signal state monitoring on the output signal, if the signal loss alarm or the signal lock loss alarm is triggered, the error code statistics is frozen.

[0019] Therefore, when the signal loss alarm or the signal lock loss alarm is triggered, the error code statistics is frozen to prevent invalid data from interfering with the test results.

[0020] In a further scheme, after the signal receiving unit freezes the error code statistics, the control module rolls back to the previous stable rate operation and sends an alarm information to the control terminal.

[0021] Therefore, when the signal loss alarm or the signal lock loss alarm is triggered, the control module rolls back to the previous stable rate operation to ensure that the overall test process is not interrupted and the link stability is ensured.

[0022] In a further scheme, the error code test device further comprises a visualization module, and the visualization module is configured to display the working state of the error code test device and the error code statistics information in real time.

[0023] Therefore, by setting the visualization module to display the working state of the error code test device and the error code statistics information in real time, the user can intuitively master the test progress.

[0024] In a further scheme, a single multi-rate switching test configuration command adopts a multi-parameter packaging structure.

[0025] Therefore, a single command encapsulates multiple parameters, reducing the number of command interactions. The corresponding rate switching can be completed by only one command configuration, improving the configuration efficiency in the rate switching test scene.

[0026] To achieve the second object of the present application, the working method of the error code test device of the present application comprises: the control terminal receives the multi-rate switching test configuration command of the user, encapsulates the multi-rate switching test configuration command as a control command, and issues the control command to the control module; the control module receives the control command issued by the control terminal, and schedules the signal generation unit and the signal receiving unit to execute the operation corresponding to the control command; wherein the step of scheduling the signal generation unit and the signal receiving unit to execute the operation corresponding to the control command comprises: the signal generation unit preloads the test signal pattern parameter matched with the current target rate from the multi-rate parameter library according to the control command, generates a test signal according to the test signal pattern parameter, and sends the test signal to the device under test; the signal receiving unit receives the output signal output by the device under test according to the test signal, and performs error code statistics on the output signal. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 is a structural block diagram of the error code test device for multi-rate switching according to the present application.

[0028] Figure 2 is a functional block diagram of the error code test device for multi-rate switching according to the present application.

[0029] Figure 3 is a flowchart of the working method of the error code test device according to the present application.

[0030] Figure 4 is a flowchart of the working method of the error code test device according to the present application.

[0031] The present application will be further described below in combination with the drawings and embodiments. DETAILED DESCRIPTION

[0032] Error code test device for multi-rate switching:

[0033] As shown in Figure 1 and Figure 2 , in this embodiment, the error code test device for multi-rate switching comprises a control terminal 1, a control module 2, a clock generation unit 3, a signal generation unit 4, a signal receiving unit 5, a visualization module 6, a data storage module 7, and a power management module 8.

[0034] The control terminal 1 is configured to receive a multi-rate switching test configuration command of a user, encapsulate the multi-rate switching test configuration command as a control command, and send the control command to the control module 2. The control terminal 1 is an interactive interface of the device, and is configured to receive operation instructions of a user, such as a rate switching instruction, a parameter configuration instruction, a test start / stop instruction, and the like, and convert the operation instructions into commands recognizable by the control module 2 to drive other modules to work cooperatively. The control terminal 1 communicates with the control module 2 in real time through an Ethernet interface, and encapsulates the parsed instructions as control commands and sends the control commands to the control module 2.

[0035] In the embodiment, a single multi-rate switching test configuration command adopts a multi-parameter encapsulation structure. The multi-rate switching test configuration command adopts a self-defined command format, and a single command can encapsulate multiple parameters (such as rate information, a PRBS code type, polarity information, and the like, including but not limited to these parameters). The single multi-rate switching test configuration command adopts the multi-parameter encapsulation structure, which can reduce the number of command interactions, and can complete corresponding rate switching through only one command configuration, thereby improving the configuration efficiency in a rate switching test scenario. Preferably, the multi-rate switching test configuration command adopts a TLV (Type-Length-Value) structure, and all dynamic rate switching parameters can be transmitted through only one command. For example, the TLV structure adopted is shown in Table 1.

[0036] Table 1

[0037]

[0038] The control module 2 is configured to receive the control command sent by the control terminal 1, and schedule the clock generation unit 3, the signal generation unit 4, the signal receiving unit 5 and the data storage module 7 to perform the operation corresponding to the control command. After receiving the command sent by the control terminal, the control module 2 schedules the clock generation unit 3, the signal generation unit 4, the signal receiving unit 5 and the data storage module 7 to perform specific operations, and feeds back the execution state to the control terminal 1. The control module 2 classifies the instructions sent by the control terminal 1 according to types, such as clock configuration instructions, protocol parameter instructions and test control instructions, and distributes the instructions to the execution units of the corresponding modules, such as the PLL register of the clock generation unit 3, the SerDes control register of the signal generation unit 4 and the signal receiving unit 5. The control module 2 also collects the state registers of the modules in real time, judges whether the modules are ready through the state machine mechanism, and feeds back the state information to the visualization module 6. For the rate switching requirement, a priority scheduling strategy is adopted, and the priority of the rate switching instruction is higher than that of the regular test instruction, so as to ensure the priority allocation of the resources of the key modules in the rate switching process and avoid task blocking. In this embodiment, the control module 2 is connected with the clock generation unit 3, the signal generation unit 4 and the signal receiving unit 5 through a data bus, to realize register-level control. The control module 2 interacts with the data storage module 7 through an SPI interface, to read / write configuration parameters and test logs.

[0039] The clock generation unit 3 is configured to receive the current target rate sent by the control module 2, and output the corresponding clock signal to the signal generation unit 4 and the signal receiving unit 5 according to the current target rate. The clock generation unit 3 directly receives the current target rate sent by the control module 2, generates the clock signal matched with the rate in real time, and synchronously outputs the same clock signal to the signal generation unit 4 and the signal receiving unit 5, so as to ensure that the test signal generation and the output signal receiving are based on the same time reference, and ensure the clock synchronization accuracy of the sending end and the receiving end. The clock generation unit receives the current target rate sent by the control module 2, calculates the corresponding frequency division ratio and VCO configuration parameters (such as loop filter bandwidth), adjusts the output clock signal to the SerDes control register of the signal generation unit 4 and the signal receiving unit 5, and simultaneously feeds back the locking state to the control module 2 through the state pin.

[0040] In this embodiment, the clock generation unit 3 generates the clock signal by using a digital phase-locked loop. The clock generation unit 3 uses a digital phase-locked loop, which can quickly adjust the frequency division ratio and the control voltage of the voltage-controlled oscillator (VCO) through the digital phase-locked loop after receiving the rate switching instruction, to realize the smooth switching of the clock frequency. The clock generation unit 3 is the clock core of the error code test device, uses a digital phase-locked loop (DPLL), and generates the clock signal corresponding to any rate according to the instruction, such as the clock signal corresponding to any rate in the 1G to 112G rate, to ensure the clock synchronization accuracy of the sending end and the receiving end.

[0041] The signal generation unit 4 is used to pre-load the test signal pattern parameters matching the current target rate from the multi-rate parameter library according to the control command, generate the test signal according to the test signal pattern parameters, and send it to the device under test 9. The control command contains information such as target rate, encoding mode (such as NRZ / PAM4), modulation parameters (such as the order of PAM4), pre-emphasis coefficient, pattern (such as PRBS7 / PRBS31), etc. For example, when receiving the control command of "switch to 50G PAM4", the signal generation unit 4 obtains the test signal pattern parameters corresponding to the 50G rate from the multi-rate parameter library and writes them into the corresponding register. The signal generation unit 4 generates the test signal according to the test signal pattern parameters and sends it to the device under test 9. After receiving the test signal, the device under test 9 processes it according to its own function and returns the processed signal to the error code test device.

[0042] The signal receiving unit 5 is used to receive the output signal output by the device under test 9 according to the test signal and perform error code statistics on the output signal. After receiving the output signal of the device under test 9, the signal receiving unit 5 compares the test signal and the output signal bit by bit. If they are not consistent, it is determined as an error code, and the error code counter is incremented by 1. The bit error rate (BER=error code number / total code number) and symbol error rate (SER, for multi-level encoding such as PAM4) are calculated in real time.

[0043] In an optional embodiment, the signal receiving unit 5 adopts a high-speed analog-to-digital converter (ADC)+programmable SerDes (deserializer) architecture. The SerDes supports adaptive equalization (such as CTLE continuous-time linear equalizer+DFE decision feedback equalizer+FFE feedforward equalizer), and the equalizer coefficients can be dynamically adjusted through DSP algorithm. The receiving end SerDes locks the clock phase of the input signal (based on PLL or DPLL) through the clock recovery unit (CDR), ensuring that the sampling clock is synchronized with the signal. After receiving the output signal output by the device under test 9, the signal receiving unit 5 samples the output signal through the high-speed analog-to-digital converter, converts it to parallel data through the SerDes deserializer, and simultaneously starts adaptive equalization to compensate for signal distortion.

[0044] In an optional embodiment, after performing error code statistics on the output signal, the test can be intervened according to the error code statistics results, for example, the first bit error rate threshold (BER: 1x10⁻¹² to 1x10⁻¹⁰) is triggered, and the second bit error rate threshold (BER: 1x10⁻¹¹ to 1x10⁻⁹) is triggered. The device under test 9 is adjusted to a lower rate, and the test is restarted. 9), it indicates that the performance of the device under test is slightly degraded, but it does not affect the core test results. At this time, the following intervention measures are taken: the signal receiving unit 5 records the “slight error code” event (including the time stamp and the current rate), the error code statistics continue, but the abnormal period is marked in the real-time curve (such as marked with a red dotted line); the control module 2 pushes the “BER slight abnormality” alarm to the control terminal 1, and suggests that the user pay attention to the subsequent trend; the signal generating unit 4 fine-tunes the pre-emphasis coefficient, such as from 9dB to 10dB, compensates for the temporary loss of the link, and tries to reduce the error rate. When the error rate triggers the second error rate threshold (BER > 1 x 10 9 ), it indicates that the device under test has significant defects, or the link is severely distorted, and the test will produce invalid data. At this time, the following intervention measures are taken: the signal receiving unit 5 immediately freezes the error code statistics, marks the “serious error code” event, and stops real-time analysis; the control module 2 pushes the “BER serious over-standard” alarm to the control terminal 1, and synchronously suspends the test process; the control module 2 schedules the signal generating unit 4 to switch to the calibration code (such as a fixed sequence with no error), and if the error rate is still over-standard, it is determined that the device under test is faulty, and if the calibration code is error-free, it is determined that the link is problematic, prompting to check the connector or cable.

[0045] In this embodiment, after the signal receiving unit 5 receives the output signal output by the device under test 9 according to the test signal, the output signal is processed by the preloaded equalizer coefficient corresponding to the current target rate. By preloading the equalizer coefficient matched with the current target rate, the signal receiving unit 5 can achieve targeted compensation. The transmission characteristics of signals of different rates are significantly different, and the pre-stored equalizer coefficient is optimized through calibration and can accurately compensate for the typical channel distortion at the current rate. Compared with real-time adaptive equalization, the preloaded coefficient can make the equalizer immediately enter a stable working state after rate switching, avoiding signal misjudgment caused by the convergence process.

[0046] In this embodiment, when the signal receiving unit 5 performs error code statistics on the output signal, it also performs signal state monitoring on the output signal. The signal state includes the signal loss (LOS, Loss of Signal) state and the signal loss of lock (LOL, Loss of Lock) state. Through signal state monitoring on the output signal, real-time early warning capability can be achieved. The control terminal 1 can pre-set the normal threshold range of each state parameter, and the signal receiving unit 5 compares the monitoring data with the threshold in real time. If the parameter is out of limit, it is immediately fed back to the control terminal 1 through the control module 2. The control terminal 1 can intervene in time according to the early warning information, so as to avoid invalid test from continuing.

[0047] In this embodiment, when the signal receiving unit 5 monitors the output signal and triggers a signal loss alarm or a signal lock loss alarm, the error code statistics are frozen. When the signal loss alarm or the signal lock loss alarm is triggered, the error code statistics are frozen to prevent invalid data from interfering with the test results. The signal loss state and the signal lock loss state are monitored in real time, and when the signal loss alarm or the signal lock loss alarm is triggered, the error code statistics are frozen immediately to prevent invalid data from interfering with the test results, and the statistics are restored after the alarm is cleared.

[0048] In an optional embodiment, when the signal receiving unit 5 determines the signal loss, any of the following conditions must be met: the signal amplitude is below the detection threshold for 100 ns, for example, the detection threshold is 0.2 V; the high-speed ADC sampling value is zero for 1000 consecutive periods. When the signal receiving unit 5 determines the signal lock loss, any of the following conditions must be met: the LOCK state bit of the clock recovery unit (CDR) is “0” for 10 ns, which cannot lock the clock phase of the input signal; the frequency of the decoded data jump deviates from the local reference clock by more than 10% (for example, the 100G signal is expected to jump at 12.5 GHz, and the actual jump frequency is less than 11.25 GHz); non-expected level appears for 100 consecutive symbols.

[0049] In this embodiment, after the signal receiving unit 5 freezes the error code statistics, the control module 2 rolls back to the previous stable rate operation and sends alarm information to the control terminal 1. If the signal loss alarm or the signal lock loss alarm is triggered during the switching process, the alarm priority unit freezes the statistics immediately and notifies the control module 2 to roll back to the previous stable rate operation to ensure the link stability. After the switching is completed, the alarm priority unit re-monitors the link state, and if there is still an alarm, logs are recorded and the control terminal 1 is notified. By rolling back to the previous stable rate operation when the signal loss alarm or the signal lock loss alarm is triggered, the control module 2 ensures that the overall test process is not interrupted and the link stability is guaranteed.

[0050] In addition, after determining signal loss, the signal receiving unit 5 freezes the error code statistics, and automatic troubleshooting and recovery attempts can also be performed. For example, a physical link self-check is performed, and if the self-check finds a physical connection problem, the control terminal 1 displays “Please check the physical connection of the device under test and the test device”. For another example, a state query is performed on the device under test 9 to check whether the device under test 9 is powered off, reset, or enters a protection mode, and if the device under test 9 does not respond, the control terminal 1 displays “The device under test may be abnormal, please replace the device under test and try again”. During the recovery attempt, the signal generating unit 4 is automatically restarted, the current rate parameters are reloaded, and a wake-up signal is sent to the device under test 9. After waiting for 500 ms, it is observed whether the signal is recovered, and the signal receiving unit 5 confirms that the signal amplitude is restored to the normal range and is stable for 100 ns, and then feeds back to the control module 2 that the signal loss is removed. The control module 2 schedules the signal generating unit 4 and the signal receiving unit 5 to re-synchronize, and the error code counter continues to count from the frozen value, ensuring data continuity.

[0051] After determining signal loss, the signal receiving unit 5 freezes the error code statistics, and automatic troubleshooting and recovery attempts can also be performed. For example, a physical link self-check is performed, and if the self-check finds a physical connection problem, the control terminal 1 displays “Please check the physical connection of the device under test and the test device”. For another example, a state query is performed on the device under test 9 to check whether the device under test 9 is powered off, reset, or enters a protection mode, and if the device under test 9 does not respond, the control terminal 1 displays “The device under test may be abnormal, please replace the device under test and try again”. During the recovery attempt, the signal generating unit 4 is automatically restarted, the current rate parameters are reloaded, and a wake-up signal is sent to the device under test 9. After waiting for 500 ms, it is observed whether the signal is recovered, and the signal receiving unit 5 confirms that the signal amplitude is restored to the normal range and is stable for 100 ns, and then feeds back to the control module 2 that the signal loss is removed. The control module 2 schedules the signal generating unit 4 and the signal receiving unit 5 to re-synchronize, and the error code counter continues to count from the frozen value, ensuring data continuity.

[0052] In this embodiment, the visualization module 6 is used to display the working state and error code statistical information of the error code test device in real time. By setting the visualization module 6, the working state and error code statistical information of the error code test device can be displayed in real time, which can facilitate the user to intuitively master the test progress.

[0053] The visualization module 6 displays the working status (e.g., current rate, clock frequency, link status, etc.) and error code statistical information (e.g., error code count, error code rate, alarm log, etc.) of the error code test device in real time, supporting users to intuitively master the test progress. For example, the visualization module 6 displays the current test rate (e.g., “100G”), clock frequency (e.g., “12.5GHz”), link status (e.g., “LOS”, “LOL”, “LOCK”), working temperature of each module (e.g., “CHIP: 55℃”), and other key parameters. The error code statistical area displays the error code count (e.g., “Total BER: 2×10⁻¹²”) in the form of numbers and charts, error code rate trend curve, draws RX receiving eye diagram, and alarm information (e.g., “PLL UNLOCKED”, “EQUALIZER FAILED”), supports historical data playback (e.g., retrieves BER curve of the previous 10 tests).

[0054] In this embodiment, the data storage module 7 is used to save the working status (e.g., configuration parameters, calibration records) and error code statistical information (e.g., test log, BER curve) of the error code test device, supporting data tracing, analysis and export. Preferably, the data storage module 7 adopts dual modes of built-in storage and extended storage. The built-in storage adopts an on-board data storage chip, which is used to store firmware programs, default configuration parameters (e.g., preloaded protocol stack of 1G, 10G, 25G) and test logs of the last 7 days, preventing data loss. The extended storage supports SD card or USB hard disk insertion, which is used to store long-term test data (e.g., records of mass production test) and user-defined configurations (e.g., protocol parameters of non-standard rate). When the test starts, a log file is automatically created (e.g., naming rule: “DUT_ID_rate_timestamp.csv”), and error code count, timestamp, error code position and other information are written in real time. When the test ends or is interrupted abnormally, the file is automatically closed and the status is marked (e.g., “COMPLETED”, “ABORTED”).

[0055] The data storage module 7 can also check the data integrity, using the CRC32 check algorithm to check the stored data, preventing data damage caused by storage medium failure. When reading data, the check code is automatically verified, and abnormal data is marked as “CORRUPTED”. The data storage module 7 supports exporting data to the PC end through the USB interface, and provides corresponding commands to realize historical data query (e.g., filtering according to time, rate, and measured device ID) and statistical analysis (e.g., BER distribution histogram). The data storage module 7 is connected with the control module 2 through the data transmission interface, receives the test data (e.g., error code count register value) sent by the control module 2 and writes it into the storage medium. The control terminal 1 can read the stored data through the instruction and forward it to the visualization module 6 for display.

[0056] The power management module 8 is used for providing power supply for the control module 2, the clock generation unit 3, the signal generation unit 4, the signal receiving unit 5, the visualization module 6 and the data storage module 7, and also obtaining the power supply instruction of the control module 2 and feeding back the power supply state to the control module 2 so as to monitor the power supply state.

[0057] In order to better illustrate the present application, the working method of the error code test device is described below.

[0058] Referring to Figure 3 In the working process of the error code test device in the embodiment, first, step S1 is performed, the control terminal 1 receives the multi-rate switching test configuration command of the user, encapsulates the multi-rate switching test configuration command as a control command and issues the control command to the control module 2. When inputting the multi-rate switching test configuration command, the user inputs the test requirements through the device control terminal 1, and the key parameters include: target test rate (for example, 10G→25G→100G rate cycle); protocol and code type configuration (encoding mode: NRZ / PAM4; code type: PRBS7 / PRBS31; pre-emphasis coefficient, equalizer parameter); test duration or error code threshold, etc. The control terminal 1 parses the multi-rate switching test configuration command into a structured command recognizable by the control module 2, and encapsulates and issues the structured command to the control module 2 through the Ethernet interface.

[0059] After the control command is issued to the control module 2, step S2 is performed, the control module 2 receives the control command issued by the control terminal 1, and schedules the signal generation unit 4 and the signal receiving unit 5 to perform the operation corresponding to the control command. The control module 2 classifies the instructions issued by the control terminal 1 according to types, such as clock configuration instructions, protocol parameter instructions and test control instructions, and distributes the instructions to the execution units of the corresponding modules, such as the PLL register of the clock generation unit 3, the SerDes control register of the signal generation unit 4 and the SerDes control register of the signal receiving unit 5. The control module 2 also collects the state registers of the modules in real time, judges whether the modules are ready through the state machine mechanism, and feeds back the state information to the visualization module 6. For the rate switching requirement, a priority scheduling strategy is adopted, the priority of the rate switching instruction is higher than that of the regular test instruction, so as to ensure the priority allocation of the resources of the key modules in the rate switching process and avoid task blocking. In the embodiment, the control module 2 is connected with the clock generation unit 3, the signal generation unit 4 and the signal receiving unit 5 through a data bus, so as to realize register-level control. The control module 2 interacts with the data storage module 8 through an SPI interface, reads / writes configuration parameters and test logs.

[0060] In the embodiment, referring to Figure 4, the clock generation unit 3 receives the current target rate sent by the control module 2, and outputs a corresponding clock signal to the signal generation unit 4 and the signal receiving unit 5 according to the current target rate. The clock generation unit 3 receives the current target rate, adjusts the frequency division ratio and the configuration parameters of the voltage controlled oscillator through the programmable digital phase-locked loop, generates a target clock signal, and simultaneously feeds back a "LOCKED" locked state. If it is not locked, an "PLL UNLOCKED" alarm is triggered and the user is prompted to check the hardware.

[0061] After outputting the corresponding clock signal to the signal generation unit 4 and the signal receiving unit 5 according to the current target rate, step S12 is performed. The signal generation unit 4 preloads test signal pattern parameters matching the current target rate from the multi-rate parameter library according to the control command, generates a test signal according to the test signal pattern parameters, and sends the test signal to the device under test 9. The signal generation unit 4 preloads the test signal pattern parameters (such as PAM4 level, pre-emphasis coefficient) corresponding to the current target rate from the multi-rate parameter library, writes into the SerDes control register, completes the parameter initialization of the signal generation unit, and the signal generation unit 4 generates a test signal according to the test signal pattern parameters and sends the test signal to the device under test 9.

[0062] After the signal generation unit 4 sends the test signal to the device under test 9, step S13 is performed. The signal receiving unit 5 receives an output signal output by the device under test 9 according to the test signal, and performs error code statistics on the output signal. The signal generation unit 4 samples the output signal through a high-speed analog-to-digital converter, converts it into parallel data through a SerDes deserializer, and simultaneously starts adaptive equalization to compensate for signal distortion. After the signal receiving unit 5 receives the output signal of the device under test 9, it compares the test signal and the output signal bit by bit, and calculates the error rate and the symbol error rate in real time. At the same time, the signal receiving unit 5 generates an RX receiving eye diagram (reflecting signal integrity, the larger the eye opening, the better the signal quality) in real time through a preset eye diagram drawing algorithm, and uploads it to the visualization module 6.

[0063] The signal receiving unit 5 also monitors the signal loss state and the signal lock loss state of the link in real time. If the signal loss alarm is triggered, the error code counter is immediately frozen to avoid invalid data interference with the result. The visualization module 6 marks "LOS alarm", and the control module 2 notifies to check the physical connection. If the clock lock loss alarm is triggered, the error code statistics are frozen, and the signal receiving unit 5 restarts the CDR clock lock. If the lock fails for three times, the "LOL alarm" is triggered and the test is paused, waiting for user intervention. After the exception is resolved, the error code counter continues to count from the value at the time of freezing, ensuring data continuity.

[0064] The control module 2 judges whether the current rate test reaches the set time length when the signal generation unit 4 and the signal receiving unit 5 perform the operation corresponding to the control command, if yes, the rate switching instruction (such as switching from 25G rate to 100G rate) is obtained, and the control module 2 schedules the signal generation unit 4 and the signal receiving unit 5 to perform the operation corresponding to the control command according to the switched rate. When all the rate tests in the multi-rate switching test configuration command are completed, the test is ended.

[0065] As known from the above, in the multi-rate switching error code test device, the multi-rate switching test configuration command is set, the multi-rate test sequence can be triggered by one key, the multi-rate continuous seamless test is realized, and the function of fast switching is realized. Meanwhile, the signal generation unit 4 preloads the test signal code type parameter matched with the current target rate from the multi-rate parameter library, manual intervention for parameter configuration and calibration is not needed, the test efficiency is improved, and the test period of batch equipment or multi-rate scene is greatly shortened.

[0066] It should be noted that the above is only the preferred embodiment of the present application, but the design concept of the present application is not limited to this, and any non-essential modification of the present application made by using the concept also falls within the protection scope of the present application.

Claims

1. A multi-rate switching bit error rate testing device, characterized in that: It includes a control terminal, a control module, a signal generating unit, and a signal receiving unit; The control terminal is used to receive the user's multi-rate switching test configuration command, encapsulate the multi-rate switching test configuration command into a control command and send it to the control module. The multi-rate switching test configuration command adopts a multi-parameter encapsulation structure and includes multiple target rates. The control module is used to receive the control command issued by the control terminal, and to schedule the signal generating unit and the signal receiving unit to execute the operation corresponding to the control command. When scheduling the signal generating unit and the signal receiving unit to execute the operation corresponding to the control command, if a rate switching instruction is obtained, the control module schedules the signal generating unit and the signal receiving unit to execute the operation corresponding to the control command according to the switched rate. The test ends when all rate tests in the multi-rate switching test configuration command are completed. The signal generation unit is used to preload test signal code parameters matching the current target rate from the multi-rate parameter library according to the control command, generate a test signal according to the test signal code parameters, and send it to the device under test. The signal receiving unit is used to receive the output signal output by the device under test according to the test signal, perform equalization processing on the output signal using a preloaded equalizer coefficient corresponding to the current target rate, and perform bit error statistics on the output signal. The control module also intervenes in the test based on the error statistics.

2. The multi-rate switching bit error rate testing device according to claim 1, characterized in that: The bit error rate testing device further includes a clock generation unit, which is used to receive the current target rate sent by the control module and output a corresponding clock signal to the signal generation unit and the signal receiving unit according to the current target rate.

3. The multi-rate switching bit error rate testing device according to claim 2, characterized in that: The clock generation unit uses a digital phase-locked loop to generate the clock signal.

4. The multi-rate switching bit error rate testing apparatus according to any one of claims 1 to 3, characterized in that: When the signal receiving unit performs bit error statistics on the output signal, it also monitors the signal status of the output signal.

5. The multi-rate switching bit error rate testing device according to claim 4, characterized in that: When the signal receiving unit monitors the signal status of the output signal, if a signal loss alarm or signal lockout alarm is triggered, the error rate statistics are frozen.

6. The multi-rate switching bit error rate testing device according to claim 5, characterized in that: After the signal receiving unit freezes the error statistics, the control module rolls back to the previous stable operating rate and sends an alarm message to the control terminal.

7. The multi-rate switching bit error rate testing apparatus according to any one of claims 1 to 3, characterized in that: The bit error rate testing device also includes a visualization module, which is used to display the working status and bit error statistics of the bit error rate testing device in real time.

8. A method for operating a bit error rate testing device, characterized in that: include: The control terminal receives the user's multi-rate handover test configuration command, encapsulates the multi-rate handover test configuration command into a control command and sends it to the control module. The multi-rate handover test configuration command adopts a multi-parameter encapsulation structure and includes multiple target rates. The control module receives the control command issued by the control terminal and schedules the signal generating unit and the signal receiving unit to execute the operation corresponding to the control command; The operation of scheduling the signal generating unit and the signal receiving unit to execute the control command includes: The signal generation unit preloads test signal code parameters matching the current target rate from the multi-rate parameter library according to the control command, generates a test signal according to the test signal code parameters, and sends it to the device under test. The signal receiving unit receives the output signal output by the device under test according to the test signal, performs equalization processing on the output signal using a preloaded equalizer coefficient corresponding to the current target rate, and performs bit error statistics on the output signal. The control module intervenes in the test based on the error statistics results; When the control module schedules the signal generating unit and the signal receiving unit to execute the operation corresponding to the control command, if a rate switching instruction is obtained, the control module schedules the signal generating unit and the signal receiving unit to execute the operation corresponding to the control command according to the switched rate; when all rate tests in the multi-rate switching test configuration command are completed, the test ends.

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