A phase real-time automatic calibration method for a scientific grade CMOS detector

Abstract

The present application relates to a kind of scientific grade CMOS detector's phase real-time automatic calibration method, belong to image processing technical field, solve the existing detector error calibration technique relies on manual intervention, low efficiency, interrupt image acquisition, cannot guarantee real-time and continuity problem.The method is when the reset stage of each row of scientific grade CMOS detector, pull high its Train pin multiple clock cycles, make its output training mode code;Real-time sampling training mode code and with standard training mode code are compared;If both do not match, then generate training enable signal, control detector to execute iterative training until converging to optimal phase;Training is completed, and training mode code comparison is carried out again, until detector enters normal imaging state.The present application can automatically, real-time compensate the clock-data phase offset caused by temperature drift, significantly improve the accuracy, stability and robustness of scientific grade CMOS detector image acquisition in dynamic environment.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of image processing, and in particular to a phase real-time automatic calibration method for a scientific CMOS detector. BACKGROUND

[0002] High-end scientific CMOS detectors (sCMOS) are widely used in astronomy, space, medical imaging, and free optical communication due to their full well capacity and response sensitivity. These detectors convert incident photons into electrons, which are then converted into voltage by floating diffusion amplifiers (FDA), amplified, and converted into digital signals by analog-to-digital converters (ADC). The photons falling on each pixel are converted into digital signals in this way and finally displayed as an image on the computer screen.

[0003] However, during this process, thermal motion of the pixel material may still produce some electrons without the influence of external photons, which will be read out by the detector and incorrectly included in the imaging signal. Since these electrons generated by thermal motion cannot be distinguished from actual photoelectric signals, a component called dark current exists in the generated signal, which is an electron current caused by thermal motion and unrelated to incident photons.

[0004] To reduce the impact of dark current, it is usually necessary to reduce thermal noise by reducing the operating temperature of the detector. Low-temperature operating environment can significantly reduce the generation of dark current. However, temperature changes not only affect the detector itself, but also affect the stability of the entire imaging system. Specifically, as the temperature of the detector and imaging board decreases, due to differences in the thermal expansion coefficient of materials and design issues, the temperature difference between the detector and high-speed data transmission lines (such as data lines on the imaging board) will cause changes in the physical properties of the lines. These changes can cause delays or errors in signal transmission, especially in the case of high-speed signal transmission, temperature changes can cause the phase of the clock signal to drift, affecting the synchronization between the clock and data, reducing the accuracy of data acquisition, and affecting image quality and system stability. This phenomenon is particularly important in astronomical observation missions, as astronomical images require very high accuracy in data.

[0005] Currently, the prior art usually adopts manual intervention to correct image errors caused by temperature drift or other factors during image acquisition. When image errors are observed, the system usually interrupts the current image acquisition and manually re-trains to adjust the data channel and realign the phase between the clock and the data. Although this method can solve the image error problem to some extent, it still has the following shortcomings:

[0006] 1. Manual intervention is not efficient: This method relies on the operator to find image errors and manually intervene, which cannot find and automatically correct data errors in real time, so image errors may last for a long time and the time point of error occurrence cannot be accurately traced back;

[0007] 2. Cannot guarantee real-time and accuracy: In complex or high-precision application scenarios such as astronomical exploration, the occurrence of image errors may affect the progress of the task and the accuracy of the data, and manual intervention cannot provide real-time correction during data acquisition;

[0008] 3. Disrupt the task: Since the image acquisition process is interrupted and retrained, the continuity of the task is affected, causing image loss during acquisition, affecting the continuity and integrity of the image, especially in scenarios where high-quality data is required, which cannot meet the requirements.

[0009] Therefore, in situations where image acquisition, data stability, and automation are required, the existing technical solution cannot effectively meet the accuracy, real-time, and continuity requirements. In view of the shortcomings of the prior art, it is necessary to provide a method that can automatically train the data channel and align the clock phase, improve the accuracy, real-time, and stability of image acquisition. SUMMARY

[0010] In view of the problems of data acquisition errors caused by clock signal phase drift of existing scientific CMOS detectors in low-temperature and other temperature fluctuation environments, and the problems of existing image error correction techniques that rely on manual intervention, low efficiency, interrupt image acquisition, and cannot guarantee real-time and continuity, the present application proposes a real-time automatic phase correction method for scientific CMOS detectors, which can automatically detect and correct image errors caused by temperature drift or other reasons during image acquisition without manual intervention, ensuring the accuracy and stability of image acquisition. Through this method, automatic training of the data channel and alignment of the clock phase can be achieved, greatly improving the robustness of the image acquisition system in dynamic environments.

[0011] The technical solutions adopted by the present application are as follows:

[0012] A real-time automatic phase correction method for scientific CMOS detectors, comprising the following steps:

[0013] Step 1: When each row of the scientific-grade CMOS detector enters the reset phase, pull the Train pin of the scientific-grade CMOS detector high for multiple clock cycles, so that all data channels of the scientific-grade CMOS detector continuously output training mode codes during the reset period.

[0014] Step 2: Sample the training mode code in real time and compare it with the preset standard training mode code in the scientific-grade CMOS detector. If they match, control the scientific-grade CMOS detector to continue normal imaging; otherwise, proceed to step 3.

[0015] Step 3: Generate a training enable signal and feed the training enable signal back to the training pin of the scientific-grade CMOS detector;

[0016] Step 4: In response to the training enable signal, force the scientific-grade CMOS detector to enter the training mode, and control the scientific-grade CMOS detector to perform a programmable number of iterative trainings according to the training logic to realign the phase of the clock signal and the data until convergence to the optimal phase. Under the optimal phase, the sampling point of the clock signal is located at the center of the data hold time.

[0017] Step 5: After training is complete, exit the training mode, return to step 1, and compare the training mode codes again until the scientific-grade CMOS detector enters the normal imaging state.

[0018] This invention, based on the row-exposure mechanism of scientific-grade CMOS detectors, proposes a method for real-time detection and automatic compensation of clock-data phase offset during the reset phase—that is, real-time automatic phase calibration—to achieve high-precision, continuous, and manual-intervention-free image acquisition with scientific-grade CMOS detectors. Compared with existing technologies, this invention has the following advantages:

[0019] (1) Strong real-time performance: Training pattern code detection and automatic training can be completed within each line reset phase of the scientific-grade CMOS detector without pausing image acquisition;

[0020] (2) High degree of automation: No need for manual observation and intervention of image errors, reducing deviations and delays caused by human operation;

[0021] (3) Good robustness: It can adapt to a wide range of temperature fluctuations, compensate for clock-data phase shift, and ensure the stability of long-term exposure and continuous observation tasks;

[0022] (4) Strong compatibility: Based on the standard CMOS detector training pin and field programmable gate array (FPGA) control logic, this invention can be seamlessly integrated into existing imaging boards and cooling platforms. Attached Figure Description

[0023] Figure 1 This is a flowchart of the real-time automatic phase calibration method described in this invention;

[0024] Figure 2 This is a timing diagram for the bit and word training and correction phases;

[0025] Figure 3 This is a timing diagram for the channel training and calibration phase.

[0026] Figure 4 This is a schematic diagram of the data collection location;

[0027] Figure 5 This is a timing diagram of the clock and data signals when there is a phase shift.

[0028] Figure 6 This is a timing diagram of the corrected clock signal and data signal;

[0029] Figure 7 The hardware block diagram for implementing the phase real-time automatic calibration method described in this invention. Detailed Implementation

[0030] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that this description is intended to enable those skilled in the art to fully understand and implement the present invention, and is not intended to limit the scope of the invention.

[0031] Based on the row-exposure mechanism of scientific-grade CMOS (sCMOS) detectors, this invention proposes a scheme to detect and automatically compensate for clock-data phase offset in real time during the reset phase, so as to achieve high-precision, continuous, and manual image acquisition.

[0032] In the sCMOS detector's row-by-row exposure mechanism, each row of the detector includes two time periods: a read phase and a reset phase. The former is responsible for outputting the photoelectric signal for that row, and the latter is responsible for clearing the pixel charge. The time difference between these two phases is the row exposure time. In conventional designs, to ensure phase alignment between the FPGA imaging board and the detector's clock-data signals after power-on, the sCMOS chip has a dedicated Train pin. Pulling this pin high causes all data channels to continuously output a preset training pattern (TP value), facilitating the FPGA imaging board's determination and calibration of the clock-data phase with the sCMOS detector. The training pattern is a special data sequence used for initializing and synchronizing high-speed serial interfaces (such as LVDS, JESD204B, PCIe, etc.) links. The preset training mode code (also known as the standard training mode code or standard TP value) is a fixed, preset value. For example, if the pixel value output by the sCMOS detector is 12-bit data, the standard training mode code can be set to 12'H98E. This standard training mode code is written into the sCMOS detector during initial configuration via SPI. It should be noted that while this invention can use an FPGA imaging board to drive and control the sCMOS detector, other hardware solutions can also be used to achieve similar functions. For example, high-performance MCUs / DSPs can be used for timing control, or a dedicated image signal processing chip (ISP) module can be used to drive the sensor and output data.

[0033] After the sCMOS detector is powered on for the first time, it enters the initial training phase to perform necessary parameter adjustments and performance calibration. Once the initial training is complete, the sCMOS detector enters normal operating mode, performs standard imaging operations, and remains stable at room temperature. Subsequently, during imaging, the external cooling system is activated to cool the sCMOS detector, ensuring it operates at a low temperature.

[0034] like Figure 1 As shown, the real-time automatic phase calibration method for the sCMOS detector of the present invention specifically includes the following steps:

[0035] Step 1: During exposure, enter the reset phase: When each row of the sCMOS detector enters the reset phase, pull the Train pin of the sCMOS detector high for several clock cycles, so that all data channels of the sCMOS detector continuously output training mode codes during the reset period.

[0036] In order not to affect normal image data, this invention automatically pulls the Train pin of the sCMOS detector high for a sufficient number of clock cycles when entering the reset phase after each line exposure, ensuring that all data channels of the sCMOS detector continuously output TP values ​​during the reset period.

[0037] Step 2: Real-time detection and comparison of TP value with standard TP value: Real-time sampling of training mode code and comparison with the preset standard training mode code in sCMOS detector. If they match, control the sCMOS detector to continue normal imaging; otherwise, proceed to step 3.

[0038] The FPGA imaging board incorporates a high-speed sampling module that samples the TP value output by the sCMOS detector in real time during each exposure. The FPGA imaging board then compares the sampled TP value with a standard TP value to determine if they match. The matching result reflects the alignment accuracy between the current clock phase and the data channel. The criterion for determining whether the sampled TP value matches the standard TP value is that the phase offset between the real-time sampled TP value and the standard TP value is less than a preset threshold.

[0039] Step 3, Automatic Training Trigger: Generate a training enable signal and feed it back to the training pin of the sCMOS detector.

[0040] When the FPGA imaging board determines that the sampled TP value does not match the standard TP value (i.e., the phase offset exceeds the preset threshold), the FPGA imaging board generates a training enable signal (Train_Enable) and feeds the training enable signal back to the training pin of the sCMOS detector through the differential data connector, forcing the sCMOS detector to enter the training mode.

[0041] Step 4, Automatic Training and Phase Compensation: In response to the training enable signal, the FPGA imaging board forces the sCMOS detector into training mode and controls the sCMOS detector to perform a programmable number of iterative training steps according to the training logic to realign the phase of the clock signal and the data until it converges to the optimal phase. Under this optimal phase, the sampling point of the clock signal is located at the center of the data hold time.

[0042] After entering training mode, the sCMOS detector supports programmable number of iterative training iterations. Through multiple adjustments, the phase of the clock signal and data is realigned, and the phase gradually converges to the optimal phase, ensuring the accuracy and stability of the imaging process.

[0043] The iterative training process in this step is divided into two stages: the sequential bit and word training and correction stage and the channel training and correction stage.

[0044] like Figure 2As shown, during the bit and word training and correction phases, the FPGA imaging board continuously pulls the Train pin of the sCMOS detector high, so that all data channels continuously output standard TP values. This process is to ensure the accuracy and stability of the acquired standard TP values. Figure 2 and Figure 3 In this context, "Train" refers to the input signal of the Train pin.

[0045] like Figure 3 As shown, during the channel training and calibration phase, channel alignment is initiated to ensure that all data channels output data under a single clock signal. Specifically, the FPGA imaging board pulls the Train pin high for one cycle, and all data channels simultaneously output a standard TP value for one cycle at the same position. After these two phases, training is complete.

[0046] Furthermore, during the iterative training process with a programmable number of iterations, if the optimal phase is not converged when the training count reaches the upper limit, the FPGA imaging board stops training and reports an imaging error.

[0047] like Figure 4 As shown, to ensure data accuracy, the clock signal sampling point should ideally be positioned at the center of the data hold period. This is to avoid metastability during sampling. Metastability refers to the uncertainty or instability of the sampling result at critical moments when the sampled signal changes, potentially leading to data errors. By positioning the clock sampling point at the center of the data hold period, data stability can be ensured, avoiding potential risks caused by misalignment between the clock and data signals, thereby improving system reliability and accuracy.

[0048] Cooling of the sCMOS detector or significant changes in ambient temperature can cause a phase shift between the clock and data signals. For example... Figure 5 As shown, when the clock signal (Clk) is offset, the sampling position falls within the data change period in the data acquisition area, leading to uncertainty in data sampling. This misalignment also causes errors in the pixel clock signal (Clk_div), thus affecting the accuracy and stability of the data.

[0049] To ensure accurate data acquisition, the phase between the clock and data signals needs to be retrained and aligned. Recalibrating the phases of the clock and data signals eliminates clock and data offset issues caused by environmental changes, ensuring the stability and consistency of data sampling, and thus improving system reliability.

[0050] like Figure 6As shown in the figure, after automatic training, the acquisition phase of the clock signal (Clk) is aligned with the changes in the data signal (Data), and the sampling point of the clock signal has been precisely adjusted to the center of the data hold time. This adjustment ensures that the data is not affected by clock offset during sampling, avoiding sampling uncertainties that may arise due to the asynchrony between the clock and data signals, and further guaranteeing the accuracy and stability of data acquisition. Through this automatic training method, the phase error between the clock signal and the data signal is effectively eliminated, thereby optimizing the data acquisition process and ensuring the efficient operation of the system.

[0051] Step 5: Check the TP value again after training: After training is completed, exit the training mode, return to step 1, and compare the training mode code again until the sCMOS detector enters the normal imaging state.

[0052] After training is completed, the FPGA imaging board pulls the Train pin high again for several clock cycles and compares the resampled TP value with the standard TP value. If the two match successfully, the FPGA imaging board controls the sCMOS detector to enter the normal imaging state. If they do not match, the FPGA imaging board generates a training enable signal and controls the sCMOS detector to perform a programmable number of iterative training cycles until the sCMOS detector enters the normal imaging state, or if the training cycle reaches the upper limit and the phase has not converged to the optimal phase, the training stops and an imaging error is reported.

[0053] The FPGA imaging board forms a closed-loop control for the entire sCMOS detector process, achieving stable phase alignment through iterative optimization. Optionally, such as Figure 7 As shown, the FPGA imaging board is also connected to the host computer. If the alignment is successful, the normal read-reset cycle is restored, and the host computer displays the image acquired by the calibrated sCMOS detector in real time. If the alignment fails to be achieved after reaching the maximum number of training attempts, the FPGA imaging board outputs an imaging error signal to the host computer, and the host computer displays a hardware device check prompt.

[0054] Furthermore, see still Figure 4The FPGA imaging board internally incorporates a phase shift (TP) detection module and an automatic training module. Centered on an sCMOS detector, it works collaboratively with a differential data connector, the TP detection module within the FPGA imaging board, the automatic training module, and a host computer to achieve precise calibration of the sCMOS detector. First, the raw image acquired by the sCMOS detector is transmitted to the TP detection module within the FPGA imaging board. This module compares the acquired TP value in the signal in real time and determines whether it matches the standard TP value. If a mismatch is detected, indicating a phase shift exceeding a preset threshold, a training enable signal is generated and output to the automatic training module. The automatic training module initiates the training process. This module directly controls the Train pin of the sCMOS detector via a differential data connector, executing a programmable number of iterative training iterations according to the training logic. It realigns the phase of the clock signal and data, gradually converging to the optimal phase. After training, the automatic training module feeds back the training results to the TP value detection module. The TP value detection module re-verifies the TP value: if the TP value matches the standard TP value, the normal read-reset cycle of the sCMOS detector resumes; if it still does not match but the maximum number of training iterations has not been reached, the training is repeated; if the maximum number of training iterations has been reached and alignment is still not achieved, the TP value detection module outputs an imaging error signal to the host computer, which displays a prompt to check the hardware. The FPGA imaging board, as the system control center, is responsible not only for scheduling the interaction between the TP value detection module and the automatic training module, but also for interconnecting image information with the host computer, which displays images with correct TP values ​​in real time.

[0055] This invention, based on the row-exposure mechanism of sCMOS detectors, proposes a scheme for real-time detection and automatic compensation of clock-data phase offset during the reset phase, thereby achieving high-precision, continuous, and manual-intervention-free image acquisition. The main technical effects include the following:

[0056] (1) Strong real-time performance: Training pattern code detection and automatic training can be completed within each line reset phase of the scientific-grade CMOS detector without pausing image acquisition;

[0057] (2) High degree of automation: No need for manual observation and intervention of image errors, reducing deviations and delays caused by human operation;

[0058] (3) Good robustness: It can adapt to a wide range of temperature fluctuations, compensate for clock-data phase shift, and ensure the stability of long-term exposure and continuous observation tasks;

[0059] (4) Strong compatibility: Based on the standard CMOS detector training pin and FPGA imaging board control logic, this invention can be seamlessly integrated into existing imaging boards and cooling platforms.

[0060] In summary, this invention solves the clock-data asynchrony problem caused by temperature drift by using the training mode TP value for real-time phase alignment detection and automatic training compensation during each row reset phase, thus achieving high-precision, high-stability, and fully automated scientific-grade CMOS detector imaging.

[0061] This invention enables fully automatic and real-time compensation for clock-data phase shift caused by temperature drift without interruption during image acquisition. It significantly improves the accuracy, stability, and robustness of scientific-grade CMOS detector image acquisition in dynamic environments, and is particularly suitable for fields with extremely high data quality requirements, such as astronomical observation.

[0062] Meanwhile, this invention has been fully verified on a hardware platform based on the Changguang Chenxin scientific-grade CMOS detector GSENSE6060BSI and Xilinx Kintex-7 (K7) FPGA: the detector is directly connected to the FPGA via an interface, and in a temperature-controlled environment ranging from -40℃ to +60℃, automatic alignment and automatic training logic are used to precisely lock the sampling windows of all data channels at the center of the data hold period, achieving continuous full-resolution (6144×6144) readout for 8 hours without frame loss or anomalies in 14-bit mode. All long-term stability and temperature cycling tests show that the solution is superior to previous manually trained solutions in terms of high resolution, high-speed readout, and environmental adaptability, fully demonstrating the feasibility and reliability of this invention.

[0063] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0064] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A real-time automatic phase calibration method for a scientific-grade CMOS detector, characterized in that, Includes the following steps: Step 1: When each row of the scientific-grade CMOS detector enters the reset phase, pull the Train pin of the scientific-grade CMOS detector high for multiple clock cycles, so that all data channels of the scientific-grade CMOS detector continuously output training mode codes during the reset period. Step 2: Sample the training mode code in real time and compare it with the preset standard training mode code in the scientific-grade CMOS detector. If they match, control the scientific-grade CMOS detector to continue normal imaging; otherwise, proceed to step 3. Step 3: Generate a training enable signal and feed the training enable signal back to the training pin of the scientific-grade CMOS detector; Step 4: In response to the training enable signal, force the scientific-grade CMOS detector to enter the training mode, and control the scientific-grade CMOS detector to perform a programmable number of iterative trainings according to the training logic to realign the phase of the clock signal and the data until convergence to the optimal phase. Under the optimal phase, the sampling point of the clock signal is located at the center of the data hold time. Step 5: After training is complete, exit the training mode, return to step 1, and compare the training mode codes again until the scientific-grade CMOS detector enters the normal imaging state.

2. The real-time automatic phase calibration method for a scientific-grade CMOS detector according to claim 1, characterized in that, In steps 1 and 3, the Train pin is pulled high and the training enable signal is generated by a field-programmable gate array.

3. The real-time automatic phase calibration method for a scientific-grade CMOS detector according to claim 2, characterized in that, The field-programmable gate array is connected to the scientific-grade CMOS detector via a differential data connector, and the training enable signal is fed back to the Train pin via the differential data connector.

4. A real-time automatic phase calibration method for a scientific-grade CMOS detector according to claim 2 or 3, characterized in that, The field-programmable gate array is connected to a host computer, which is used to display the calibrated images acquired by the scientific-grade CMOS detector in real time.

5. The real-time automatic phase calibration method for a scientific-grade CMOS detector according to claim 1, characterized in that, The iterative training process includes sequential bit and word training and correction phases and channel training and correction phases.

6. The real-time automatic phase calibration method for a scientific-grade CMOS detector according to claim 5, characterized in that, The bit and word training and correction phase includes continuously pulling the Train pin high so that all data channels continuously output standard training mode codes; The channel training and correction phase includes raising the Train pin for one cycle, so that all data channels simultaneously output one cycle of standard training mode code at the same position.

7. The real-time automatic phase calibration method for a scientific-grade CMOS detector according to claim 1, characterized in that, Step 4, which involves performing programmable iterations of training, includes: If the training iterations reach the maximum limit and the optimal phase has not yet been reached, training will stop and an imaging error will be reported.

8. The real-time automatic phase calibration method for a scientific-grade CMOS detector according to claim 1, characterized in that, The matching criterion in step 2 is that the phase offset between the real-time sampled training mode code and the standard training mode code is less than a preset threshold.

9. The real-time automatic phase calibration method for a scientific-grade CMOS detector according to claim 1, characterized in that, The standard training mode code is a preset fixed value that is written into the scientific-grade CMOS detector via SPI during the initial configuration of the scientific-grade CMOS detector.

10. The real-time automatic phase calibration method for a scientific-grade CMOS detector according to claim 1, characterized in that, The scientific-grade CMOS detector is cooled by an external cooling system.

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