Novel ultra-high resolution photoetching process-atom guide photoetching method for chip manufacturing

Abstract

The invention relates to a novel ultra-high resolution photoetching process, namely an atom-guided photoetching method, for chip manufacturing. The method comprises the following steps: (A1) constructing a crystal layer with an atomic-scale periodic structure on the surface of a substrate; (A2) the surface of the crystal layer is coated with ink A to form a photoresist layer A, the ink A is a solution containing photoresist A, the photoresist A is a block copolymer, at least one block of the photoresist A is subjected to phase separation in the mode of forming a pattern structure with the sub-nano-scale minimum size, and the photoresist layer A is a solution containing the photoresist A; therefore, an array pattern aligned with the atomic-scale periodic structure is formed; and (A3) selectively etching the block phase of the photoresist A, so that the photoresist A exists in a selected region on the crystal layer and does not exist in other regions on the crystal layer, and the photoresist layer A existing on the crystal layer forms an array structure pattern of which the minimum scale is sub-nano scale.

Description

TECHNICAL FIELD

[0001] The present application relates to a new type of ultra-high resolution photolithography process-atomic directed photolithography method for chip manufacturing, belonging to the field of advanced photolithography method. BACKGROUND

[0002] Advanced photolithography technology is constantly evolving towards shorter wavelengths to achieve higher chip pattern resolution. From the early DUV (deep ultraviolet, 193nm) to the EUV (extreme ultraviolet, 13.5nm) era, mainstream photolithography technology has made a leap from 65nm, 45nm nodes to today's advanced nodes below 7nm. The current EUV photolithography technology represented by ASML, although it successfully breaks through the DUV optical diffraction limit and meets the urgent needs of sub-10nm high-precision patterns for mass production of logic chips, the technology implementation process is extremely complex: because the 13.5nm extreme ultraviolet wavelength is too short and the energy is extremely high, EUV light cannot penetrate traditional lenses and air, and can only be projected through a total reflection optical system in a vacuum environment. Its optical elements use a multilayer mirror structure, which requires the mirror surface to be an atomically smooth surface; the light source uses high-power pulsed laser to hit tin droplets to generate plasma EUV radiation, and the system has hundreds of thousands of parts, with extremely high manufacturing and maintenance costs. In addition, with the demand for further improving the resolution of photolithography, EUV photolithography has exposed increasingly obvious technical bottlenecks in key areas such as high numerical aperture (High-NA) projection optical systems, high-precision mask defect-free manufacturing, material stability and service life of protective films (Pellicle), which restricts the technical expansion of future more advanced process nodes.

[0003] At the same time, the industry has also explored non-traditional photolithography technology routes such as directed self-assembly (DSA) and nanoimprint (NIL) in addition to traditional photolithography routes, trying to supplement or enhance the resolution and cost advantages of EUV photolithography in specific application scenarios. The patterning solution of the International Roadmap for Devices and Systems (IRDS) in 2021 emphasizes the trend of using directed self-assembly (DSA) photolithography and nanoimprint photolithography technology to improve pattern accuracy and reduce process complexity in smaller process nodes in the future.

[0004] DSA technology utilizes block copolymer (BCP) materials to spontaneously form nano-scale pattern structures, which can theoretically achieve resolution beyond the traditional optical diffraction limit, while having the potential advantage of relatively low process cost. However, DSA technology faces several significant defects and technical bottlenecks in practical application. First, its initial process is highly dependent on traditional photolithography technologies such as EUV, DUV, or electron beam lithography (EBL) to pre-prepare a nano-scale guiding template, which significantly increases process complexity, equipment investment cost, and production cycle, regardless of chemical pattern epitaxy or physical pattern epitaxy. In addition, since the self-assembly process of BCP is essentially driven by thermodynamics, there are significant challenges in pattern accuracy and defect control after self-assembly. Specifically, micro-phase separation is non-uniform, domain boundary defects are present, and pattern spacing is difficult to control accurately, which severely restricts the reliability and repeatability of the structure. At the same time, in the process of manufacturing high-density logic chips, the complex and variable pattern layout requires precise alignment of interlayer structures, while the thermodynamic spontaneous behavior of existing DSA technology cannot achieve this precise control, which seriously hinders its large-scale application in actual industrial production.

[0005] Similarly, nanoimprint lithography (NIL) technology theoretically has the advantage of breaking through the optical diffraction limit, but also has significant problems in actual industrialization promotion. NIL technology requires the use of ultra-high precision hard templates for pattern transfer, and the manufacture of such templates usually relies on high-cost and complex technologies such as electron beam direct writing (EBL), resulting in extremely high upfront investment costs. In addition, in the actual imprint process, the template demolding process is prone to defects, such as pattern damage, deformation, and even residual contaminants, which severely affect pattern quality and reusability. At the same time, it is difficult to achieve precise pattern alignment in large areas during the imprinting process, especially when aligning multiple layers of structures, the deviation is easily accumulated, which greatly limits its industrial applicability in the field of precision and high-density chips.

[0006] In summary, whether it is traditional EUV lithography technology or non-traditional lithography technology represented by DSA and NIL, there are many technical bottlenecks and limitations at present, which are difficult to meet the extremely high resolution and accuracy requirements of future chip manufacturing technology at the sub-5nm or even sub-3nm node. Therefore, the industry urgently needs a new lithography paradigm that can fundamentally break through the existing technical bottlenecks.

[0007] Therefore, there is a need in the prior art to provide a lithography technology that breaks through the bottlenecks of the above existing lithography technologies in terms of resolution, alignment accuracy, process complexity, and cost control. SUMMARY

[0008] <Problems to be solved by the invention>

[0009] The present application aims to provide a new type of ultra-high resolution photolithography process for chip manufacturing, i.e., atomic guiding photolithography technology, which can form sub-nanometer stripe array patterning structure based on the "bottom-up" guiding paradigm, reduce the dependence on large photolithography machines and expensive masks compared with existing photolithography technology, and overcome the problem that the resolution is limited by the diffraction limit (the pattern line width can reach below 10 nm, or even below 1 nm), the method can also be implemented in a large area, and the pattern can be adjusted according to the design, which is beneficial to improve the functionalization and integration of materials, and further, the nanometer patterns of each layer can be automatically and accurately aligned when implementing the multi-layer photoresist layer stacking process, without the cumbersome calibration process in traditional multiple photolithography, thereby avoiding the accumulation of interlayer pattern overlay error.

[0010] The present application aims to provide a patterned structure with an array structure pattern having a minimum size of sub-nanometer level, which is easy to obtain and has high quality and high resolution (the pattern line width can reach below 10 nm, or even below 1 nm), and is suitable for constructing advanced process electronic devices, optoelectronic devices, and optoelectromagnetic devices, etc.

[0011] The present application also aims to provide a method for patterning a substrate, which is easy to implement and can be implemented in a large area, which is beneficial to improve the functionalization and integration of materials, and the obtained patterned structure has high quality and high resolution (the pattern line width can reach below 10 nm, or even below 1 nm), and is suitable for constructing advanced process electronic devices, optoelectronic devices, and optoelectromagnetic devices, etc.

[0012] <Solution to the problem>

[0013] In view of the above, the inventors have found that the above objects can be achieved by the following technical solutions.

[0014] [1]. An atomic guiding photolithography method for chip manufacturing, comprising:

[0015] (A1) constructing a crystal layer with an atomic level periodic structure on the surface of a substrate,

[0016] (A2) forming a photoresist layer A on the surface of the crystal layer by coating ink A, the ink A being a solution containing photoresist A, the photoresist A being a block copolymer, and at least one block of the photoresist A being phase separated in a manner to form a pattern structure with a minimum size of sub-nanometer level, thereby forming an array pattern aligned with the atomic level periodic structure,

[0017] (A3) selectively etching the block phase of the photoresist A so that the photoresist A exists on the selected regions of the crystal layer and does not exist on other regions of the crystal layer, and the photoresist layer A existing on the crystal layer forms an array structure pattern with a minimum size of sub-nanometer level.

[0018] [2]. The atomically guided lithography method according to [1], wherein the substrate is a silicon wafer; and / or

[0019] The material forming the crystal layer comprises at least one selected from hafnium oxide (Hf02), zirconium oxide (Zr02), gallium oxide (Ga203), beryllium oxide (BeO), strontium titanate (SrTi03) and aluminum nitride (AIN).

[0020] [3]. The atomically guided lithography method according to [1] or [2], wherein the thickness of the crystal layer is 0.1-10 nm; and / or

[0021] The pattern line width of the photoresist layer A existing on the crystal layer is 10 nm or less; and / or

[0022] The thickness of the photoresist layer A is 1-200 nm.

[0023] [4]. The atomically guided lithography method according to any one of [1]-[3], wherein the phase separation starts before the ink A bottom dries, and an additional time of 5 minutes-10 hours is allowed for standing after coating to complete the phase separation.

[0024] [5]. The atomically guided lithography method according to any one of [1]-[4], wherein the photoresist layer A is only one layer; or,

[0025] The photoresist layer A is multiple layers, and each layer of the multiple layers of the photoresist layer A is formed by the same way as steps (A2) and (A3) respectively.

[0026] [6]. The atomically guided lithography method according to any one of [1]-[5], further comprising:

[0027] (A4) forming a functional layer on the etched photoresist layer A in contact with the layer,

[0028] (A5) forming a photoresist layer B on the functional layer by coating an ink B, the ink B being a solution containing a photoresist B, the photoresist B being a block copolymer, and at least one block of the photoresist B is phase separated in a self-aligned manner with the array structure pattern of the photoresist A,

[0029] (A6) selectively etching the segments of the photoresist B, so that the remaining photoresist layer B forms an array structure pattern with a minimum size of sub-nanometer level, which is aligned with the stripe pattern of the photoresist layer A.

[0030] [7]. The atomically guided lithography method according to [6], wherein the photoresist A and the photoresist B are the same or different.

[0031] [8]. The atomically guided lithography method according to [6] or [7], wherein the material forming the functional layer is selected from two-dimensional materials.

[0032] [9]. A patterned structure with an array structure pattern with a minimum size of sub-nanometer level, which is obtained by the atomically guided lithography method according to any one of [1] to [8].

[0033]

[10] . A method for patterning a substrate, which comprises:

[0034] (B1) etching or electron injection to the patterned structure according to [9] from the side of the substrate where the photoresist layer A is present, so that the crystal layer is present in selected regions on the substrate and absent in other regions on the substrate, and the crystal layer present on the substrate forms an array structure pattern with a minimum size of sub-nanometer level,

[0035] (B2) etching or electron injection to the substrate exposed from the side of the crystal layer, so that the surface of the substrate forms an array structure pattern with a minimum size of sub-nanometer level.

[0036] <Effects of the Invention>

[0037] Through the above technical solutions, the present application achieves the following technical effects:

[0038] In the present application, a thermodynamically stable periodic coupling potential field can be formed by precisely constructing a pre-set atomic-level periodic structure at the substrate interface according to the required patterning design (for example, based on wafer-level atomic coupling interface patterning design). This potential field can induce the micro-phase separation and directional arrangement of the polymer photoresist (a typical representative is block copolymer) coated thereon, and form a nanostructure according to the designed periodic pattern. The cross-scale coupling between atoms and molecules / polymers and the van der Waals force between interfaces drive pattern replication, and the polymer chain segments are precisely pulled by the atomic potential field of the crystal layer during the phase separation process, thereby realizing high-fidelity transfer of the atomic pattern of the crystal layer to the polymer pattern. Therefore, the present application can achieve a pattern transfer precision with a minimum size of sub-nanometer level, which far exceeds the alignment and resolution capability of traditional photolithography process.

[0039] Based on the above-mentioned atom-leading technology from bottom to top, the pattern replication precision (the resolution can reach below 10 nm, even below 8 nm, and even the limit resolution of less than 1 nm of a single process linewidth) is realized, and the complexity and high cost of the traditional template preparation are completely avoided.

[0040] Further, through the bottom atomic-level pattern induction, even if the photoresist layer is composed of multiple layers formed by respective layers, the self-alignment between the multiple-layer photoresist structures can be realized.

[0041] On the basis of the above, through the bottom atomic-level pattern induction and the synergistic coupling potential field regulation of the upper and lower interfaces, the sub-nanometer self-alignment between the multiple-layer photoresist structures can be realized. Specifically, at the bottom of the photoresist layer, as described above, a precise guide template is provided by the substrate atomic pattern; at the same time, a functional layer is introduced at the top interface of the single-layer or multi-layer photoresist, forming a synergistic potential field environment with the bottom crystal layer template. The joint action of the upper and lower interfaces enables the nanometer patterns formed by the self-assembly of each layer to be automatically and accurately aligned (even achieving an interlayer alignment error of less than 1 nm) when the multiple-layer photoresist is stacked, without the cumbersome calibration process in traditional multiple lithography, thereby avoiding the accumulation of interlayer pattern overlay errors.

[0042] In summary, the atom-leading lithography (ALL) of the present application constructs an atomic-level pattern transfer approach without a mask and a complex optical projection system, which can realize sub-nanometer high-precision pattern construction while significantly reducing the complexity and cost of the manufacturing process, thereby providing a new type of ultra-high resolution lithography process. Compared with existing lithography techniques, the atom-leading lithography of the present application has made a breakthrough in resolution and further in self-alignment, and has taken into account the practicality and cost-effectiveness of the process.

[0043] Therefore, the patterning method of the substrate of the present application is based on the above-mentioned atom-leading lithography technology, does not need to rely on traditional optical imaging systems or complex template processes, can solve the resolution limitation and process complexity problems in the prior art, saves the process and reduces the cost, and can significantly improve the performance density and integration of the chip, has important industrial strategic significance for continuing Moore's law, and brings a revolutionary breakthrough to chip manufacturing. BRIEF DESCRIPTION OF DRAWINGS

[0044] Figure 1 A schematic diagram showing the process flow of the atom-leading technology (ALL) involved in the atom-leading lithography method of the present application.

[0045] Figure 2 A photo of the nanometer directional patterned microstructure array of PS-b-PDMS on the crystal layer of Example 1.

[0046] Figure 3 A photograph of a nano-patterned microstructure array of a bilayer PS-b-P2VP on a crystal layer for Example 2.

[0047] Figure 4 A transfer characteristic curve (left) and an output characteristic curve (right) of a field effect transistor constructed based on the nano-patterned structure prepared in Example 1 are shown.

[0048] Figure 5 An electrical performance curve of an optoelectronic device constructed using the patterned structure prepared in Example 1 is shown.

[0049] Figure 6 A conductive property curve of the patterned laminate prepared in Example 2 obtained by using a semiconductor parameter analysis tester is shown. DETAILED DESCRIPTION

[0050] Various exemplary embodiments, features, and aspects of the present application will be described in detail below. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations.

[0051] In addition, for the purpose of convenience and brevity, specific details of implementations are set forth in the description below. It should be appreciated that the present application can be practiced in the absence of some of these specific details. In other instances, well-known methods, structures and techniques have not been described in detail in order to avoid obscuring the present application.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the application pertains. It will be further understood that the boundaries of the application are not limited to the specific embodiments described herein. Accordingly, although specific embodiments have been described herein, these are not intended to limit the scope of the present application, as described. Numbers, ranges, and values appearing herein should be read as if prefaced by "about" or "approximately," even if the term does not expressly appear. The numerical values, ranges and values should be understood to encompass numbers that are the same as well as numbers that vary by a small amount due to system variability and measurement methodology.

[0053] In this specification, the meaning of "can" includes both the meaning of performing a certain process and the meaning of not performing a certain process.

[0054] In this specification, "some specific / preferred embodiments," "other specific / preferred embodiments," "embodiments," and the like mean that a certain feature, structure, property, and / or characteristic described is included in at least one embodiment of the present application and can exist in other embodiments or can not exist in other embodiments. In addition, it should be understood that the described elements can be combined in a variety of ways without departing from the scope of the present application.

[0055] In the present specification, a numerical range indicated using "numerical value A to numerical value B" means a range including the end point numerical values A and B. In the present specification, a numerical range indicated using "and above" and "and below" means a range including the end point numerical value. In the present specification, a numerical range indicated using "greater than" and "less than" means a range not including the end point numerical value.

[0056] In the present specification, "optional" or "optionally" means that the event or circumstance described next can or can not occur, and the description includes the case where the event occurs and the case where the event does not occur.

[0057] <Atomic directed lithography technique for chip manufacturing>

[0058] The atomic directed lithography method of the present application includes: (A1) constructing a crystal layer having an atomic periodic structure on a surface of a substrate; (A2) forming a photoresist layer A on a surface of the crystal layer by coating an ink A, the ink A being a solution containing a photoresist A, the photoresist A being a block copolymer, and at least one block of the photoresist A being phase separated in a manner to form a pattern of a minimum dimension of a sub-nanometer order, thereby forming an array pattern aligned with the atomic periodic structure; (A3) selectively etching the block phase of the photoresist A, the photoresist A being present in selected regions on the crystal layer and absent in other regions on the crystal layer, and the photoresist layer A present on the crystal layer forming an array structure pattern of a minimum dimension of a sub-nanometer order.

[0059] In the present application, the term "sub-nanometer order" means a size range of less than 1 nm, which can be approximately between 0.1 nm or more and less than 1 nm.

[0060] Hereinafter, each step will be described in detail. It is to be understood that in the present application, the numerals of the steps (for example, (A1) to (A7), (B1), (B2), and the like) are merely used for the convenience of labeling the steps, and do not mean that the steps are performed in the order of the numerals. In addition, each step can be performed independently of each other, or a part or all of the steps can be performed continuously. In the case of performing a plurality of steps continuously, the next step can be performed after one step is completed, or two steps can be performed simultaneously or partially simultaneously.

[0061] (Step (A1))

[0062] In step (A1), a crystal layer having an atomic periodic structure is constructed on a surface of a substrate.

[0063] In the present application, the composition of the substrate is not particularly limited, and synthetic resins such as polyethylene terephthalate, polyethylene naphthalate, polyethylene, polycarbonate, cellulose triacetate, cellophane, polyimide, polyamide, polyphenylene sulfide, polystyrene sulfonate (PSS), polyetherimide, polyether sulfone, aromatic polyamide, polymethyl methacrylate (PMMA), perfluoro(l-butene vinyl ether) polymer (CYTOP), benzocyclobutene polymer (BCB), or polysulfone, semiconductor substrates such as pure silicon wafers, doped silicon wafers (e.g., heavily doped silicon wafers, oxidized doped silicon wafers), wiring substrates, glass, metals such as copper, titanium, or aluminum, ceramic materials such as aluminum oxide, hafnium oxide, silicon nitride, and the like can be widely used. These substrates can be modified or treated as needed (e.g., oxygen plasma treatment, etc.).

[0064] In some preferred embodiments, the substrate is a silicon wafer.

[0065] In addition, the form of the substrate is also not particularly limited, and can be any object on which a patterned film is desired to be formed and can have any shape.

[0066] In the present application, the material forming the crystal layer is not particularly limited, as long as it can induce the photoresist to undergo phase separation. For example, two-dimensional materials such as molybdenum disulfide (MoS2), graphene, hexagonal boron nitride (h-BN), tungsten disulfide (WS2), rhenium disulfide (ReS2), tungsten diselenide (WSe2), tin selenide (SnSe), bismuth selenide (Bi2O2Se), copper indium phosphorus hexasulfide (CuInP2S6), black phosphorus (BP), and the like, as well as hafnium oxide (HfO2), zirconium oxide (ZrO2), gallium oxide (Ga2O3), beryllium oxide (BeO), strontium titanate (SrTiO3), aluminum nitride (AIN), silicon germanium (SiGe) alloys and heterostructures, gallium arsenide (GaAs) and other III-V materials (such as InP, InAs, GaSb, etc.), silicon carbide (SiC), barium titanate (BaTiO3), lead zirconate titanate (PZT), magnetic oxides (such as magnetite Fe3O4, ferrite, etc.), topological insulators (such as Bi2Se3, Bi2Te3, etc.), and the like can be used.

[0067] In the present application, the crystal layer can be a layer of uniform material, or a layer made of different materials at different positions, according to the desired pattern.

[0068] In addition, in the present application, the surface of the crystal layer can be treated as needed, for example, plasma hydrophilization modification, doping modification, or hydrophilic / hydrophobic monolayer modification, etc.

[0069] In some preferred embodiments, the material forming the crystal layer includes at least one selected from hafnium oxide (Hf02), zirconium oxide (Zr02), gallium oxide (Ga203), beryllium oxide (BeO), strontium titanate (SrTi03), and aluminum nitride (AIN).

[0070] In some preferred embodiments, the thickness of the crystal layer is preferably 0.1 to 10 nm, more preferably 0.2 to 3 nm.

[0071] The method for constructing the crystal layer is not particularly limited, and those known in the art can be used, for example, ALD deposition can be used.

[0072] The atomic-scale periodic structure formed by the material of the crystal layer is not particularly limited, and can be appropriately adjusted as needed. The atomic-scale periodic structure can form a stripe array structure, or a cylindrical array structure.

[0073] The atomic-scale periodic structure plays a guiding role in the phase separation of the photoresist described later, and further affects the shape, line width, etc. of the resulting pattern.

[0074] In addition, for example, the amplitude and / or frequency of the periodic variation of the atomic crystal can be adjusted, specifically, as shown in Figure 1 .

[0075] (Step (A2))

[0076] In step (A2), a photoresist layer A is formed on the surface of the crystal layer by coating an ink A, the ink A being a solution containing a photoresist A, the photoresist A being a block copolymer, and at least one block of the photoresist A is phase separated to form a pattern structure with a minimum scale of sub-nanometer, thereby self-forming an array pattern aligned with the atomic-scale periodic structure.

[0077] By phase separation, the photoresist layer forms a molecular chain aggregation structure that separates at least one block phase. Accordingly, the atomic-scale structure pattern of the crystal layer is transferred to the pattern of the photoresist layer.

[0078] In the present application, the type and structure of the photoresist A are not particularly limited, as long as it can achieve phase separation.

[0079] The photoresist A can be any copolymer of two or more monomers known in the art, and from the viewpoint of more easily achieving the effects of the present application, it is preferably a binary copolymer.

[0080] The photoresist A can have two or more blocks, and from the viewpoint of more easily achieving the effects of the present application, it is preferably has two blocks, i.e., a first block and a second block.

[0081] Each of the blocks of the photoresist A can be formed from one or more kinds of monomers, and from the viewpoint of more easily achieving the effects of the present application, it is preferable that each of the blocks be formed from a single kind of monomer.

[0082] In addition, the number of blocks of the photoresist can be two or more, and from the viewpoint of more easily achieving the effects of the present application, it is preferable that the number of blocks be two to five, and more preferably two to three.

[0083] Examples of photoresist A include, without limitation, polystyrene-b- polymethyl methacrylate (PS-b-PMMA), polystyrene-b-polyisoprene (PS-b-PI), polystyrene-b-poly-lactic acid (PS-b-PLA), polystyrene-b-polydimethylsiloxane (PS-b-PDMS), polystyrene-b-polytrimethylene carbonate (PS-b-PTMC), polystyrene-b-poly(2-vinylpyridine) (PS-b-P2VP), poly(2-vinylpyridine)-b-polystyrene-b-poly(2-vinylpyridine) (P2VP-b-PS-b-P2VP), polystyrene-b-polypropylene carbonate (polystyrene-b-polypropylene carbonate), poly(4-tert-butylstyrene)-b-poly(methyl methacrylate) (PtBS-b-PMMA), poly(4-methoxystyrene)-b-poly(4-trimethylsilylstyrene) (PMOST-b-PTMSS), polystyrene-b-polypropylene acetonide acrylate (PS-b-PSA), polystyrene-b-poly-lactic-glycolic acid (PS-b-PLGA), polystyrene-b-poly(methyl acrylate) (PS-b-PMA), polystyrene-b-poly(methyl propylene acetonide acrylate) (PS-b-PSM), polystyrene-b-poly(4-hydroxystyrene) (PS-b-PHS), polystyrene-b-poly(4-vinylpyridine) (PS-b-P4VP), polystyrene-b-poly(2,2,2-trifluoroethyl acrylate) (PS-b-PTFEA), poly(4-tert-butylstyrene)-b-poly(2-vinylpyridine) (PtBS-b-P2VP), polyvinylcyclohexane-b-poly(methyl methacrylate) (PCHE-b-PMMA), polydimethylsiloxane-b-poly(methyl methacrylate) (PDMS-b-PMMA), polystyrene-b-poly(pentadecafluorooctyl methacrylate) (PS-b-PPDFMA), poly(2-vinylpyridine)-b-poly(heptafluorobutyl-2-methylprop-2-enoate) (P2VP-b-PHFBMA), poly(3-hydroxystyrene)-b-polydimethylsiloxane (P3HS-b-PDMS), polystyrene-b-polyglycerol acrylate (PS-b-PGA), polystyrene-b-polyhydroxyisobutylene (PS-b-PiBOH), polystyrene-b-poly(acrylic acid) (PS-b-PAA), polystyrene-b-poly(3,4-dihydroxystyrene) (PS-b-PDHS), poly(4-trimethylsilylstyrene)-b-poly-lactic acid (PTMSS-b-PLA), polystyrene-b-poly(2,3-dihydroxypropyl isobutylene acrylate) (PS-b-PGM), and the like.

[0084] In some preferred embodiments, from the viewpoint of more easily achieving phase separation and more favoring the etching described later, the photoresist A preferably has a styrene-based monomer polymer block, more preferably at least one selected from the group consisting of PS-b-PMMA, PS-b-PDMS, PS-b-P2VP, and P2VP-b-PS-b-P2VP.

[0085] In the present application, the solvent in the ink A is not particularly limited as long as it can dissolve the photoresist A. In some preferred embodiments, the solvent is at least one selected from the group consisting of an ether-based solvent, an alcohol-based solvent, a substituted or unsubstituted alkane-based solvent, a substituted or unsubstituted arene-based solvent, an organic acid alkyl ester-based solvent, a ketone-based solvent, an amide-based solvent, an aldehyde-based solvent.

[0086] Examples of the ether-based solvent include, but are not limited to, tetrahydrofuran, diethyl ether, anisole, and the like.

[0087] Examples of the alcohol-based solvent include, but are not limited to, monohydric alcohols such as ethanol, isopropanol, n-butanol, n-pentanol, cyclopentanol, n-hexanol, cyclohexanol, n-heptanol, and the like; and dihydric alcohols such as ethylene glycol and the like.

[0088] Examples of the substituted or unsubstituted alkane-based solvent include, but are not limited to, unsubstituted alkane-based solvents such as pentane, n-hexane, cyclohexane, n-heptane, cycloheptane, undecane, dodecane, tridecane, tetradecane, pentadecane, hexadecane, octadecane, petroleum ether, and the like; and halogenated alkane-based solvents such as monochloromethane, dichloromethane, trichloromethane, monochloroethane, dichloroethane, and the like.

[0089] Examples of the substituted or unsubstituted arene-based solvent include, but are not limited to, unsubstituted arene-based solvents such as benzene, toluene, xylene, mesitylene, phenylcyclohexane, tetralin, and the like; and halogenated arene-based solvents such as chlorobenzene, dichlorobenzene, bromobenzene, and the like.

[0090] Examples of the organic acid alkyl ester-based solvent include, but are not limited to, ethyl acetate, butyl acetate, dimethyl carbonate, isoamyl acetate, ethyl propionate, ethyl butyrate, and the like.

[0091] Examples of the ketone-based solvent include, but are not limited to, acetone, butanone, cyclohexanone, and the like.

[0092] Examples of the amide-based solvent include, but are not limited to, methylformamide, N,N-dimethylacetamide, N,N-dimethylformamide, and the like.

[0093] Examples of the aldehyde-based solvent include, but are not limited to, n-butyraldehyde, anisaldehyde, and the like.

[0094] In some preferred embodiments, the solvent is at least one selected from the group consisting of tetrahydrofuran, anisole, isopropyl alcohol, ethylene glycol, n-hexane, cyclohexane, heptane, dodecane, tetradecane, hexadecane, petroleum ether, chloroform, benzene, toluene, xylene, mesitylene, phenylcyclohexane, tetralin, chlorobenzene, dichlorobenzene, butyl acetate, cyclohexanone, N,N-dimethylacetamide, N,N-dimethylformamide, and anisaldehyde.

[0095] Further, in some specific embodiments, the concentration of the photoresist in the ink A can be, for example, 0.5 mg / mL to 210 mg / mL, for example, 0.5 mg / mL, 1 mg / mL, 1.5 mg / mL, 5 mg / mL, 10 mg / mL, 20 mg / mL, 30 mg / mL, 50 mg / mL, 100 mg / mL, and the like (any range with any two of these point values as end values can be used, for example, 0.5 to 5 mg / mL or 1 to 5 mg / mL, and the like).

[0096] The coating method for the ink A is not particularly limited, and those generally known in the art can be used, for example, brush coating, spray coating, dip coating, spin coating, flow coating, curtain coating, extrusion coating, and the like. In some particularly preferred embodiments, spin coating is preferably used.

[0097] In some specific embodiments, after the ink A is coated, an independent drying step can be performed on the resulting ink coating film to form the photoresist layer. In the present application, the drying method is not particularly limited, and those generally known in the art can be used, for example, natural drying, air blowing drying, heating drying, oven drying, and the like.

[0098] In other specific embodiments, drying is started during the coating of the ink A to form the photoresist layer A.

[0099] In the present application, the conditions for forming the photoresist layer A by coating the ink are not particularly limited.

[0100] In some specific embodiments, the coating of the ink is preferably performed in a temperature range of 0°C to 400°C, more preferably in a temperature range of 100°C to 300°C, in a temperature range of 180°C to 280°C, and particularly preferably in a temperature range of 205°C to 240°C, from the viewpoint of making the phase separation of the photoresist more accurate.

[0101] In other specific embodiments, step (A2) can be performed in either an atmospheric environment or a gas atmosphere, and is preferably performed in an atmospheric environment from the viewpoint of reducing costs. The gas atmosphere is at least one selected from the group consisting of an inert gas atmosphere and other solvent gas atmosphere.

[0102] In the present application, the condition for phase separation of the photoresist A is not particularly limited.

[0103] In some specific embodiments, the phase separation is preferably performed at a temperature ranging from 0°C to 400°C, more preferably at a temperature ranging from 100°C to 300°C, at a temperature ranging from 180°C to 280°C, and particularly preferably at a temperature ranging from 205°C to 240°C from the viewpoint of more accurately performing the phase separation of the photoresist. In addition, in some preferred embodiments, the temperature at which the photoresist is subjected to the phase separation is preferably equal to or lower than the temperature at which the ink is applied from the viewpoint of more favorably performing the phase separation, for example, the photoresist is subjected to the phase separation under annealing conditions.

[0104] In other specific embodiments, the phase separation can be performed in an atmospheric environment or a gas atmosphere, and is preferably performed in an atmospheric environment from the viewpoint of reducing the cost. The gas atmosphere is at least one selected from the group consisting of an inert gas atmosphere and a solvent gas atmosphere.

[0105] In the present application, the timing at which the phase separation occurs is not particularly limited, and the phase separation can be started before the ink film is completely dried or after the ink film is completely dried. Preferably, the phase separation is started before the ink film is completely dried.

[0106] In addition, in some preferred embodiments, an additional time is left after the application is completed for the photoresist to sufficiently and favorably perform the phase separation. The length of the additional time is not particularly limited, and can be, for example, 1 minute to 15 days, and is preferably 5 minutes to 10 hours, for example, 6 minutes, 10 minutes, 15 minutes, 20 minutes, 30 minutes, 35 minutes, 40 minutes, 45 minutes, 50 minutes, 55 minutes, 1 hour, 1.2 hours, 1.5 hours, 1.8 hours, 2 hours, 2.5 hours, 3 hours, 4 hours, 5 hours, 6 hours, 7 hours, 8 hours, 9 hours, and the like, and more preferably 1.5 hours to 10 hours, and further preferably 1.8 hours to 6 hours, from the viewpoint of more accurately performing the phase separation of the photoresist while taking into account a relatively short operation time.

[0107] In some more preferred embodiments, after the application of the ink A is completed, the phase separation of at least one block of the photoresist A is started under annealing conditions before the solvent is completely volatilized, and an array pattern is formed in a self-aligned manner in accordance with the atomic-level periodic structure of the crystal layer, with the minimum size of the pattern structure being sub-nanometer.

[0108] In some preferred embodiments, in the case where the photoresist A has two blocks (a first block and a second block), the photoresist A is phase-separated into a block phase a and a block phase b.

[0109] In addition, the thickness of the photoresist layer A is preferably 1 to 200 nm from the viewpoint of facilitating more accurate phase separation. Generally, the thickness range is the total thickness of the photoresist layer A.

[0110] (Step (A3))

[0111] In step (A3), at least one block phase of the photoresist A is selectively etched, the photoresist A is present in the selected area on the crystal layer and absent in the other area on the crystal layer, and the photoresist layer A present on the crystal layer forms an array structure pattern with a minimum size of sub-nanometer level.

[0112] In the present application, the etching method is not particularly limited, for example, step (A3) is performed by dry etching or wet etching. In the present application, dry etching and wet etching can each be performed by a method known in the art.

[0113] In some preferred embodiments, step (A3) is performed by dry etching. In the present application, the etching conditions are not particularly limited and can be changed depending on the process requirements, etching selectivity, and etching rate. In some preferred examples, examples of etching gas include, but are not limited to, Cl2+O2, HBr+Cl2, SF6, CF4+O2, CHF3+O2, BCl3.

[0114] In addition, the line width of the photoresist layer A present on the crystal layer (i.e., the width of the photoresist line remaining on the crystal layer after etching) is preferably 10 nm or less, for example, 9 nm or less, 8 nm or less, 5 nm or less, 3 nm or less, or even 1 nm or less.

[0115] In the present application, the photoresist A remaining on the crystal layer after etching can be used as a mask, and a film can be formed in accordance with the pattern shown by the mask, and etching is performed on the crystal layer and the substrate, thereby obtaining a patterned substrate.

[0116] In some specific embodiments, the photoresist layer A is only one layer, i.e., only one time of the operation of step (A2) and step (A3) is performed. Specifically, in the coating step (the same operation as step (A2)), the ink A is coated in direct contact with the surface of the crystal layer, so that the photoresist layer A formed as only one layer is in direct contact with the surface of the crystal layer.

[0117] In other specific embodiments, the photoresist layer A is a multilayer, and each layer of the photoresist layer A in the multilayer is formed by the same manner as step (A2) and step (A3).

[0118] In some preferred embodiments, the number of layers of the multilayered photoresist layer A is preferably 2 to 4 layers, more preferably 2 or 3 layers, and further preferably 2 layers.

[0119] It is understood that in the formation of each layer of the photoresist layer A, after the etching of the previous layer is completed, the coating of the ink of the next layer is performed. Taking the two-layered photoresist layer A (photoresist layer A-1 and photoresist layer A-2) as an example, the ink A-1 is coated in direct contact with the surface of the crystal layer to form the photoresist layer A-1, the photoresist A-1 is phase separated to form an array pattern self-aligned, and a certain segment of the photoresist A-1 is etched to form an array structure pattern; then the ink A-2 is coated on the surface of the photoresist layer A-1 present on the crystal layer to form the photoresist layer A-2, the photoresist A-2 is phase separated to form an array pattern self-aligned, and a certain segment of the photoresist A-2 is etched to form an array structure pattern.

[0120] In addition, in the formation of the multilayered photoresist layer A, the photoresists used to form each layer can be the same or different, and preferably the same photoresist is used.

[0121] When the photoresist layer A is multilayered, the patterns between each layer of the photoresist layer A (e.g., the photoresist layer A-1 and the photoresist layer A-2) are aligned, i.e., substantially consistent. Preferably, the resolution error of the patterns of each layer of the photoresist layer A (e.g., the pattern of the photoresist layer A-1 and the pattern of the photoresist layer A-2) can be less than 3 nm, for example, 2 nm or less, and even less than 1 nm.

[0122] In addition, the atomically directed photolithography method of the present application can further include the following steps (A4) to (A6). The use of the upper and lower interfaces in this process allows the nanometer patterns formed by the self-assembly of each layer to be automatically and accurately aligned (even achieving an interlayer alignment error of less than 1 nm) when the multilayered photoresist is stacked.

[0123] In the case of including the following steps (A4) to (A6), it is preferred that the photoresist layer A is a structure of only one layer.

[0124] In the case of not including the following steps (A4) to (A6), it is preferred that the photoresist layer A is a structure of 2 or 3 layers.

[0125] (Step (A4))

[0126] In step (A4), a functional layer is formed on the etched photoresist layer A in contact with the layer.

[0127] The thickness of the functional layer is not particularly limited and can generally be 0.5 to 20 nm, for example, 1 to 10 nm, 2 nm, 3 nm, 5 nm, 7 nm, etc.

[0128] The material forming the functional layer can also be an atomic crystal, such as those compounds listed with respect to the crystal layer. In some preferred embodiments, the material forming the functional layer is selected from two-dimensional materials. Examples of two-dimensional materials are those listed above, which are not repeated here.

[0129] There is no particular limitation to the method of forming the functional layer, and those known in the art can be employed, such as ALD deposition.

[0130] (Step (A5))

[0131] A photoresist layer B is formed on the functional layer by coating an ink B, the ink B being a solution comprising a photoresist B, the photoresist B being a block copolymer, and at least one block of the photoresist B is phase separated in a self-aligned manner with the stripe pattern of the photoresist A.

[0132] Details of the photoresist B and the ink B, the manner and conditions of coating the ink B, details of phase separation of the photoresist B, etc. are the same as those of the photoresist A and the ink A described above, the manner and conditions of coating the ink A, details of phase separation of the photoresist A, etc. which are not repeated here.

[0133] With respect to phase separation, the above-mentioned functional layer and the crystal layer form a synergistic potential field environment, which collectively guides the phase separation of the photoresist B and aligns with the pattern of the photoresist A in a self-aligned manner.

[0134] The photoresist B can be the same as or different from the photoresist A, and the composition (such as solvent, etc.) and concentration, etc. of the ink A and the ink B can also be the same or different.

[0135] In some preferred embodiments, the photoresist A and the photoresist B are the same.

[0136] In other preferred embodiments, the ink A and the ink B are the same.

[0137] In addition, from the point of view of facilitating more accurate phase separation, the thickness of the photoresist layer B is 1-200 nm. Generally, this thickness range is the total thickness of the photoresist layer B.

[0138] (Step (A6))

[0139] In step (A6), any block phase of the photoresist B is selectively etched, leaving the remaining photoresist layer B to form an array structure pattern with a minimum scale of sub-nanometer aligned with the stripe pattern of the photoresist layer A.

[0140] Details of the etching process of the photoresist B are the same as those of the etching process of the photoresist A described above, which are not repeated here.

[0141] In the present application, the pattern of the photoresist layer B is aligned with the pattern of the photoresist layer A, i.e. substantially consistent. Preferably, the resolution error of the pattern of the photoresist layer B and the pattern of the photoresist layer A can be less than 3 nm, for example, 2 nm or less, and even can reach 1 nm or less.

[0142] In some specific embodiments, the photoresist layer B is only one layer. Specifically, the ink B is coated in direct contact with the surface of the functional layer, so that the photoresist layer B formed is only one layer and is in direct contact with the surface of the functional layer.

[0143] In other specific embodiments, the photoresist layer B is a multi-layer, which is formed in the same way as the multi-layer photoresist layer A.

[0144] In some preferred embodiments, the number of layers of the multi-layer photoresist layer B is preferably 2-4 layers, more preferably 2 layers or 3 layers, and further preferably 2 layers.

[0145] It can be understood that in the formation of the multi-layer photoresist layer B, after the etching of the previous layer is completed, the coating of the ink of the next layer is carried out. Taking the two-layer photoresist layer B (photoresist layer B-1 and photoresist layer B-2) as an example, the ink B-1 is coated in direct contact with the surface of the functional layer to form the photoresist layer B-1, the photoresist B-1 is separated to form an array pattern in self-alignment, and a certain segment of the photoresist B-1 is etched to form an array structure pattern; then the ink B-2 is coated on the surface of the photoresist layer B-1 existing on the crystal layer to form the photoresist layer B-2, the photoresist B-2 is separated to form an array pattern in self-alignment, and a certain segment of the photoresist B-2 is etched to form an array structure pattern.

[0146] In addition, in the formation of the multi-layer photoresist layer B, the photoresists used to form each layer can be the same or different, and preferably the same photoresist is used.

[0147] When the photoresist layer B is a multi-layer, the patterns between the layers of the photoresist layer B (for example, the photoresist layer B-1 and the photoresist layer B-2) are aligned, i.e. substantially consistent. Preferably, the resolution error of the pattern of the photoresist layer B (for example, the pattern of the photoresist layer B-1 and the pattern of the photoresist layer B-2) can be less than 3 nm, for example, 2 nm or less, and even can reach 1 nm or less.

[0148] In some particularly preferred embodiments, the photoresist layer B is particularly preferably only one layer.

[0149] (Other steps)

[0150] The production method of the sub-nanometer scale stripe array patterned structure of the present application can include various other steps known in the art as needed. The other steps include a step of treating the surface of the crystal layer, a step of washing and drying the surface of the etched photoresist A and B, and the like.

[0151] <Patterned structure having array pattern with minimum size of sub-nanometer scale>

[0152] The patterned structure having array pattern with minimum size of sub-nanometer scale of the present application is obtained by the above-mentioned atomic directed lithography technique of the present application.

[0153] In some specific embodiments, the patterned structure sequentially includes a substrate, a crystal layer, and a photoresist layer A disposed directly on the crystal layer, the photoresist layer A being present in selected areas on the crystal layer and absent in other areas on the crystal layer, and the photoresist layer present on the crystal layer forming an array pattern with minimum size of sub-nanometer scale.

[0154] The photoresist layer A can be only one layer or multiple layers.

[0155] In the case where the photoresist layer A is multiple layers, the patterned structure of the present application includes a substrate, a crystal layer, and a photoresist layer A disposed directly on the crystal layer, the photoresist layer A sequentially including two or more photoresist layers from the crystal layer side, such as a photoresist layer A-1 and a photoresist layer A-2, the photoresist layer A being present in selected areas on the crystal layer and absent in other areas on the crystal layer, and the photoresist layer present on the crystal layer forming an array pattern with minimum size of sub-nanometer scale.

[0156] In other specific embodiments, the patterned structure sequentially includes a substrate, a crystal layer, a photoresist layer A (preferably only one layer) disposed directly on the crystal layer, a functional layer, a photoresist layer B disposed directly on the functional layer, the photoresist layer A being present in selected areas on the crystal layer and absent in other areas on the crystal layer, and the photoresist layer present on the crystal layer forming an array pattern with minimum size of sub-nanometer scale, the photoresist layer B having a through array pattern aligned with the array pattern of the photoresist layer A (i.e., the photoresist layer B being present in selected areas on the functional layer and absent in other areas on the functional layer, and the photoresist layer B having an array pattern with minimum size of sub-nanometer scale aligned with the array pattern of the photoresist layer A).

[0157] In addition, the line width of the photoresist layer (i.e. the photoresist left after etching) (layer A only, or layers A and B) is preferably 10 nm or less, for example, 8 nm or less, 5 nm or less, 3 nm or less, or even 1 nm or less.

[0158] <Method for patterning a substrate>

[0159] The method for patterning a substrate of the present application comprises: (B1) etching or electron injection from the side of the substrate where the photoresist layer A is present, to the above-mentioned patterned structure having an array structure pattern with a minimum size of sub-nanometer level of the present application, so that the crystal layer is present in selected areas on the substrate and absent in other areas on the substrate (when a functional layer is present, the functional layer forms a through structure accordingly), and the crystal layer present on the substrate forms an array structure pattern with a minimum size of sub-nanometer level (the substrate can be observed from the side of the crystal layer); (B2) etching or electron injection to the substrate exposed from the side of the crystal layer, so that the surface of the substrate forms an array structure pattern with a minimum size of sub-nanometer level.

[0160] Accordingly, a patterned structure is formed on the surface of the substrate of the present application.

[0161] In the present application, the etching method and ion injection method are not particularly limited, and various methods known in the art can be used.

[0162] In some specific embodiments, a dry etching method is preferably used. In the present application, the etching conditions are not particularly limited and can be changed according to the process requirements, etching selectivity and etching rate. In some preferred embodiments, examples of etching gas include, but are not limited to, Cl2+O2, HBr+Cl2, SF6, CF4+O2, CHF3+O2, BCl3.

[0163] <Use>

[0164] The above-mentioned patterned substrate of the present application can be used to prepare advanced process electronic, optoelectronic and opto-electromagnetic devices.

[0165] The electronic, optoelectronic and opto-electromagnetic devices can be one of a transistor, a memory, a light-emitting diode, a solar cell, an electronic spin device, an AI chip, and a photodetector, or an integration of several of them.

[0166] The patterned microstructure contained in the patterned substrate of the present application has a precision of sub-nanometer level and a highly ordered structure arrangement. The short channel transistor built from these large-area arrayed, multi-dimensional sub-nanometer patterned microstructures has a higher carrier mobility and a lower threshold voltage.

[0167] Examples

[0168] The embodiments of the present application will be described in detail below with examples, but those skilled in the art will understand that the following examples are only for illustration of the present application and should not be regarded as limiting the scope of the present application. The specific conditions not specified in the examples are carried out according to the conventional conditions or the conditions recommended by the manufacturer. The reagents or instruments used are not specified by the manufacturer, which are all conventional products that can be obtained by purchase.

[0169] Example 1: Preparation of arrayed nano-orientation patterned microstructure of PS-b-PDMS on ALD-grown InSe surface

[0170] The PS-b-PDMS was deposited on the ALD-grown atomic crystal InSe surface arranged on a silicon substrate using ink (solvent: toluene, copolymer concentration: 5 mg / mL) in an atmospheric environment. Specifically, on a temperature-controllable substrate with variable temperature, the substrate was heated to 210°C, and the ink was spin-coated onto the atomic crystal InSe surface at a spin-coating speed of 2000 rpm for 30 s. Then, after spin-coating, annealing was carried out for 2 hours to achieve microphase separation (by precisely constructing a pre-designed atomic-level periodic structure at the substrate interface, a thermodynamically stable periodic coupling potential field is formed. This potential field can induce the microphase separation and directional arrangement of the polymer photoresist PS-b-PDMS coated thereon, and self-assemble into nanostructures according to the designed periodic pattern), and then the PS phase of the photoresist was etched using CF4+O2, thereby forming a polymer photoresist layer with patterned microstructure on the InSe surface with atomic-level interface, realizing pattern transfer or patterning from the polymer photoresist to the atomic crystal.

[0171] The SEM photo of the obtained photoresist patterned structure is shown in Figure 2 It can be seen that the photoresist patterned structure prepared in the present embodiment has a smooth surface, uniform line precision and very good repeatability. Figure 2

[0172] Example 2: Preparation of arrayed nano-orientation patterned structure of PS-b-P2VP on ALD-grown InSe surface (multi-layer alignment)

[0173] ​The PS-b-P2VP was deposited on the ALD-grown atomic crystal InSe surface arranged on a silicon substrate under atmospheric environment using ink (solvent: toluene, copolymer concentration: 3 mg / mL). Specifically, on a variable-temperature temperature-controlled substrate, the substrate was heated to 220°C, the ink was spin-coated onto the atomic crystal InSe surface, the spin-coating speed was 2000 rpm, and the spin-coating time was 30 s. Then, after spin-coating film annealing for 2 hours to realize micro-phase separation (by precisely constructing a preset atomic-level periodic structure at the substrate interface, a thermodynamically stable periodic coupling potential field is formed. This potential field can induce the micro-phase separation and directional arrangement of the polymer photoresist PS-b-P2VP coated thereon, and form a nanostructure by self-assembly according to the designed periodic pattern), the PS phase of the photoresist was etched using CF4+O2, thereby forming a polymer photoresist layer A-1 with a patterned microstructure on the InSe surface with an atomic-level interface. Accordingly, a patterned structure with 2 layers of aligned photoresist was obtained.

[0174] Next, the same ink was used and the same conditions were used to spin-coat, phase separate and etch the top surface of the etched polymer photoresist layer A-1 in the same way as the formation of the polymer photoresist layer A-1, thereby forming a polymer photoresist layer A-2.

[0175] <Example 3: Preparation of an arrayed nano-directional patterned structure on an ALD-grown InSe surface by PS-b-P2VP (multi-layer alignment)>

[0176] The PS-b-P2VP was deposited on the ALD-grown atomic crystal InSe surface arranged on a silicon substrate under atmospheric environment using ink (solvent: toluene, copolymer concentration: 3 mg / mL). Specifically, on a variable-temperature temperature-controlled substrate, the substrate was heated to 220°C, the ink was spin-coated onto the atomic crystal InSe surface, the spin-coating speed was 2000 rpm, and the spin-coating time was 30 s. Then, after spin-coating film annealing for 2 hours to realize micro-phase separation (by precisely constructing a preset atomic-level periodic structure at the substrate interface, a thermodynamically stable periodic coupling potential field is formed. This potential field can induce the micro-phase separation and directional arrangement of the polymer photoresist PS-b-P2VP coated thereon, and form a nanostructure by self-assembly according to the designed periodic pattern), the PS phase of the photoresist was etched using CF4+O2, thereby forming a polymer photoresist layer A with a patterned microstructure on the InSe surface with an atomic-level interface.

[0177] Next, a functional layer (3-5 nm h-BN atomic crystals deposited by ALD) is introduced onto the top surface of the etched polymer photoresist layer A, forming a synergistic potential field environment with the atomic pattern template of the crystal layer. Finally, using the same ink as that used to form polymer photoresist layer A and under the same conditions, spin-coating, phase separation, and etching operations are performed on the functional layer in the same manner as those used to form polymer photoresist layer A, thereby forming polymer photoresist layer B. Based on this, a patterned structure with two aligned photoresist layers is obtained.

[0178] The resulting SEM images of the multilayer (2-layer) aligned photoresist patterned structure are as follows: Figure 3 As shown in the image. Figure 3 As can be seen, the photoresist patterned structure prepared in this embodiment has a smooth surface, uniform line precision, and excellent repeatability.

[0179] <Example 4>

[0180] The transfer characteristic curves (left) and output characteristic curves (right) of the field-effect transistor constructed based on the nano-oriented patterned structure prepared in Example 1 are shown. Figure 4 As shown.

[0181] Depend on Figure 4 It can be seen that the device constructed based on the nano-oriented patterned structure of the present invention has high mobility, full line shape, and low contact resistance.

[0182] <Example 5>

[0183] Using the patterned structure prepared in Example 1, source and drain electrodes were deposited by electron beam lithography and electron beam evaporation to construct an optoelectronic device. The electrical performance curve of the optoelectronic device is shown below. Figure 5 As shown.

[0184] Depend on Figure 5 It can be seen that the constructed optoelectronic devices work very well.

[0185] <Example 6>

[0186] The conductivity curves of the patterned structure prepared in Example 2 were obtained by using a semiconductor parameter analysis and testing instrument, such as... Figure 6 As shown.

[0187] Depend on Figure 6 As can be seen, it has excellent electrical conductivity.

[0188] It should be noted that although the technical solution of the present invention has been described with specific examples, those skilled in the art will understand that the present invention should not be limited thereto.

[0189] Having described various embodiments of the application, it is to be understood that the above description is meant not to limit and not to encompass all of the possible embodiments covered by the claims. Many modifications and variations of this application can be apparent to those of ordinary skill in the art without departing from the spirit and scope of the described embodiments. It is intended that the scope of the application should only be limited by the appended claims.

Claims

1. An atom-guided photolithography method for chip manufacturing, characterized in that, include: (A1) Constructing a crystal layer with an atomic-level periodic structure on the surface of a substrate. (A2) A photoresist layer A is formed on the surface of the crystal layer by coating with ink A, wherein ink A is a solution containing photoresist A, and photoresist A is a block copolymer. At least one block of photoresist A is phase-separated in a manner that forms a patterned structure with a minimum scale of sub-nanometer, thereby forming an array pattern aligned with the atomic-level periodic structure. (A3) Selectively etch the block phase of the photoresist A so that the photoresist A exists in selected regions of the crystal layer and does not exist in other regions of the crystal layer, and the photoresist layer A present on the crystal layer forms an array structure pattern with a minimum scale of sub-nanometer.

2. The atom-guided photolithography method according to claim 1, characterized in that, The substrate is a silicon wafer; and / or The material forming the crystal layer includes at least one selected from hafnium oxide (HfO2), zirconium oxide (ZrO2), gallium oxide (Ga2O3), beryllium oxide (BeO), strontium titanate (SrTiO3), and aluminum nitride (AlN).

3. The atomic-guided lithography method according to claim 1 or 2, characterized in that, The thickness of the crystal layer is 0.1–10 nm; and / or The pattern linewidth of the photoresist layer A present on the crystal layer is less than 10 nm; and / or The thickness of the photoresist layer A is 1–200 nm.

4. The atom-guided photolithography method according to any one of claims 1 to 3, characterized in that, The phase separation begins before the base of ink A dries, and after coating is completed, the mixture is allowed to stand for an additional 5 minutes to 10 hours to complete the phase separation.

5. The atom-guided photolithography method according to any one of claims 1 to 4, characterized in that, The photoresist layer A is a single layer; or... The photoresist layer A is multilayered, and each layer in the multilayered photoresist layer A is formed in the same manner as in steps (A2) and (A3).

6. The atom-guided photolithography method according to any one of claims 1 to 5, characterized in that, Also includes: (A4) A functional layer is formed on the etched photoresist layer A in a manner that contacts the layer. (A5) A photoresist layer B is formed on the functional layer by coating ink B, wherein ink B is a solution containing photoresist B, wherein photoresist B is a block copolymer, and at least one block of photoresist B is phase-separated in a manner that is self-aligned with the array structure pattern of photoresist A. (A6) Selectively etch the segment phases of the photoresist B, so that the remaining photoresist layer B forms an array structure pattern with a minimum scale of sub-nanometer aligned with the stripe pattern of the photoresist layer A.

7. The atomic-guided lithography method according to claim 6, characterized in that, The photoresist A and the photoresist B may be the same or different.

8. The atom-guided photolithography method according to claim 6 or 7, characterized in that, The material forming the functional layer is selected from two-dimensional materials.

9. A patterned structure having an array pattern with a minimum size in the sub-nanometer range, characterized in that, It is obtained by the atomic guided lithography method according to any one of claims 1 to 8.

10. A method for patterning a substrate, characterized in that, include: (B1) The patterned structure according to claim 9 is etched or electron-implanted from the side of the substrate where the photoresist layer A exists, such that the crystal layer exists in selected regions of the substrate and does not exist in other regions of the substrate, and the crystal layer existing on the substrate forms an array structure pattern with a minimum scale of sub-nanometer. (B2) The substrate exposed from the crystal layer side is etched or electron-injected to form an array structure pattern on the surface of the substrate with a minimum scale of sub-nanometer.

Images