A remote online upgrading method and system for a distributed FPGA system

Abstract

The application discloses a remote online upgrading method and system for a distributed FPGA system, and belongs to the technical field of FPGA upgrading. A PC transmits firmware updating instructions and data to an address mapping module of a master FPGA board card through a PCIE interface; the master FPGA board card distributes the firmware updating instructions and data to an address mapping module of a sub FPGA board card through an Ethernet controller; and the sub FPGA board card transmits the firmware updating instructions and data to a Flash control module after receiving the firmware updating instructions and data. The sub FPGA board card reads firmware data, calculates a local CRC value, and compares the local CRC value with a check code issued by the PC. If the CRC values are consistent, a jump switch command is executed, and a Flash header control bit is switched to a new version of firmware. The application realizes real-time data stream writing without caching, parallel upgrading of multiple board cards, and a safe rollback mechanism, and significantly improves upgrading efficiency and system reliability in a complex heterogeneous environment.

Description

Technical Field

[0001] This invention belongs to the field of FPGA upgrade technology, specifically relating to a remote online upgrade method and system for distributed FPGA systems. Background Technology

[0002] Field-programmable gate arrays (FPGAs) have been widely used in various fields such as communications, industrial control, artificial intelligence, and aerospace due to their high flexibility and parallel processing capabilities. FPGAs can achieve functional reconfiguration by loading different configuration bitstreams, possessing a high degree of hardware and software programmability.

[0003] However, firmware upgrades for traditional FPGA systems typically rely on the vendor-provided JTAG (Joint Test Action Group) interface. This approach has significant limitations after product deployment: system upgrades often require disassembling the FPGA board and reconnecting the debugger, which is cumbersome and costly to maintain. Although some solutions have attempted to achieve online upgrades using a single general-purpose interface (such as UART or Ethernet), these methods generally suffer from poor interface compatibility, weak protocol adaptation capabilities, and insufficient scalability. They struggle to meet the needs of multi-interface, multi-board collaborative upgrades in complex FPGA systems, especially lacking a unified firmware loading mechanism and address mapping support in distributed architectures. Summary of the Invention

[0004] To address the shortcomings of the aforementioned background technology, this invention provides a remote online upgrade method and system for distributed FPGA systems, possessing excellent interface scalability and protocol compatibility. This method introduces a configurable interface address mapping module to achieve unified addressing management of multiple physical interfaces, supporting parallel or serial firmware loading for multiple FPGA boards on different communication links.

[0005] The technical solution is as follows:

[0006] On the one hand, a remote online upgrade method for distributed FPGA systems is provided, including the following steps:

[0007] The PC transmits firmware update instructions and data to the address mapping module of the main control FPGA board via the PCIE interface. The main control FPGA board distributes the firmware update instructions and data to the address mapping module of the sub-FPGA board via the Ethernet controller. After receiving the firmware update instructions and data, the sub-FPGA board sends them to the Flash control module of the sub-FPGA board.

[0008] The sub-FPGA board reads the firmware data and calculates the local CRC value, which is then compared with the checksum sent by the PC. If the CRC values ​​match, the jump switch command is executed to switch the Flash header control bit to the new firmware version.

[0009] Preferably, the address mapping module includes:

[0010] The control command register is used to receive and decode the erase, write, read, and verification operation commands of the FLASH memory.

[0011] The handshake signal register is used to configure the data packet transmission handshake mechanism to ensure that the next packet transmission is triggered after each data packet is written.

[0012] Write to the data register to temporarily store the Flash data to be written and its target address;

[0013] The verification length register is used to read data from a specified address in the verification Flash memory;

[0014] Write time interval register, used to dynamically configure the time interval for write operations.

[0015] Preferably, the upgrade method further includes:

[0016] If the CRC value verification is inconsistent, the process will proceed to retry, and the erase, write, and read verification steps will be executed again. If the CRC value verification is inconsistent multiple times in a row, the upgrade will be determined to have failed, triggering the automatic rollback mechanism and jumping to the secure firmware version.

[0017] Preferably, the address mapping module is configured with a register address space and an APB bus, and interconnects with the upper layer through the register address space and the APB bus to convert the instructions and data received by the upper layer communication interface into read and write transactions that conform to the APB protocol.

[0018] Preferably, the address mapping module is provided with multiple upper-layer communication interfaces. The upper-layer interface controller is connected to the physical layer hardware interface through the upper-layer communication interface and is responsible for parsing the received data stream and extracting valid data frames that conform to the protocol specifications according to the corresponding UART, PCIE, Ethernet, and CAN communication protocols.

[0019] Preferably, the address mapping module is communicatively connected to the FLASH control module. The FLASH control module includes an instruction conversion and execution module and an SPI controller. The instruction conversion and execution module obtains the abstract status instructions sent down from the upper layer from the register address space, parses and converts them into low-level operation instructions for FLASH, and drives the external FLASH storage chip through the SPI interface controller to complete the firmware update operation.

[0020] Preferably, the PC sends firmware data to the main control FPGA board in data packets. The structure of the data packets includes an Ethernet preamble and start-of-frame delimiter, memory address, instruction / data, link status, frame sequence number, and CRC checksum. The Ethernet preamble and start-of-frame delimiter are retained to support direct parsing by network analysis tools. The CRC checksum is used to verify whether an error has occurred during data transmission.

[0021] On the other hand, a remote online upgrade system for distributed FPGA systems is provided, employing the aforementioned remote online upgrade method for distributed FPGA systems. The upgrade system includes:

[0022] The PC is used to encrypt the firmware to be written and attach verification information before transmission, and to send instructions and data.

[0023] The main control FPGA board connects to the PC via the PCIe interface to receive firmware update commands and data from the PC, and connects to the sub-FPGA board via the Ethernet interface to transmit network data packets.

[0024] At least one sub-FPGA board receives instructions distributed by the main control card and operates the local Flash memory;

[0025] Both the main control card and the daughter board are equipped with an address mapping module and a Flash control module, and the Flash partition structure is consistent.

[0026] Preferably, the address mapping module is used to parse the received PCIE or Ethernet protocol data into unified Flash operation instructions, including erase, write, and read verification instructions;

[0027] The Flash control module is used to partition the Flash memory, which is divided into a secure version area and an updated version area. The Flash memory header address space is equipped with a status control bit that controls the current boot version.

[0028] Preferably, the encryption process includes: before the firmware file is transmitted, the PC performs an MD5 calculation on the entire firmware file to generate a unique hash value.

[0029] The technical solution includes at least the following technical effects:

[0030] 1. Employing a real-time data transmission mechanism, this invention eliminates the need for external caching, resulting in low resource consumption and excellent platform portability. During firmware updates, the invention utilizes a real-time data stream transmission mechanism, independent of external DDR or SRAM cache resources and FPGA internal RAM resources. All data received via the PCIe and Ethernet interfaces is directly written to the Flash storage area through an address mapping module. This mechanism, implemented through register-level data caching and forwarding strategies, significantly reduces the consumption of FPGA internal storage resources, enhancing the system's portability and deployment flexibility across different FPGA platforms.

[0031] 2. A multi-interface adaptive address mapping module based on a handshake protocol is adopted to support firmware update expansion for various physical interfaces. This invention introduces a register-based handshake protocol mechanism between the PC and the underlying address mapping module to ensure data transmission reliability and interface protocol compatibility. This mechanism ensures that after each data packet completes its write operation, the transmission of the next data packet is automatically triggered, forming a continuous, seamless data stream. Simultaneously, this protocol has excellent interface adaptability, compatible with physical interfaces of different speeds and protocol types. This system uses PCIe and Ethernet interfaces as the foundation for FPGA firmware updates. Furthermore, by configuring the control registers and handshake protocol registers of the address mapping module, it can be further expanded to support multiple interfaces such as CAN and UART, enabling unified management and remote upgrades of the backend Flash control module.

[0032] 3. A precise firmware version management mechanism based on Flash factory ID is adopted. This invention integrates a Flash factory ID identification module into the Flash control module to achieve refined management of multi-board systems. The PC can accurately identify and manage the firmware version of each board by reading the unique ID information of the Flash on each board. This mechanism not only improves the traceability of system operation and maintenance, but also provides technical support for differentiated deployment of firmware versions and fault location. Attached Figure Description

[0033] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0034] Figure 1 This is a schematic diagram of a remote online upgrade system structure for distributed FPGA systems according to the present invention;

[0035] Figure 2 A flowchart illustrating the specific upgrade instructions for a remote online upgrade method for a distributed FPGA system, provided in a preferred embodiment of the present invention.

[0036] Figure 3 for Figure 1 Timing diagram of register operations in the address mapping module. Figure 3 The horizontal axis represents the time axis, and the vertical axis represents the address of the relevant register.

[0037] Figure 4 for Figure 1 Framework diagram of the address mapping module and FLASH control module;

[0038] Figure 5 This is a structural diagram of the data packet of the present invention. Detailed Implementation

[0039] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention as detailed in the appended claims.

[0040] This invention proposes a method and system for remote online upgrades of distributed FPGA systems. It is a remote online upgrade method for FPGA systems based on PCIe and Ethernet interfaces, suitable for multi-level interconnected and scalable FPGA system architectures. In this system, the main control FPGA board, directly connected to the industrial control computer, receives firmware update data through the high-speed PCIe interface and transmits network data packets with the back-end subboards via the Ethernet interface, thereby completing the remote firmware version upgrade.

[0041] The upgrade method adopts a real-time data stream transmission mechanism. Data received through the PCIe or Ethernet interface is directly written to the Flash control module via the address mapping module. It does not rely on external DDR or SRAM or other large-capacity cache resources or independent RAM resources inside the FPGA. All data received through the PCIe and Ethernet interfaces is directly written to the Flash storage area via the address mapping module.

[0042] At the PC software level, the firmware to be written is encrypted using MD5 before transmission and accompanied by integrity verification information. MD5 is a widely used hash function that generates a 128-bit hash value used to verify data integrity. Before firmware file transmission, the PC software performs an MD5 calculation on the entire firmware file, generating a unique hash value. This hash value can be used to check whether the file has been tampered with or corrupted, ensuring the security and integrity of data during transmission.

[0043] The Flash memory on the FPGA board is divided into two independent firmware storage areas: a secure version area and an updated version area. A status control bit, or "switch," is set in the Flash header address space to control the firmware version used for current startup. During the upgrade process, the system first disables this control bit, then erases the updated version area and writes the new firmware to this area in real time. After writing is complete, the system performs a readback verification to confirm data correctness. Once confirmed, the control bit is re-enabled, allowing the system to load the new firmware version upon the next startup. Throughout the entire upgrade process, the secure version area remains unchanged, ensuring that in the event of upgrade failure or system anomalies, the FPGA can still revert to the original secure version, avoiding a "flash crash" and significantly improving system reliability and maintainability.

[0044] As attached Figure 1 As shown, a remote online upgrade system for distributed FPGA systems is provided, the upgrade system comprising:

[0045] The PC (i.e., the host computer) is used to encrypt the firmware to be written and attach verification information before transmission, and to send instructions and data. The encryption process includes: MD5 encryption before firmware file transmission. The PC (i.e., the host computer) performs MD5 calculation on the entire firmware file to generate a unique hash value.

[0046] The main control FPGA board connects to the PC via the PCIe interface to receive firmware update commands and data from the PC, and connects to the sub-FPGA board via the Ethernet interface to transmit network data packets.

[0047] At least one sub-FPGA board receives instructions distributed by the main control card and operates the local Flash memory;

[0048] Both the main control card and the daughter board are equipped with an address mapping module and a Flash control module, and the Flash partition structure is consistent.

[0049] The address mapping module is used to parse the received PCIE or Ethernet protocol data into unified Flash operation instructions, including erase, write, and read verification instructions.

[0050] like Figure 3 As shown, Figure 3 The horizontal axis represents the time axis, and the vertical axis represents the relevant register addresses. Each operation writes control instructions or data to a specified register address within a specific time window, thereby driving the upgrade state machine to complete the entire firmware update process. The address mapping module includes five key register addresses, among which:

[0051] The control command register is used to configure the current FLASH operation mode, such as erase, program, read verification, etc. Before entering any operation mode, the PC must first write the corresponding operation command to this register to activate the access permissions of subsequent related registers and data transmission.

[0052] The handshake signal register is used to configure the data packet transmission handshake mechanism. As a key mechanism for status feedback and process advancement, this register must be polled and read at each operational stage to confirm whether the current operation is complete or whether the conditions for proceeding to the next stage are met. For example, in the write bitstream data state, new data can only be written to the write data register when the handshake signal register returns to a valid state, thereby ensuring the continuity and reliability of data writing.

[0053] The write data register is used to temporarily store the Flash data to be written and its target address; it carries the bit stream data to be written to the Flash. The bit width of this register can be dynamically adapted according to the transmission characteristics of the upper-layer communication interface (such as Gigabit Ethernet, PCIe, UART, etc.), supporting different data width configurations and improving interface compatibility and transmission efficiency.

[0054] The verification length register is used to read data from a specified address in the Flash memory. During the read verification phase, after the PC writes the total length of the firmware to be verified to the verification length register, the FLASH control module reads the corresponding length of data from the specified storage area and performs a local CRC-32 checksum calculation within the FPGA. After verification is complete, a handshake signal register notifies the PC that the result is ready, and then the CRC checksum value is sent back to the PC for comparison and verification via a specified CRC data register. If the verification matches, the PC executes the final write switch command, restoring the system control switch and completing the upgrade process.

[0055] Write time interval register, used to dynamically configure the time interval for write operations.

[0056] The Flash control module is used to partition the Flash memory, which is divided into a secure version area and an updated version area. The Flash memory's header address space is equipped with a status control bit that controls the current boot version.

[0057] Because different Flash chips require different times to execute the same instructions, and the execution time of the same chip will also vary under different working environments (such as temperature and voltage) and different life cycles (such as aging degree and number of erase and write cycles), for example, page write time usually fluctuates between 0.4ms and 4ms, mainly affected by the following factors: chip manufacturing process and material characteristics, power supply voltage fluctuations, operating temperature changes, data write mode (such as continuous write or random write), and storage cell aging effect.

[0058] This invention implements a feedback mechanism for PC software by reading the Flash chip status and a configurable write time interval register, enabling the software to dynamically adjust the data packet sending rhythm according to the actual write delay, thereby improving transmission efficiency and system stability.

[0059] This method implements a complete control flow for reading, writing, and erasing operations on the Flash chip based on an address mapping module and a Flash control module. The control protocol logic is centrally deployed in the address mapping module, forming a unified instruction execution unit together with the backend Flash control module. This unit is independent of specific physical communication interface protocols, only recognizing and executing received commands, exhibiting good interface independence and system portability. In practical implementation, the address mapping module can seamlessly interface with various communication interfaces (such as PCIe, Ethernet, UART, etc.) without modifying the original interface protocol stack. Only the data buffer module in the original communication link needs to be replaced with this module to achieve the parsing and execution of remote Flash operation instructions.

[0060] like Figure 4 As shown, in this invention, various upper-layer interface controllers are connected to the physical layer hardware interface and are responsible for parsing the received data stream according to the corresponding communication protocol (such as UART, PCIe, Ethernet, CAN, etc.) to extract valid data frames that conform to the protocol specifications. The data frame contains predefined register operation instructions and bit stream data, wherein the operation instructions are used to control the state, and the bit stream data contains the original information to be written or read.

[0061] The address mapping module interconnects with the APB bus via a dedicated register address space, thereby converting instructions and data received from the upper-layer communication interface into read / write transactions conforming to the APB protocol. The system is further configured with an instruction conversion and execution module. This module retrieves abstracted status instructions from the upper layer in the address space, which are then parsed and converted into low-level operation instructions for the FLASH memory by the back-end module. These instructions are then used to drive the external FLASH memory chip via the SPI interface controller to complete the firmware update operation.

[0062] The upper-layer interface controller and the SPI interface controller, acting as master and slave devices on the APB bus, can access registers in the address space. The master control unit only needs to perform standard read and write operations to the APB address space corresponding to the SPI interface controller to achieve unified control of the FLASH chip through different peripherals. For high-speed peripheral interfaces (such as PCIe or Ethernet), a handshake mechanism is introduced in the address mapping module to ensure data transmission reliability and timing matching, using a valid signal to achieve data synchronization across clock domain interfaces. By mapping the transmit and receive data channels of different peripheral controllers to specific register address spaces, this architecture achieves centralized management and scheduling of multi-interface data.

[0063] In summary, this invention, by constructing a peripheral interconnection architecture based on the APB bus and combining protocol parsing, interface conversion, and instruction execution mechanisms, achieves efficient and reliable data interaction between different communication interfaces and underlying FLASH storage devices with SPI interfaces. It is particularly suitable for application scenarios such as remote firmware upgrades and has good scalability and hardware abstraction capabilities.

[0064] A remote online upgrade method for distributed FPGA systems includes:

[0065] The PC transmits firmware update instructions and data to the address mapping module of the main control FPGA board via the PCIE interface. The main control FPGA board distributes the firmware update instructions and data to the address mapping module of the sub-FPGA board via the Ethernet controller. After receiving the firmware update instructions and data, the sub-FPGA board sends them to the Flash control module of the sub-FPGA board.

[0066] The sub-FPGA board reads the firmware data and calculates the local CRC value, comparing it with the checksum sent by the PC. If the CRC values ​​match, the jump switch command is executed to switch the Flash header control bit to the new firmware version. If the CRC values ​​do not match, the retry process is initiated, and the erase, write, and read verification steps are executed again. If the verification fails multiple times, the upgrade is deemed to have failed, triggering the automatic rollback mechanism and jumping to the secure firmware version.

[0067] Figure 2 The preferred embodiment shown provides a remote online upgrade method for distributed FPGA systems. The specific upgrade process is as follows:

[0068] like Figure 1 He Ru Figure 2As shown, in step S1, the erasure stage: the PC software sends a "half-area erase" command to the address mapping module of the main control FPGA board (A card) through the PCIE interface. The main control FPGA board (A card) distributes the "half-area erase" command to the address mapping module of the sub-FPGA board through the Ethernet controller. After receiving the erase command, the sub-FPGA board sends a "half-area erase" command to the Flash chip and reports the operation status to the PC after the erasure is completed.

[0069] Step S2, Writing Stage: The PC sends firmware data to the main control FPGA board in data packets. The main control FPGA board distributes the data to the address mapping modules of each sub-FPGA board through the Ethernet controller.

[0070] To improve the reliability of data transmission and the ease of debugging, this paper proposes an optimized data packet structure design. Figure 5 As shown, the structure of a data packet includes an Ethernet preamble and start-of-frame delimiter, memory address, instruction-data, link status, frame sequence number, and CRC checksum.

[0071] Specifically, retaining the preamble and start-of-frame delimiter in the Ethernet frame header allows network analysis tools like Wireshark to directly capture and parse these packets, simplifying the debugging process and enhancing the understanding and monitoring capabilities of transport layer protocol behavior. Memory addresses and data instructions are crucial for the backend address mapping module. Separating the address and data information involved in the interface protocol and passing it to the address mapping module enables support for various types of physical interfaces, enhancing system compatibility and scalability. Link status can be used to detect physical connection anomalies and track the transmission order of data packets, helping the receiver determine if packet loss or other transmission errors have occurred. By comparing the sequence numbers of received data packets, lost packets can be quickly located, triggering a retransmission mechanism to ensure data arrives at its destination intact. CRC checksums are used to verify whether errors have occurred during data transmission.

[0072] The PC sends data to the main control FPGA board (card a) in packets, with each packet being in N*32-bit format. The main control FPGA board (card a) distributes the data to the address mapping modules of each sub-FPGA board (card b) via an Ethernet controller. The sub-FPGA boards (card b) write the data to the designated address space according to the Flash page write instruction format and provide status information after the write is complete.

[0073] Step S3, Verification Stage: The sub-FPGA board reads the firmware data and calculates the local CRC value, which is compared with the verification code sent by the PC. If the CRC values ​​match, the jump switch command is executed to switch the Flash header control bit to the new firmware version. If the verification fails, the retry process is entered, and the erase, write, and read verification steps are executed again.

[0074] Specifically, after all data is written, the PC sends a "read verification" command to the sub-FPGA board (b card). The sub-FPGA board (b card) sequentially reads the data from the entire firmware area and performs a CRC checksum locally. After verification, the 32-bit CRC checksum is uploaded to the PC for comparison. If the CRC values ​​match, the "jump switch" command is executed to switch the Flash header control bits to the new firmware version, and the new firmware is loaded on the next system startup. If the verification fails, the system automatically enters the retry process and re-executes the erase, write, and verification steps.

[0075] Step S4, Abnormal Phase: If multiple consecutive verifications fail, the upgrade is deemed a failure, triggering an automatic rollback mechanism to switch to a secure firmware version, ensuring the FPGA system remains operational and avoiding the risk of being "flash-frozen." This invention improves system fault tolerance by setting up a multiple retry mechanism.

[0076] Preferably, the upgrade method adopts a real-time data stream transmission mechanism, whereby data received through a PCIE or Ethernet interface is directly written to the Flash control module via an address mapping module.

[0077] Compared to existing technologies, this invention offers significant advantages in resource utilization. Traditional methods typically employ a segmented transmission mechanism, where the complete firmware is first cached in off-chip DDR or on-chip BRAM, and then written to FLASH in batches. This approach requires at least 2MB or more of intermediate storage space equivalent to the firmware size, resulting in high resource overhead, high cost, and hindering miniaturization design. While some optimization schemes use FIFO or distributed RAM for rate matching, they still rely on additional storage resources to balance the bandwidth difference between the high-speed interface and the low-speed FLASH. This invention, based on a multi-state register collaboration and handshake protocol-driven write mechanism, achieves a minimal buffer depth to complete large-capacity firmware updates. Data does not need to reside entirely in local storage after reception; instead, it is directly written to the target FLASH area through state machine control and real-time handshake feedback. This mechanism significantly reduces reliance on FPGA internal Block RAM and external memory, substantially saving hardware resources and improving system integration and portability.

[0078] The remote online upgrade system for distributed FPGA systems, as described in this invention, achieves unbuffered real-time data stream writing, parallel upgrade of multiple boards, and a secure rollback mechanism through multi-level interface collaboration between PCIe and Ethernet, combined with an address mapping module of dynamically configurable interfaces. This significantly improves upgrade efficiency and system reliability in complex heterogeneous environments.

[0079] The upgraded method of the invention introduces a configurable interface address mapping module to achieve unified addressing management of multiple physical interfaces (such as I²C, Ethernet, PCIe, etc.) and supports parallel or serial firmware loading of multiple FPGA boards on different communication links.

[0080] The invention's upgrade system dynamically configures upgrade paths based on network topology, enabling a highly efficient remote upgrade mechanism that requires no physical contact. This significantly improves the maintainability and flexibility of FPGA systems after deployment and is suitable for reconfigurable hardware platforms in complex, multi-node, and heterogeneous interface environments.

[0081] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0082] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

Claims

1. A remote online upgrade method for distributed FPGA systems, characterized in that, include: The PC transmits firmware update instructions and data to the address mapping module of the main control FPGA board via the PCIE interface. The main control FPGA board distributes the firmware update instructions and data to the address mapping module of the sub-FPGA board via the Ethernet controller. After receiving the firmware update instructions and data, the sub-FPGA board sends them to the Flash control module of the sub-FPGA board. The sub-FPGA board reads the firmware data and calculates the local CRC value, which is then compared with the check code sent by the PC. If the CRC values ​​match, the jump switch command is executed to switch the Flash header control bit to the new firmware version. The address mapping module includes: a control command register for receiving and decoding erase, write, and read verification operation commands from the FLASH memory; a handshake signal register for configuring the data packet transmission handshake mechanism; a write data register for temporarily storing the Flash data to be written and its target address; a verification length register for reading and verifying data at a specified address in the Flash memory; and a write time interval register for dynamically configuring the time interval for write operations. The address mapping module is configured with a register address space and an APB bus. It is interconnected with the upper layer through the register address space and the APB bus, and converts the instructions and data received by the upper layer communication interface into read and write transactions that conform to the APB protocol. The address mapping module is equipped with multiple upper-layer communication interfaces. The upper-layer interface controller is connected to the physical layer hardware interface through the upper-layer communication interface. It is responsible for parsing the received data stream according to the corresponding UART, PCIE, Ethernet, and CAN communication protocols and extracting valid data frames that conform to the protocol specifications.

2. The remote online upgrade method for distributed FPGA systems according to claim 1, characterized in that, The upgrade method also includes: If the CRC value verification is inconsistent, the process will proceed to a retry, and the erase, write, and read verification steps will be executed again. If the verification is inconsistent multiple times, the upgrade will be deemed to have failed, triggering an automatic rollback mechanism and jumping to a secure firmware version.

3. The remote online upgrade method for distributed FPGA systems according to claim 1, characterized in that, The address mapping module is communicatively connected to the FLASH control module. The FLASH control module includes an instruction conversion and execution module and an SPI controller. It obtains abstract status instructions from the upper layer in the register address space through instruction conversion and execution, parses and converts them into low-level operation instructions for FLASH, and drives the external FLASH storage chip through the SPI interface controller to complete the firmware update operation.

4. The remote online upgrade method for distributed FPGA systems according to claim 1, characterized in that, The PC sends firmware data to the main control FPGA board according to the data packet. The structure of the data packet includes Ethernet preamble and frame start delimiter, memory address, instruction / data, link status, frame sequence number and CRC check code.

5. A remote online upgrade system for distributed FPGA systems, employing the remote online upgrade method for distributed FPGA systems as described in any one of claims 1-4, characterized in that, The upgrade system includes: The PC is used to encrypt the firmware data to be written and attach verification information before transmission, and then send update instructions and firmware data. The main control FPGA board connects to the PC via a PCIe interface to receive firmware update commands and data from the PC, and connects to the sub-FPGA board via an Ethernet interface. At least one sub-FPGA board receives instructions distributed by the main control card and operates the local Flash memory; Both the main control card and the daughter board are equipped with an address mapping module and a Flash control module, and the Flash partition structure is consistent.

6. The remote online upgrade system for distributed FPGA systems according to claim 5, characterized in that: The address mapping module is used to parse the received PCIE or Ethernet protocol data into unified Flash operation instructions, including erase, write, and read verification instructions. The Flash control module is used to partition the Flash memory, which is divided into a secure version area and an updated version area. The Flash header address space is equipped with a status control bit that controls the current boot version.

7. The remote online upgrade system for distributed FPGA systems according to claim 6, characterized in that, The encryption process includes: MD5 encryption before firmware file transmission, whereby the PC performs MD5 calculation on the entire firmware file to generate a unique hash value.

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