Interrupt reporting processing circuit and electronic device

Abstract

An interrupt reporting and processing circuit and electronic device are disclosed. The interrupt reporting and processing circuit includes multiple interrupt generator modules coupled one-to-one with multiple functional units, a daisy chain for connecting the multiple interrupt generator modules, and an interrupt controller module located at the end of the daisy chain. Each interrupt generator module is configured to buffer interrupt requests from the coupled functional units and serially output the received interrupt requests to the daisy chain. A delay module is coupled between every two interrupt generators, configured to generate a delay of a fixed clock period. The interrupt controller module is coupled to a higher interrupt controller via a bus. The interrupt controller module is configured to buffer the interrupt requests received and transmitted via the daisy chain according to priority, perform interrupt arbitration based on the priority of the interrupt requests, and transmit the selected interrupt request to the higher interrupt controller via the bus. This interrupt reporting and processing circuit effectively avoids arbitration conflicts between multifunctional units and alleviates arbitration pressure.

Description

Technical Field

[0001] Embodiments of this disclosure relate to an interrupt reporting processing circuit and electronic device. Background Technology

[0002] Larger intellectual property cores (IP cores) in chips, such as processor IP cores, graphics processor IP cores, and memory controller IP cores, are composed of multiple functional units or modules. For example, a memory controller IP core may contain data read / write units, error detection units, cache management units, etc., with each functional unit responsible for a specific task, such as detecting data transmission errors or managing cache hit rates.

[0003] An interrupt request is essentially a distress signal from a functional unit. When a functional unit encounters a problem it cannot solve or requires external intervention, it sends an interrupt request to the chip's Advanced Interrupt Controller (AIC). Over a period of time, multiple functional units, or even a single functional unit, may simultaneously report interrupts and send them to the corresponding interrupt controller via the bus, causing bus congestion. This affects the transmission of other requests on the bus, and a large number of interrupts can lead to arbitration conflicts. When a large number of functional units report interrupts, due to the limited receiving capacity of the interrupt controller, interrupts are inevitably dropped, and the processor cannot detect the lost interrupt information, impacting processor performance. Summary of the Invention

[0004] This invention application provides at least one embodiment of an interrupt reporting processing circuit for serially reporting interrupt requests generated by multiple functional units to an advanced interrupt controller. The interrupt requests from the multiple functional units are processed uniformly. The interrupt reporting processing circuit includes multiple interrupt generator modules coupled one-to-one with the multiple functional units, a daisy chain for connecting the multiple interrupt generator modules, and an interrupt controller module located at the end of the daisy chain. Each interrupt generator module is configured to buffer interrupt requests from the coupled functional units and serially output the received interrupt requests to the daisy chain. A delay module is coupled between every two interrupt generator modules. The delay module is configured to generate a delay of a fixed clock period. The interrupt controller module is coupled to the advanced interrupt controller via a bus. The interrupt controller module is configured to buffer the interrupt requests received and transmitted through the daisy chain according to priority, perform interrupt arbitration according to the priority of the interrupt requests, and transmit the selected interrupt requests to the advanced interrupt controller via the bus.

[0005] For example, in the interrupt reporting processing circuit provided in at least one embodiment of this invention application, the interrupt generator module supports the coupled functional unit to report up to M interrupt requests simultaneously. The interrupt generator module includes a register matrix and a selection module. The register matrix includes N layers, each layer including M register modules. The register matrix is ​​configured to store the interrupt requests reported by the coupled functional unit in batches. Interrupt requests reported in the same clock cycle are stored in the same layer of the register matrix. The selection module is coupled to the Nth layer of the register matrix and configured to convert the interrupt requests stored in the M register modules of the Nth layer into serial requests and output them sequentially, where M and N are positive integers.

[0006] For example, in the interrupt reporting processing circuit provided in at least one embodiment of this application, the interrupt requests reported by the coupled functional unit within one clock cycle are first stored in the first layer of the register matrix. In multiple clock cycles after the first clock cycle, the interrupt requests stored in the first layer of the register matrix are batched into the next layer of the register matrix every t clock cycles until they enter the Nth layer of the register matrix, where t is a positive integer.

[0007] For example, in the interrupt reporting processing circuit provided in at least one embodiment of this application, the interrupt generator module further includes a first storage module, which is coupled to the selection module. The first storage module includes L storage units, each of which is configured to store interrupt information of an interrupt request. The interrupt information of the interrupt request serially output by the selection module is cached in the first storage module.

[0008] For example, in the interrupt reporting processing circuit provided in at least one embodiment of this invention application, the first storage module is further configured to clear all interrupt information currently stored in the first storage module in response to receiving a clear instruction. The first storage module also includes at least one backup storage unit. In response to the fact that all L storage units have stored interrupt information, the interrupt request serially output by the selection module is cached in the at least one backup storage unit so as to be sent to the daisy chain when it needs to be sent. Each backup storage unit is cleared after the cached interrupt request is sent to the daisy chain so as to receive the next interrupt request.

[0009] For example, in the interrupt reporting processing circuit provided in at least one embodiment of this application, the selection module serially sends the interrupt request to the daisy chain.

[0010] For example, in the interrupt reporting processing circuit provided in at least one embodiment of this application, the interrupt generator module further includes a delay control module. The delay control module is located between and coupled to the selection module and the daisy chain. The delay control module is configured to send the interrupt request to the daisy chain sequentially according to a preset delay.

[0011] For example, in the interrupt reporting processing circuit provided in at least one embodiment of this application, the plurality of interrupt generator modules are obtained by instantiating an interrupt generator template. M and N of each interrupt generator module are configurable parameters, M is determined according to the coupled functional unit, and N is determined according to the circuit area allocated to the interrupt generator module.

[0012] For example, in the interrupt reporting processing circuit provided in at least one embodiment of this application, the interrupt generator module further includes a filtering module. The filtering module is located between the functional unit and the register matrix and is coupled to the functional unit and the register matrix. The filtering module is configured to filter interrupt requests of a predetermined priority according to the priority of the interrupt requests reported by the coupled functional unit, and send the remaining interrupt requests to the register matrix for storage in the register matrix.

[0013] For example, in the interrupt reporting processing circuit provided in at least one embodiment of this invention application, the interrupt controller module includes a first selector, a plurality of first-in-first-out (FIFO) buffer modules corresponding to a plurality of priorities, and a second selector. The first selector is configured to receive the interrupt request transmitted by the daisy chain and store the interrupt request in the corresponding FIFO buffer module according to the priority of each interrupt request. The plurality of FIFO buffer modules are configured to store interrupt requests of corresponding priorities respectively. The second selector is configured to perform interrupt arbitration according to the priority of the interrupt request and send the first interrupt request in the selected FIFO buffer module to the high-level interrupt controller through the bus. The FIFO buffer module with the higher priority is selected first. The first interrupt request is the interrupt request that enters first among all current interrupt requests in the selected FIFO buffer module.

[0014] For example, in the interrupt reporting processing circuit provided in at least one embodiment of this invention application, the plurality of first-in-first-out (FIFO) cache modules are also respectively associated with a credit counter. The credit counter is set with an initial value as the maximum upper limit. The credit counter is configured such that, in response to the corresponding FIFO cache module outputting an interrupt request, the value of the credit counter is decremented by 1, and in response to receiving a request response from the advanced interrupt controller for the priority corresponding to the corresponding FIFO cache module, the value of the credit counter is incremented by 1. When the second selector performs interrupt arbitration based on the priority of the interrupt request, it includes performing the following operations: in response to the FIFO cache module corresponding to the first priority storing an interrupt request, and in response to the credit counter value corresponding to the FIFO cache module corresponding to the first priority not being 0, the first interrupt request in the FIFO cache module corresponding to the first priority is selected as the selected interrupt request, wherein the first priority is the highest priority among at least one priority corresponding to at least one FIFO cache module currently storing an interrupt request.

[0015] For example, in the interrupt reporting processing circuit provided in at least one embodiment of this application, the interrupt controller module further includes a second storage module, which is configured to store the received interrupt request with the priority of the first-in-first-out buffer module corresponding to any priority when the buffer module is full.

[0016] For example, in the interrupt reporting processing circuit provided in at least one embodiment of this invention application, the plurality of functional units belong to the same intellectual property core.

[0017] This application provides at least one embodiment of an electronic device, including an interrupt reporting processing circuit as described in any embodiment of this application.

[0018] For example, in an electronic device provided in at least one embodiment of this application, the interrupt generator module includes a first storage module for storing interrupt information of interrupt requests, and the electronic device is further configured to actively access the first storage module to obtain interrupt information reported by various functional units.

[0019] For example, in an electronic device provided in at least one embodiment of this application, the interrupt controller module includes a plurality of first-in-first-out (FIFO) cache modules for storing interrupt requests of corresponding priorities, and a second storage module for storing interrupt requests that failed to be stored in the plurality of FIFO cache modules. The electronic device is further configured to actively access the second storage module to obtain interrupt information of interrupt requests that failed to be transmitted to the advanced interrupt controller.

[0020] The interrupt reporting processing circuit provided in at least one embodiment of this invention uses a daisy chain structure to redirect concurrent interrupts to serial reporting, thus alleviating arbitration conflicts. Furthermore, interrupts from different functional units are transmitted serially in chronological order. Even if multiple functional units report interrupt requests simultaneously, they will be sent to the interrupt control terminal in a serial transmission manner, effectively avoiding arbitration conflicts between multifunctional units and effectively alleviating the arbitration pressure of a large number of interrupts of different priorities being reported simultaneously in the circuit. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0022] Figure 1 This is a diagram of an interrupt request reporting architecture.

[0023] Figure 2 A schematic diagram of the structure of an interrupt reporting processing circuit provided in at least one embodiment of this disclosure;

[0024] Figure 3 A schematic structural diagram of an interrupt generator module provided in at least one embodiment of this disclosure;

[0025] Figure 4 A schematic structural diagram of a register matrix provided for at least one embodiment of this disclosure;

[0026] Figure 5 A schematic structural diagram of an interrupt generator module provided in another embodiment of this disclosure;

[0027] Figure 6 A schematic structural diagram of an interrupt controller module provided in at least one embodiment of this disclosure;

[0028] Figure 7 A schematic structural diagram of an interrupt controller module provided in another embodiment of this disclosure;

[0029] Figure 8 A schematic structural diagram of an electronic device provided for at least one embodiment of this disclosure;

[0030] Figure 9 A schematic diagram of the specific structure of an electronic device provided in an embodiment of this disclosure;

[0031] Figure 10 This is a schematic diagram of a general-purpose graphics processing unit (GPGPU). Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0033] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0034] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and known components have been omitted.

[0035] Interrupt requests can generally be categorized into two types. The first type is at the business level, including error or exception recovery. For example, a data read / write unit might encounter a data verification error while executing instructions, or a cache management unit might experience a cache overflow. Failure to resolve these issues will lead to business interruption, requiring intervention from the processor or software, such as retransmitting data or clearing the cache. The second type is at the debugging level, involving hardware status monitoring. For instance, during chip development, engineers cannot directly see the internal hardware status. Interrupt requests act as hardware logs. For example, frequent timeout interrupts from a functional unit might indicate a problem with its clock signal, while a unit that never reports an interrupt might mean it's not even activated. Developers can use this information to pinpoint hardware design flaws.

[0036] In a chip, a larger intellectual property core typically contains many functional units or modules. These functional units report interrupt requests based on the actual business scenario.

[0037] Figure 1 This is a diagram of an interruption request reporting architecture.

[0038] like Figure 1As shown, the Intellectual Property Core (IP0) comprises multiple functional units, namely... Figure 1 The system includes functional units A, B, C, and D. Functional units A, B, C, and D contain interrupts of various types that need to be reported and processed. Furthermore, the interrupt types of each functional unit are classified into different Interrupt Priority Levels (IPLs) according to their importance. Figure 1 The interrupts reported by different functional units are aggregated and sent to the interrupt controller via the bus. Within the same clock cycle, the interrupt controller will only receive one reported interrupt from the intellectual property core (IP0). If multiple functional units report interrupts simultaneously, these interrupt requests need to be arbitrated according to certain rules; interrupt requests that meet the conditions can then be reported to the interrupt controller.

[0039] like Figure 1 As shown, within a certain period of time, multiple functional units may need to report interrupts simultaneously and send them to the corresponding interrupt controllers via the bus. A large number of interrupts may cause arbitration conflicts.

[0040] Furthermore, within a single functional unit, multiple interrupts may be triggered simultaneously, leading to arbitration conflicts. If each functional unit caches a large number of interrupts based on the arbitration type, it would result in wasted module space.

[0041] During interrupt request transmission, the bus used is not only for transmitting interrupt requests but also for transmitting other information. When the bus is occupied, the interrupt request that needs to be transmitted may be lost. In addition, when a large number of functional unit interrupts are reported, interrupts will inevitably be dropped due to the limited receiving capacity of the interrupt controller. However, currently, the processor or software cannot detect the lost interrupt information, resulting in some interrupts not being processed and affecting processor performance.

[0042] In addition, a large number of interrupts generated by multiple functional units are reported to the interrupt controller in sequence through the bus. Since the bus is not dedicated to interrupt reporting but is also used for other information transmission, the transmission of a large number of interrupts will cause bus congestion and affect the transmission of other requests on the bus.

[0043] At least one embodiment of this disclosure provides an interrupt reporting processing circuit for serially reporting interrupt requests generated by multiple functional units to an advanced interrupt controller. The interrupt requests from multiple functional units are processed uniformly. The interrupt reporting processing circuit includes multiple interrupt generator modules coupled one-to-one with the multiple functional units, a daisy chain for mounting the multiple interrupt generator modules, and an interrupt controller module located at the end of the daisy chain. Each interrupt generator module is configured to buffer interrupt requests from the coupled functional units and serially output the received interrupt requests to the daisy chain. A delay module is coupled between every two interrupt generators. The delay module is configured to generate a delay of a fixed clock period. The interrupt controller module is coupled to the advanced interrupt controller via a bus. The interrupt controller module is configured to buffer the interrupt requests received and transmitted via the daisy chain according to priority, perform interrupt arbitration according to the priority of the interrupt requests, and transmit the selected interrupt requests to the advanced interrupt controller via the bus.

[0044] The interrupt reporting processing circuit provided in at least one embodiment of this disclosure uses a daisy chain to redirect concurrent interrupts to serial reporting, thereby mitigating arbitration conflicts. Furthermore, interrupts from different functional units are transmitted serially in chronological order. Even if multiple functional units report interrupt requests simultaneously, they will be sent to the interrupt control terminal in a serial transmission manner, effectively avoiding arbitration conflicts between multifunctional units and effectively alleviating the arbitration pressure of a large number of interrupts of different priorities being reported simultaneously in the circuit.

[0045] The circuit structure of the interrupt reporting processing circuit provided in at least one embodiment of this disclosure will be described in detail below with reference to the accompanying drawings.

[0046] Figure 2 This is a schematic diagram of the structure of an interrupt reporting processing circuit provided in at least one embodiment of the present disclosure.

[0047] The interrupt reporting processing circuit provided in at least one embodiment of this disclosure is used to serially report interrupt requests generated by multiple functional units to the advanced interrupt controller, and the interrupt requests of multiple functional units are processed in a unified manner.

[0048] For example, multiple functional units include Figure 2 Functional units A, B, C, D, and E are listed in the text.

[0049] Multiple functional units can be selected as needed, and their interrupt requests can be processed uniformly. For example, multiple functional units can be located close to each other on the circuit and have functional cooperation relationships. For instance, multiple functional units can belong to the same intellectual property core, which can be a large-scale intellectual property core, such as a graphics processing unit core or a central processing unit core. This disclosure does not impose specific limitations on the type and number of functional units.

[0050] like Figure 2 As shown, the interrupt reporting processing circuit 100 may include Figure 2 The portion defined by the dashed box.

[0051] The interrupt reporting and processing circuit 100 may include multiple interrupt generator modules 101, each coupled to a corresponding functional unit. For example... Figure 2 As shown, the multiple interrupt generator modules 101 may include an interrupt generator module 101 coupled to functional unit A (hereinafter referred to as interrupt generator module 101_A for easy distinction), an interrupt generator module 101 coupled to functional unit B (hereinafter referred to as interrupt generator module 101_B for easy distinction), an interrupt generator module 101 coupled to functional unit C (hereinafter referred to as interrupt generator module 101_C for easy distinction), an interrupt generator module 101 coupled to functional unit D (hereinafter referred to as interrupt generator module 101_D for easy distinction), and an interrupt generator module 101 coupled to functional unit E (hereinafter referred to as interrupt generator module 101_E for easy distinction), etc.

[0052] For example, multiple interrupt generator modules can be obtained by instantiating an interrupt generator template. For instance, for each functional unit, a corresponding interrupt generator module is instantiated, dedicated to the interrupt handling and reporting operations of that functional unit. During instantiation, multiple configurable parameters can be configured for the interrupt generator template. Users can select appropriate parameters such as the coupled functional units and the circuit area allocated to the interrupt generator module to instantiate the corresponding interrupt generator module, simplifying the cost of obtaining interrupt generator modules and enabling rapid deployment of multiple interrupt generator modules.

[0053] like Figure 2 As shown, the interrupt reporting processing circuit 100 also includes a daisy chain 102 for mounting multiple interrupt generator modules, and an interrupt controller module 103 located at the end of the daisy chain.

[0054] A daisy-chain is a connection method that links multiple devices or modules sequentially end-to-end, allowing data to be transferred between these devices or modules. For example, ... Figure 2 As shown, the data starts from the position uploaded to the daisy chain, and is ordered... Figure 2 The direction indicated by the arrow is transmitted to the end module, namely the interrupt controller module 103, via daisy chain 102.

[0055] Each interrupt generator module 101 is configured to buffer interrupt requests from coupled functional units and serially output the received interrupt requests to the daisy chain 102.

[0056] Interrupt controller module 103 is coupled to advanced interrupt controller AIC via a bus. Interrupt controller module 103 is configured to buffer interrupt requests received via daisy chain 102 according to priority, perform interrupt arbitration according to the priority of the interrupt request, and transmit the selected interrupt request to advanced interrupt controller via bus.

[0057] In addition, such as Figure 2 As shown, a delay module is coupled between every two interrupt generators, and the delay module is configured to generate a delay of a fixed clock period. Figure 2 The diagram shows a delay module 104 between an interrupt generator module 101_A coupled to functional unit A and an interrupt generator module 101_B coupled to functional unit B. It can be understood that, although... Figure 2 As not shown, a delay module 104 is also provided between the interrupt generator module 101_B coupled to functional unit B and the interrupt generator module 101_C coupled to functional unit C, and a delay module 104 is also provided between the interrupt generator module 101_C coupled to functional unit C and the interrupt generator module 101_D coupled to functional unit D, and so on.

[0058] For example, the delay module can be implemented using registers, and the delay can be determined by setting the number of beats in the register.

[0059] Therefore, in the interrupt reporting processing circuit provided in at least one embodiment of this disclosure, the interrupt generator module can buffer the interrupt requests of the coupled functional units. Even if multiple interrupt requests are received at the same time, these interrupt requests can be serially output to the daisy chain for transmission to the interrupt controller module. This can effectively avoid arbitration conflicts caused when a functional unit reports multiple interrupt requests at the same time.

[0060] A delay module is coupled between each pair of interrupt generator modules. Thus, even if multiple interrupt requests are uploaded to the daisy chain at the same time, they can still be transmitted serially to the interrupt controller module 103 in sequence. This effectively avoids arbitration conflicts caused by multiple functional units reporting multiple interrupt requests at the same time, and effectively alleviates the arbitration pressure of a large number of interrupts of different priorities being reported at the same time in the circuit.

[0061] By setting up a special chain structure (daisy chain), concurrent interrupt request reporting is redirected to serial reporting, which effectively alleviates arbitration conflicts and allows interrupts from different functional units to be transmitted serially in chronological order, effectively relieving the arbitration pressure when a large number of interrupt requests of different priorities are reported simultaneously from multiple functional units.

[0062] The interrupt generator module can buffer interrupt requests from coupled functional units, and the interrupt controller module can also buffer interrupt requests received through a daisy chain, effectively preventing the loss of interrupt information.

[0063] The circuit structure of the interrupt generator module and the interrupt controller module provided in at least one embodiment of this disclosure is described in detail below with reference to the accompanying drawings.

[0064] Figure 3 This is a schematic structural diagram of an interrupt generator module provided in at least one embodiment of the present disclosure.

[0065] Figure 3 The circuit structure of the interrupt generator module 101 shown can be Figure 2 The circuit structure of any interrupt generator module in the system, such as interrupt generator module 101_A, etc.

[0066] like Figure 3 As shown, the interrupt generator module 101 includes a register matrix and a selection module.

[0067] The register matrix is ​​coupled to the functional unit and configured to receive interrupt requests sent by the functional unit and buffer the received interrupt requests.

[0068] Select the module configuration to convert interrupt requests stored in the register matrix into serial output.

[0069] Figure 4 This is a schematic structural diagram of a register matrix provided for at least one embodiment of the present disclosure.

[0070] like Figure 4 As shown, the register matrix consists of N layers, with each layer containing M register modules. Figure 4 The diagram shows the first and Nth layers. The structure of the intermediate N-2 layers is the same and will not be described again here. M and N are positive integers.

[0071] The first layer of the register matrix is ​​coupled to the functional units. Specifically, the M register modules of the register matrix can be electrically connected to the corresponding functional units, so that they can simultaneously receive up to M interrupt requests reported by the functional units. Thus, the interrupt generator module supports the coupled functional units to simultaneously report up to M interrupt requests, which are stored in the M register modules.

[0072] The register matrix is ​​configured to store interrupt requests reported by coupled functional units in batches, and interrupt requests reported in the same clock cycle are stored in the same layer of the register matrix.

[0073] For example, the M interrupt requests reported by the functional unit are stored in the corresponding M register modules. For example, in Figure 4 In the example, the functional unit reports three interrupt requests during the current clock cycle, which are stored in register modules numbered 0, 3, and M-2 in the first level of the register matrix, respectively. The other register modules are empty. It should be noted that... Figure 4The diagram shows three lines connecting the functional unit and the first layer of the register matrix, indicating that only three interrupt requests are sent to the register matrix. Other register modules are also physically electrically connected to the functional unit. Figure 4 Not shown in the image.

[0074] For example, interrupt requests reported by coupled functional units within one clock cycle are first stored in the first layer of the register matrix. In multiple clock cycles after one clock cycle, the interrupt requests stored in the first layer of the register matrix are entered into the next layer of the register matrix in batches every t clock cycles, until they enter the Nth layer of the register matrix, where t is a positive integer.

[0075] For example, in one embodiment, the plurality of clock cycles can be N-1 clock cycles, t=1. For example, refer to Figure 4 For an interrupt request currently stored in the first level, in the next clock cycle, the data stored in the first-level register modules is batch-pushed to the second level of the register matrix. At this time, the register modules labeled 0, 3, and M-2 in the second level contain interrupt requests, while the other memory modules are empty. In the next clock cycle after that, the data stored in the second-level register modules is batch-pushed to the third level of the register matrix. At this time, the register modules labeled 0, 3, and M-2 in the third level contain interrupt requests, and so on, until the Nth level of the register matrix is ​​reached.

[0076] exist Figure 4 In the example, the register modules labeled 2 and M-3 in the Nth layer of the register matrix store interrupt requests. These interrupt requests are sent in batches by the functional unit in a certain clock cycle and are pushed to the Nth layer of the register matrix after the above process.

[0077] As mentioned earlier, multiple interrupt generator modules are obtained by instantiating an interrupt generator template. For each interrupt generator module, M and N are configurable parameters. For example, M is determined based on the coupled functional units, and N is determined based on the circuit area allocated to the interrupt generator module. M is determined based on the maximum number of interrupt requests that the coupled functional units may report simultaneously. N is determined based on the circuit area pre-allocated to the interrupt generator module. A larger N allows for more interrupt requests to be buffered, but on the other hand, it also occupies a larger circuit area. Therefore, the number of register matrix layers N needs to be determined by considering the resource overhead.

[0078] For example, such as Figure 4 As shown, the selection module is coupled to the Nth layer of the register matrix and configured to convert the interrupt requests stored in the M register modules of the Nth layer into serial requests and output them sequentially.

[0079] For example, the selection module can be implemented using a selector. For example, the selection module can serially send interrupt requests to the daisy chain. For example, in this case, interrupt requests can be continuously uploaded to the daisy chain whenever they are received.

[0080] Therefore, by configuring the register matrix, interrupt requests received in each clock cycle can be batched into the register matrix, and interrupt requests stored in each register module can be batched into the next register module, ensuring that batch interrupt requests reported in different clock cycles can be processed in sequence. By using a selection module to convert batch interrupt requests into serial output, arbitration conflicts caused by multiple interrupt requests being sent simultaneously are effectively avoided.

[0081] Since interrupt requests from multiple functional units are generated concurrently, and the receiving end of the advanced interrupt controller has limited interrupt processing capabilities, a certain number of interrupts will be dropped on the path. In at least one embodiment of this disclosure, a storage component can also be provided to store valid interrupt information.

[0082] For example, in the interrupt reporting processing circuit provided in at least one embodiment of this disclosure, a first storage module is further included. The first storage module is coupled to the selection module. The first storage module includes L storage units, each storage unit is configured to store interrupt information of an interrupt request, and the interrupt information of the interrupt request serially output by the selection module is cached in the first storage module.

[0083] Figure 5 This is a schematic structural diagram of an interrupt generator module provided in another embodiment of the present disclosure.

[0084] like Figure 5 As shown, the interrupt generator module also includes a first storage module, which is coupled to the selection module. The first storage module includes L storage units, which are respectively... Figure 5 There are L memory cells numbered 0, 1, ..., L-1. Each memory cell is configured to store interrupt information for one interrupt request.

[0085] For example, the selection module selects the interrupt request output from register module number 2 in layer N and caches it in memory cell number 0 in the first storage module. The cached content includes the interrupt information of the interrupt request, such as interrupt type, interrupt status, and the number of the functional unit or submodule where the interrupt occurred.

[0086] For example, the selection module selects the interrupt request output from the register module labeled M-3 in the Nth layer and caches it in the memory cell labeled 1 in the first storage module. And so on, which will not be elaborated here.

[0087] For example, when an interrupt request can be uploaded to the chain, the interrupt request in storage unit number 0 can be uploaded to the daisy chain in sequence; however, its interrupt information is still stored in the storage unit. Similarly, the same applies to interrupt requests in other storage units; even if the interrupt request has been sent to the daisy chain, its interrupt information remains in the storage unit. Although this interrupt information has been sent to the daisy chain, it may still be lost during transmission, and upstream modules or software may not be able to detect situations where interrupt requests reported by functional units have not reached the advanced interrupt controller and been recovered. By setting up a first storage module, upstream modules can actively access the first storage module to read the interrupt information generated by the corresponding functional units, understand the interrupt information reported by each functional unit, avoid missing important interrupts, understand the interruption situation of each functional unit, and locate abnormal scenarios based on the interrupt information. For example, if reading the first storage module confirms the existence of an interrupt request that has not been received, the interrupt request can be processed as needed; or if no interrupt request has been received from a certain functional unit for a long time, the working status of that functional unit can be determined by reading the first storage module.

[0088] The first storage module can store interrupt information for up to L interrupt requests. The first storage module is also configured to clear all currently stored interrupt information in the first storage module in response to a clear command.

[0089] When all L storage units contain interrupt information, other interrupt requests need to be cached in backup storage units before being passed to the daisy chain. For example, in some embodiments, the first storage module further includes at least one backup storage unit. In response to the fact that all L storage units have stored interrupt information, the interrupt requests serially output by the selection module are cached in at least one backup storage unit so that they can be sent to the daisy chain when necessary.

[0090] It should be noted that for backup storage units, each backup storage unit is cleared after a cached interrupt request is sent to the daisy chain, in order to receive the next interrupt request. In other words, the interrupt information of the interrupt requests cached in the backup storage unit is not continued to be stored; it is cleared after the interrupt request is sent to the daisy chain and used to cache the next interrupt request.

[0091] Therefore, this disclosure can ensure that interrupt information of interrupt requests sent by functional units can be retained so that upstream modules can actively read this interrupt information when needed, and can also avoid the inability to continue sending interrupt requests to the chain when there are no spare storage units due to the storage of interrupt information. It also provides cache space to provide storage function for subsequent delay control modules.

[0092] For example, in the interrupt reporting processing circuit provided in at least one embodiment of this disclosure, the interrupt generator module further includes a delay control module. The delay control module is located between the selection module and the daisy chain and is coupled to the selection module and the daisy chain. The delay control module is configured to send serial interrupt requests to the daisy chain in sequence according to a preset delay.

[0093] like Figure 5 As shown, when a first storage module is provided, a delay control module is set between the first storage module and the daisy chain. It can adjust the rate of interrupt requests sent to the daisy chain according to a preset delay, providing a delayed interrupt reporting mechanism. This effectively avoids a large number of interrupt requests being sent to the interrupt controller module through the daisy chain, and effectively alleviates the situation of a large number of interrupts reported by functional units in certain abnormal scenarios.

[0094] For example, in some embodiments, different types of interrupt masking mechanisms can be flexibly controlled at the interrupt generation end of the functional unit by setting a filtering module.

[0095] For example, in some embodiments, the interrupt generator module further includes a filtering module located between and coupled to the functional unit and the register matrix.

[0096] The filtering module is configured to filter out interrupt requests of a predetermined priority based on the priority of the interrupt requests reported by the coupled functional units, and send the remaining interrupt requests to the register matrix for storage in the register matrix.

[0097] For example, the filtering module can be implemented through registers, and the reporting of different types of interrupt requests can be controlled by register enable signals.

[0098] For example, such as Figure 5 As shown, a filtering module is also set between the functional unit and the register matrix. The filtering module receives M interrupt requests sent by the functional unit, filters out interrupt requests with predetermined priorities according to the set predetermined priorities, and sends the remaining 3 interrupt requests to the register matrix and stores them in the three register modules labeled 0, 3, and M-2 in the first layer of the register matrix.

[0099] For example, the predetermined priority can be set as needed, such as setting at least one low priority as the predetermined priority. Therefore, the filtering module can provide a flexible interrupt masking mechanism to control different types of interrupts. In certain abnormal and complex scenarios, it can effectively eliminate interference from multiple low-priority interrupt reports, preventing a certain type of interrupt from sending a large number of interrupts for a long time due to abnormal conditions, occupying the buffer and bus, and overwhelming the reporting of other types of interrupts. This avoids the circuit from causing a large number of arbitration conflicts and storage overhead due to these low-priority interrupts. Furthermore, it can flexibly mask low-priority interrupts and prioritize the identification of abnormal scenarios where high-priority interrupts are reported.

[0100] The interrupt generator module provided in at least one embodiment of this disclosure is configured with multi-level interrupt control, which flexibly controls the generation and reporting of interrupts, controls the number of interrupts reported by each functional unit, and avoids bus congestion.

[0101] For example, such as Figure 5 As shown, a filtering module is set at the entry point of the interrupt generator module to flexibly control the reporting of interrupt requests with different priorities; the register matrix pushes multiple interrupt requests received in each clock cycle to the register matrix in batches, and each layer of interrupt requests is processed in batches when entering the next layer, ensuring that interrupt requests reported in different clock cycles can be processed in sequence; the selection module converts the batch of incoming interrupt requests into serial data so as to transmit the interrupt requests of the functional unit serially in chronological order; the first storage module can cache the interrupt information of the interrupt requests output by the selection module, and temporarily cache the interrupt requests when they cannot be pushed onto the chain, and output the interrupt requests and retain the interrupt information when they can be pushed onto the chain, so that upstream modules can read them to know the interrupt-related information of the functional unit and avoid missing important interrupts; the delay control module can adjust the rate at which the functional unit sends interrupt requests onto the chain, effectively alleviating the situation of a large number of interrupts reported by the functional unit in some abnormal scenarios.

[0102] Of course, it should be noted that in some embodiments, the structure of the interrupt generator module can be adjusted as needed, and this disclosure does not limit the structure of the interrupt generator module to include... Figure 5 All components in the module can be configured as needed by those skilled in the art. Furthermore, the interrupt generator module may include more or fewer circuit elements; this disclosure does not impose specific limitations in this regard.

[0103] The interrupt controller module is responsible for interrupt collection, data packaging, control, and forwarding functions for multiple functional units (such as within an intellectual property core). The interrupt generator module implements unit-level interrupt handling, while the interrupt controller module implements IP-level interrupt handling.

[0104] Figure 6 This is a schematic structural diagram of an interrupt controller module provided in at least one embodiment of the present disclosure.

[0105] like Figure 6 As shown, the interrupt controller module includes a first selector, multiple first-in-first-out buffer modules corresponding to multiple priorities, and a second selector.

[0106] The first selector is configured to receive interrupt requests transmitted via a daisy chain and store the interrupt requests in the corresponding first-in-first-out (FIFO) cache module according to the priority of each interrupt request.

[0107] Multiple First-In-First-Out (FIFO) cache modules are configured to store interrupt requests of corresponding priorities. These multiple FIFO cache modules include... Figure 6 The IPL consists of IPLn FIFO, ..., IPL1 FIFO, and IPL0 FIFO. IPL0 represents the lowest priority, IPL1 has a higher priority than IPL0, and IPLn has the highest priority.

[0108] As mentioned earlier, interrupt requests generated by each functional unit are transmitted serially on a daisy chain via the delay module and the interrupt generator module. Interrupt requests from the daisy chain are packaged and sent to different priority FIFO (First-In-First-Out) buffer modules based on their interrupt priorities. For example, interrupt requests with priority IPLn are buffered in the IPLn FIFO buffer module, and interrupt requests with priority IPL0 are buffered in the IPL0 FIFO buffer module.

[0109] The second selector is configured to perform interrupt arbitration based on priority, sending the first interrupt request from the selected FIFO buffer module to the high interrupt controller via the bus. The FIFO buffer module with the higher priority is selected first, and the first interrupt request is the first interrupt request to enter among all the current interrupt requests of the selected FIFO buffer module.

[0110] In the interrupt controller module provided in at least one embodiment of this disclosure, interrupt types are prioritized, and high-priority interrupts are reported first. For interrupt requests generated in different scenarios, the severity of the interrupt type is determined, thereby confirming the order of priority processing. For high-priority interrupts, they are reported to the advanced interrupt controller first via the bus.

[0111] In at least one embodiment of the interrupt controller module provided in this disclosure, a data transmission scheme based on a credit mechanism with a remote advanced interrupt controller is also provided. The credit mechanism is a core mechanism for flow control. Since the interrupt processing capability of the advanced interrupt controller (AIC) is limited, this mechanism can effectively prevent interrupts from blocking the bus.

[0112] Figure 7 This is a schematic structural diagram of an interrupt controller module provided in another embodiment of the present disclosure.

[0113] like Figure 7 As shown, in at least one embodiment of this disclosure, the multiple first-in-first-out (FIFO) cache modules in the interrupt controller module also each correspond to a credit counter. For example, as Figure 7As shown, credit counter 0 corresponds to the first-in-first-out (FIFO) cache module IPL0, credit counter 1 corresponds to the first-in-first-out (FIFO) cache module IPL1, and credit counter n corresponds to the first-in-first-out (FIFO) cache module IPLn.

[0114] Each credit counter is set with an initial value that serves as the maximum limit, and this initial value is greater than 0.

[0115] For different credit counters, the initial maximum value can be the same or different. For example, the initial value of the credit counter corresponding to a high-priority FIFO buffer module can be larger, while the initial value of the credit counter corresponding to a low-priority FIFO buffer module can be smaller, so that limited transmission resources can be provided to high-priority interrupt requests that have a greater impact on the system.

[0116] The credit counter is configured such that, in response to an interrupt request from the corresponding FIFO cache module, the value of the credit counter is decremented by 1, and in response to a request response from the advanced interrupt controller for the priority corresponding to the FIFO cache module, the value of the credit counter is incremented by 1.

[0117] For example, taking credit counter n as an example, when the system powers on, credit counter n is configured with an initial value, such as 10. Afterwards, for each interrupt request output by the corresponding FIFO (In-First-Out) buffer module IPLn, the value of credit counter n is decremented by 1. If an ACK response is received from the advanced interrupt controller for an interrupt request with priority IPLn, the value of credit counter n is incremented by 1. When the advanced interrupt controller receives an interrupt request, it returns a ACK response. Due to the transmission delay, the corresponding credit counter is updated upon receiving the ACK response from the advanced interrupt controller, indicating that the advanced interrupt controller is capable of receiving interrupt requests.

[0118] For example, the highest value of the credit counter n is kept at 10 and the lowest value is 0. When the value of the credit counter n is 0, even if there are interrupt requests in the first-in-first-out buffer module IPLn FIFO, the interrupt request cannot be output to the advanced interrupt controller module.

[0119] When the second selector performs interrupt arbitration based on the priority of the interrupt request, it includes performing the following operations: in response to the fact that an interrupt request is stored in the first-in-first-out cache module corresponding to the first priority, and in response to the fact that the value of the credit counter corresponding to the first-in-first-out cache module corresponding to the first priority is not 0, the first interrupt request in the first-in-first-out cache module corresponding to the first priority is selected as the selected interrupt request, wherein the first priority is the highest priority among at least one priority corresponding to at least one first-in-first-out cache module currently storing interrupt requests, and the first interrupt request is the first interrupt request to enter among all current interrupt requests of the first-in-first-out cache module corresponding to the first priority.

[0120] For the second selector, it first selects the highest-priority FIFO (First-In, First-Out) cache module storing interrupt requests. Then, it checks if the credit counter value corresponding to that cache module is 0. If it is not 0, the first interrupt request in that cache module (the first interrupt request to enter the cache module) can be output to the bus. If it is 0, the interrupt request from that cache module cannot be selected. It then checks if the credit counter value corresponding to the next highest-priority FIFO cache module storing interrupt requests is 0. If it is not 0, the first interrupt request from that cache module can be output to the bus. If it is 0, it checks if the credit counter value corresponding to the next lower-priority FIFO cache module is 0, and so on. In other words, for high-priority interrupt requests, if the credit counter value meets the condition (e.g., greater than 0), it is reported to the higher-priority interrupt controller via the bus.

[0121] Of course, it should be noted that in the above embodiment, the credit counter value is decreased for each request sent and increased for each request received. However, the same principle can be applied to increase the credit counter value for each request sent and decrease it for each request received. The process is similar and will not be repeated here.

[0122] Furthermore, the second selector can also control the timing of the output interrupt request. For example, if the bus itself also transmits other information, the second selector can output an interrupt request to the high interrupt controller when the bus is not occupied, reducing the possibility of interrupt request loss.

[0123] In this embodiment, based on a credit mechanism, the initial values ​​of credit counters corresponding to different priorities can be different. By controlling the credit counters, interrupt requests are sent only when the conditions of the credit counter value are met. This effectively controls the number of interrupt requests sent to the advanced interrupt controller, reducing interrupt drop issues caused by the limited receiving capacity of the interrupt controller, and reducing the bus occupation caused by a large number of interrupts, avoiding bus congestion and minimizing the impact on other request transmissions. Furthermore, under the condition of meeting the credit counter value, a fixed-priority arbitration method is adopted to ensure that high-priority interrupts have priority in obtaining arbitration opportunities. Interrupt requests that obtain arbitration are converted into AXI protocol requests and sent to the advanced interrupt controller via the bus.

[0124] Since the capacity of the first-in-first-out (FIFO) cache module is limited, and the interrupt handling capability of the advanced interrupt controller is limited, a second storage module can be set up to store the discarded interrupt information.

[0125] For example, in some embodiments, the interrupt controller module further includes a second storage module, which is configured to store the received interrupt request with priority of any priority when the first-in-first-out cache module corresponding to any priority is full.

[0126] like Figure 7 As shown, the second storage module may also include multiple storage units, for example... Figure 7 The memory cells numbered 0, 1, ..., m are each configured to store interrupt information for one interrupt request.

[0127] For example, assuming the IPL1 FIFO is full, when an interrupt request with priority IPL1 is received from the daisy chain, this interrupt request can no longer be cached in the IPL1 FIFO. In this case, the interrupt request can be cached in the second storage module. Subsequently, upstream modules can actively read these interrupt information when needed to obtain interrupt information for interrupt requests that failed to be transmitted to the higher interrupt controller, improving the efficiency of locating abnormal functional units and avoiding missing important interrupts.

[0128] In the interrupt reporting processing circuit provided in at least one embodiment of this disclosure, a daisy-chain structure is designed to transmit interrupt requests from different functional units, resolving arbitration conflicts. Specifically, multiple functional units (such as functional units within an intellectual property core) are connected in series through a daisy chain, with a fixed clock cycle delay between each pair of functional units. In this way, even if multiple functional units report interrupt requests simultaneously, they will be sent to the interrupt control terminal in a serial transmission manner, effectively avoiding arbitration conflicts between multifunctional units.

[0129] Furthermore, at least one embodiment of the interrupt reporting processing circuit provided in this disclosure includes an interrupt generator module and an interrupt controller module. Both the interrupt generator module and the interrupt controller module are equipped with storage modules to cache interrupt information, preventing the loss of valid interrupt information. Moreover, upstream modules, software, and other clients cannot detect situations where interrupts reported by certain functional modules fail to reach the high-level interrupt controller and are discarded. In such cases, an active reading mechanism can be established to access each storage module (the first storage module and the second storage module) to understand the interrupt information reported by each functional unit, avoiding the omission of important interrupts and locating abnormal scenarios based on the interrupt information.

[0130] The interrupt reporting processing circuit provided in at least one embodiment of this disclosure also includes a three-level interrupt control, which flexibly controls the number of interrupt requests reported by each functional unit to avoid bus congestion. Specifically, it includes:

[0131] 1) Set up a filtering module in the interrupt generator module to flexibly control different types of interrupt masking mechanisms and effectively eliminate interference from multiple low-priority interrupt reports in some exceptionally complex scenarios.

[0132] 2) Set up a delay control module in the interrupt generator module to control the rate at which each functional unit reports interrupts to the daisy chain, effectively alleviating the situation of a large number of interrupts reported by functional units in certain abnormal scenarios.

[0133] 3) Establish a data transmission scheme based on a credit mechanism with the advanced interrupt controller in the interrupt controller module. Since the advanced interrupt controller has limited interrupt processing capabilities, this method can effectively avoid interrupt blocking the bus.

[0134] Furthermore, the interrupt controller module in the interrupt reporting processing circuit provided in at least one embodiment of this disclosure prioritizes interrupts generated in different scenarios, clarifies the severity of interrupt types, and thus determines the order of priority processing. For high-priority interrupts, under the condition that the value of the credit counter is met, they are reported to the advanced interrupt controller via the bus first, and interrupts in severe abnormal scenarios are processed first, so as to efficiently locate and resolve problems in chip operation.

[0135] At least one embodiment of this disclosure also provides an electronic device. Figure 8 A schematic structural diagram of an electronic device provided for at least one embodiment of this disclosure.

[0136] like Figure 8 As shown, the electronic device 200 includes an interrupt reporting processing circuit 100 as described in any of the above embodiments.

[0137] For details regarding the interrupt reporting processing circuit 100, please refer to the relevant descriptions in the foregoing embodiments; they will not be repeated here.

[0138] For example, in some embodiments, the interrupt generator module includes a first storage module for storing interrupt information of interrupt requests, and the electronic device is further configured to actively access the first storage module to obtain interrupt information reported by various functional units.

[0139] For example, in some embodiments, the interrupt controller module includes a plurality of first-in-first-out (FIFO) cache modules for storing interrupt requests of corresponding priorities, and a second storage module for storing interrupt requests that fail to be stored in the plurality of FIFO cache modules. The electronic device is also configured to actively access the second storage module to obtain interrupt information of interrupt requests that failed to be transmitted to the higher interrupt controller.

[0140] For example, the electronic device can be implemented as any circuit that requires interrupt reporting processing circuitry. For example, the circuit may include one circuit board or a combination of multiple circuit boards. In the embodiments of this application, the one circuit board or the combination of multiple circuit boards may include: (1) one or more processors, wherein the processor may be a general-purpose processor (such as an ARM architecture processor, x86...). (1) A processor or a dedicated processor (such as a digital signal processor (DSP) or a microcontroller (MCU); (2) One or more non-temporary memories connected to the processor, the memories may include volatile memories (such as dynamic random access memory (DRAM) or static random access memory (SRAM)) and non-volatile memories (such as flash memory (Flash) or read-only memory (ROM), wherein the non-volatile memories, in addition to storing the firmware that the processor can execute, may also pre-store the configuration parameters of the interrupt reporting processing circuit (such as interrupt priority lookup table, interrupt mask). When the electronic device is powered on, the processor can first read the configuration parameters from the non-volatile memories and send them to the interrupt reporting processing circuit to complete the initialization settings of the circuit; (3) Firmware that the processor can execute and stored in the memory, the firmware, in addition to containing the control logic of the core functions of the device, may also integrate the interrupt event processing subroutines (such as interrupt service function (ISR)). When the processor receives the interrupt event transmitted by the interrupt reporting processing circuit through the interrupt controller, it can quickly call the corresponding interrupt service function to perform preset operations (such as starting alarm, recording interrupt log, adjusting module working status).

[0141] For example, the digital circuit may include a large-scale integrated circuit. The interrupt reporting processing circuit can be integrated into the large-scale integrated circuit as an independent functional module—it can be packaged together with modules such as processors and memory into a multi-chip module (MCM), or it can be integrated monolithically with other functional modules (such as data acquisition modules and communication modules).

[0142] For example, the electronic device may include a system on chip (SOC) or similar form. An SOC can integrate interrupt reporting and processing circuits, processor cores, memory, peripheral interfaces (such as UART interfaces, SPI interfaces, GPIO interfaces) and other modules into a single chip, forming a highly integrated hardware architecture.

[0143] For example, the electronic device may include a central processing unit, a graphics processing unit, a tensor processor, or other large-scale integrated circuits with data processing and / or instruction execution capabilities. Alternatively, the electronic device may include digital circuits or digital circuit units that implement specific functions, such as field-programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs).

[0144] In addition, the electronic device may also include auxiliary circuit modules to ensure the stable operation of the interrupt reporting processing circuit. For example, it may include a power management module to provide a stable operating voltage for the interrupt reporting processing circuit; a clock module to provide a precise clock signal for the interrupt reporting processing circuit; and a reset module that generates a reset signal. Upon receiving the reset signal, the interrupt reporting processing circuit can first clear its internal cache (e.g., the first storage module, the second storage module, etc.) and configuration parameters, and then work with the processor to complete the device reset and restart, ensuring that the interrupt reporting function can work normally after the device restarts.

[0145] This disclosure does not limit the function, form, or purpose of the electronic device, and the electronic device may include the interrupt reporting processing circuit described in any embodiment of this disclosure.

[0146] Figure 9 This is a schematic diagram of the specific structure of an electronic device provided in an embodiment of the present disclosure.

[0147] The following is for reference. Figure 9 The diagram illustrates a specific structural schematic of an electronic device (e.g., a terminal device or a server) 300 suitable for implementing an interrupt reporting processing circuit including embodiments of the present disclosure.

[0148] The electronic devices in this disclosure can include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), and in-vehicle terminals (e.g., in-vehicle navigation terminals), as well as fixed terminals such as digital TVs and desktop computers. For example, the electronic device can be in the form of a server, used in various application scenarios such as deep learning and artificial intelligence, scientific computing, graphics rendering and video editing, virtual reality and game development, and cloud services. For example, the electronic device can be a dedicated server such as a data center or cloud computing center that is deployed with tasks such as deep learning training, large-scale data analysis, and high-performance computing.

[0149] Figure 9 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments disclosed herein.

[0150] like Figure 9 As shown, the electronic device 300 may include a processing device 301, such as the aforementioned processor 200, which can execute various appropriate actions and processes according to non-transitory computer-readable instructions stored in memory to achieve various functions. The processing device 301 may also include devices with instruction optimization capabilities and / or program execution capabilities, such as a central processing unit (CPU) or a tensor processor (TPU). The CPU can be based on x86, ARM, or RISC-V architectures. The GPU can be directly integrated into the SOC, directly integrated onto the motherboard, or built into the northbridge chip of the motherboard.

[0151] like Figure 9 As shown, for example, the memory may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) 303 and / or cache memory, etc., for example, computer-readable instructions may be loaded from storage device 308 into RAM 303 to execute computer-readable instructions. Non-volatile memory may include, for example, read-only memory (ROM) 302, hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. Various applications and various data, such as style images, and various data used and / or generated by the applications, may also be stored in the computer-readable storage medium.

[0152] For example, the processing device 301, the read-only memory (ROM) 302, and the random access memory (RAM) 303 are interconnected via a bus 304. The input / output (I / O) interface 305 is also connected to the bus 304.

[0153] Typically, the following devices can be connected to the input / output (I / O) interface 305: input devices 306 including, for example, a touchscreen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 307 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 308 including, for example, magnetic tape, hard disk, flash memory, etc.; and communication devices 309. Communication device 309 allows electronic device 300 to communicate wirelessly or wiredly with other electronic devices to exchange data. Although Figure 9An electronic device 300 with various devices is shown, but it should be understood that it is not required to implement or possess all of the devices shown, and the electronic device 300 may alternatively implement or possess more or fewer devices. For example, the processing device 301 may control other components in the electronic device 300 to perform desired functions.

[0154] For example, the electronic device provided in at least one embodiment of this disclosure may specifically be a general-purpose graphics processor. Figure 10 This is a schematic diagram of a general-purpose graphics processing unit (GPGPU).

[0155] like Figure 10 As shown, a general-purpose graphics processor is actually an array of programmable multiprocessors. For example, a programmable multiprocessor can be a streaming processor cluster (SPC), such as including... Figure 10 The diagram shows streaming processor clusters 1, ..., M, where M is a positive integer greater than 1. In a general-purpose graphics processor, one streaming processor cluster handles one computational task, or multiple streaming processor clusters handle one computational task. Multiple streaming processor clusters share data through a global cache or global memory.

[0156] like Figure 10 As shown, taking streaming processor cluster 1 as an example, one streaming processor cluster includes multiple computing units, such as... Figure 10 The system is structured as Computation Unit 1, Computation Unit 2, ..., Computation Unit N, where N is a positive integer. Each Computation Unit (CU) performs arithmetic and logical operations, such as accumulation, reduction, and standard addition, subtraction, multiplication, and division. A Computation Unit includes multiple Computation Cores (also called cores or computing kernels). Each Computation Core includes an Arithmetic Logic Unit (ALU), a floating-point unit, etc., and is used to execute specific computational tasks. In addition, the Computation Unit also includes registers (e.g., ...). Figure 10 The register file and shared memory in a computing unit are used to store source and destination data related to computing tasks in a hierarchical manner. The shared memory in a computing unit is used to share data between the cores of that computing unit.

[0157] like Figure 10 As shown, each computing unit also provides a tensor core for performing tensor-related computations, such as tensor shrinking operations. Tensor cores can accelerate tensor operations such as matrix multiplication. Tensor cores in multiple computing units can be scheduled and controlled uniformly.

[0158] like Figure 10As shown, each streaming processor cluster also provides a buffer for caching data across the N computing units within the streaming processor cluster.

[0159] In parallel computing, computational tasks are typically executed by multiple threads. These threads are divided into multiple thread blocks before execution in a general-purpose graphics processor (or parallel computing processor), and then dispatched via a thread block distribution module. Figure 10 (Not shown in the image) Multiple thread blocks are distributed to various computation units. All threads in a thread block must be assigned to the same computation unit for execution. Simultaneously, thread blocks are broken down into minimum execution thread bundles (or simply warps), each containing a fixed number (or less than this fixed number) of threads, for example, 32 threads. Multiple thread blocks can execute in the same computation unit or in different computation units.

[0160] In each computing unit, the thread beam scheduling / distribution module ( Figure 10 (Not shown in the diagram) Thread bundles are scheduled and allocated so that multiple computing cores within the computing unit can run thread bundles. Depending on the number of computing cores in the computing unit, multiple thread bundles within a thread block can execute concurrently or in a time-sharing manner. Multiple threads within each thread bundle execute the same instructions. Memory-executed instructions are issued to shared memory within the computing unit or further issued to intermediate-level caches, global caches, or global memory (e.g., [example cache]). Figure 10 High Bandwidth Memory (HBM) is used for read and write operations.

[0161] For example, in this embodiment, the GPU core of the graphics processor can be equipped with an interrupt reporting processing circuit to manage the interrupt reporting of multiple functional units within the GPU core. For example, the functional units may include the instruction execution unit, shared cache, instruction cache, tensor core, instruction scheduling module, in-core routing module, in-core computing module, etc. in the graphics processor.

[0162] Outside the GPU core, the graphics processing unit can also have multiple different interrupt reporting and processing circuits, each used to manage a complete functional intellectual property core, such as the on-chip network bus, the System Memory Management Unit (SMMU), and the L2 cache. For example, the interrupt reporting and processing circuit corresponding to the System Memory Management Unit can specifically be a Translation Buffer Unit (TBU) or a Translation Control Unit (TCU); similarly, the interrupt reporting and processing circuit corresponding to the L2 cache can specifically be a storage unit, a computation unit, or an execution / scheduling unit within the L2 cache. The following points also need to be clarified regarding this disclosure:

[0163] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0164] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0165] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

[0166] The following points should be noted regarding this disclosure:

[0167] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0168] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0169] The above description is only a specific embodiment of this disclosure, but the protection scope of this disclosure is not limited thereto. The protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. An interrupt reporting processing circuit, characterized in that, This is used to serially report interrupt requests generated by multiple functional units to the higher interrupt controller, whereby the interrupt requests from these multiple functional units are processed uniformly. The interrupt reporting and processing circuit includes multiple interrupt generator modules coupled one-to-one with the multiple functional units, a daisy chain for mounting the multiple interrupt generator modules, and an interrupt controller module located at the end of the daisy chain. Each interrupt generator module is configured to buffer interrupt requests from coupled functional units and serially output the received interrupt requests to the daisy chain. A delay module is coupled between every two interrupt generator modules. The delay module is configured to generate a delay of a fixed clock period. The interrupt controller module is coupled to the advanced interrupt controller via a bus. The interrupt controller module is configured to buffer interrupt requests received through the daisy chain according to priority, perform interrupt arbitration according to the priority of the interrupt requests, and transmit the selected interrupt requests to the advanced interrupt controller via the bus.

2. The interrupt reporting processing circuit according to claim 1, characterized in that, The interrupt generator module supports the coupled functional units to report up to M interrupt requests simultaneously. The interrupt generator module includes a register matrix and a selection module. The register matrix comprises N layers, each layer containing M register modules. The register matrix is ​​configured to store interrupt requests reported by the coupled functional units in batches, with interrupt requests reported in the same clock cycle stored in the same layer of the register matrix. The selection module is coupled to the Nth layer of the register matrix and configured to convert the interrupt requests stored in the M register modules of the Nth layer into serial requests and output them sequentially. Where M and N are positive integers.

3. The interrupt reporting processing circuit according to claim 2, characterized in that, The interrupt requests reported by the coupled functional units within one clock cycle are first stored in the first layer of the register matrix. In multiple clock cycles following the first clock cycle, the interrupt requests stored in the first layer of the register matrix are entered into the next layer of the register matrix in batches every t clock cycles, until they enter the Nth layer of the register matrix, where t is a positive integer.

4. The interrupt reporting processing circuit according to claim 2, characterized in that, The interrupt generator module further includes a first storage module, which is coupled to the selection module. The first storage module includes L storage units, each configured to store interrupt information for one interrupt request. The interrupt information of the interrupt request serially output by the selection module is cached in the first storage module.

5. The interrupt reporting processing circuit according to claim 4, characterized in that, The first storage module is also configured to, in response to receiving a clear command, clear all interrupt information currently stored in the first storage module. The first storage module also includes at least one backup storage unit. Since all L storage units have stored interrupt information, the interrupt request serially output by the selection module is cached in at least one backup storage unit so that it can be sent to the daisy chain when needed. Each backup storage unit is cleared after a cached interrupt request is sent to the daisy chain in order to receive the next interrupt request.

6. The interrupt reporting processing circuit according to claim 2, characterized in that, The selection module serially sends the interrupt request to the daisy chain.

7. The interrupt reporting processing circuit according to claim 2, characterized in that, The interrupt generator module further includes a delay control module, which is located between and coupled to the selection module and the daisy chain. The delay control module is configured to send the interruption request sequentially to the daisy chain according to a preset delay.

8. The interrupt reporting processing circuit according to claim 2, characterized in that, The multiple interrupt generator modules are obtained by instantiating an interrupt generator template. M and N are configurable parameters for each interrupt generator module, where M is determined based on the coupled functional unit and N is determined based on the circuit area allocated to the interrupt generator module.

9. The interrupt reporting processing circuit according to claim 2, characterized in that, The interrupt generator module further includes a filtering module, which is located between and coupled to the functional unit and the register matrix. The filtering module is configured to, based on the priority of the interrupt requests reported by the coupled functional units, block interrupt requests of a predetermined priority and send the remaining interrupt requests to the register matrix for storage in the register matrix.

10. The interrupt reporting processing circuit according to claim 1, characterized in that, The interrupt controller module includes a first selector, multiple first-in-first-out buffer modules corresponding to multiple priorities, and a second selector. The first selector is configured to receive the interrupt request transmitted by the daisy chain and store the interrupt request in the corresponding first-in-first-out cache module according to the priority of each interrupt request; The multiple first-in-first-out (FIFO) cache modules are configured to store interrupt requests of corresponding priorities respectively; The second selector is configured to perform interrupt arbitration based on the priority of the interrupt request, and send the first interrupt request in the selected first-in-first-out buffer module to the advanced interrupt controller through the bus. The first interrupt request is the first interrupt request that enters among all the current interrupt requests of the selected first-in-first-out buffer module.

11. The interrupt reporting processing circuit according to claim 10, characterized in that, Each of the multiple first-in-first-out (FIFO) cache modules also corresponds to a credit counter. The credit counter is set with an initial value as its maximum limit. The credit counter is configured such that, in response to an interrupt request from the corresponding FIFO cache module, the value of the credit counter is decremented by 1; and in response to receiving a request response from the advanced interrupt controller for the priority corresponding to the FIFO cache module, the value of the credit counter is incremented by 1. When the second selector performs interrupt arbitration based on the priority of the interrupt request, it includes performing the following operations: In response to the presence of an interrupt request stored in the first-priority FIFO cache module, and in response to the fact that the value of the credit counter corresponding to the first-priority FIFO cache module is not 0, the first interrupt request in the first-priority FIFO cache module is selected as the selected interrupt request, wherein the first priority is the highest priority among at least one priority corresponding to at least one FIFO cache module currently storing an interrupt request.

12. The interrupt reporting processing circuit according to claim 10, characterized in that, The interrupt controller module also includes a second storage module. The second storage module is configured such that when the first-in-first-out cache module corresponding to any priority is full, the storage receives an interrupt request with the priority of that priority.

13. The interrupt reporting processing circuit according to claim 1, characterized in that, The multiple functional units belong to the same intellectual property core.

14. An electronic device, characterized in that, Includes the interrupt reporting processing circuit as described in any one of claims 1-13.

15. The electronic device according to claim 14, characterized in that, The interrupt generator module includes a first storage module for storing interrupt information of the interrupt request. The electronic device is also configured to actively access the first storage module to obtain interrupt information from interrupt requests reported by each functional unit.

16. The electronic device according to claim 14, characterized in that, The interrupt controller module includes multiple first-in-first-out (FIFO) buffer modules for storing interrupt requests of corresponding priorities, and a second storage module for storing interrupt requests that failed to be stored in the multiple FIFO buffer modules. The electronic device is also configured to actively access the second storage module to obtain interrupt information for interrupt requests that failed to be transmitted to the advanced interrupt controller.

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