ROM (Read Only Memory), data reading method thereof and electronic equipment

Abstract

The invention relates to the technical field of memories, and particularly provides an ROM (Read Only Memory), a data reading method thereof and electronic equipment, and the ROM comprises a storage circuit, a reference circuit, a comparison circuit and a cross coupling circuit, the storage circuit comprises a multiplexer and a storage array; the voltage-time change slope of the reference voltage generated by the reference circuit is smaller than the slope when the memory unit reads 0 and larger than the slope when the memory unit reads 1; the grid electrodes of the two first MOS tubes of the comparison circuit are directly connected and are respectively connected with the reference circuit and the storage circuit; and the cross coupling circuit is connected with the comparison circuit and is used for comparing the reference voltage with the reading voltage and determining a corresponding output reading digital signal. The problems that due to the fact that an ROM is large in capacity and high in load, voltage input into a phase inverter changes slowly, the reading speed of the phase inverter is low, and misreading is prone to occurring in the prior art are solved.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of memories, in particular to a ROM memory and a data reading method thereof and an electronic device. BACKGROUND

[0002] In the related art, a ROM memory comprises a multiplexing circuit 200*, a storage matrix 100*, and an inverter. Figure 1 As shown in the figure, the multiplexing circuit 200* can select to open one column BL, and the WL can select to open one row, so as to lock a certain storage unit in the storage matrix 100*. The storage matrix 100* comprises a plurality of storage units N11*, N12* and N13* arranged in an array, which are composed of field effect transistors; the transistors can be programmed to determine whether the gate is connected to the word line WL and whether the source level or the drain is connected to the bit line BL. If the source level or the drain of the transistor is connected to the ground after programming, 0 is stored, and in another case, if the source level or the drain of the transistor is not connected to the ground after programming, 1 is stored. The inversion voltage of the inverter is a fixed threshold value, and the GBL output voltage reaches the inversion voltage of the inverter and then outputs a corresponding signal after passing through two-stage inverters.

[0003] However, the memory capacity of the ROM is large, and the load on the BL is heavy, which leads to a large slope of the input voltage signal of the inverter, slow voltage change of the input inverter, and slow reading speed of the inverter. The leakage of the MOS tube on the small-size process is relatively obvious, which may cause the problem that in the case of reading 1, the GBL leaks to the low level to cause the inverter to flip, and thus the wrong value is read out.

[0004] In view of the problem that the ROM read-only memory in the related art has a large capacity and high load, which leads to slow voltage change of the input inverter, slow reading speed of the inverter, and easy reading error, no effective solution has been proposed at present. SUMMARY

[0005] The ROM memory and the data reading method thereof and the electronic device provided by the embodiments of the application at least solve the problem that the ROM read-only memory in the related art has a large capacity and high load, which leads to slow voltage change of the input inverter, slow reading speed of the inverter, and easy reading error.

[0006] According to one aspect of the present application, a ROM memory is provided, comprising a storage circuit, a reference circuit, a comparison circuit and a cross-coupling circuit; the storage circuit comprises a multiplexer and a storage array, the storage array comprises a plurality of storage cells arranged in an array; the reference circuit is configured to generate a reference voltage based on a reference load during reading, wherein the reference voltage is less than a read voltage of the storage circuit when reading 1 and greater than the read voltage of the storage circuit when reading 0, wherein the read voltage is an output voltage of the storage circuit when reading the storage data of the storage cell; the comparison circuit comprises two first MOS transistors, the gates of the two first MOS transistors are connected to the reference circuit and the storage circuit respectively, and the gates of the two first MOS transistors are directly connected; the cross-coupling circuit is connected to the comparison circuit and configured to compare the reference voltage and the read voltage to determine a corresponding output read digital signal.

[0007] As an optional solution, the cross-coupling circuit comprises two cross-coupled second MOS transistors; both the second MOS transistors are PMOS transistors, the gate of the second MOS transistor is connected to the drain of the other second MOS transistor, and the source of the second MOS transistor is connected to a high-voltage source; the gate of the second MOS transistor is also connected to the drain of the corresponding first MOS transistor, and the gate of the second MOS transistor is connected as an output terminal of the cross-coupling circuit and configured to output the read digital signal.

[0008] As an optional solution, the output terminal is further provided with an inverter.

[0009] As an optional solution, the gates of the two first MOS transistors are respectively connected to the source and the drain of an NMOS transistor.

[0010] As an optional solution, a pre-charging device is further included, and the pre-charging device is connected to the reference circuit and the storage circuit; the pre-charging device is provided with two independent pre-charging devices, and the reference circuit and the storage circuit are respectively provided with independent pre-charging devices.

[0011] As an optional solution, both the second MOS transistors are provided with independent pull-up circuits.

[0012] As an optional solution, the pre-charging device and the pull-up circuit are both PMOS transistors; the gate of the PMOS transistor is enabled by a pre-charging signal, the source of the PMOS transistor is connected to a high-voltage source, and the drain of the PMOS transistor is connected to the pre-charging and pull-up circuits.

[0013] As an optional solution, the reference load of the reference circuit is greater than the minimum load of any read bit line and less than the maximum load of any read bit line, so that the voltage-time variation slope of the reference voltage is less than the voltage-time variation slope when the storage unit reads 0 and greater than the voltage-time variation slope when the storage unit reads 1, wherein the read bit line is the bit line corresponding to the multiplexer in the storage array during reading.

[0014] As an optional solution, the reference circuit includes a larger number of third MOS tubes on the read bit line and the same number of storage units as reference units, and a plurality of the third MOS tubes are connected in series; one end of the source level or the drain of the reference unit is connected to the bit line, and the other end is connected to the ground, so that all the reference units are stored as 0; the gate of one of the reference units is connected to the corresponding virtual bit line, so that any corresponding bit line in the storage array is enabled, and the virtual bit line is enabled; the gates of the remaining storage units in the reference unit are set to low level to ensure that the storage units are in the closed state.

[0015] According to another aspect of the present application, a data reading method of a ROM memory is also provided, comprising: keeping the reference voltage of the reference circuit consistent with the read initial voltage value of the read voltage of the storage circuit by two first MOS tubes of a comparison circuit, wherein the gates of the two first MOS tubes are connected to the reference circuit and the storage circuit respectively, and the gates of the two first MOS tubes are directly connected; selecting the read voltage of the bit line of the storage unit to be read based on the multiplexer of the storage circuit, wherein the storage circuit comprises a multiplexer and a storage array, and the storage array comprises a plurality of storage units arranged in an array; obtaining the reference voltage based on the reference circuit, wherein the reference voltage is less than the read voltage of the storage circuit when reading 1 and greater than the read voltage of the storage circuit when reading 0, wherein the read voltage is the output voltage of the storage circuit when reading the storage data of the storage unit; inputting the reference voltage and the read voltage into the comparison circuit, and outputting the corresponding read digital signal from the cross-coupled circuit, wherein the comparison circuit is connected to the cross-coupled circuit, and is used to compare the reference voltage and the read voltage to determine the corresponding output read digital signal.

[0016] As an optional solution, by comparing the two first MOS tubes of the comparison circuit, the method further comprises: independently pre-charging the reference circuit and the storage circuit by independent pre-charging devices, wherein the pre-charging devices are provided with two, and the two pre-charging devices are connected with the reference circuit and the storage circuit respectively; and the corresponding nodes of the cross-coupled circuit are pulled up in level by independent pull-up circuits, wherein the cross-coupled circuit is connected with the independent pull-up circuits.

[0017] According to another aspect of the present application, there is also provided an electronic device comprising any of the ROM memories described above.

[0018] The ROM memory provided by the embodiments of the present application adopts a comparison circuit and a reference circuit, and the reference circuit can generate a voltage change signal with a slope between the voltage of reading 0 of a storage unit and the voltage of reading 1 of the storage unit when reading data, so that the output data signal can be quickly determined according to the reference voltage and the reading voltage when reading data. The gates of the two first MOS tubes of the comparison circuit are directly connected, and the levels of the reference circuit and the storage circuit are pulled to the same level at the pre-charging stage, so that the misadjustment of the comparison circuit is reduced to a certain extent, and the problem of reading error caused by the voltage difference is avoided. Thus, the problems of high load of the ROM memory, large slope of the input end of the inverter, slow voltage change of the input inverter and slow reading speed and easy reading error in the related art are solved, and the technical effects of faster reading after comparison of the reference voltage and the reading voltage and avoiding reading error are achieved. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can also obtain other embodiments according to these drawings without creative labor.

[0020] Figure 1 is a schematic diagram of the structure of the ROM memory of the prior art.

[0021] Figure 2 is a schematic diagram of the structure of the ROM memory of the embodiments of the present application.

[0022] Figure 3 is a flowchart of the implementation process of the ROM memory of the embodiments of the present application.

[0023] Figure 4 is a schematic diagram of the voltage state of GBL and RBL in the ROM memory of the present application.

[0024] The reference numerals in the above figures are as follows: 100, storage array; 100*, storage matrix; 200, multiplexer; 200*, multiplexing circuit; 300, sense amplifier; 400, reference circuit; 500, precharge device. Detailed Implementation

[0025] Embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. While some embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0026] like Figure 1 As shown, a traditional ROM (Read-Only Memory) memory includes: a pre-charge device, a multiplexer circuit 200*, a storage matrix 100*, and an inverter.

[0027] The precharge device pulls the precharge enable low to turn on the PMOS (P-channel metal-oxide-semiconductor field-effect transistor) for precharge. After pulling the bit line to VDD (power supply voltage), the precharge enable is pulled high to turn the PMOS off.

[0028] In the multiplexing circuit 200*, NMOS (N-type Metal-Oxide-Semiconductor Field-Effect Transistor) transistors N21*, N22*, and N23* can be selected to enable one column of BL (Bit Line) and WL (Word Line) can be selected to enable one row, thus locking a specific memory cell N11*, N12*, or N13* in the memory matrix 100*.

[0029] The memory array 100 includes a plurality of memory cells arranged in an array, which are composed of field effect transistors, the gates of which can be connected to a word line WL by programming, and the source level or the drain level of which can be connected to a bit line BL by programming. If the source level or the drain level of the transistor is connected to the ground after programming, 0 is stored; otherwise, 1 is stored. The GBL (Global Bit Line) outputs 0 after two inverters, and outputs 1 after two inverters if the BL state is high after pre-charging.

[0030] Therefore, the time for reading 0 is determined by the speed of the inverter. Since the memory capacity of the ROM is large, the load on the BL is heavy, the slope of the input end of the inverter is large, the voltage change of the input of the inverter is slow, and the reading speed of the inverter is slow. In a small-size process, the leakage of the MOS (Metal-Oxide-Semiconductor) tube is obvious, which may cause the GBL to leak to the low level in the case of reading 1, so that the inverter is flipped, and the wrong value is read out.

[0031] According to one aspect of the present application, a ROM memory is provided, which includes a memory circuit, a reference circuit 400, a comparison circuit and a cross-coupling circuit; the memory circuit includes a multiplexer 200 and a memory array 100, and the memory array 100 includes a plurality of memory cells arranged in an array; the reference circuit 400 is configured to generate a reference voltage based on a reference load during reading, wherein the reference voltage is smaller than the reading voltage of the memory circuit during reading 1, and is larger than the reading voltage of the memory circuit during reading 0, wherein the reading voltage is the output voltage of the memory circuit when reading the stored data of the memory cell; the comparison circuit includes two first MOS tubes N32 and N33, the gates of the two first MOS tubes N32 and N33 are connected to the reference circuit 400 and the memory circuit respectively, and the gates of the two first MOS tubes N32 and N33 are directly connected; the comparison circuit is connected to the cross-coupling circuit, and is configured to compare the reference voltage and the reading voltage, and determine the corresponding output reading digital signal.

[0032] In the embodiment of the present application, the memory circuit provided by the present application includes the multiplexer 200 and the memory array 100, and the memory array 100 includes a plurality of memory cells arranged in an array. Figure 2As shown, the array includes a multiplexer 200 and a memory array 100. The multiplexer 200 consists of multiple NMOS transistors arranged in rows, including N21, N22, and N23. The gates of these NMOS transistors are selected by the SEL (select function) to enable one column of bit lines. Their drains are connected to the GBL (Gateway Block Layer), and their sources are connected to each bit line. The memory array 100 includes multiple memory cells arranged in an array. These cells include NMOS transistors N11, N12, N13, N14, N15, N16, N17, N18, and N19. These NMOS transistors can be programmed to determine whether their gates are connected to word lines and whether their sources or drains are connected to bit lines. If the transistor's source or drain is grounded after programming, a 0 is stored; otherwise, if the transistor's source or drain is not grounded after programming, a 1 is stored.

[0033] The reference circuit 400 provided in the embodiments of the present invention, such as... Figure 2 As shown, the drain of N41 in the reference circuit 400 is connected to the drain of P51 in the precharge device, and the drain of N41 in the reference circuit 400 is connected to the gate of N32 in the comparator circuit.

[0034] In related technologies, the scheme using inverters for reading data suffers from limitations imposed by the inverter's flip voltage and flip time, leading to increased read time and significant leakage. This can cause the GBL to leak to a low level when reading a 1, causing the inverter to flip and resulting in an incorrect reading of a 0. For example... Figure 4 As shown, the black line of RBL (Read Bit-Line) represents the reference voltage change, the red line of GBL represents the voltage change when reading 0 from the memory cell, and the blue line of GBL represents the voltage change when reading 1 from the memory cell. When reading data, the reference circuit 400 can generate a voltage change signal with a slope that is always between reading 0 and reading 1 from the memory cell. When reading data, the output data signal can be quickly determined based on the magnitude of the reference voltage and the reading voltage of the memory cell, avoiding the reading voltage at the time of reading 1 decaying to the toggling threshold of the inverter when the reading time is long, which would lead to reading errors.

[0035] The cross-coupling circuit and comparator circuit used in this embodiment together constitute a possible sensing amplifier. The sensing amplifier can be a voltage-type sensing amplifier or a current-type sensing amplifier. The function of the sensing amplifier is to rapidly amplify the weak voltage difference output from the memory cell to a standard logic level, thereby achieving accurate data reading. The sensing amplifier has a relatively sensitive and accurate voltage comparison function, and can be directly applied to ROMs without requiring changes to the ROM design circuit, resulting in low modification costs.

[0036] The comparison circuit has two input terminals connected to the N41 drain of the reference circuit 400 and the N23 drain of the storage circuit respectively. The comparison circuit has the function of comparing the sizes of two voltages, and can be analog comparison circuit, digital comparison circuit, and mixed signal comparison circuit. In this example, a digital comparison circuit is used, which has the advantages of low cost, flexibility, and seamless integration with digital systems.

[0037] Because the loads of the reference circuit 400 and the storage circuit are different, the initial voltages reached during pre-charging are different, which can easily cause a voltage difference between the reference voltage and the read voltage at the beginning of data reading. This voltage difference is not caused by reading, but by pre-charging. The voltage difference is not consistent with the relationship between the read voltage and the reference voltage, which can cause the comparison circuit to output incorrect results when comparing the reference voltage and the read voltage, and the actual reading results are different.

[0038] Connecting the two input terminals of the comparison circuit can level the reference voltage and the read voltage during pre-charging, eliminating the voltage difference, so that the comparison of the true read voltage and the reference voltage is not affected during reading, ensuring fast and accurate reading.

[0039] Because the loads of the reference circuit 400 and the storage circuit are different, a voltage difference can easily occur after pre-charging, which can further cause the comparison circuit to output incorrect data based on the voltage difference and cause reading errors. The gates of the two first MOS transistors N32 and N33 of the comparison circuit are connected to the reference circuit 400 and the storage circuit respectively, and the gates of the two first MOS transistors N32 and N33 are directly connected. During the pre-charging phase, the reference circuit 400 and the storage circuit are simultaneously pulled to the same level, which can reduce the bias of the comparison circuit to some extent, achieving the technical effect of avoiding reading errors.

[0040] As an optional solution, the cross-coupled circuit includes two cross-coupled second MOS transistors P36 and P37. Both of the two second MOS transistors P36 and P37 are PMOS transistors. The gate of the second MOS transistor P36 is connected to the drain of the other second MOS transistor P37, and the sources of the second MOS transistors P36 and P37 are connected to a high-voltage source. The gates of the second MOS transistors P36 and P37 are also connected to the drains of the corresponding first MOS transistors N32 and N33, and the gates of the second MOS transistors P36 and P37 are connected as the output terminals of the cross-coupled circuit and are configured to output the read digital signal.

[0041] When the PMOS tube is turned on, the drain is close to the source voltage, and the gate voltage of the PMOS tube is reduced to enhance the conduction, and the gate voltage of the PMOS tube is increased to weaken the conduction. When the input signal of the storage circuit slightly reduces the gate voltage of the PMOS tube P36, the drain voltage of P36 will rise, and the gate voltage of another PMOS tube P37 will rise, which will weaken the conduction of P37, resulting in the reduction of the drain voltage of P37, and further reducing the gate voltage of P36. This positive feedback can quickly amplify the small input difference, and finally stabilize the two output terminals in high and low two clear states, realizing the amplification of the input signal.

[0042] The cross-coupled circuit structure can stably latch the output state and realize data storage. Once the output state is triggered by the input signal, the positive feedback will maintain the output state even if the input signal disappears. This feature enables the cross-coupled circuit to latch the read digital signal, ensuring that the signal state remains stable before subsequent circuit processing, and avoiding data errors caused by input signal fluctuations.

[0043] In the cross-coupled circuit, the second MOS tube can be a PMOS tube or an NMOS tube. In this embodiment, a PMOS tube is used as the second MOS tube. The carrier of PMOS is a hole, and when it is turned on under high voltage source, the drain output voltage is closer to the high voltage source, and the high level swing is larger, which is better matched with the high level standard of digital circuit. When the source is connected to high voltage, the gate voltage of PMOS has a larger dynamic range, and the sensitivity to weak input signals is higher, which is beneficial to detecting small amplitude signal differences. Compared with NMOS tube, the noise coefficient of PMOS tube under the same process may be lower, reducing the noise interference in the signal amplification process and improving the comparison accuracy.

[0044] In this embodiment, two cross-coupled PMOS tubes P36 and P37 can realize the functions of amplification and latching, without additional complex modules. The multi-stage amplification circuit in the traditional sense amplifier is omitted, reducing the number of devices, chip area and power consumption, and suitable for high-density integrated scenarios.

[0045] As an optional solution, the output end is also provided with an inverter.

[0046] The output end OUT1 of the cross-coupled circuit is provided with an inverter connected to the gate of the second MOS tube P37 and the drain of the second MOS tube P36, and the output end OUT2 is provided with an inverter connected to the gate of the second MOS tube P36 and the second MOS tube P37.

[0047] The function of the inverter is signal inversion, which can correct the phase deviation by one inversion, so that the phase of the output signal matches the timing logic of the subsequent circuit.

[0048] The cross-coupled circuit composed of PMOS tubes P36 and P37 outputs a high level close to the high voltage source VDD (such as 5V), but the subsequent digital circuit can work in a low voltage domain (such as 3.3V). If the inverter is powered by a 3.3V power supply, the 5V high level input by the cross-coupled circuit can be converted into a 3.3V high level, and the low level can be converted from the upper limit bottleneck (such as 4.5V) of the output voltage close to the conduction of the MOS tube to close to 0V, so that the output level strictly matches the high and low level thresholds of the subsequent circuit, avoiding logic misjudgment.

[0049] The comparison circuit and the subsequent circuit can work in different noise environments (such as the comparison circuit close to the analog signal source, easy to be disturbed by noise; the subsequent digital circuit has large switching noise, etc.), and the inverter can be used as an isolation stage to reduce the reverse conduction of noise from the subsequent circuit to the comparison circuit, avoiding interference with the detection accuracy of the weak signal by the comparison circuit. The input impedance of the inverter is high, and the output of the comparison circuit is small, ensuring the stable working point of the comparison circuit.

[0050] The purpose of setting the inverter at the output end of the comparison circuit is to optimize the output signal characteristics through level matching, enhanced driving, noise shaping, phase adjustment and isolation protection, ensure compatibility with the subsequent circuit, and improve the reliability and stability of the entire system.

[0051] As an optional solution, the gates of the two first MOS tubes N32 and N33 are connected to the source and drain of an NMOS tube N34, respectively.

[0052] The first MOS tube can be a PMOS tube or an NMOS tube. In this embodiment, an NMOS tube is used as the first MOS tube, mainly because the voltage characteristics of the NMOS tube adapt to the logic conversion requirements of different level domains, the threshold voltage is low and stable, which is beneficial to low-voltage operation and power consumption reduction. The NMOS tube can realize signal amplification, latching and other functions in cooperation with the cross-coupled circuit composed of PMOS tubes. The conduction characteristics of the NMOS tube are also convenient for signal control transmission; at the same time, the NMOS tube has good compatibility in manufacturing process and low cost, is suitable for large-scale integration, and can guarantee the overall performance and reliability of the circuit.

[0053] The source and drain of the NMOS tube N34 form a stable voltage difference in the opening stage, and the voltage difference is applied to the gate of the two first MOS tubes N32 and N33 as an input signal, which can balance the voltage difference of the two first MOS tubes N32 and N33, so that the voltage of RBL and GBL is consistent at the initial moment of reading, and then the signal difference is transmitted to the cross-coupled circuit through the first MOS tubes N32 and N33 in the comparison, and finally the comparison result is output. The gate of the NMOS tube N31 is connected to the enable pre-charge signal, the drain of the NMOS tube N31 is connected to the source of the first MOS tube N32 and the first MOS tube N33, and the source of the NMOS tube N31 is grounded. The NMOS tube N31 is turned on at a low level, and the comparison circuit is quickly discharged.

[0054] In the pre-charge stage, the NMOS tube N34 is turned on, and the gate capacitances of the first MOS tubes N32 and N33 are charged through the source and drain of the NMOS tube N34, so as to avoid slow voltage change caused by node capacitance discharge and make the gate voltage reach a stable value in a short time. After entering the reading stage, the pre-charge tube N34 is turned off, and the difference between the signals input by the GBL of the storage circuit and the RBL of the reference circuit 400 can be directly reflected by the conduction state of the first MOS tube, without waiting for the natural charge and discharge of the node, so as to greatly shorten the response time of the comparison circuit.

[0055] The voltage difference between the source and drain of the NMOS tube N34 is used as a differential input signal, and the conduction state of the first MOS tubes N32 and N33 is determined by the voltage difference. The differential structure has the ability to suppress common-mode noise, so that the voltage difference between the source and drain of the NMOS tube N34 remains basically unchanged, and the gate voltage difference of the first MOS tubes N32 and N33 is not disturbed, thereby ensuring the accuracy of the comparison result.

[0056] The above common-mode noise includes simultaneous increase or decrease of the source and drain voltages caused by power supply fluctuation and environmental interference, and the common-mode noise will simultaneously affect the source and drain voltages.

[0057] In the pre-charge stage, the gate voltage of the first MOS tubes N32 and N33 is stabilized near the critical conduction, and even if the difference between the input signals is very small, the conduction current of the two first MOS tubes N32 and N33 will also be significantly different in the reading stage of the comparison circuit, because the MOS tube is very sensitive to the voltage difference between the gate and the source. The current difference will further affect the gate voltage of the subsequent cross-coupled circuit, and finally be amplified into clear high and low levels through the positive feedback effect of the cross-coupling, so as to realize accurate comparison of the tiny signal.

[0058] As an optional solution, the pre-charge device 500 is further included, and the pre-charge device 500 is connected with the reference circuit 400 and the storage circuit. The pre-charge device 500 is provided with two, and the reference circuit 400 and the storage circuit are respectively provided with independent pre-charge devices 500.

[0059] As shown in Figure 2 P51 drain of the pre-charge device 500 is connected with the reference bit line RBL of the reference circuit 400, and P52 drain of the pre-charge device 500 is connected with the global bit line GBL of the storage circuit.

[0060] The pre-charge device 500 pre-charges the bit lines of the storage circuit and the bit lines of the reference circuit 400, and sets the PREEN signal to low to turn on P51 and P52 for pre-charging to pull up the GBL and RBL to VDD.

[0061] The connection of the storage circuit with the pre-charge device 500 is to quickly charge the bit line to high to prepare for reading 0 state, and the connection of the reference circuit 400 with the pre-charge device 500 is to charge the reference bit line to VDD, and the voltage value of the reference bit line needs to be stable and accurate.

[0062] If one pre-charge device 500 is shared, the charging time may not be consistent due to load difference, and the charge and discharge noise of the storage circuit may interfere with the stability of the reference voltage. Setting multiple pre-charge devices 500 can ensure that the timing of each circuit does not affect each other, and the charging current or timing can be adjusted according to the respective needs.

[0063] The pre-charge power consumption of the storage circuit is usually high, while the reference circuit 400 only needs to maintain a small stable current. In standby state, only the pre-charge of the reference circuit 400 can be activated to maintain the stability of the reference voltage, and the pre-charge of the storage circuit can be suspended to further reduce power consumption. Independent power supply can avoid overdesigning the power supply of the reference circuit 400 to meet the storage pre-charge requirements, and achieve the effect of reducing overall power consumption.

[0064] As an optional solution, both the second MOS tubes P36 and P37 are provided with independent pull-up circuits.

[0065] Two independent pull-up circuits, as shown in Figure 2 P35 and P38 respectively pull up the A and B nodes of the P36 and P37 drains, the drains of P35 and P38 are respectively connected with the drains of P36 and P37, and the sources of P35 and P38 are connected with the positive power supply. The gates of PMOS in the pull-up circuit are controlled by the enable signal.

[0066] The two second MOS tubes P36 and P37 in cross-coupling may have mismatch due to manufacturing process difference, which may cause static error voltage of the comparison circuit. The independent pull-up circuit can adjust the pre-charge voltage of the two paths through digital calibration to offset such error and ensure that the initial states of the two are consistent in the evaluation stage.

[0067] The environmental temperature or power voltage fluctuation may cause parameter drift of the MOS tubes P36 and P37, and the independent pull-up circuit can adjust the node voltage in real time to maintain the stability of the comparison threshold.

[0068] Through independent clock control, the overlapping operation can be realized, the bit line of the next unit is pulled high in advance when the current storage unit is read, the waiting time is reduced, and the access speed of the ROM is improved.

[0069] The independent pull-up circuit can reduce the current of the charging path by adjusting the size of the MOS tube, reduce the power supply noise and dynamic power consumption, and compared with the shared pull-up circuit, the independent design can avoid the instantaneous large current impact caused by the simultaneous pull-up of multiple paths.

[0070] As an optional solution, the pre-charging device 500 and the pull-up circuit are both PMOS tubes; the gate of the PMOS tube enables the pre-charging signal, the source of the PMOS tube is connected to the high-voltage source, and the drain of the PMOS tube is connected to the circuit to be pre-charged and pulled up.

[0071] As shown in the pre-charging device 500 provided by the embodiment of the application, Figure 2 The PMOS tubes P51 and P52 are connected to the gate of the enable pre-charging signal, the source of P51 and P52 is connected to the high-voltage source, the drain of P51 is connected to the RBL of the reference circuit 400, and the drain of P52 is connected to the GBL of the storage circuit; the PMOS tubes P35 and P38 are connected to the gate of the enable signal, the source of P35 and P38 is connected to the high-voltage source, the drain of P35 is connected to the drain of P36, and the drain of P38 is connected to the drain of P37.

[0072] The PMOS tube is usually used to pull the pre-charged node to VDD, and the NMOS tube is suitable for quickly pulling the node to GND; in the pre-charging device, the pre-charging device 500 uses the PMOS tube to pre-charge the memory bit line to VDD, and then discharges through the storage unit to determine 0 or 1; the PMOS tube is used in the comparison circuit to pre-charge and establish the reference voltage.

[0073] As an optional solution, the reference load of the reference circuit 400 is greater than the minimum load of any read bit line and less than the maximum load of any read bit line, so that the voltage-time variation slope of the reference voltage is less than the voltage-time variation slope when the storage unit reads 0, and greater than the voltage-time variation slope when the storage unit reads 1, wherein the read bit line is the bit line corresponding to the storage array 100 in the read and the multiplexer 200.

[0074] In the related art, the scheme of using an inverter for reading is limited by the inverter flip voltage and flip time, which increases the readout time and causes obvious leakage, which may cause the GBL to leak to the low level in the case of reading 1, causing the inverter to flip and thus reading the wrong value 0. Figure 4As shown, the RBL (Read Bit-Line) black line represents the reference voltage change, the GBL red line represents the voltage change when the memory cell reads 0, and the GBL blue line represents the voltage change when the memory cell reads 1; when reading data, the reference circuit 400 can generate a voltage change signal with a slope always between the voltage when the memory cell reads 0 and the voltage when the memory cell reads 1, and can quickly determine the output data signal according to the reference voltage and the memory cell reading voltage when reading data, thereby avoiding the problem of reading error caused by the reading voltage when reading 1 decaying to the inverter flip threshold value in the case of long reading time.

[0075] As an optional solution, the reference circuit 400 includes a larger number of third MOS tubes N41, N42, N43, N44 on the read bit line, and the same number of memory cells N45, N46 as reference cells, and the plurality of third MOS tubes N41, N42, N43, N44 are connected in series; one end of the source level or the drain of the reference cells N45, N46 is connected to the bit line, and the other end is connected to the ground, so that all the reference cells are stored as 0; the gate of one of the reference cells N45 is connected to the corresponding virtual bit line, so that any corresponding bit line in the memory array 100 is enabled, and the virtual bit line is enabled; the gates of the remaining memory cells N46 in the reference cells are set to low to ensure that the memory cells are in the closed state.

[0076] If the current of the reference circuit 400 fluctuates, the reference circuit 400 will be directly affected, causing the comparison circuit to misjudge, so the reference circuit 400 needs to provide a stable reference voltage. The plurality of third MOS tubes are connected in series to accurately control the current, and further stabilize the reference voltage through voltage division and other methods, thereby providing an accurate reference level for reading data in the memory array 100 and ensuring the accuracy of the reading operation.

[0077] The reference cells are usually fixed to store 0 and do not need to be dynamically flipped, so only a small leakage current is needed to maintain the state. The low current design of the plurality of third MOS tubes in series can avoid the problem of false triggering or leakage of the reference cells caused by overcurrent.

[0078] The memory cells need to be quickly charged and discharged when reading, so the MOS tubes of the memory circuit need to support large current to shorten the bit line signal establishment time. The large current of the memory circuit may cause power supply noise when charging and discharging the bit line. The low current characteristic of the plurality of third MOS tubes in series in the reference circuit 400 reduces the noise sensitivity of the reference circuit 400, thereby ensuring the stability of the voltage.

[0079] The reference cells are preset to store 0, which is to provide a reference voltage representing 0. The number of preset reference cells matches the number of memory cells on the bit line, which can simulate the actual load condition of the bit line, so that the reference voltage accurately reflects the real voltage of the bit line in the 0 state, thereby avoiding comparison errors caused by load differences.

[0080] The virtual bit line is designed to be opened synchronously with any bit line in the memory array 100, so that the MOS transistor N45 in the reference cell is turned on, and the reference circuit 400 enters the working state. This synchronous design ensures that the reference signal is consistent with the bit line signal in time, avoiding misreading caused by the reference signal being ahead or lagging behind.

[0081] The gates of the storage cells N46 are set to low to ensure that the storage cells are in the off state. TIE0 indicates that the gate of the transistor N46 is permanently connected to the logic low level, forcing N46 to be off or in a fixed state. The selection tubes of the unselected cells on the bit line, except for the selected storage cell, are in the off state, but these cells still affect the voltage change speed of the bit line through the off selection tube. The non-selected load of the bit line can be simulated to ensure that the load of the reference bit line is completely matched with the actual bit line.

[0082] According to another aspect of the present application, a data reading method of a ROM memory is also provided, as shown in the accompanying drawings, comprising the steps of: Figure 3 S101, maintaining the reference voltage of the reference circuit 400 consistent with the read initial voltage value of the read voltage of the storage circuit by two first MOS transistors N32, N33 of the comparison circuit, wherein the gates of the two first MOS transistors N32, N33 are connected with the reference circuit 400 and the storage circuit respectively, and the gates of the two first MOS transistors N32, N33 are directly connected.

[0083] S102, selecting the storage cell to be read based on the multiplexer 200 of the storage circuit, and the read voltage of the bit line, wherein the storage circuit comprises the multiplexer 200 and the storage array 100, and the storage array 100 comprises a plurality of storage cells arranged in an array.

[0084] S103, obtaining the reference voltage based on the reference circuit 400, wherein the reference voltage is smaller than the read voltage of the storage circuit when reading 1, and is greater than the read voltage of the storage circuit when reading 0, and the read voltage is the output voltage of the storage circuit when reading the storage data of the storage cell.

[0085] S104, inputting the reference voltage and the read voltage into the comparison circuit of the sense amplifier 300, and outputting the corresponding read digital signal from the cross-coupled circuit, wherein the comparison circuit is connected with the cross-coupled circuit, and is used to compare the reference voltage and the read voltage to determine the corresponding output read digital signal.

[0086] The ROM memory provided by the embodiment of the application adopts a comparison circuit and a reference circuit 400, and the reference circuit 400 and a storage circuit are simultaneously pulled to the same level in a pre-charging stage, so that the offset of a sense amplifier is reduced to a certain extent, and the problem of reading error caused by the voltage difference is avoided. When reading data, the reference circuit 400 can generate a voltage change signal with a slope between the voltage of a storage unit reading 0 and the voltage of a storage unit reading 1, and the output data signal can be quickly determined according to the reference voltage and the reading voltage when reading data. The gates of two first MOS tubes N32 and N33 of the comparison circuit are directly connected, so that the problems of high load of the ROM memory, large slope of the input end of the inverter, slow voltage change of the input inverter and slow reading speed in the prior art are solved, and the technical effects of reading data faster after comparing the reference voltage and the reading voltage and avoiding reading error are achieved.

[0087] The embodiment of the application further provides a ROM memory data specific reading process. Before reading data, one of the multiple selectors 200 is opened through the address line SEL0. Since the source end and the drain end of N11 in the storage array 100 are connected to BL0 and VSS respectively (which can be determined by programming), the data to be read is 0, and the N11 and N21 are opened in the embodiment. SEL0 in the multiple selector 200 is opened at the same time, DWL in the reference circuit is opened, and WL0 in the storage array 100 is opened at the same time.

[0088] The PREEN signal in the pre-charging device is set to low to open P52 for pre-charging, the GBL level is pulled to VDD, the PREEN in the pull-up circuit is also set to low after a certain delay, the nodes A and B are pulled to high, the gate PREENB of the NMOS tube N34 is set to low to open N34, and the levels of RBL and GBL are pulled to the same level, so that the offset of the sense amplifier is reduced to a certain extent, and the problem of different voltage differences of RBL and GBL caused by the different numbers of tubes on both sides is avoided.

[0089] In the process of reading data, the gate of NMOS N31 is set to high level to open N31, so that the sense amplifier starts the comparison process. After the WL0 in the storage array 100 is opened, the N11 transistor pulls down the BL0, and then the BL0 signal is transmitted to the GBL through the transmission gate of the multiplexer 200, and is coupled into the input terminal of the sense amplifier N33. Thus, the voltage level of the GBL starts to continuously decrease from VDD, and the RBL is pulled down under the action of the DWL, but since the loading on the side of the RBL is heavier than that of the GBL, the pull-down trend of the RBL is bound to be smaller than that of the GBL, which will cause the voltage of node A to be greater than that of node B. Finally, rail-to-rail output is achieved: out1 outputs 1, and out2 outputs 0.

[0090] The above-mentioned rail-to-rail output means that the output voltage of the device can be very close to the upper and lower limits of the input voltage of the device. Here, the rail refers to the input voltage of the circuit. The rail-to-rail output of the present circuit is a cross-coupled positive feedback that amplifies a small input voltage difference, and this structural characteristic ensures that the amplified voltage can reach the limit of the input voltage of the circuit. In combination with the pre-charge device 500, intermediate state interference is eliminated, and finally the output is stabilized at VDD or 0V. This characteristic is crucial for data comparison. Only rail-to-rail output can clearly distinguish between “0” and “1”, avoiding reading errors.

[0091] As an optional solution, before the reference voltage of the reference circuit 400 is kept consistent with the read initial voltage value of the read voltage of the storage circuit by comparing the two first MOS transistors N32 and N33 of the comparison circuit, the method further comprises: independently pre-charging the reference circuit 400 and the storage circuit by independent pre-charge devices 500, wherein two pre-charge devices 500 are provided, and the two pre-charge devices 500 are connected to the reference circuit 400 and the storage circuit respectively; and raising the levels of the corresponding nodes A and B of the cross-coupled circuit by an independent pull-up circuit, wherein the cross-coupled circuit is connected to the independent pull-up circuit.

[0092] If a pre-charge device 500 is shared, the bit line of the storage circuit can be connected to multiple storage units, and current fluctuations and charge transfer during pre-charging can interfere with the reference circuit 400 through the shared path; the pre-charge noise of the reference circuit 400 can also affect the pre-charge stability of the bit line of the storage circuit.

[0093] When pre-charging independently, the pre-charge paths of the two are completely isolated, and the load changes and charge fluctuations of the storage circuit will not be transmitted to the reference circuit 400, ensuring that the reference voltage is always maintained at a preset accurate value, providing a reliable reference for subsequent sensing comparison.

[0094] The independent pre-charge circuit can optimize parameters according to the characteristics of two different circuits that need to be pre-charged, and pre-charge in a targeted manner. The above-mentioned characteristic optimization parameters can be understood as pre-charge preference settings, for example, the storage circuit aims to pre-charge a large capacitor to stabilize quickly, and the reference circuit aims to accurately reach a reference value.

[0095] For the reference circuit and the storage circuit, using an independent pre-charge circuit can avoid the problem that the reference circuit and the storage circuit share one pre-charge circuit, which can cause the storage circuit to pre-charge slowly and slow down the whole, or the reference circuit 400 to overshoot due to pre-charge of a large current, thereby shortening the total time consumption of the pre-charge phase of the ROM storage containing the reference circuit and the storage circuit, and achieving the effect of improving the reading speed of the ROM memory.

[0096] Independent pre-charging completely isolates the charge of the storage circuit bit line from the reference circuit 400 through a physically isolated path, so that even if there is local leakage or noise, they will not affect each other, ensuring that both are in a stable initial voltage state when reading starts, reducing sensing errors caused by voltage drift, and increasing the reading accuracy of the ROM memory.

[0097] According to another aspect of the present application, an electronic device is also provided, which includes any of the above ROM memories.

[0098] The ROM memory is an important non-volatile memory device in electronic devices. Non-volatility means that data is not lost after power failure. The characteristics of the ROM memory are that information once written or pre-set at the factory can be stored for a long time after power failure, and the ROM memory is mainly used for reading data during normal operation, and the writing operation is usually limited to factory programming, high-voltage programming, etc.

[0099] The above-mentioned factory programming refers to the process of writing programs or configuring electronic devices in a factory production environment. High-voltage programming is a programming technology for memory, which mainly uses high voltage to realize programming operation.

[0100] The embodiments of the present application also provide a non-transitory machine readable medium storing a computer program, wherein the computer program, when executed by a processor of a computer, is used to make the computer execute the method of the embodiments of the present application.

[0101] The embodiments of the present application also provide a computer program product comprising a computer program, wherein the computer program, when executed by a processor of a computer, is used to make the computer execute the method of the embodiments of the present application.

[0102] The electronic device includes at least one processor and a memory connected to the at least one processor. The memory stores a computer program executable by the at least one processor. The computer program, when executed by the at least one processor, causes the electronic device to perform the method of the embodiments of the present application.

[0103] It should be noted that the term "comprising" and its variants, used in the embodiments of the present application, are intended to cover both open and closed ended systems, i.e., "comprising, but not limited to". The term "based on" is intended to mean "based, at least in part, on". The term "one embodiment" means "at least one embodiment". The term "another embodiment" means "at least one additional embodiment". The term "some embodiments" means "at least some embodiments". The terms "a" or "an", as used herein, mean "one or more" unless the context clearly dictates otherwise. The term "plurality" means "two or more".

[0104] The steps described in the method embodiments provided by the embodiments of the present application can be executed in different orders and / or in parallel. In addition, the method embodiments can include additional steps and / or omit the steps shown. The scope of protection of the present application is not limited in this respect.

[0105] The word "embodiment" in the specification means that the specific features, structures, or characteristics described in connection with the embodiment can be included in at least one embodiment of the present application. The presence of the phrase in the specification at various places does not necessarily mean the same embodiment, nor does it mean independence or alternative to other embodiments. Each embodiment in the specification is described in a relevant manner, and the same or similar parts between each embodiment are referred to each other. In particular, for device, equipment, and system embodiments, since they are basically similar to method embodiments, the description is relatively simple, and the relevant parts are referred to the part of the method embodiment.

[0106] The above-described embodiments only express several embodiments of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of protection. It should be noted that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of protection of the present application. Therefore, the scope of protection of the present application should be subject to the appended claims.

Claims

1. A ROM memory, characterized by, The application relates to a memory circuit, which comprises a storage circuit, a reference circuit, a comparison circuit and a cross-coupling circuit. The storage circuit comprises a multiplexer and a storage array, and the storage array comprises a plurality of storage units arranged in an array. The reference circuit is used for generating a reference voltage based on a reference load during reading, wherein the reference voltage is smaller than a reading voltage of the storage circuit during reading 1 and larger than the reading voltage of the storage circuit during reading 0, and the reading voltage is an output voltage of the storage circuit during reading storage data. The comparison circuit comprises two first MOS transistors, the gates of the two first MOS transistors are connected with the reference circuit and the storage circuit respectively, and the gates of the two first MOS transistors are connected. The cross-coupling circuit is connected with the comparison circuit and is used for comparing the reference voltage and the reading voltage to determine a corresponding output reading digital signal. The cross-coupling circuit comprises two cross-coupled second MOS transistors.

2. The ROM memory according to claim 1, characterized in that, The two second MOS transistors are PMOS transistors, the gate of the second MOS transistor is connected with the drain of the other second MOS transistor, and the source of the second MOS transistor is connected with a high-voltage source. The gate of the second MOS transistor is also connected with the drain of the corresponding first MOS transistor, and the gate of the second MOS transistor is connected as an output terminal of the cross-coupling circuit and is configured to output the reading digital signal. The output terminal is also provided with an inverter.

3. The ROM memory according to claim 2, characterized in that, The gates of the two first MOS transistors are connected with the source and the drain of an NMOS transistor respectively.

4. The ROM memory of claim 1, wherein, The memory circuit further comprises a pre-charging device, and the pre-charging device is connected with the reference circuit and the storage circuit.

5. The ROM memory of claim 1, wherein, The pre-charging device is provided with two independent pre-charging devices, and the reference circuit and the storage circuit are respectively provided with independent pre-charging devices. The two second MOS transistors of the cross-coupling circuit are provided with independent pull-up circuits.

6. The ROM memory according to claim 5, characterized in that, The pre-charging device and the pull-up circuit are PMOS transistors.

7. The ROM memory according to claim 6, characterized in that, The gate of the PMOS transistor is enabled by a pre-charging signal, the source of the PMOS transistor is connected with a high-voltage source, and the drain of the PMOS transistor is connected with a circuit for pre-charging and pull-up. The reference load of the reference circuit is greater than the minimum load of any reading bit line and smaller than the maximum load of any reading bit line, so that the voltage-time variation slope of the reference voltage is smaller than the voltage-time variation slope during reading 0 of the storage unit and greater than the voltage-time variation slope during reading 1 of the storage unit, wherein the reading bit line is a corresponding bit line in the storage array during reading.

8. The ROM memory of claim 1, wherein, The reference circuit comprises a plurality of third MOS transistors on the reading bit line and a plurality of reference units which are the same as the storage units in number, 9. The ROM memory according to claim 8, characterized in that, The third MOS transistors are connected in series. One end of the source level or the drain level of the reference unit is connected with the bit line, and the other end is connected with the ground, so that all the reference units store 0. The gate of one of the reference units is connected with a corresponding virtual bit line, so that any corresponding bit line in the storage array is enabled, and the virtual bit line is enabled. The gates of the remaining reference units are set to low level to ensure that the storage units are in the closed state. ​ 10. A data read method of a ROM memory, characterized by, ​ The reference voltage of the reference circuit is kept consistent with the read initial voltage value of the read voltage of the storage circuit by comparing two first MOS transistors of a comparison circuit, wherein the gates of the two first MOS transistors are connected with the reference circuit and the storage circuit respectively, and the gates of the two first MOS transistors are directly connected; The storage unit to be read and the read voltage of the bit line are selected based on a multiplexer of the storage circuit, wherein the storage circuit comprises the multiplexer and a storage array, and the storage array comprises a plurality of storage units arranged in an array; The reference voltage is obtained based on a reference circuit, wherein the reference voltage is less than the read voltage of the storage circuit when reading 1 and greater than the read voltage of the storage circuit when reading 0, and the read voltage is the output voltage of the storage circuit when reading the stored data of the storage unit; The reference voltage and the read voltage are input into a comparison circuit, and a corresponding read digital signal is output by a cross-coupled circuit, wherein the comparison circuit is connected with the cross-coupled circuit and used for comparing the sizes of the reference voltage and the read voltage to determine the corresponding output read digital signal.

11. The method of claim 10, wherein, Before keeping the reference voltage of the reference circuit consistent with the read initial voltage value of the read voltage of the storage circuit by comparing two first MOS transistors of a comparison circuit, the method further comprises: The reference circuit and the storage circuit are pre-charged by independent pre-charging devices respectively, wherein the pre-charging devices are provided in two, and the two pre-charging devices are connected with the reference circuit and the storage circuit respectively; The corresponding nodes of the cross-coupled circuit are pulled up in level by a pull-up circuit, wherein the cross-coupled circuit is connected with the pull-up circuit.

12. An electronic device, comprising: The ROM memory comprises any one of claims 1 to 9.

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