Semiconductor wafer structure and semiconductor device

Abstract

The invention discloses a semiconductor wafer structure and a semiconductor device. The semiconductor wafer structure includes a semiconductor wafer and a plurality of trench groups. The semiconductor wafer has a plurality of die regions and a plurality of dicing lanes disposed between the die regions for separating the plurality of die regions. The plurality of trench groups are disposed between the plurality of die regions and the plurality of scribe lines. Each of the plurality of die regions is surrounded by one of a plurality of trench groups, each of the plurality of trench groups including a plurality of stress relief trenches parallel to each other.

Description

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor wafer structure and a semiconductor device. BACKGROUND

[0002] In semiconductor wafer processing, integrated circuits are formed on wafers (also referred to as substrates) composed of silicon or other semiconductor materials. Generally, various layers of semiconductor, conductive, or insulating materials are utilized to form the integrated circuits. These materials are doped, deposited, and etched using various well-known processes to form the integrated circuits. Each wafer is processed to form a large number of individual regions containing integrated circuits, referred to as dies.

[0003] After the integrated circuit formation process, the wafers are "singulated" to separate the individual dies from one another for packaging or use in larger circuits in unpackaged form. For the singulation process, the wafers are typically mounted on a support member, such as an adhesive film extending across a thin film frame, and a saw is repeatedly applied to vertical and horizontal streets. One problem with scribing or sawing is that chipping and notching can form along the severed edges of the dies. In addition, cracks can form and propagate from the die edges into the substrate and render the integrated circuits inoperable. Due to chipping and cracking, additional spacing between the dies on the wafer is typically required to prevent damage to the integrated circuits. This additional spacing can keep the chipping and cracking away from the actual integrated circuits. Due to the spacing requirement, fewer dies can be formed on a standard size wafer, and wafer area that could otherwise be used for circuits is wasted. SUMMARY

[0004] The present invention provides a semiconductor wafer structure and a semiconductor device having stress relief trenches around die (die) regions to relieve stress caused by a singulation process.

[0005] The present invention provides a semiconductor wafer structure including a semiconductor wafer and a plurality of trench groups. The semiconductor wafer has a plurality of die regions and a plurality of streets disposed between the die regions for separating the plurality of die regions. The plurality of trench groups is disposed between the plurality of die regions and the plurality of streets. Each of the plurality of die regions is surrounded by one of the plurality of trench groups, and each of the plurality of trench groups includes a plurality of stress relief trenches parallel to each other.

[0006] According to an embodiment of the present invention, the semiconductor wafer further includes a semiconductor substrate, a redistribution structure formed over the semiconductor substrate, and a passivation layer covering the redistribution structure and the plurality of streets.

[0007] According to an embodiment of the present invention, each of the plurality of stress relief trenches extends at least through the passivation layer.

[0008] According to embodiments of the present application, each of the plurality of trench groups includes at least 3 stress release trenches, and each of the at least 3 stress release trenches encloses a respective one of the plurality of die regions.

[0009] According to embodiments of the present application, the semiconductor wafer further includes a cut region to be removed during a cutting process, and the cut region overlaps the plurality of cut streets.

[0010] According to embodiments of the present application, the cut region partially overlaps each of the plurality of trench groups.

[0011] According to embodiments of the present application, a width of the cut region is greater than a width of each of the plurality of cut streets.

[0012] According to embodiments of the present application, a width of each of the plurality of cut streets is substantially equal to or less than 50 microns.

[0013] According to embodiments of the present application, a gap between two adjacent ones of the plurality of stress release trenches is substantially equal to or less than 4 microns.

[0014] According to embodiments of the present application, a width of each of the plurality of stress release trenches is substantially equal to or less than 4 microns.

[0015] The present application provides a semiconductor device including a semiconductor substrate having a die region and a edge region outside a periphery of the die region and surrounding the die region, and a plurality of stress release trenches disposed within the edge region and surrounding the die region. The plurality of stress release trenches are parallel to each other.

[0016] According to embodiments of the present application, the plurality of stress release trenches includes at least a first trench surrounding the die region and a second trench surrounding the at least a first trench and the die region.

[0017] According to embodiments of the present application, a width of the second trench is less than a width of the at least a first trench.

[0018] According to embodiments of the present application, a bottom surface of the second trench extends to and connects an outermost surface of the semiconductor device.

[0019] According to embodiments of the present application, the semiconductor device further includes a redistribution structure disposed on the semiconductor substrate, and a passivation layer disposed on the redistribution structure and the edge region.

[0020] According to embodiments of the present application, each of the plurality of stress release trenches extends at least through the passivation layer.

[0021] According to embodiments of the present application, a gap between two adjacent ones of the plurality of stress release trenches is substantially equal to or less than 4 microns (pm).

[0022] According to embodiments of the present application, the width of each of the plurality of stress release trenches is substantially equal to or less than 4 μm.

[0023] A semiconductor device includes a semiconductor substrate having a die region and a edge region outside a periphery of the die region and surrounding the die region, and a stress release trench disposed within the edge region and surrounding the die region. A bottom surface of the stress release trench extends to and connects an outermost surface of the semiconductor device.

[0024] According to embodiments of the present application, the semiconductor device further includes at least one trench surrounding the die region and surrounded by the stress release trench, wherein a width of the stress release trench is less than a width of the at least one trench.

[0025] In order that the foregoing can be more fully understood, a number of embodiments are set forth hereinafter with reference to the drawings, in which: BRIEF DESCRIPTION OF DRAWINGS

[0026] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate exemplary embodiments of the present application and, together with the description, further serve to explain the principles of the present application.

[0027] Figure 1 Partial plan view of a semiconductor wafer structure for some exemplary embodiments of the present application;

[0028] Figure 2 Partial cross-sectional view of a semiconductor wafer structure for some exemplary embodiments of the present application;

[0029] Figure 3 Cross-sectional view of a semiconductor device for some exemplary embodiments of the present application;

[0030] Figure 4 Partial enlarged view of an edge region of a semiconductor device in Figure 3

[0031] Figures 5 to 7 Cross-sectional view of a semiconductor device for different exemplary embodiments of the present application.

[0032] LIST OF SYMBOLS:

[0033] 10: semiconductor wafer structure

[0034] 100, 100a, 100b, 100c: semiconductor device

[0035] 110: semiconductor substrate

[0036] 112: stress release trench

[0037] 120: redistribution structure​

[0038] 122: redistribution layer

[0039] 124: dielectric layer

[0040] 130: passivation layer

[0041] 1121: first trench

[0042] 1122: second trench

[0043] DR: die region

[0044] DS: dicing street

[0045] DW: dicing region

[0046] ER: edge region

[0047] G1: gap

[0048] GS: group of trenches

[0049] S1: outermost surface

[0050] S2: bottom surface

[0051] SR: sealing ring

[0052] W1: semiconductor wafer

[0053] d1, d2, W1, W2: width

[0054] d3: horizontal distance DETAILED DESCRIPTION

[0055] Reference will now be made in detail to exemplary embodiments of the application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the drawings and the description to refer to the same or like parts.

[0056] As used in herein, the terms "on", "over", "under", "in front of", "behind", "to the left of", and "to the right of" are used for the purpose of description with respect to the orientation of the figures and are not intended to limit the application. In addition, in the discussion herein and in the claims, the use of the term "on" with respect to two materials, one "on" the other, means that there is at least some contact between the materials, while "over", "above", and "overlying" means that the materials are close, but can have one or more additional intervening materials such that physical contact is possible but not necessary. "On" and "over" as used herein do not imply any directionality.

[0057] The terms "disposed," "connected," "coupled," "mounted," and their derivatives, as used herein, are used generically and not by way of limitation to connote either a direct or indirect connection, coupling, mounting, or the like. Similarly, the terms "faces," "facing," and their derivatives, as used herein, are used generically and not by way of limitation to connote either a direct or indirect facing, and the term "adjacent," and its derivatives, as used herein, are used generically and not by way of limitation to connote either a direct or indirect adjacency. Thus, the drawings and descriptions will be regarded as illustrative in nature and not as restrictive.

[0058] Figure 1 Partial top view of a semiconductor wafer structure according to some example embodiments of the present invention. Figure 2 Partial cross-sectional view of a semiconductor wafer structure according to some example embodiments of the present invention. Reference is made to Figure 1 and Figure 2 The semiconductor wafer structure 10 includes a semiconductor wafer Wl and a plurality of trench groups GS formed on the semiconductor wafer Wl for surrounding each die region (die) DR on the semiconductor wafer Wl. In some embodiments, the semiconductor wafer Wl includes a plurality of die regions DR and a plurality of streets DS disposed between the die regions DR for separating the die regions DR. The streets DS are configured to allow passage of a dicing saw while reducing the risk of damage to adjacent die regions DR on the semiconductor wafer Wl. In one embodiment, the streets DS can include features such as test pads to test the performance of the die regions DR formed during a manufacturing process, alignment marks to assist in alignment of various photomasks during the manufacturing process, and / or other identifying information.

[0059] In some embodiments, the semiconductor wafer Wl includes a semiconductor substrate 110 for supporting the die regions (dies) DR formed thereon. In some embodiments, the devices of the dies extend into the semiconductor substrate 110. In some embodiments, the semiconductor substrate 110 includes elemental semiconductors including silicon or germanium in crystalline, polycrystalline, or amorphous structure; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; alloy semiconductors including silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material or combination thereof.

[0060] According to some example embodiments of the present invention, each die region DR can have the same functionality. In some embodiments, at least one of the die regions DR has a different functionality than another of the die regions DR. In some embodiments, each die region DR has the same size. In some embodiments, at least one of the die regions DR has a different size than another of the die regions DR.

[0061] In some embodiments, the die regions DR are formed over the semiconductor substrate 110. The die regions DR are formed by a combination of fabrication processes, such as photolithography, deposition, etching, epitaxy, implantation, or other suitable processes. In some embodiments, each die region DR can include planar devices, such as complementary metal-oxide-semiconductor (CMOS) devices, high electron mobility transistors (HEMTs), bi-polar junction transistors (BJTs), or other suitable planar devices. In some embodiments, each die region DR includes passive elements, such as capacitors, resistors, inductors, or other suitable passive elements. In some embodiments, each die region DR includes a combination of passive devices and active devices, such as transistors or other suitable active devices.

[0062] The die regions DR are separated by streets DS, which can include similar metallization and dielectric layers as the die regions DR. For example, the streets DS can be composed of layers of dielectric material, semiconductor material, and metallization. In one embodiment, one or more of the streets DS include test devices similar to the actual devices of the die regions DR. In some embodiments, a backside metallization layer (and corresponding dielectric layer) can be included on the backside of the semiconductor wafer Wl or the semiconductor substrate 110.

[0063] According to some embodiments of the present disclosure, the semiconductor wafer Wl further includes a redistribution structure 120 formed over the semiconductor substrate 110 and a passivation layer 130 covering the redistribution structure 120 and the plurality of dicing streets DS. In some embodiments, the redistribution structure 120 can include a plurality of redistribution layers (RDLs) 122 and a plurality of dielectric layers 124 stacked on top of each other. Each dielectric layer 124 can be formed of a polymer, such as PBO, polyimide, or the like. The formation process includes coating the dielectric layer 124 in a flowable form, and then curing the dielectric layer 124. According to alternative embodiments of the present disclosure, the dielectric layer 124 is formed of an inorganic dielectric material, such as silicon nitride, silicon oxide, or the like. The formation method can include Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Plasma-Enhanced Chemical Vapor Deposition (PECVD), or other suitable deposition methods. Openings (occupied by via portions of the redistribution layers 122) are then formed, such as by a photolithography process. According to some embodiments in which the dielectric layer 124 is formed of a photosensitive material, such as PBO, polyimide, or benzocyclobutene (BCB), the formation of the openings involves exposing the dielectric layer 124 to light using a photomask (not shown), and developing the dielectric layer 124.

[0064] The redistribution layers 122 can be formed over the corresponding dielectric layers 124, respectively. In some embodiments, the redistribution layers 122 include via portions formed in the dielectric layers 124 for interconnection. According to some embodiments of the present disclosure, the redistribution layers 122 are formed in an electroplating process that includes depositing a metal seed layer (not shown), forming and patterning a photoresist (not shown) over the metal seed layer, and electroplating a metal material, such as copper and / or aluminum, over the metal seed layer. The metal seed layer and the electroplated metal material can be formed of the same material or different materials. The patterned photoresist is then removed, followed by etching the portions of the metal seed layer that were previously covered by the patterned photoresist. The number of redistribution layers 122 and dielectric layers 124 illustrated in the present disclosure is for illustrative purposes only. The layout and number of layers of the redistribution structure 120 are not limited thereto.

[0065] In some embodiments, as shown in FIG. 1C, each die region DR can further include a seal ring SR extending along the perimeter of the corresponding die region DR. The seal ring SR is formed over the non-active area surrounding the active area of the die region DR. The seal ring structure SR helps to reduce crack propagation into the active area of the redistribution structure 120, and also helps to block the electromigration of contaminant ions. Figure 2 In some embodiments, as shown in FIG. 1C, each die region DR can further include a seal ring SR extending along the perimeter of the corresponding die region DR. The seal ring SR is formed over the non-active area surrounding the active area of the die region DR. The seal ring structure SR helps to reduce crack propagation into the active area of the redistribution structure 120, and also helps to block the electromigration of contaminant ions.

[0066] After the redistribution structures 120 are formed, a passivation layer 130 is formed to cover the upper surface of the semiconductor wafer Wl (including the redistribution structures 120 and the plurality of dicing streets DS). The passivation layer 130 can have a function of isolating the redistribution layer 122 and the (low-k) dielectric layer 124 from the adverse effects of harmful chemicals and moisture. The passivation layer 130 can be formed of a non-low-k dielectric material, such as silicon oxide, silicon nitride, undoped silicate glass (USG), etc. There can be metal pads in the passivation layer, such as aluminum pads (e.g., formed of aluminum copper).

[0067] According to some example embodiments in the present disclosure, a trench group GS is disposed between the die regions DR, and each die region DR is surrounded by one of the trench groups GS. In detail, each trench group GS includes a plurality of stress release trenches 112 parallel to each other. For example, each trench group GS includes at least 3 stress release trenches 112, and each stress release trench 112 surrounds a corresponding one of the die regions DR. In some embodiments, the stress release trenches 112 can be formed, e.g., by an etching process, around the periphery of each die region DR. In one embodiment, each stress release trench 112 is etched to extend at least through the passivation layer 130. The stress release trenches 112 are formed prior to the wafer dicing process, and are configured to separate the active region of each die region DR and a portion of the surrounding non-active region (edge region) from the dicing streets DS.

[0068] Referring to Figure 2 In some embodiments, the semiconductor wafer Wl further includes a dicing region DW to be removed during the dicing process, and the dicing region DW overlaps the dicing streets DS. The dicing streets DS are configured to separate the plurality of die regions DR fabricated on the semiconductor substrate 110. The dicing streets DS can include alignment marks for dicing and other structures, such as test and monitor structures. The dicing region DW is the region that is actually removed by a dicing tool (e.g., a blade saw) during the dicing process. The width Wl of the dicing region DW is substantially equal to the width of the dicing tool. In some embodiments, the dicing region DW overlapping the dicing streets DS from a top view means that the width Wl of the dicing region DW is substantially greater than the width W2 of each dicing street DS. For example, the width Wl of the dicing region DW is greater than about 50 pm, and the width W2 of each dicing street DS is substantially equal to or less than about 50 pm.

[0069] Accordingly, the dicing region DW can partially overlap each trench group GS, because the trench groups GS are configured to be immediately adjacent to the dicing streets DS. That is, a portion of the trench groups GS can be removed during the dicing process. With such a configuration, as Figure 2 and Figure 3As shown in FIG. 1, any stress concentration caused by the dicing process can be released by the stress release trenches 112 at the outset, and any dicing-induced defects or cracks can be blocked by the stress release trenches 112 from propagating or migrating into the active region of the die region DR. In some embodiments, the gap Gl between two adjacent stress release trenches 112 is substantially equal to or less than 4 μιη, and the width d2 of each stress release trench 112 is substantially equal to or less than 4 μιη. The aspect ratio of each stress release trench 112 can be about 3: 1 or about 4: 1. The present disclosure is not limited thereto. In addition, the stress release trenches 112 divide the semiconductor wafer structure 10 into a plurality of smaller regions (by surrounding each die region DR), such that the total integrated tensile stress of the entire wafer is released.

[0070] Figure 3 is a cross-sectional view of a semiconductor device according to some example embodiments of the present disclosure. Figure 4 is Figure 3 is a partial enlarged view of the edge region of the semiconductor device in Figure 3 and Figure 4 The semiconductor device 100 shown in FIG. 1 is one of the dies diced from the semiconductor wafer structure 10 shown in Figure 1 and Figure 2 Thus, Figure 3 and Figure 4 The semiconductor device 100 shown in FIG. 1 contains many features that are the same or similar to the semiconductor wafer structure 10 previously disclosed with reference to Figure 1 and Figure 2 For purposes of clarity and simplicity, detailed descriptions of the same or similar features can be omitted, and the same or similar reference numerals designate the same or similar components.

[0071] Referring to Figure 3 and Figure 4 In some embodiments, the semiconductor device 100 includes a semiconductor substrate 110 and a plurality of stress release trenches 112. The semiconductor substrate 110 has a die region DR and an edge region ER outside the periphery of the die region DR, and the edge region ER surrounds the die region DR. In some embodiments, the semiconductor device 100 further includes a redistribution structure 120 disposed on the semiconductor substrate 110, and a passivation layer 130 disposed on the redistribution structure 120 and the edge region ER. The stress release trenches 112 are disposed within the edge region ER and surround the die region DR. In some embodiments, the stress release trenches 112 are parallel to each other and extend at least through the passivation layer 130. In one embodiment, the gap Gl between two adjacent stress release trenches 112 is substantially equal to or less than about 4 μιη.

[0072] In the present embodiment, at least a portion of the stress release trench 112 is removed by the cutting tool during the cutting process. Thus, the stress release trench 112 includes at least one first trench 1121 (three first trenches 1121 are illustrated here, but not limited to) surrounding the die region DR and a second trench 1122 surrounding the first trench 1121 and the die region DR. For example, a width d2 of each first trench 1121 is substantially equal to or less than about 4 μm, and a width dl of the second trench 1122 is less than the width d2 of the first trench 1121, since the second trench 1122 is the trench of the stress release trench 112 that is partially removed by the cutting tool. As such, a bottom surface S2 of the second trench 1122 extends to and connects with the outermost surface SI of the semiconductor device 100.

[0073] Figure 5 is a cross-sectional view of a semiconductor device according to some example embodiments of the present invention. It should be noted that, Figure 5 The semiconductor device 100a shown in FIG. 10A includes many features that are the same as or similar to the semiconductor devices disclosed in the previous embodiments. For the purpose of clarity and simplicity, detailed descriptions of the same or similar features can be omitted, and the same or similar reference numerals denote the same or similar components.

[0074] Referring to Figure 5 In the present embodiment, the cutting tool does not cut away any one of the stress release trenches 112 or the cutting tool cuts in the region between two adjacent stress release trenches 112. That is, none of the stress release trenches 112 is partially removed by the cutting tool during the cutting process. Thus, the semiconductor device 100a includes at least one stress release trench 112 (two stress release trenches 112 are illustrated here, but not limited to) disposed within the edge region ER and surrounding the die region DR, and the width d2 of the stress release trench 112 is substantially the same. As such, the outermost surface SI of the semiconductor device 100a is a planar surface, and a horizontal distance d3 from the outermost surface SI to the closest sidewall of the stress release trench 112 is substantially less than about 4 μm. For example, the horizontal distance d3 is substantially equal to or less than about 2 μm. The present invention is not limited thereto.

[0075] Figure 6 is a cross-sectional view of a semiconductor device according to some example embodiments of the present invention. It should be noted that, Figure 6 The semiconductor device 100b shown in FIG. 11A includes many features that are the same as or similar to the semiconductor devices disclosed in the previous embodiments. For the purpose of clarity and simplicity, detailed descriptions of the same or similar features can be omitted, and the same or similar reference numerals denote the same or similar components.

[0076] Referring to Figure 6In this embodiment, the stress release trench 112 includes a first trench 1121 surrounding the die region DR and a second trench 1122 surrounding the first trench 1121, and a portion of the second trench 1122 is removed by the cutting tool during the cutting process. Thus, the width dl of the second trench 1122 is less than the width d2 of the first trench 1121, since the second trench 1122 is the trench of the stress release trench 112 that is partially removed by the cutting tool. As such, the bottom surface S2 of the second trench 1122 extends to and connects the outermost surface Sl of the semiconductor device 100b.

[0077] Figure 7 FIG. 1 is a cross-sectional view of a semiconductor device according to some example embodiments of the present disclosure. It should be noted that Figure 7 The semiconductor device 100c shown in FIG. 1 includes many features that are the same as or similar to the semiconductor devices disclosed in the previous embodiments. For the purpose of clarity and simplicity, detailed descriptions of the same or similar features can be omitted, and the same or similar reference numbers represent the same or similar components.

[0078] Referring to Figure 7 In this embodiment, the cutting tool cuts on the semiconductor wafer closest to one of the stress release trenches 112 of the die region DR. Thus, the semiconductor device 100c includes a stress release trench 1122 disposed within the edge region ER and surrounding the die region DR, and the stress release trench 1122 is partially removed by the cutting tool. As such, the bottom surface S2 of the stress release trench 1122 extends to and connects the outermost surface Sl of the semiconductor device 100c. In some embodiments, the width dl of the stress release trench 1122 is less than about 4 μm. For example, the width dl of the stress release trench 1122 is substantially equal to or less than about 2 μm.

[0079] In summary, the present disclosure provides a semiconductor wafer structure having a plurality of stress release trenches disposed around each of the die regions and at the immediate vicinity of the cutting lanes. Thus, the semiconductor devices cut from the semiconductor wafer structure include at least one stress release trench surrounding the die region. With this configuration, any stress concentration caused by the cutting process can be immediately released by the stress release trench before any cutting-induced defects or cracks are formed. Even if some defects or cracks are formed, they can be blocked by the stress release trench at the beginning to prevent them from propagating or migrating into the active region of the die region. Thus, the yield and reliability of the semiconductor devices can be improved, and the edge region of the semiconductor wafer structure can be reduced to optimize the space utilization of the semiconductor wafer structure.

[0080] Based on the above discussion, it can be seen that the present disclosure provides various advantages. However, it should be understood that not necessarily all advantages discussed herein are to be necessarily encountered, and other embodiments can provide different advantages, and particular advantages need not be encountered for all embodiments.

[0081] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor wafer structure, characterized by, Comprising: a semiconductor wafer having a plurality of die regions and a plurality of streets disposed between the plurality of die regions for separating the plurality of die regions; and a plurality of trench groups disposed between the plurality of die regions, wherein each of the plurality of die regions is surrounded by one of the plurality of trench groups, each of the plurality of trench groups comprising a plurality of stress relief trenches parallel to each other.

2. The semiconductor wafer structure of claim 1, wherein The semiconductor wafer further comprises a semiconductor substrate, a redistribution structure over the semiconductor substrate, and a passivation layer covering the redistribution structure and the plurality of streets.

3. The semiconductor wafer structure of claim 2, wherein Each of the plurality of stress relief trenches extends at least through the passivation layer.

4. The semiconductor wafer structure of claim 1, wherein, Each of the plurality of trench groups comprises at least 3 stress relief trenches, and each of the at least 3 stress relief trenches surrounds a respective one of the plurality of die regions.

5. The semiconductor wafer structure of claim 1, wherein, The semiconductor wafer further comprises a street region to be removed during a streeting process, and the street region overlaps the plurality of streets.

6. The semiconductor wafer structure of claim 1, wherein, The street region partially overlaps each of the plurality of trench groups.

7. The semiconductor wafer structure of claim 5, wherein, A width of the street region is greater than a width of each of the plurality of streets.

8. The semiconductor wafer structure of claim 1, wherein A width of each of the plurality of streets is equal to or less than 50 microns.

9. The semiconductor wafer structure of claim 1, wherein, A gap between two adjacent ones of the plurality of stress relief trenches is equal to or less than 4 microns.

10. The semiconductor wafer structure of claim 1, wherein A width of each of the plurality of stress relief trenches is equal to or less than 4 microns.

11. A semiconductor device, characterized by comprising: Comprising: a semiconductor substrate having a die region and an edge region outside a periphery of the die region and surrounding the die region; and a plurality of stress relief trenches disposed within the edge region and surrounding the die region, wherein the plurality of stress relief trenches are parallel to each other.

12. The semiconductor device of claim 11, wherein, The plurality of stress relief trenches comprises at least a first trench surrounding the die region and a second trench surrounding the at least a first trench and the die region.

13. The semiconductor device of claim 12, wherein, A width of the second trench is less than a width of the at least a first trench.

14. The semiconductor device of claim 12, wherein, A bottom surface of the second trench extends to and connects with an outermost surface of the semiconductor device.

15. The semiconductor device of claim 11, wherein, Further comprising a redistribution structure over the semiconductor substrate and a passivation layer over the redistribution structure and the edge region.

16. The semiconductor device of claim 15, wherein, Each of the plurality of stress relief trenches extends at least through the passivation layer.

17. The semiconductor device of claim 11, wherein, A gap between two adjacent ones of the plurality of stress relief trenches is equal to or less than 4 microns.

18. The semiconductor device of claim 11, wherein, A width of each of the plurality of stress relief trenches is equal to or less than 4 microns.

19. A semiconductor device, characterized by comprising: Comprising: a semiconductor substrate having a die region and an edge region outside a periphery of the die region and surrounding the die region; and a stress relief trench disposed within the edge region and surrounding the die region, wherein a bottom surface of the stress relief trench extends to and connects with an outermost surface of the semiconductor device.

20. The semiconductor device of claim 19, wherein, Further comprising at least a trench surrounding the die region and surrounded by the stress relief trench, wherein a width of the stress relief trench is less than a width of the at least a trench.

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