Charge pump phase-locked loop real-time calibration circuit, method and device based on phase detection

Abstract

The invention provides a charge pump phase-locked loop real-time calibration circuit, method and device based on phase detection, and the circuit comprises a time-to-digital conversion circuit, a thermometer code conversion circuit, and a logic state machine circuit. The time-to-digital conversion circuit converts two output signals of the phase frequency detector into time-to-digital signals based on phase-locked loop locking indication signals output by the locking detection circuit, the thermometer code conversion circuit converts the time-to-digital signals into binary codes, and the logic state machine circuit forms calibration feedback control signals based on the binary codes. And transmitting the calibration feedback control signal to a current steering type two-way switch charge pump of a charge pump phase-locked loop circuit so as to calibrate a voltage control signal output by the current steering type two-way switch charge pump in real time. According to the charge pump phase-locked loop real-time calibration circuit, the consistency of the circuit under different processes, temperatures and power voltages can be improved, and the reference stray level of the charge pump phase-locked loop circuit is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a phase detection based charge pump phase-locked loop real-time calibration circuit, method and device. BACKGROUND

[0002] This section is intended to provide background information to facilitate a better understanding of embodiments of this application. It includes references to publications that describe in more detail some of the technologies relating to this application. This section is not admitted to be prior art to this application by inclusion in this section.

[0003] In the field of integrated circuit technology, the charge pump phase-locked loop, as an important frequency synthesis and phase control circuit, is widely used in various electronic systems such as communication, data processing and radio frequency. Its core function is to achieve accurate locking of the frequency and phase of the output signal and the reference signal through closed-loop feedback, and to provide stable clock or carrier signals for the system.

[0004] Current charge pump phase-locked loop circuits face many performance problems in practical applications, such as phase error caused by non-ideal characteristics, influence of environmental and process fluctuations, and limitations of traditional calibration methods.

[0005] Therefore, in order to solve the above problems, a technology is needed that can detect phase error in real time and dynamically calibrate the charge pump based on the error to improve the stability and accuracy of the charge pump phase-locked loop circuit under various environmental and process conditions. SUMMARY

[0006] The purpose of the present application is to provide a phase detection based charge pump phase-locked loop real-time calibration circuit, method and device to solve the technical problem of large area and power consumption of the charge pump phase-locked loop circuit in the prior art.

[0007] One purpose of the present application is to provide a phase detection based charge pump phase-locked loop real-time calibration circuit to improve analog mismatch with digital calibration logic, effectively improve the consistency of the charge pump phase-locked loop circuit under different processes, temperatures and power supply voltages through real-time calibration, and improve the phase-locked loop reference spurious level at a smaller power consumption and area cost. Another purpose of the present application is to provide a phase detection based charge pump phase-locked loop real-time calibration method. Another purpose of the present application is to provide a phase detection based charge pump phase-locked loop device.

[0008] In order to achieve the above purpose, the present application discloses a phase detection based charge pump phase-locked loop real-time calibration circuit, comprising: The time-to-digital conversion circuit is connected with the frequency discriminator and the lock detection circuit of the charge pump phase-locked loop circuit, and is configured to convert frequency discrimination positive output signals and frequency discrimination negative output signals of the frequency discriminator into time-to-digital signals corresponding to phase errors based on a phase-locked loop lock indication signal output by the lock detection circuit; The thermometer code conversion circuit is connected with the time-to-digital conversion circuit, and is configured to convert the time-to-digital signals into binary codes; The logic state machine circuit is coupled with the thermometer code conversion circuit, and is configured to form a calibration feedback control signal based on the binary codes and transmit the calibration feedback control signal to a current steering dual-path switch charge pump of the charge pump phase-locked loop circuit, so as to calibrate a voltage control signal output by the current steering dual-path switch charge pump in real time.

[0009] Optionally, the application further comprises: The subtracter circuit is connected with the thermometer code conversion circuit and the logic state machine circuit respectively, and is configured to output a phase calibration indication signal based on a preset reference phase error signal and the binary codes, and the logic state machine circuit is configured to output the calibration feedback control signal based on the phase calibration indication signal.

[0010] Optionally, the application further comprises a clock synchronization circuit configured to generate a clock synchronization signal based on a reference signal of the charge pump phase-locked loop circuit and transmit the clock synchronization signal to the logic state machine circuit.

[0011] Optionally, the clock synchronization circuit comprises: The buffer circuit is connected with the logic state machine circuit, and is configured to convert a preset first calibration clock signal into an intermediate calibration clock signal based on an enable signal of the calibration feedback control signal; The frequency divider circuit is connected with the buffer circuit and the logic state machine circuit respectively, and is configured to perform frequency reduction processing on the intermediate calibration clock signal to obtain a second calibration clock signal based on the enable signal of the calibration feedback control signal, and transmit the second calibration clock signal to the logic state machine circuit as the clock synchronization signal.

[0012] Optionally, the charge pump phase-locked loop circuit comprises a current steering dual-path switch charge pump, and the current steering dual-path switch charge pump comprises an up pull branch, a down pull branch and a plurality of calibration down pull branches, and the plurality of calibration down pull branches are connected in parallel through a switch selection circuit; The logic state machine circuit is configured to form a calibration feedback control signal input into the switch selection circuit based on the binary codes, and the switch selection circuit is configured to control conduction or disconnection of each calibration down pull branch based on the calibration feedback control signal.

[0013] The application also discloses a phase detection-based charge pump phase-locked loop real-time calibration method, comprising the following steps: Converting the frequency discrimination phase discriminator positive output signal and the frequency discrimination phase discriminator negative output signal of the frequency discriminator into a time-to-digital signal corresponding to a phase error based on a phase-locked loop locking indication signal output by the locking detection circuit; Converting the time-to-digital signal into a binary code; Forming a calibration feedback control signal based on the binary code, and transmitting the calibration feedback control signal to a charge pump circuit of the charge pump phase-locked loop circuit to calibrate a voltage control signal output by the charge pump circuit in real time.

[0014] The application also discloses a phase detection-based charge pump phase-locked loop device, comprising the charge pump phase-locked loop real-time calibration circuit and the charge pump phase-locked loop circuit of any one of the application; The charge pump phase-locked loop circuit comprises a frequency discriminator, a current steering dual-path switch charge pump, a low-pass filter, a voltage-controlled oscillator, a feedback frequency division circuit and a locking detection circuit; The frequency discriminator is connected with the feedback frequency division circuit, the current steering dual-path switch charge pump and the time-to-digital conversion circuit respectively, is used for comparing a frequency difference and a phase difference of the calibration feedback control signal formed by a preset reference signal and an output signal of the voltage-controlled oscillator, outputting a charge and discharge instruction to the current steering dual-path switch charge pump, and outputting a frequency discrimination phase discriminator positive output signal and a frequency discrimination phase discriminator negative output signal to the time-to-digital conversion circuit; The current steering dual-path switch charge pump is connected with the frequency discriminator and the low-pass filter respectively, is used for outputting a charging or discharging current to the low-pass filter based on the charge and discharge instruction output by the frequency discriminator; The low-pass filter is connected with the current steering dual-path switch charge pump and the voltage-controlled oscillator respectively, is used for converting the charging or discharging current output by the current steering dual-path switch charge pump into a control voltage; The voltage-controlled oscillator is connected with the low-pass filter and the feedback frequency division circuit respectively, is used for converting the control voltage output by the low-pass filter into a voltage control high-frequency signal proportional to the control voltage; The feedback frequency division circuit is connected with the voltage-controlled oscillator, the locking detection circuit and the frequency discriminator respectively, is used for performing frequency division processing on the voltage control high-frequency signal output by the voltage-controlled oscillator, and generating a feedback frequency division signal matched with the frequency of the reference signal and returning the feedback frequency division signal to the frequency discriminator and the locking detection circuit; The lock detection circuit is connected with the frequency discriminator, the feedback frequency division circuit and the time-to-digital conversion circuit respectively, is used for monitoring the frequency difference and the phase difference between the reference signal and the feedback frequency division signal output by the feedback frequency division circuit in real time, judging whether the difference value exceeds a predetermined threshold, and outputting a phase-locked loop lock indication signal to the time-to-digital conversion circuit.

[0015] Optionally, the current steering dual-path switch charge pump comprises a pull-up branch, a pull-down branch and a charge pump circuit output node, the pull-down branch comprises a plurality of calibration pull-down branches, and the plurality of calibration pull-down branches are connected in parallel through a switch selection circuit. The pull-up branch comprises a first switch and a pull-up current source, a first end of the pull-up current source is connected with a current source, a second end of the pull-up current source is connected with the low-pass filter through the output node after the first switch, and the first switch is turned on or turned off based on the positive output signal of the frequency discriminator, and the first switch provides a pull-up direction current to the low-pass filter after being turned on. The pull-down branch comprises a second switch and a pull-down current source, a first end of the pull-down current source is connected with the output node through the second switch, the second switch is turned on or turned off based on the negative output signal of the frequency discriminator, and the second switch provides a pull-down direction current to the low-pass filter after being turned on, and a second end of the pull-down current source is grounded. The plurality of calibration pull-down branches are connected in parallel through the switch selection circuit, the switch selection circuit comprises a plurality of electronic switches, each electronic switch corresponds to a pull-down current source, and each electronic switch is used for receiving a calibration feedback control signal to control the turn-on or turn-off of each calibration pull-down branch. The charge pump circuit output node is connected with the low-pass filter, and the currents of the pull-up branch and the pull-down branch are collected at the node.

[0016] Optionally, the feedback frequency division circuit comprises a multi-mode frequency divider and an integral comparison modulator. A first end of the multi-mode frequency divider is connected with a voltage-controlled oscillator, and a second end of the multi-mode frequency divider is connected with the lock detection circuit, the frequency discriminator and the integral comparison modulator respectively, the multi-mode frequency divider is used for receiving a voltage-controlled high-frequency signal output by the voltage-controlled oscillator and performing frequency division processing, and the multi-mode frequency divider provides a feedback frequency division signal for the frequency discriminator and the lock detection circuit. The integral comparison modulator is connected with the input and output ends of the multi-mode frequency divider respectively, and is used for outputting a modulated control signal to adjust the frequency division precision of the multi-mode frequency divider based on the frequency division signal output by the multi-mode frequency divider.

[0017] Optionally, the low-pass filter comprises a resistor, a first capacitor and a second capacitor. A first end of the resistor is connected with the current steering dual-path switch charge pump and the voltage-controlled oscillator respectively, and a second end of the resistor is connected with a first end of the first capacitor. The second end of the first capacitor is grounded. The first end of the second capacitor is connected with the current steering dual-path switch charge pump and the voltage controlled oscillator respectively, and the second end is grounded.

[0018] The beneficial effects of the present application are as follows: Compared with the prior art, the application provides a charge pump phase-locked loop real-time calibration circuit based on phase detection, which comprises a time-to-digital conversion circuit, a thermometer code conversion circuit and a logic state machine circuit, wherein the time-to-digital conversion circuit is used to convert the frequency and phase discriminator positive output signal and the frequency and phase discriminator negative output signal of the frequency and phase discriminator into a time-to-digital signal corresponding to the phase error based on the phase-locked loop locking indication signal output by the locking detection circuit, the thermometer code conversion circuit is used to convert the time-to-digital signal into a binary code, and the logic state machine circuit is used to form a calibration feedback control signal based on the binary code and transmit the calibration feedback control signal to the current steering dual-path switch charge pump of the charge pump phase-locked loop circuit to calibrate the voltage control signal output by the current steering dual-path switch charge pump in real time. The charge pump phase-locked loop real-time calibration circuit improves analog mismatch with digital calibration logic, effectively improves the consistency of the charge pump phase-locked loop circuit under different processes, temperatures and power voltages with real-time calibration, and improves the reference spur level of the charge pump phase-locked loop circuit at a smaller power consumption and area cost. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0020] Figure 1 A structure schematic diagram of a charge pump phase-locked loop real-time calibration circuit based on phase detection provided by the present application is shown in the figure. Figure 2 A structure schematic diagram of a charge pump phase-locked loop circuit provided by the present application is shown in the figure. Figure 3 A structure schematic diagram of a charge pump phase-locked loop real-time calibration circuit based on phase detection and a charge pump phase-locked loop circuit provided by the present application is shown in the figure. Figure 4 A structure schematic diagram of a time-to-digital conversion circuit provided by the present application is shown in the figure. Figure 5 A flowchart of a charge pump phase-locked loop real-time calibration method based on phase detection provided by the present application is shown in the figure.

[0021] Reference signs: 100: charge pump phase-locked loop circuit; 110: reference signal; 120: frequency discriminator; 130: current-steering dual-path switched charge pump; 140: low pass filter; 150: voltage controlled oscillator; 160: feedback frequency divider circuit; 170: lock detection circuit; 200: charge pump phase-locked loop real-time calibration circuit; 210: time-to-digital conversion circuit; 220: thermometer code conversion circuit; 230: subtractor circuit; 240: buffer circuit; 250: frequency divider circuit; 260: logic state machine circuit. DETAILED DESCRIPTION

[0022] In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular sequences of acts, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known methods, devices, circuits, and

[0023] It will be understood that the terms "comprises" and / or "comprising," when used in this specification, include the presence of one or more features, integers, steps, operations, elements, and / or components described in the specification, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0024] It will be understood that the term "and / or," when used in the specification and in the claims, is intended to mean one or more of the associated listed items can be present, and, in the absence of more specific language, is intended to include all possible combinations of the associated listed items.

[0025] As used in this specification and claims, the terms "if" and "when" can be interpreted to mean "upon determination" or "in response to a determination" or "upon detection" or "in response to a detection," depending on the context. Similarly, the phrase "if determined" or "if detected" can be interpreted to mean "upon determination" or "in response to a determination" or "upon detection" or "in response to a detection," depending on the context.

[0026] In addition, the terms "first," "second," "third," etc. are used herein only to distinguish one element from another, and do not imply a relative importance or a specific order.

[0027] Reference to "one embodiment" or "an embodiment" or "some embodiments" or "one implementation" or "an implementation" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrase "in one embodiment" or "in some embodiments" or "in other embodiments" or "in still other embodiments" or other similar phrases in the specification are not necessarily all referring to the same embodiment.

[0028] To solve at least one of the problems existing in the prior art, according to one aspect of the application, the embodiments disclose a phase detection based charge pump phase-locked loop real-time calibration circuit 200, as shown in the figure, the circuit comprises: Figures 1-3 A time-to-digital conversion circuit 210 is connected with the frequency discriminator 120 and the lock detection circuit 170 of the charge pump phase-locked loop circuit, and is used for converting the frequency discrimination positive output signal and the frequency discrimination negative output signal of the frequency discriminator 120 into a time-to-digital signal corresponding to a phase error based on the phase-locked loop lock indication signal output by the lock detection circuit 170.

[0029] It should be noted that the time-to-digital signal corresponding to the phase error is a digital signal expressed in 31-bit thermometer code, and the thermometer code has higher noise immunity and linearity than binary, can capture a small phase error, and provides a quantitative basis for subsequent high-precision calibration.

[0030] A thermometer code conversion circuit 220 is connected with the time-to-digital conversion circuit 210, and is used for converting the time-to-digital signal into binary code.

[0031] Wherein, the thermometer code retains the high precision of the time-to-digital conversion circuit, and after being converted into binary code, it is convenient for subsequent digital logic processing in the subtracter, greatly reduces the operation complexity of the subsequent digital logic, and solves the problems of high operation complexity of the thermometer code and large circuit size and high delay when directly participating in operation.

[0032] Wherein, the time-to-digital conversion circuit 210 is as shown in the figure. Figure 4 ​As shown, the time-to-digital conversion circuit 210 is based on a differential delay chain and a data flip-flop sampling structure, removes the edge asymmetry of the input differential signal through an edge calibration module, and then converts the phase error corresponding time difference into signal propagation stage number through a differential delay chain composed of two paths of 32 inverters. Finally, the data flip-flop array is sampled and latched by the reference clock to form a thermometer code, and the quantization of the phase error of the differential signal output by the phase frequency detector 120 is realized. After the charge pump phase-locked loop circuit 100 is locked, the differential output signal (with phase error information) of the phase frequency detector 120 is first passed through the edge calibration module to calibrate the rising edge and falling edge of the input differential signal to a preset intermediate level, thereby eliminating the influence of edge asymmetry on quantization accuracy. The calibrated differential signal enters the differential delay chain composed of two paths of 32 inverter modules. The positive and negative paths of the differential signal propagate in their respective inverter chains, and the greater the time difference corresponding to the phase error, the more inverter stages the signal can propagate through. The output end of each inverter module is connected to a data flip-flop, and the data flip-flop uses the reference clock (or the synchronous calibration clock) as the sampling clock to sample and latch the level state output by the inverter at the rising edge of the clock. The output state (1 indicates that the signal has reached this stage, and 0 indicates that it has not reached this stage) of different stages of data flip-flops together form a thermometer code, and the time-to-digital conversion is completed.

[0033] It should be noted that the inverter stage number of the time-to-digital conversion circuit can be flexibly adjusted according to the time resolution and quantization range requirements, and the present application does not limit this.

[0034] Specifically, the resolution of the time-to-digital conversion circuit 210 is 50ps, and the phase error range that can be detected by the 31-bit time-to-digital conversion circuit 210 is 50ps-1550ps. The time-to-digital signal output by the time-to-digital conversion circuit 210 is a 31-bit thermometer code, and to optimize the number of registers and facilitate digital operation, the thermometer code conversion circuit 220 converts the thermometer code into a binary code. In one specific example, the phase error signal output by the charge pump phase-locked loop circuit 100 after locking is 250ps, and the output of the time-to-digital conversion circuit 210 is 1111100000000000000000000000000, which converts the 5-bit binary code 00101 containing the 250ps phase error information.

[0035] The logic state machine circuit 260 is coupled to the thermometer code conversion circuit 220 and is used to form a calibration feedback control signal based on the binary code and transmit the calibration feedback control signal to the current steering dual-path switch charge pump 130 of the charge pump phase-locked loop circuit to real-time calibrate the voltage control signal output by the current steering dual-path switch charge pump.

[0036] The logic state machine circuit 260 generates a calibration feedback control signal or a calibration circuit end indication signal or a calibration circuit overflow indication signal according to the quantized binary code through preset calibration conditions. The logic state machine circuit 260 generates a targeted calibration feedback control signal based on the quantized binary code through preset calibration conditions, which directly acts on the current steering dual-path switch charge pump 130 to adjust the current matching degree in real time and correct the voltage control high-frequency signal of the voltage controlled oscillator 150 in real time. This dynamic calibration mechanism can track and correct the phase error caused by process deviation, power voltage fluctuation, temperature change and the like in real time, avoid the limitation that the traditional one-time calibration cannot cope with dynamic changes, and ensure that the charge pump phase-locked loop circuit 100 can still maintain stable performance under complex working conditions.

[0037] The output characteristics of the current steering dual-path switch charge pump 130 are calibrated in real time, and finally the stability of the output signal of the voltage controlled oscillator 150 can be improved, the reference spur caused by the phase error can be reduced, and the consistency of the charge pump phase-locked loop circuit 100 under different processes and environmental conditions can be improved.

[0038] It should be noted that the preset calibration conditions include a calibration start condition and a calibration end condition, and the preset calibration conditions are limited according to requirements, which are not limited in the present application.

[0039] In an optional embodiment, as shown in Figure 1 Further comprising: The subtracter circuit 230 is connected with the thermometer code conversion circuit 220 and the logic state machine circuit 260 respectively, and is used for outputting a phase calibration indication signal based on a preset reference phase error signal and the binary code. The logic state machine circuit outputs the calibration feedback control signal based on the phase calibration indication signal.

[0040] The phase calibration indication signal output by the subtracter circuit 230 is transmitted to the logic state machine circuit 260, which generates a corresponding calibration feedback control signal according to the specific error direction or signal size of the indication signal, and finally acts on the current steering dual-path switch charge pump 130 as shown in the figure. The current steering dual-path switch charge pump 130 starts the detection and calibration process of the phase error of the charge pump phase-locked loop circuit 100, compensates the phase error by adjusting the output charge-discharge current of the current steering dual-path switch charge pump 130, until the phase error of the system approaches the preset reference value. The logic state machine circuit 260 outputs a charge pump calibration circuit end indication signal, and the current calibration process is completed. The charge pump phase-locked loop real-time calibration circuit 200 stops working or enters a sleep state.

[0041] Specifically, the subtractor circuit 230 implements binary subtraction through a complement operation based on the principle of full adder, compares the binary code (containing the actual limit error) with the binary code of the reference phase error signal, and outputs a phase calibration indication signal to the logic state machine circuit 260. When the binary code containing the actual phase error is greater than or equal to the reference phase error signal, a high level is output, and the logic state machine circuit 260 forms a calibration feedback control signal acting on the current steering dual-path switched charge pump 130 to start the detection and calibration of the phase error. Otherwise, a low level is output, and the detection and calibration process of the phase error of the charge pump phase-locked loop circuit 100 is not started. In a specific embodiment, the reference phase error is 300 ps (binary code 00110), and when the actual phase error is 450 ps (binary code 01001), the subtractor circuit 230 outputs a high level to generate a calibration feedback control signal acting on the current steering dual-path switched charge pump 130, triggering the detection and calibration process of the phase error of the charge pump phase-locked loop circuit 100.

[0042] In an optional embodiment, as shown in Figure 2 the clock synchronization circuit is further included for generating a clock synchronization signal based on the reference signal 110 of the charge pump phase-locked loop circuit 100 and transmitting the clock synchronization signal to the logic state machine circuit 260.

[0043] The clock synchronization circuit provides a stable and synchronized clock signal for the logic state machine circuit 260, ensuring that all operations in the calibration process are performed under a unified time reference, avoiding calibration errors caused by timing disorders.

[0044] The clock synchronization circuit is based on the original reference signal (such as a reference clock input from outside the system) used by the charge pump phase-locked loop circuit to implement frequency or phase locking, generates a clock synchronization signal through internal buffering, frequency division, shaping, and other signal processing, so that the clock of the calibration system is homologous to the core reference signal 110 of the charge pump phase-locked loop circuit 100, ensuring the timing consistency of the calibration action and the operation of the charge pump phase-locked loop circuit.

[0045] In addition, after the generated clock synchronization signal is transmitted to the logic state machine circuit 260, it is mainly used to control the state switching of the logic state machine and ensure that the sampling and processing actions of the logic state machine on the phase calibration indication signal output by the subtractor circuit 230 are synchronized with the working timing of the charge pump phase-locked loop circuit 100, avoiding additional phase disturbances caused by asynchronous operations.

[0046] In an optional embodiment, as shown in Figure 1 the clock synchronization circuit includes: The buffer circuit 240 is connected with the logic state machine circuit 260, and is configured to convert the preset first calibration clock signal into an intermediate calibration clock signal based on the enable signal of the calibration feedback control signal.

[0047] The buffer circuit 240 can enhance the driving capability of the first calibration clock signal, avoid signal attenuation caused by long-distance transmission or heavy load, and isolate the front and rear circuits to prevent the load change of the frequency divider circuit 250 from interfering with the first calibration clock signal.

[0048] The frequency divider circuit 250 is connected with the buffer circuit 240 and the logic state machine circuit 260, respectively, and is configured to perform frequency reduction on the intermediate calibration clock signal to obtain a second calibration clock signal based on the enable signal of the calibration feedback control signal, and transmit the second calibration clock signal to the logic state machine circuit 260 as the clock synchronization signal.

[0049] The frequency divider circuit 250 matches the clock frequency with the working rate of the logic state machine circuit 260, ensures that the frequency of the synchronization signal is synchronized with the working timing of the charge pump phase-locked loop circuit 100, and triggers the logic state machine circuit 260 to perform calibration once every rising edge of the second calibration clock signal output.

[0050] The logic state machine circuit 260 first determines the current calibration period according to the second calibration clock signal output by the frequency divider circuit 250, performs phase error calibration based on the division of the initial period and the non-initialization period, and realizes calibration by outputting a calibration feedback control signal. If it is the initial period, it is determined whether the phase error is greater than or equal to a preset reference phase error. If the phase error is greater than the preset reference phase error, it is determined whether the phase calibration indication signal meets the preset calibration condition of the calibration start condition. If the phase calibration indication signal meets the preset calibration condition of the calibration start condition, the calibration feedback control signal is set to the first control signal and output. If the phase calibration indication signal does not meet the preset calibration condition of the calibration start condition, an overflow indication signal of the phase detection and calibration circuit is output to prompt an abnormality. If the phase error is less than the preset reference phase error, the initial value of the preset calibration feedback control signal is directly output and a calibration circuit end indication signal is output to terminate the calibration.

[0051] If the calibration period is not the initial period, the logic state machine circuit 260 provides two implementations, both of which are based on the phase calibration indication signal as the basis for outputting the second or third control signal. In one implementation, the logic state machine circuit 260 directly determines whether the phase calibration indication signal satisfies the calibration start condition, and if it satisfies the preset calibration condition of the calibration start condition, the calibration feedback control signal is set to the second control signal and output; if it does not satisfy the preset calibration condition of the calibration start condition, the calibration feedback control signal is set to the third control signal and output. In another implementation, the logic state machine circuit 260 first determines whether the phase calibration indication signal satisfies the preset calibration condition of the calibration end condition, and then determines the calibration start condition of the preset calibration condition. If the calibration end condition of the preset calibration condition is satisfied, the current calibration feedback control signal is set to the second control signal and the calibration circuit end indication signal is output, and if the calibration end condition of the preset calibration condition is not satisfied, the above-mentioned determination of whether the current charge pump phase-locked loop circuit satisfies the calibration start condition of the preset calibration condition is performed, and if it is satisfied, the second control signal (decrease adjustment) is output, and if it is not satisfied, the third control signal (increase adjustment) is output.

[0052] When the calibration end condition of the preset calibration condition is satisfied, the logic state machine circuit 260 outputs the calibration circuit end indication signal (high level effective). If it is an abnormal end, the logic state machine circuit 260 synchronously outputs the calibration circuit overflow indication signal, and at the same time, the enable signal of the calibration feedback control signal is pulled down to low level, the charge pump phase-locked loop real-time calibration circuit 200 is turned off, and the power consumption is reduced.

[0053] In a specific example, taking the digital calibration bit n=5 of the calibration feedback control signal as an example, the digital calibration bit is 5 bits, and the logic state machine circuit 260 realizes phase error calibration based on a successive approximation register logic, and gradually adjusts the digital calibration bit of the current steering dual-path switched charge pump 130 through phased adjustment from a large range to a small range. The initial state of the digital calibration bit is that the highest bit is high and the remaining bits are low (n=5, initial value is 5'b10000, corresponding to decimal 16). There are 2n=10 control periods, and in the initial period, it is determined whether the phase calibration indication signal satisfies the calibration start condition of the preset calibration condition. If it does not satisfy the calibration start condition of the preset calibration condition, the digital calibration bit remains the initial value 5'b10000 output, or triggers an abnormal process (such as the calibration circuit overflow indication signal), and if it satisfies the calibration start condition of the preset calibration condition, the calibration is performed and the digital calibration bit is decreased (n=5, =8), that is, from 5'b10000 to 5'b01000; in the second to n-1 period (2nd to 4th period), the digital calibration bit is adjusted by decreasing the weight bit by bit (t is a cycle number, t≥1), when n=5, the digital calibration bit step is 2, 1, 1, 1, 1, respectively =2, =1, that is, when the calibration start condition of the preset calibration condition is met, the digital calibration bit is reduced by the current step, and when the calibration start condition of the preset calibration condition is not met, the digital calibration bit is increased by the current step; in the n+1th to 2n-1th cycle (the 6th to 9th cycle), the digital calibration bit is adjusted by ±1, that is, fine adjustment, when the calibration start condition of the preset calibration condition is met, the digital calibration bit is reduced by 1; when the calibration start condition of the preset calibration condition is not met, the digital calibration bit is increased by 1. For example, after the 5th cycle, the calibration bit is 5'b00101, in the 6th cycle, when the calibration start condition of the preset calibration condition is met, it is adjusted to 5'b00100, and when the calibration start condition of the preset calibration condition is not met, it is adjusted to 5'b00110; in the 2n cycle (the 10th cycle), only the step is adjusted by 1 or the step is kept, when the calibration start condition of the preset calibration condition is met, the digital calibration bit is reduced by 1, and when the calibration start condition of the preset calibration condition is not met, the digital calibration bit is kept unchanged. After the first 9 cycles, the calibration bit is 5'b00111, in the 10th cycle, when the calibration start condition of the preset calibration condition is not met, it is kept as 5'b00111, and when the calibration start condition of the preset calibration condition is met, it is adjusted to 5'b00110.

[0054] It should be noted that the calibration start condition of the preset calibration condition is related to the initial value of the phase calibration indication signal, and if the initial value of the phase calibration indication signal is high, it indicates that the phase error output by the charge pump circuit is greater than the input reference phase error in the first calibration cycle. The calibration end condition of the preset calibration condition can be set to be that the digital calibration bits of the charge pump phase-locked loop circuit 100 are all 0 and the phase detection indication signal is still high, or the adjustment process of 2n control cycles is completed.

[0055] In the embodiment, the calibration feedback control signals output by the logic state machine circuit 260 include three control signals, namely a first control signal, a second control signal and a third control signal. The first control signal is used to instruct the charge pump circuit to increase the compensation current (or to make a large amplitude phase adjustment when the phase error is too large). In the initial calibration period, the first control signal is output when the phase error is greater than the preset reference phase error and the phase calibration indication signal satisfies the preset calibration start condition. The second control signal is used to instruct the charge pump circuit to reduce the compensation current (or to make a small amplitude phase adjustment). In the non-initial calibration period, the second control signal is output when the phase calibration indication signal satisfies the preset calibration start condition, or in some embodiments, the second control signal is output when the calibration end condition is satisfied. The third control signal is used to instruct the charge pump circuit to keep the current compensation current unchanged (i.e. no phase adjustment). In the non-initial calibration period, the third control signal is output when the phase calibration indication signal does not satisfy the preset calibration start condition. In the initial period, if the phase error has exceeded the reference value and the start condition is satisfied, the logic state machine outputs the first control signal to make a large adjustment to quickly converge. In the non-initial period, if adjustment is still needed, the second control signal is output to make fine adjustment; if adjustment is not needed, the third control signal is output to keep the status quo.

[0056] In optional embodiments, as shown in Figure 1 and Figure 2 The charge pump phase-locked loop circuit 100 includes a current steering dual-path switch charge pump 130, which includes a pull-up branch, a pull-down branch and a charge pump circuit external output node. The pull-down branch includes a plurality of calibration pull-down branches connected in parallel through a switch selection module.

[0057] The logic state machine circuit 260 is configured to form calibration feedback control signals for the switch selection circuit based on the binary code input. The switch selection circuit is configured to control the conduction or disconnection of each calibration pull-down branch based on the calibration feedback control signals.

[0058] The charge pump circuit external output node is connected to a low-pass filter 140, and the currents of the pull-up branch and the pull-down branch are aggregated at this node.

[0059] Each calibration pull-down circuit includes an independent current source and a switch, and the parallel design means that the total pull-down current can be flexibly adjusted by controlling the conduction or disconnection of different branches.

[0060] It should be noted that the logic state machine circuit 260 generates corresponding calibration feedback control signals based on the binary code output by the subtractor circuit 230, which reflects the current phase error, to indicate which calibration pull-down branches need to be turned on or off. After receiving the calibration feedback control signals, the switch selection circuit controls the on-off state of the switches in each calibration pull-down branch. If the current phase error indicates that the pull-down current is insufficient, causing the phase to lag, more calibration pull-down branches are turned on to increase the total pull-down current. If the pull-down current is too large, causing the phase to lead, some calibration pull-down branches are turned off to reduce the total pull-down current.

[0061] This structure can achieve fine adjustment of the pull-down current through multi-parallel and switch selection, thereby compensating for the current mismatch (e.g., asymmetric pull-up and pull-down currents) of the current steering dual-path switch charge pump 130 caused by factors such as process and temperature; real-time correction of the phase error to improve the locking accuracy and stability of the charge pump phase-locked loop circuit 100. Compared with single current source adjustment, the multi-calibration branch can provide a more flexible current adjustment range and resolution. This circuit design makes the pull-down current of the current steering dual-path switch charge pump 130 configurable, and the logic state machine circuit 260 dynamically adjusts this configuration by outputting calibration control signals, ultimately achieving real-time calibration of the phase error of the charge pump phase-locked loop circuit 100.

[0062] Based on the same inventive concept, the present application also discloses a charge pump phase-locked loop real-time calibration method based on phase detection, as shown in Figure 5 The method comprises the following steps: S100: converting the frequency discrimination phase discriminator positive output signal and the frequency discrimination phase discriminator negative output signal of the frequency discrimination phase discriminator 120 into a time-to-digital signal corresponding to the phase error based on the phase-locked loop locking indication signal output by the locking detection circuit 170.

[0063] S200: converting the time-to-digital signal into a binary code.

[0064] S300: forming a calibration feedback control signal based on the binary code and transmitting the calibration feedback control signal to the charge pump circuit of the charge pump phase-locked loop circuit 100 to real-time calibrate the voltage control signal output by the charge pump circuit.

[0065] Since the principle of solving the problem of the system is similar to the above method, the implementation of the system can refer to the implementation of the method, which will not be described here.

[0066] Based on the same inventive concept, the present application also discloses a charge pump phase-locked loop device based on phase detection, comprising the charge pump phase-locked loop circuit 100 and the charge pump phase-locked loop real-time calibration circuit 200 as described above.

[0067] The charge pump phase-locked loop circuit comprises a frequency discriminator, a current steering dual-path switch charge pump, a low-pass filter, a voltage-controlled oscillator, a feedback frequency division circuit and a lock detection circuit.

[0068] The frequency discriminator 120 is connected with the feedback frequency division circuit 160, the current steering dual-path switch charge pump 130 and the time-to-digital conversion circuit 210, respectively, for comparing the frequency difference and phase difference of the preset reference signal 110 and the output signal of the voltage-controlled oscillator 150 to form the calibration feedback control signal, outputting the charge and discharge command to the current steering dual-path switch charge pump 130, and outputting the frequency discriminator positive output signal and the frequency discriminator negative output signal to the time-to-digital conversion circuit 210.

[0069] It should be noted that the frequency discriminator 120, as the error detection core, receives the external preset reference signal 110 and the feedback frequency division signal returned by the feedback frequency division circuit 160, compares the frequency difference and phase difference of the two signals, outputs the charge and discharge command to control the charging and discharging of the current steering dual-path switch charge pump 130, and transmits the frequency discriminator positive output signal and the frequency discriminator negative output signal reflecting the phase error to the time-to-digital conversion circuit 210 for subsequent calibration by the charge pump phase-locked loop real-time calibration circuit 200.

[0070] The current steering dual-path switch charge pump 130 is connected with the frequency discriminator 120 and the low-pass filter 140, respectively, for outputting the charging or discharging current to the low-pass filter 140 based on the charge and discharge command output by the frequency discriminator 120.

[0071] It should be noted that the current steering dual-path switch charge pump 130 receives the charge and discharge command of the frequency discriminator 120, and outputs the charging current (pull-up current) or discharging current (pull-down current) to the low-pass filter 140; at the same time, the current steering dual-path switch charge pump 130 receives the feedback control signal of the charge pump phase-locked loop real-time calibration circuit 200, and adjusts the internal branch switch to realize current calibration.

[0072] The low-pass filter 140 is connected with the current steering dual-path switch charge pump 130 and the voltage-controlled oscillator 150, respectively, for converting the charging or discharging current output by the current steering dual-path switch charge pump 130 into a control voltage.

[0073] The low-pass filter 140 converts the charging or discharging current output by the current steering dual-path switch charge pump 130 into a stable DC control voltage, and transmits the stable DC control voltage to the voltage-controlled oscillator 150.

[0074] The voltage-controlled oscillator 150 is connected with the low-pass filter 140 and the feedback frequency division circuit 160 respectively, for converting the control voltage outputted by the low-pass filter 140 into a voltage-controlled high-frequency signal proportional to the control voltage.

[0075] The voltage-controlled oscillator 150 generates a high-frequency signal with a frequency proportional to the control voltage outputted by the low-pass filter 140, and transmits the voltage-controlled high-frequency signal to the feedback frequency division circuit 160.

[0076] The feedback frequency division circuit 160 is connected with the voltage-controlled oscillator 150, the lock detection circuit 170 and the phase-frequency detector 120 respectively, for performing frequency division processing on the voltage-controlled high-frequency signal outputted by the voltage-controlled oscillator 150, and generating a feedback frequency division signal matching the frequency of the reference signal 110, which is transmitted back to the phase-frequency detector 120 and the lock detection circuit 170.

[0077] The lock detection circuit 170 is connected with the phase-frequency detector 120, the feedback frequency division circuit 160 and the time-to-digital conversion circuit 210 respectively, for monitoring the frequency difference and phase difference between the reference signal 110 and the feedback frequency division signal outputted by the feedback frequency division circuit 160 in real time, judging whether the difference exceeds a predetermined threshold, and outputting a phase-locked loop lock indication signal to the time-to-digital conversion circuit 210.

[0078] It should be noted that the lock detection circuit 170 monitors the frequency and phase difference between the reference signal 110 and the feedback frequency division signal in real time, and outputs a phase-locked loop lock indication signal when the difference is less than a predetermined threshold, triggering the charge pump phase-locked loop real-time calibration circuit 200 to start working. At this time, the charge pump phase-locked loop circuit 100 has been basically locked, but needs to calibrate the slight error.

[0079] A specific example is used to illustrate, for example, Figure 1 and Figure 2As shown, the whole device workflow forms a double closed loop of the charge pump phase-locked loop circuit 100 and the charge pump phase-locked loop real-time calibration circuit 200. The locking process of the charge pump phase-locked loop circuit 100 is that the frequency discriminator 120 detects the difference between the reference signal 110 and the feedback frequency-divided signal, and outputs a charge-discharge command to the current-steering dual-path switch charge pump 130. The current-steering dual-path switch charge pump 130 outputs a corresponding charging or discharging current to the low-pass filter 140, which converts the charging or discharging current into a control voltage to the voltage-controlled oscillator 150. The voltage-controlled oscillator 150 adjusts the output frequency to a voltage-controlled high-frequency signal to the feedback frequency-dividing circuit 160, which is fed back after frequency division until the basic locking is detected by the locking detection circuit 170, and outputs a phase-locked loop locking indication signal to the time-to-digital conversion circuit 210. The correction process of the charge pump phase-locked loop real-time calibration circuit 200 is that after the locking detection circuit 170 confirms the basic locking, it outputs a phase-locked loop locking indication signal to the time-to-digital conversion circuit 210. The time-to-digital conversion circuit 210 quantizes the phase error into a corresponding time-to-digital signal and transmits it to the thermometer code conversion circuit 220. The thermometer code conversion circuit 220 converts the time-to-digital signal into a binary code and transmits it to the subtracter circuit 230. The subtracter circuit 230 outputs a phase calibration indication signal based on the preset reference phase error signal and the binary code to the logic state machine circuit 260. The logic state machine circuit 260 generates a calibration feedback control signal to the current-steering dual-path switch charge pump 130, which adjusts the charging and discharging current to compensate for the error, thereby further improving the accuracy of the charge pump phase-locked loop circuit 100.

[0080] This design realizes the basic locking function through the charge pump phase-locked loop circuit 100, and eliminates non-ideal errors caused by process, environment, etc. through the charge pump phase-locked loop real-time calibration circuit, ultimately achieving high-precision, high-stability frequency and phase control, and is suitable for scenes with strict requirements on signal quality.

[0081] In an optional implementation, the current-steering dual-path switch charge pump 130 includes a pull-up branch, a pull-down branch, and a charge pump circuit output node. The pull-down branch includes multiple calibration pull-down branches, and the multiple calibration pull-down branches are connected in parallel through a switch selection circuit.

[0082] The pull-up branch includes a first switch and a pull-up current source. The first end of the pull-up current source is connected to a current source, and the second end is connected to the low-pass filter 140 through the output node after passing through the first switch. The first switch is turned on or turned off based on the positive output signal of the frequency discriminator 120, and provides a pull-up direction current to the low-pass filter 140 after being turned on.

[0083] The pull-down branch comprises a second switch and a pull-down current source, a first end of the pull-down current source is connected with the output node through the second switch, the second switch is turned on or turned off based on the frequency and phase discriminator negative output signal, and the pull-down current source provides a pull-down direction current to the low-pass filter after being turned on.

[0084] The multiple calibration pull-down branches are connected in parallel through a switch selection circuit, the switch selection circuit comprises multiple electronic switches, each electronic switch corresponds to a pull-down current source, and is used to receive a calibration feedback control signal to control the turn-on or turn-off of each calibration pull-down branch.

[0085] The charge pump circuit is connected with a low-pass filter 140 at an output node, and the currents of the pull-up branch and the pull-down branch are collected at the output node.

[0086] The switch selection circuit receives the calibration feedback control signal, controls the turn-on or turn-off of the corresponding switch in each calibration pull-down branch, adjusts the calibration current superimposed on the basis pull-down current in different gears, and makes the total discharge current of the pull-down branch be flexibly adjusted according to the phase error requirement.

[0087] Taking a specific example, it is assumed that the frequency and phase discriminator 120 detects that the reference signal 110 is ahead of the feedback frequency signal in phase (that is, the frequency of the voltage-controlled oscillator 150 needs to be increased), at this time, the pull-up branch works, the frequency and phase discriminator positive output signal is effective, the first switch is turned on, the pull-up current source provides the pull-up current to the low-pass filter 140 through the first switch and the output node of the current steering type double switch charge pump 130, charges, makes the control voltage output by the low-pass filter 140 be increased, and then makes the frequency of the voltage-controlled oscillator 150 be increased. When the frequency and phase discriminator 120 detects that the reference signal 110 is lagged behind the feedback frequency signal in phase (that is, the frequency of the voltage-controlled oscillator 150 needs to be reduced), at this time, the pull-down branch works, the frequency and phase discriminator negative output signal is effective, and the second switch is turned on. If the calibration feedback control signal indicates that a small pull-down current is required at this time, only part of the electronic switches in the switch selection circuit are turned on, a corresponding number of calibration pull-down branches are connected, a small pull-down current is extracted from the low-pass filter 140 through the turned-on second switch, and the low-pass filter 140 is discharged. If the calibration feedback control signal indicates that a large pull-down current is required, more electronic switches in the switch selection circuit are turned on, a larger number of calibration pull-down branches are connected, a large pull-down current is extracted from the low-pass filter 140, the control voltage output by the low-pass filter 140 is reduced, and the frequency of the voltage-controlled oscillator 150 is reduced.

[0088] In an optional embodiment, the feedback frequency dividing circuit 160 comprises a multi-mode frequency divider and an integral comparison modulator.

[0089] The first end of the multi-mode frequency divider is connected with the voltage-controlled oscillator 150, the second end is connected with the lock detection circuit 170, the frequency discriminator 120 and the integral comparison modulator respectively, for receiving the voltage-controlled high-frequency signal output by the voltage-controlled oscillator 150 and performing frequency division processing, providing feedback frequency division signals for the frequency discriminator 120 and the lock detection circuit 170.

[0090] The integral comparison modulator is connected with the input and output ends of the multi-mode frequency divider respectively, for outputting the modulated control signal based on the frequency division signal output by the multi-mode frequency divider to adjust the frequency division precision of the multi-mode frequency divider.

[0091] The multi-mode frequency divider has multiple frequency division ratios, and can switch between different frequency division coefficients such as N, N+1, rather than a single fixed frequency division ratio, and can adapt to different frequency requirements. The integral comparison modulator generates a dynamic control signal to optimize the frequency division effect by monitoring the input and output signals of the multi-mode frequency divider, and effectively reduces the quantization error in the frequency division process through dynamic adjustment, so that the feedback frequency division signal is closer to the ideal value, thereby improving the frequency synthesis precision and phase noise performance of the entire phase-locked loop. The feedback frequency division circuit realizes the conversion of high-frequency signal to feedback frequency division signal through the cooperation of the two modules, and guarantees the conversion precision through the dynamic adjustment mechanism, which is an important support for the charge pump phase-locked loop device to realize high-precision locking.

[0092] In an optional embodiment, the low-pass filter 140 includes a resistor, a first capacitor and a second capacitor.

[0093] The first end of the resistor is connected with the current-steering dual-path switch charge pump 130 and the voltage-controlled oscillator 150 respectively, and the second end is connected with the first end of the first capacitor.

[0094] The second end of the first capacitor is grounded.

[0095] The first end of the second capacitor is connected with the current-steering dual-path switch charge pump 130 and the voltage-controlled oscillator 150 respectively, and the second end is grounded.

[0096] It should be noted that the low-pass filter 140 utilizes the attenuation characteristic of the resistor-capacitor circuit to the high-frequency signal to filter out the high-frequency components (such as the glitches and noise generated by the switching action) in the output current of the current-steering dual-path switch charge pump 130, avoids the high-frequency interference from affecting the stability of the voltage-controlled oscillator 150, and at the same time converts the pulsed charging and discharging current output by the current-steering dual-path switch charge pump 130 into a continuous and stable DC control voltage, to provide a smooth control signal for the voltage-controlled oscillator 150. This resistor-capacitor combined low-pass filter 140 realizes the dual functions of current-to-voltage conversion and high-frequency noise filtering through a simple structure, provides a stable control voltage for the voltage-controlled oscillator 150, and is an important link to ensure the output signal quality of the charge pump phase-locked loop device.

[0097] The above only describes the embodiments of the present application and is not intended to limit the present application. The present application can have various modifications and changes for those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the scope of the claims of the present application.

Claims

1. A phase-detection-based charge-pump phase-locked loop real-time calibration circuit, characterized by, The application relates to a phase detection based charge pump phase-locked loop real-time calibration circuit. The time-to-digital conversion circuit is connected with a frequency discriminator and a lock detection circuit of the charge pump phase-locked loop circuit, and is used for converting frequency discrimination positive and negative output signals of the frequency discriminator into time-to-digital signals corresponding to phase errors based on a phase-locked loop lock indication signal output by the lock detection circuit; A thermometer code conversion circuit is connected with the time-to-digital conversion circuit, and is used for converting the time-to-digital signals into binary codes; A logic state machine circuit is coupled with the thermometer code conversion circuit, and is used for forming a calibration feedback control signal based on the binary codes, and transmitting the calibration feedback control signal to a current steering dual-path switch charge pump of the charge pump phase-locked loop circuit, so as to calibrate a voltage control signal output by the current steering dual-path switch charge pump in real time.

2. The phase-detect-based charge-pump phase-locked loop real-time calibration circuit of claim 1, wherein, Further comprising: A subtractor circuit is connected with the thermometer code conversion circuit and the logic state machine circuit respectively, and is used for outputting a phase calibration indication signal based on a preset reference phase error signal and the binary codes, and the logic state machine circuit outputs the calibration feedback control signal based on the phase calibration indication signal.

3. The phase-detect-based charge-pump phase-locked loop real-time calibration circuit of claim 1, wherein, Further comprising a clock synchronization circuit, which is used for generating a clock synchronization signal based on a reference signal of the charge pump phase-locked loop circuit, and transmitting the clock synchronization signal to the logic state machine circuit.

4. The phase-detect-based charge-pump phase-locked loop real-time calibration circuit of claim 3, wherein, The clock synchronization circuit comprises: A buffer circuit is connected with the logic state machine circuit, and is used for converting a preset first calibration clock signal into an intermediate calibration clock signal based on an enable signal of the calibration feedback control signal; A frequency divider circuit is connected with the buffer circuit and the logic state machine circuit respectively, and is used for performing frequency reduction processing on the intermediate calibration clock signal to obtain a second calibration clock signal based on the enable signal of the calibration feedback control signal, and transmitting the second calibration clock signal to the logic state machine circuit as the clock synchronization signal.

5. The phase-detect-based charge-pump phase-locked loop real-time calibration circuit of claim 1, wherein, The charge pump phase-locked loop circuit comprises a current steering dual-path switch charge pump, the current steering dual-path switch charge pump comprises an up pull branch, a down pull branch and a plurality of calibration down pull branches, and the plurality of calibration down pull branches are arranged in parallel through a switch selection circuit; The logic state machine circuit is used for forming a calibration feedback control signal input into the switch selection circuit based on the binary codes, and the switch selection circuit is used for controlling conduction or disconnection of each calibration down pull branch based on the calibration feedback control signal.

6. A phase-detection-based charge-pump phase-locked loop real-time calibration method, characterized in that, The application relates to a phase detection based charge pump phase-locked loop real-time calibration circuit. The time-to-digital conversion circuit is connected with a frequency discriminator and a lock detection circuit of the charge pump phase-locked loop circuit, and is used for converting frequency discrimination positive and negative output signals of the frequency discriminator into time-to-digital signals corresponding to phase errors based on a phase-locked loop lock indication signal output by the lock detection circuit; A thermometer code conversion circuit is connected with the time-to-digital conversion circuit, and is used for converting the time-to-digital signals into binary codes; A logic state machine circuit is coupled with the thermometer code conversion circuit, and is used for forming a calibration feedback control signal based on the binary codes, and transmitting the calibration feedback control signal to a current steering dual-path switch charge pump of the charge pump phase-locked loop circuit, so as to calibrate a voltage control signal output by the current steering dual-path switch charge pump in real time.

7. A phase-detect-based charge-pump phase-locked loop apparatus, characterized by, The application relates to a phase detection based charge pump phase-locked loop real-time calibration circuit and a charge pump phase-locked loop circuit. The charge pump phase-locked loop circuit comprises a frequency discriminator, a current steering dual-path switch charge pump, a low-pass filter, a voltage-controlled oscillator, a feedback frequency division circuit and a lock detection circuit; The frequency discriminator is connected with the feedback frequency division circuit, the current steering dual-path switch charge pump and the time-to-digital conversion circuit respectively, and is used for comparing a frequency difference and a phase difference of the calibration feedback control signal formed by comparing a preset reference signal and an output signal of the voltage-controlled oscillator, outputting a charge-discharge instruction to the current steering dual-path switch charge pump, and outputting a frequency discriminator positive output signal and a frequency discriminator negative output signal to the time-to-digital conversion circuit; The current steering dual-path switch charge pump is connected with the frequency discriminator and the low-pass filter respectively, and is used for outputting a charging or discharging current to the low-pass filter based on the charge-discharge instruction output by the frequency discriminator; The low-pass filter is connected with the current steering dual-path switch charge pump and the voltage-controlled oscillator respectively, and is used for converting the charging or discharging current output by the current steering dual-path switch charge pump into a control voltage; The voltage-controlled oscillator is connected with the low-pass filter and the feedback frequency division circuit respectively, and is used for converting the control voltage output by the low-pass filter into a voltage-controlled high-frequency signal proportional to the control voltage; The feedback frequency division circuit is connected with the voltage-controlled oscillator, the lock detection circuit and the frequency discriminator respectively, and is used for performing frequency division processing on the voltage-controlled high-frequency signal output by the voltage-controlled oscillator to generate a feedback frequency division signal matched with the frequency of the reference signal, and feeding back the feedback frequency division signal to the frequency discriminator and the lock detection circuit; The lock detection circuit is connected with the frequency discriminator, the feedback frequency division circuit and the time-to-digital conversion circuit respectively, and is used for monitoring the frequency difference and the phase difference between the reference signal and the feedback frequency division signal output by the feedback frequency division circuit in real time, judging whether the difference value exceeds a predetermined threshold, and outputting a phase-locked loop lock indication signal to the time-to-digital conversion circuit.

8. The phase-detect-based charge-pump phase-locked loop device of claim 7, wherein, The current steering dual-path switch charge pump comprises a pull-up branch, a pull-down branch and a charge pump circuit output node, the pull-down branch comprises a plurality of calibration pull-down branches, and the plurality of calibration pull-down branches are connected in parallel through a switch selection circuit; The pull-up branch comprises a first switch and a pull-up current source, a first end of the pull-up current source is connected with a current source, a second end of the pull-up current source is connected with the low-pass filter through the output node after passing through the first switch, the first switch is turned on or turned off based on the frequency discriminator positive output signal, and the first switch provides a pull-up direction current to the low-pass filter after being turned on; The pull-down branch comprises a second switch and a pull-down current source, a first end of the pull-down current source is connected with the output node through the second switch, the second switch is turned on or turned off based on the frequency discriminator negative output signal, the second switch provides a pull-down direction current to the low-pass filter after being turned on, and a second end of the pull-down current source is grounded; The plurality of calibration pull-down branches are connected in parallel through the switch selection circuit, the switch selection circuit comprises a plurality of electronic switches, each electronic switch corresponds to a pull-down current source, and is used for receiving a calibration feedback control signal to control the turn-on or turn-off of each calibration pull-down branch; The plurality of calibration pull-down branches are connected in parallel through the switch selection circuit, the switch selection circuit comprises a plurality of electronic switches, each electronic switch corresponds to a pull-down current source, and is used for receiving a calibration feedback control signal to control the turn-on or turn-off of each calibration pull-down branch; The charge pump circuit is connected with a low pass filter, and the current of the pull-up branch and the pull-down branch is gathered at an output node of the charge pump circuit.

9. The phase-detect-based charge-pump phase-locked loop device of claim 7, wherein, The feedback frequency division circuit comprises a multi-mode frequency divider and an integral comparison modulator. The multi-mode frequency divider is connected with a voltage controlled oscillator at a first end and connected with the lock detection circuit, the frequency discriminator and phase detector and the integral comparison modulator at a second end, respectively, for receiving a voltage controlled high frequency signal output by the voltage controlled oscillator and performing frequency division processing to provide feedback frequency division signals for the frequency discriminator and phase detector and the lock detection circuit. The integral comparison modulator is connected with the input and output ends of the multi-mode frequency divider, respectively, for outputting a modulated control signal based on the frequency division signal output by the multi-mode frequency divider to adjust the frequency division precision of the multi-mode frequency divider.

10. The phase-detect-based charge-pump phase-locked loop device of claim 7, wherein, The low pass filter comprises a resistor, a first capacitor and a second capacitor. The resistor is connected with the current steering dual-path switch charge pump and the voltage controlled oscillator at a first end, respectively, and connected with the first end of the first capacitor at a second end. The second end of the first capacitor is grounded. The first end of the second capacitor is connected with the current steering dual-path switch charge pump and the voltage controlled oscillator, respectively, and the second end is grounded.

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