Two-wire serial shift communication protocol implementation method and device

Abstract

The invention relates to a two-wire serial shift communication protocol implementation method, which comprises the following steps of: starting serial communication according to the level change of a data line or a clock line, and transmitting data bits according to the level change of the data line in the serial communication; and after the last data bit is sent out, the clock line and the data line are finally changed into high levels, and serial communication is ended. New serial data can be sent at any moment, any number of serial data can be sent, after logic operation is carried out on the clock line and the data line, a latch signal can be conveniently generated, and meanwhile original two-line SPI serial data are compatible.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of computer communication technology, in particular to a new two-wire serial shift communication protocol implementation method and device. BACKGROUND

[0002] The current serial shift protocol is SPI (serial peripheral interface), which is connected with independent serial shift chip or built-in serial shift module to complete the conversion from serial to parallel signal. The SPI bus is usually composed of a chip select signal (CS), a clock signal (CLK), an output signal (MOSI) and an input signal (MISO), wherein the simplest connection mode is one clock signal and one output signal to complete one-way communication.

[0003] In the two-wire working mode, in order to correctly complete the correct decoding from serial to parallel, two conditions need to be met: the interval between two serial communications (the first clock edge of this communication and the last clock edge of the last communication) must be much larger than the maximum clock period in serial communication, so as to distinguish two different serial communications; the effective data clock period of each serial communication is fixed. So as to determine the position of each serial bit. SUMMARY

[0004] Therefore, the present application provides a two-wire serial shift communication protocol implementation method to solve the problems in the background art.

[0005] The present application provides a two-wire serial shift communication protocol implementation method, characterized in that it comprises: According to the level change of the data line and / or the clock line, the serial communication is started; According to the level change of the data line in the serial communication, the data bit is transmitted; After sending the last data bit, the clock line remains high, the data line becomes high, and the serial communication ends.

[0006] Optionally, the serial communication is started according to the level change of the data line and / or the clock line, comprising: When the data line changes from high to low as the serial communication start flag, and then the clock line also changes to low, it is judged that the transmission starts when the clock line is high; In the case of having an end flag, the clock line can be judged to start transmission when it changes from high to low, and the data line remains high. The device directly judges the data start flag when the clock line changes from high to low.

[0007] Optionally, the serial communication ends, comprising: The serial communication end must include an end flag or a start flag. The serial communication end does not immediately generate an end flag.

[0008] Optionally, the two-wire serial shift communication protocol implementation method is characterized in that: After the serial communication starts, the data line level remains unchanged when the clock line is high. The data line level can change when the clock line is low.

[0009] Optionally, the two-wire serial shift communication protocol implementation method is characterized in that: After the serial communication starts, any number of serial data conforming to the clock and data timing relationship can be transmitted. After all data transmission is completed, the clock line and the data line remain high.

[0010] Optionally, the serial communication end must include an end flag or a start flag, including: After transmitting the last data bit, the last data is low, the clock line remains high, and then the data line must become high. The above actions serve as the end flag of the serial communication, indicating the end of the serial communication and waiting for the start of the next communication. After transmitting the last data bit, the last data is high. In order to generate the end flag, the clock line remains high, the data line first changes from high to low to form a start flag, and then changes from low to high to form an end flag, indicating the end of the serial communication and waiting for the start of the next communication. After transmitting the last data bit, the last data is high, the clock line remains high, and the data line also remains high. At this time, the serial communication ends, but does not generate an end flag. Next, the clock line remains high, and the data line becomes low to generate a new start flag, indicating the end of the previous serial communication and the start of a new serial communication.

[0011] Optionally, the two-wire serial shift communication protocol implementation method further includes: The two-wire serial shift communication protocol implementation method serves as a simplex communication protocol and can be compatible with two-wire SPI serial data which are also simplex communication protocols.

[0012] The application also provides a two-wire serial shift communication protocol device, characterized in that the device includes a shift latch chip and a register.

[0013] Optionally, the two-wire serial shift communication protocol device is characterized in that the shift latch chip is a timing logic circuit mainly used for storing and transmitting data.

[0014] The application also provides an electronic device, characterized in that comprising: A single-chip microcomputer device comprising a central processing unit, a random access memory, a read-only memory and an input / output port, wherein the single-chip microcomputer is configured to implement the method of any one of claims 1 to 7 when executing the executable instructions.

[0015] The application has the beneficial effect that new serial data transmission can be started at any time, any number of serial data is transmitted, a latch signal is conveniently generated after logical operation on the clock line and the data line, and the original two-wire SPI serial data is compatible. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed in the embodiment or prior art description are briefly introduced as follows. Obviously, the drawings in the following description are only embodiments of the present application, and those skilled in the art can obtain other drawings according to the provided drawings without creative labor.

[0017] Figure 1 A flow chart of a two-wire serial shift communication protocol implementation method disclosed by the present application is shown; Figure 2 A SPI bus serial communication timing diagram disclosed by the present application is shown; Figure 3 A SPI bus serial communication simplest connection timing diagram disclosed by the present application is shown; Figure 4 A two-wire serial shift communication protocol timing diagram disclosed by the present application is shown; Figure 5 A two-wire SPI schematic diagram disclosed by the present application is shown; Figure 6 A two-wire serial shift communication protocol schematic diagram disclosed by the present application is shown.

[0018] Figure 7 A byte transmission timing diagram disclosed by the present application is shown. DETAILED DESCRIPTION

[0019] Various exemplary embodiments, features and aspects of the present application will be described in detail below with reference to the accompanying drawings. The same reference signs in the drawings represent functionally identical or similar elements. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0020] The terms "first", "second", etc., are used only for descriptive purposes and do not connote or imply relative importance or a quantity of the specified technical features. Thus, features defined with "first", "second", etc., can include one or more of the features explicitly or implicitly.

[0021] The term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations.

[0022] In addition, for the purpose of convenience and brevity, detailed descriptions of well-known functions and constructions are omitted when their detailed descriptions are deemed unnecessary for those of ordinary skill in the art with the interest in the present application.

[0023] The current serial shift protocol is SPI (Serial Peripheral Interface), and the SPI bus is a high-speed, full-duplex synchronous communication bus, mainly used for communication between CPU and various peripheral devices. Data is transmitted in a serial manner, with the characteristics of simple and easy use. SPI bus can complete communication with only four lines: serial clock line (SCK), host input / slave output data line (MISO), host output / slave input data line (MOSI) and low-level effective slave selection line (CS) Chip Select (CS) is a signal used to select a specific chip in digital circuit design, usually a low-level signal. In digital circuits, open input pins usually appear as high-level, so the chip select signal is mostly low-level. The chip select signal is generated by a logic circuit to divide the address space and ensure independent transmission of data and addresses. MOSI (Master Out Slave In) is an important signal line in SPI communication, mainly used for the master device to send data to the slave device. MOSI is a data transmission line from the master device to the slave device, and the master device sends data to the slave device through the MOSI line. On the contrary, MISO (Master-Input Slave-Output) is used for the slave device to send data to the master device, or the master device to receive data from the slave device. Shift latch chip is an electronic component, mainly used for serial input and parallel output of data. Among them, 74HC595 is one of the most common shift latch chips, and 74HC595 is an 8-bit shift register / latch, using CMOS silicon gate technology, with high-speed transmission characteristics.

[0024] Specifically, the SPI bus basically needs 4 lines (serial data lines MOSI and MISO, serial clock line SCK and slave selection CS) as shown in Figure 2 , and needs 2 lines (serial data line MOSI and serial clock line SCK) as shown in Figure 3 in the simplest connection mode.

[0025] As shown in Figure 2 , the SPI bus serial communication timing diagram includes the following: clock signal line SPI_CLK0, clock signal line SPI_CLK1, chip selection signal line SPI_CSn, output signal line SPI_MOSI and input signal line SPI_MISO. Among them, the output signal line SPI_MOSI is used to send data to other devices, the input signal line SPI_MISO is used to receive data sent to the host device, the clock signal line SPI_CLK0 is used to output the clock signal to the register, the clock signal line SPI_CLK1 is used to output the clock signal to the clock generator, and the chip selection signal line SPI_CSn is low active, controlled by the host to send the slave enable signal.

[0026] As shown in Figure 3 , the SPI bus serial communication simplest connection timing diagram includes the following: the simplest connection mode of the SPI bus only includes the clock signal line SPI_CLK0, the clock signal line SPI_CLK1 and the output signal line SPI_MOSI. Among them, the clock signal line SPI_CLK0 is used to output the clock signal to the register, the clock signal line SPI_CLK1 is used to output the clock signal to the clock generator, and the output signal line SPI_MOSI is used to send data to other devices. In this connection mode, the SPI bus can only complete one-way communication.

[0027] As shown in Figure 4 , the improved two-wire protocol of the application has two starting judgment schemes, the difference between the two is whether to generate a starting flag. Scheme one, if there is an end flag, it can be judged as the start of sending by SER_CLK becoming low, such as when the first SER_CLK becomes low, SER_DATx remains high, and the slave directly judges it as the start of data. Scheme two, the start of sending is judged by the start flag, when the second SER_CLK is at high level, SER_DATx changes from high level to low level, which is a start flag, and then SER_CLK becomes low, which is judged as the start of sending. When the sending is finished, the clock needs to be kept at high level and the data line needs to be changed to high level.

[0028] Wherein, SER DAT0 indicates the last data is low, then becomes high level, naturally will produce an end mark. SER DAT1 indicates the last data is high, in order to produce end mark, first from high to low (start mark), then from low to high (end mark). It can also keep high level, through the start mark of scheme two to judge the sending start.

[0029] As shown in Figure 1 The flow chart of the two-wire serial shift communication protocol implementation method includes the following contents: S100, according to the level change of the data line and / or the clock line, realizing the start of serial communication.

[0030] Specifically, when there is no data, the clock line SER CLK and the data line SER DAT keep high level. When the serial communication starts, if the clock line keeps high level, the data line will change from high level to low level, and then the clock line also changes to low level, which is used as the start mark of serial communication, indicating the start of new serial communication; if the data line keeps high level, the clock line will change from high level to low level, which is used as the start mark of serial communication, indicating the start of new serial communication.

[0031] S200, according to the level change of the data line in serial communication, transmitting data bits.

[0032] Specifically, the serial communication transmits one byte after another byte in order on the data line, and the data of each byte is transmitted one bit after another bit in order for 8 times.

[0033] Specifically, as shown in Figure 7 During the high level of the serial clock SER CLK line, the high level or low level state of the SER DAT line must be kept stable, at this time the stable high level or low level on the SER DAT line is the effective data 1 or 0. The data change of SER DAT, that is, the level state change, can only be carried out during the low level of the SER CLK line. The serial clock SER CLK generates a high level pulse, and the serial data SER DAT line transmits one bit of effective data. The SER DAT line changes data (changes level) during the low level of the SER CLK line, and after the change is completed, the SER CLK line changes from low level to high level and keeps stable, at this time the stable level of the SER DAT line is the effective data.

[0034] As shown in Figure 7As shown, the byte transmission timing diagram includes that, during the low level of the clock line SER CLK, the host puts the data to be sent on the data line SER DAT, and then releases the SER CLK, giving a rising edge signal to the slave. After receiving the rising edge signal, the slave reads the level signal on SER DAT during the high level of SER CLK, and during the high level of SER CLK, the SER DAT is not allowed to change data.

[0035] S300, after the last data bit is sent, the clock line and the data line are finally both high, and the serial communication ends.

[0036] Specifically, after the last data bit is output, the level of the clock line is fixed as high, and the data line needs to be low (if the last data bit is low, it remains low), and then the data line is high again as the end of data identifier, indicating that the serial communication ends.

[0037] The beneficial effects of the above are that the serial data transmission starts at any moment, and any number of serial data is transmitted.

[0038] Specifically, when the data line changes from high to low while the clock line is high, and the clock line also changes to low, as the start of serial communication identifier, it indicates that the new serial communication starts.

[0039] As shown in Figure 4 When SER CLK is high, SER DAT0 and SER DAT1 change from high to low, and then SER CLK also changes to low, which is the start of serial communication identifier, indicating that the serial communication starts.

[0040] Specifically, when the clock line changes from high to low while the data line is high, as the start of serial communication identifier, it indicates that the new serial communication starts.

[0041] As shown in Figure 4 When SER DAT0 and SER_DAT1 are high, SER CLK changes from high to low, which is the start of serial communication identifier, indicating that the serial communication starts.

[0042] Specifically, after the serial communication starts, when the clock line is high, the data line level remains unchanged; when the clock line is low, the data line level can change.

[0043] As shown in Figure 7As shown, during the low level of SER CLK, the host puts data bits on SER DAT one by one, and then releases SER CLK, and the slave reads data during the high level of SER CLK. Therefore, no data change is allowed on SER DAT during the high level of SER CLK, and the above process is repeated 8 times to send one byte.

[0044] Specifically, after the start of serial communication, any number of serial data conforming to the clock and data timing relationship can be transmitted; when there is no data, the clock line and the data line remain high.

[0045] After the start flag of serial communication, any number of serial data conforming to the timing relationship can be transmitted on SER CLK and SER DAT, wherein the serial data conforming to the timing relationship refers to the transmission of data bits one by one in time sequence to ensure correct reception and analysis of data; when there is no data, SER CLK and SER DAT both remain in a high level state to change the level at any time to make a start flag to start data transmission.

[0046] After transmitting the last data bit, the clock line remains high, and the data line first becomes low and then high, which is the end flag of serial communication, indicating the end of serial communication.

[0047] As shown in Figure 4 SER CLK remains in a high level state, SER DAT0 and SER DAT1 become low (if the last data bit is low, it remains low) and then high, which is the end flag of serial communication, indicating the end of serial communication.

[0048] The two-wire serial shift communication protocol implementation method is a kind of simplex communication protocol, and can be compatible with two-wire SPI serial data which is also a simplex communication protocol.

[0049] The main difference between simplex communication and duplex communication lies in the directionality of data transmission and device configuration. Simplex communication means that data can only be transmitted in one direction, that is, the sending end and the receiving end are fixed, the sending end can only send information and cannot receive information; the receiving end can only receive information and cannot send information. This communication mode is suitable for media transmission modes such as radio and television, because their data transmission direction is fixed. The advantages of simplex communication are simple device, power saving, and only one frequency point is occupied; the disadvantage is that it can only transmit in one direction, and the flexibility is poor. Duplex communication allows data to be transmitted in two directions at the same time or alternately, and is divided into half-duplex and full-duplex. In half-duplex communication, the devices of the two communication parties are both transmitters and receivers, but they cannot transmit and receive data at the same time, and must coordinate through some mechanism.

[0050] Among them, Full Duplex and Half Duplex are two modes in communication transmission, which have significant differences in the direction and synchronicity of data transmission. Full Duplex allows data transmission in both directions at the same time, which is equivalent to the combination of two simplex communication methods. Full duplex communication can simultaneously transmit signals in both directions (A→B and B→A), and is instantaneous synchronous. Half duplex is a signal transmission in one direction within a time period, which can only send or receive data within a time period, and cannot be done simultaneously.

[0051] In addition, Simplex Communication is a working method in which messages can only be transmitted in one direction. In simplex communication, the communication channel is unidirectional, and the sending end and the receiving end are fixed. The sending end can only send information and cannot receive information; the receiving end can only receive information and cannot send information. Data signals are transmitted from one end to the other end, and the signal flow is unidirectional.

[0052] Specifically, as shown in the two-wire SPI schematic diagram of Figure 5 , in the original two-wire SPI shift LED, SLED will change during the shift process. If the serial clock is slow, SLED will flicker.

[0053] As shown in Figure 5 , the two-wire SPI schematic diagram includes the following: serial data LED_R_SDA is connected to the A and B ends of the shift 74AHC64 chip for data input, serial clock SCLK1 and SCLK2 are connected to the CLK input clock signal of chips U2 and U3, respectively, the reset signal is input to U2 and U3 CLR#, Vcc is the power supply voltage, GND is the ground, and Qa to Qh are data outputs.

[0054] Specifically, as shown in the two-wire serial shift communication protocol schematic diagram Figure 6 , by analyzing the two-wire SPI, the hardware scheme of the present application is used to latch the output of the parallel signal after the shift.

[0055] As shown in Figure 6 , the two-wire serial shift communication protocol schematic diagram includes the following: the original shift 74AHC64 chip is replaced with a shift latch chip 74AHC595, the serial data SER_DAT is connected to SER, the serial clock SER_CLK is connected to SCLK, Qa to Qh are data outputs, and a register is added. The register is reset by SER_CLK and uses SER_DAT as the clock. When SER_CLK is low, Q output is low, and when SER_CLK is high and SER_DAT is high, Q output is high. The signal is connected to the latch signal input RCLK.

[0056] Among them, the main pin SER of the shift latch chip 74AHC595 is a serial data input, which is used to receive data bit by bit; SCK is a shift register clock input, which is used to read a bit of data at each SCK rising edge; RCK is a storage register clock input, which converts data from serial to parallel output at each RCK rising edge; Qa to Qh are parallel data outputs, and 8 pins output data in parallel.

[0057] The specific implementation process of the present application is as follows: 1. When there is no data, the clock line (SER CLK) and the data line (SER DAT) remain high.

[0058] 2. When the serial communication starts, the clock line remains high, the data line changes from high to low, and then the clock line also changes to low. Or the data line remains high, and the clock line changes to low.

[0059] 3. The changing clock and data are sent. When the clock line is low, the data line can change, and when the clock line is high, the data line must remain unchanged.

[0060] 4. After sending the last data bit, the clock line remains high.

[0061] 5. Then the data line becomes low (if the last data bit is low, it remains low), and then the data line becomes high again.

[0062] The specific implementation of the present application is as follows: The original two-wire SPI can be used, or the two-wire protocol of the present application can be used.

[0063] However, the original two-wire SPI shift LED has a problem that SLED will also change during the shift process, and if the serial clock is relatively slow, SLED will be seen to flicker. In the new hardware scheme, the two-wire protocol of the present application is used by retaining the original two-wire connection, and the parallel signal after shifting is latched and output after the data ends by analyzing the protocol.

[0064] The original shift 74AHC64 chip is replaced with a shift latch chip 74AHC595. The serial data SER DAT (data line) is connected to SER, and the serial clock SER CLK (clock line) is connected to SCLK. Then a register is added, which is reset by SER CLK and uses SER DAT as the clock. When SER CLK is low, Q output is low, and when SER CLK is high and SER DAT is high, Q output is high. The signal is connected to the latch signal input RCLK.

[0065] The beneficial effect of the present application is that it can start a new serial data transmission at any time, transmit any number of serial data, and after logical operation on the clock line and data line, it can easily generate a latch signal, and it is compatible with the original two-wire SPI serial data.

[0066] Embodiments of the application have been described above, along with the explanations of the preferred embodiments. The description is illustrative of the embodiments and not restrictive of them. Many modifications and variations of the described embodiments are possible in light of this disclosure without departing from the scope and spirit of the described embodiments. The use of the terms "including", "comprising", or "having" and variations thereof in this disclosure is intended to be broad and encompass the selection of one or more elements from any of the examples given, as well as examples not specifically given. The use of the terms "a", "an" or "the" is intended to be broad and encompass one or more of the items. The use of the term "based on" is intended to be broad and encompass both an unadulterated based on and an adulterated based on. The use of the term "based on" is intended to be broad and encompass both an unadulterated based on and an adulterated based on. The use of the term "based on" is intended to be broad and encompass both an unadulterated based on and an adulterated based on. The use of the term "based on" is intended to be broad and encompass both an unadulterated based on and an adulterated based on. The use of the term "based on" is intended to be broad and encompass both an unadulterated based on and an adulterated based on. The use of the term "based on" is intended to be broad and encompass both an unadulterated based on and an adul

Claims

1. A method of implementing a two-wire serial shift communication protocol, characterized by, The method comprises the following steps: According to the level change of the data line and / or the clock line, the serial communication is started; According to the level change of the data line in the serial communication, the data bit is transmitted; After the last data bit is transmitted, the clock line is kept high, the data line is changed to high, and the serial communication is ended.

2. The method of claim 1, wherein, The method of starting the serial communication according to the level change of the data line and / or the clock line comprises the following steps: When the data line is changed from high to low while the clock line is high, the change is taken as the start mark of the serial communication, and then the clock line is changed to low. In the case of the end mark, the clock line is changed to low to determine the start of the transmission, the data line is kept high when the clock line is changed from high to low, and the start mark of the data is directly determined from the device to determine the start of the transmission.

3. The method of claim 1, wherein the two-wire serial shift communication protocol implementation method is characterized by, The serial communication is ended, which comprises the following steps: The serial communication must include an end mark or a start mark; The serial communication is not ended immediately.

4. The method of claim 1, wherein: After the serial communication is started, the level of the data line is kept unchanged when the clock line is high; When the clock line is low, the level of the data line can be changed.

5. The method of claim 1, wherein: After the serial communication is started, any number of serial data meeting the clock and data timing relationship can be transmitted; After all the data transmission is completed, the clock line and the data line are kept high.

6. The method of claim 3, wherein the two-wire serial shift communication protocol implementation method further comprises: The serial communication must include an end mark or a start mark, which comprises the following steps: After the last data bit is transmitted, the last data is low, the clock line is kept high, and then the data line must be changed to high, which is taken as the end mark of the serial communication, indicating that the serial communication is ended and waiting for the start of the next communication; After the last data bit is transmitted, the last data is high, the clock line is kept high, and the data line is changed from high to low to form the start mark, and then changed from low to high to form the end mark, indicating that the serial communication is ended and waiting for the start of the next communication; After the last data bit is transmitted, the last data is high, the clock line is kept high, and the data line is kept high, indicating that the serial communication is ended but no end mark is generated.

7. The method of implementing a two-line serial shift communication protocol of claim 1, wherein, The method further comprises the following steps: The two-wire serial shift communication protocol implementation method is a simplex communication protocol, which can be compatible with the two-wire SPI serial data which is also a simplex communication protocol.

8. An apparatus for a two-wire serial shift communication protocol, characterized in that, The device comprises a shift latch chip and a register.

9. The apparatus of the two-wire serial shift communication protocol according to claim 8, wherein, The shift latch chip is a timing logic circuit, which is mainly used for storing and transmitting data.

10. An electronic device, comprising: The method comprises the following steps: A single-chip microcomputer device comprises a central processing unit, a random access memory, a read-only memory and an input / output port, wherein the single-chip microcomputer is configured to implement the method of any one of claims 1 to 7 when the executable instructions are executed.

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