Computing node and data transmission method

Abstract

The invention provides a computing node and a data transmission method, and relates to the technical field of computers, in particular to the technical field of digital circuits. The specific implementation scheme of the computing node is as follows: the computing node comprises a network-on-chip module; the inter-chip processing module is configured to be a message sequence from another computing node and store data messages in the message sequence to the on-chip storage module through the on-chip network module; and sending the identification message in the message sequence to the on-chip storage module through the on-chip network module under the condition that the target data in the data message is determined to be written according to a first response signal returned by the on-chip storage module through the on-chip network module. And the processor is configured to send a query signal to the on-chip storage module through the on-chip network module, and read target data from the on-chip storage module through the on-chip network module under the condition of determining that the synchronous identifier in the identifier message is written according to a second response signal returned by the on-chip storage module through the on-chip network module.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of computer, in particular to the technical field of digital circuit, and more particularly to a computing node and a data transmission method. BACKGROUND

[0002] With the development of artificial intelligence technology, in the training scene of large language models, multiple computing nodes are usually distributedly deployed, and the core communication operation (All-reduce) for data aggregation and result synchronization of multiple computing nodes in distributed computing is widely used in gradient synchronization in distributed deep learning training.

[0003] Therefore, there is an urgent need for a method capable of reducing communication latency and improving data synchronization efficiency between computing nodes to meet the gradient synchronization requirements in the distributed deep learning training scene. SUMMARY

[0004] The present disclosure provides a computing node and a data transmission method.

[0005] In one aspect of the present disclosure, a computing node is provided, comprising: an on-chip network module; an inter-chip processing module configured to store data packets in a packet sequence from another computing node to an on-chip storage module via the on-chip network module; and in the case where it is determined that target data in the data packets has been written according to a first response signal returned by the on-chip storage module via the on-chip network module, send an identification packet in the packet sequence to the on-chip storage module via the on-chip network module; wherein the arrangement order of the data packets in the packet sequence is before the identification packet. A processor configured to send a query signal to the on-chip storage module via the on-chip network module, and in the case where it is determined that a synchronization identifier in the identification packet has been written according to a second response signal returned by the on-chip storage module via the on-chip network module, read the target data from the on-chip storage module via the on-chip network module.

[0006] Another aspect of the present disclosure provides a data transmission method, comprising: in response to receiving a packet sequence from another computing node, storing data packets in the packet sequence to an on-chip storage module via an on-chip network module; in response to determining that target data in the data packets has been written, sending an identification packet in the packet sequence to the on-chip storage module via the on-chip network module; and in the case where it is determined that a synchronization identifier in the identification packet has been written, reading the target data from the on-chip storage module via the on-chip network module; wherein the arrangement order of the data packets in the packet sequence is before the identification packet.

[0007] It should be understood that nothing in this section is intended to limit the scope of the embodiments of the present disclosure. Other aspects of the present disclosure will become apparent to those skilled in the art upon reading the following specification and / or upon inspection of the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0008] The accompanying drawings are included to provide a better understanding of the present scheme, and not to limit the present disclosure. Among them:

[0009] Figure 1 An exemplary architecture in which computing nodes according to embodiments of the present disclosure are deployed is schematically shown;

[0010] Figure 2 An exemplary architecture in which computing nodes according to embodiments of the present disclosure are deployed is schematically shown; Figure 1 A circuit architecture diagram of an inter-chip processing module in any of the computing nodes shown;

[0011] Figure 3 An exemplary architecture in which computing nodes according to embodiments of the present disclosure are deployed is schematically shown; Figure 2 A circuit architecture diagram of a pre-processing module in any of the computing nodes shown;

[0012] Figure 4 An exemplary architecture in which computing nodes according to embodiments of the present disclosure are deployed is schematically shown; Figure 2 A circuit architecture diagram of a first processing sub-module in the inter-chip processing module shown;

[0013] Figure 5 An exemplary architecture in which computing nodes according to embodiments of the present disclosure are deployed is schematically shown; Figure 2 A circuit architecture diagram of a first processing sub-module in the inter-chip processing module shown;

[0014] Figure 6 An exemplary architecture in which computing nodes according to embodiments of the present disclosure are deployed is schematically shown; Figure 4 OrA circuit architecture diagram of an identification determining unit in any of Figure 5

[0015] An exemplary architecture in which computing nodes according to embodiments of the present disclosure are deployed is schematically shown; Figure 7 A circuit architecture diagram of a second processing sub-module in the inter-chip processing module shown; Figure 2

[0016] An exemplary architecture in which computing nodes according to embodiments of the present disclosure are deployed is schematically shown; Figure 8 A circuit architecture diagram of a second processing sub-module in the inter-chip processing module shown; Figure 2

[0017] An exemplary architecture in which computing nodes according to embodiments of the present disclosure are deployed is schematically shown; Figure 9 A circuit architecture diagram of a second processing sub-module in the inter-chip processing module shown; Figure 2

[0018] Figure 10Fig. 1 schematically shows a circuit architecture diagram of an inter-slice processing module in any computing node according to another embodiment of the present disclosure;

[0019] Figure 11 Fig. 2 schematically shows a circuit architecture diagram of an inter-slice processing module according to an embodiment of the present disclosure; Figure 10 Fig. 3 schematically shows a circuit architecture diagram of a third processing sub-module in the inter-slice processing module shown in Fig. 2;

[0020] Figure 12 Fig. 4 schematically shows a circuit architecture diagram of a fourth processing sub-module in the inter-slice processing module shown in Fig. 2; Figure 10 Fig. 5 schematically shows a circuit architecture diagram of a fourth processing sub-module in the inter-slice processing module shown in Fig. 2;

[0021] Figure 13 Fig. 6 schematically shows a flow chart of a data transmission method according to an embodiment of the present disclosure;

[0022] Figure 14 Fig. 7 schematically shows a logic block diagram of a data transmission method according to an embodiment of the present disclosure;

[0023] Figure 15 Fig. 8 schematically shows a logic block diagram of a data transmission method according to an embodiment of the present disclosure; and

[0024] Figure 16 Fig. 9 schematically shows an exemplary architecture diagram to which the data transmission method according to an embodiment of the present disclosure is applied. DETAILED DESCRIPTION

[0025] Exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings, which include various details of the embodiments of the present disclosure to assist in understanding, and should be considered as merely exemplary. Thus, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and structures are omitted in the following description for clarity and conciseness.

[0026] In the training scenario of distributed deep learning, the time and computing resources consumed by cross-processor parameter synchronization gradually become a system performance bottleneck. In order to improve the storage consistency between multiple computing nodes, related examples generally insert a synchronization point with get-release semantics at the data sending end after the core computing unit completes the complete writing of business data by calling a kernel-level memory barrier instruction (MemoryBarrier). This mechanism guarantees data consistency through double constraints: one is to prevent the processor instruction pipeline from rearranging the data write operation before the barrier to after the barrier; the other is to rely on the strong memory order feature to perform atomic writing of the completion flag, ensuring that the visibility timing of the identification bit update strictly lags behind the actual business data persistence operation.

[0027] However, due to the complexity of the atomic order-preserving logic of the hierarchical synchronization mechanism, in large-scale distributed computing scenarios, frequent software intervention can cause significant synchronization delay and computing resource occupation, thereby reducing the efficiency of accelerated computing. At the same time, with the continuous development of large language models, the number of model parameters participating in computing is growing explosively, and the scale of data processors under the same network segment in the computing power expansion network is expanding, the complex synchronization mechanism also increases the burden of the processors, reducing the data sharing and synchronization efficiency between different computing nodes in the distributed system.

[0028] Therefore, the embodiments of the present disclosure provide a computing node, which includes an on-chip network module, an inter-chip processing module, configured to receive a packet sequence from another computing node, store data packets in the packet sequence to an on-chip storage module via the on-chip network module, and send an identification packet in the packet sequence to the on-chip storage module via the on-chip network module in a case where it is determined that target data in the data packets has been written according to a first response signal returned by the on-chip storage module via the on-chip network module; a processor, configured to send a query signal to the on-chip storage module via the on-chip network module, and read the target data from the on-chip storage module via the on-chip network module in a case where it is determined that a synchronization identifier in the identification packet has been written according to a second response signal returned by the on-chip storage module via the on-chip network module.

[0029] Figure 1 An exemplary architecture in which the computing node according to the embodiments of the present disclosure is deployed is schematically shown.

[0030] As shown in Figure 1 The exemplary architecture can include a first computing node 100 and a second computing node 200, and the first computing node 100 and the second computing node 200 communicate based on an interconnection mechanism. The interconnection mechanism can be based on Ethernet and switches, or based on PCIE (Peripheral Component Interconnect Express) interconnection protocols and switches.

[0031] The circuit structures of the first computing node 100 and the second computing node 200 are the same, and each includes a processor, an on-chip network module, an on-chip storage module, and an inter-chip processing module. The on-chip network module is communicatively connected with the processor, the on-chip storage module, and the inter-chip processing module.

[0032] In the exemplary architecture 100, the first computing node 100 can act as a data sending end to send synchronization data to the second computing node 200. Similarly, the second computing node 200 can also act as a data sending end to send synchronization data to the first computing node 100.

[0033] In some embodiments, the first computing node 100 is taken as a data sending end, and the target data output by the processor in the first computing node can be transmitted to the inter-chip processing module via the on-chip network module in the first computing node, and then the target data is sent to the second computing node by the inter-chip processing module based on the interconnection mechanism.

[0034] The inter-chip processing module 210 in the second computing node 200 can be configured with a data input interface matched with the corresponding interconnection mechanism, for receiving the message sequence from the first computing node 100. The message sequence can include data messages and identification messages. The target data is included in the data messages. The synchronization identification can be included in the identification messages. The synchronization identification can be understood as being used to identify the validity of the target data. Therefore, the arrangement order of the data messages in the message sequence is before the identification messages. It can be understood that the first computing node 100 sends the identification messages to the second computing node 200 only after sending a predetermined number of data messages to the second computing node 200.

[0035] After the inter-chip processing module 210 in the second computing node 200 receives the message sequence via the data input interface, the data messages in the message sequence can be stored to the on-chip storage module 240 via the on-chip network module 230 in the second computing node 200 according to the order of receiving. For the identification messages, the inter-chip processing module 210 temporarily intercepts. For example, the identification messages can be stored on the inter-chip processing module 210.

[0036] The on-chip network module 230 can be a communication subsystem inside an integrated circuit (chip), including a router responsible for data forwarding and routing decision, a network interface responsible for data packaging, unpackaging and protocol conversion, and a physical link for realizing communication connection with the processor 220, the on-chip storage module 240 and the inter-chip processing module 210.

[0037] The on-chip storage module 240 can be configured with a storage with large capacity and a logic circuit. The storage includes but is not limited to a GDDR (Graphics Double Data Rate) storage or an HBM (High Bandwidth Memory) storage, for realizing persistent shared storage data. When the data messages are written into the storage, the logic circuit will correspondingly generate a first response signal for representing the writing completion of the data messages, and send the first response signal to the inter-chip processing module 210 via the on-chip network module 230.

[0038] When the inter-chip processing module 210 determines that the target data in the data packet has been written completely based on the first response signal returned by the on-chip storage module via the on-chip network module, it sends the identification message in the message sequence to the on-chip storage module 240 via the on-chip network module 230 so that the identification message is written to the on-chip storage module 240.

[0039] Processor 220 is configured to send a query signal to on-chip storage module 240 via on-chip network module 230. Upon receiving the query signal, on-chip storage module 240 queries whether the synchronization flag in the identification message has been written successfully. If the synchronization flag in the identification message has been written successfully, on-chip storage module 240 sends a second response signal to processor 220.

[0040] At this time, when the processor 220 determines that the synchronization flag in the identification message has been written completely based on the second response signal returned by the on-chip storage module 240 via the on-chip network module 230, it reads the target data from the on-chip storage module 240 via the on-chip network module 230.

[0041] In this embodiment, the computing node utilizes the inter-chip processing module to store the identification message via the on-chip network module to the on-chip storage module only after confirming that all data messages preceding the identification message in the message sequence have been written, thus forming a closed-loop transmission verification mechanism. The processor only reads the target data when it receives a response signal indicating that the identification message has been written. This avoids the mismatch between the data sent by the sending computing node and the data observed by the receiving computing node, improving the validity of the data read by the processor configured in the receiving computing node without complex software intervention. While meeting the data synchronization requirements between computing nodes, it reduces communication latency and improves the efficiency of data sharing and synchronization between different computing nodes.

[0042] To achieve the functionality of the inter-chip processing module 210 described above, the following steps are combined with... Figures 2-12 .

[0043] Figure 2 This illustration schematically depicts an embodiment according to the present disclosure. Figure 1 The circuit architecture diagram of the inter-chip processing module in any of the computing nodes is shown.

[0044] like Figure 2 As shown, the inter-chip processing module 210 is configured with a first processing submodule 211 and a second processing submodule 212 that are connected to each other in communication.

[0045] The first processing submodule 211 is configured to determine the message type of any message according to the message address of the any message in the message sequence, and determine the first transaction identifier of the any message according to the data source identifier of the any message. In the case of determining that the message type is a data message, the data message is stored into the on-chip storage module via the on-chip network module according to the message address, and a first counting signal is sent to the second processing submodule.

[0046] In the embodiments of the present disclosure, the message address can be used to indicate the receiving end of any message and the storage address of the receiving end. For example, for any message from the first computing node 100, the message address can be used to indicate the second computing node 200 and the address for storing the any message in the on-chip storage module 240.

[0047] In the embodiments of the present disclosure, the message type can be used to indicate whether the message is a data message or an identification message.

[0048] Figure 2 The solid arrow shown indicates that the first processing submodule 211 sends the first counting signal to the second processing submodule while issuing the data message to the on-chip network module 230. The data message is stored into the data message via the on-chip network module 230.

[0049] The second processing submodule 212 is configured to control the first counter associated with the first transaction identifier to count in response to the first counting signal, to obtain a first counting value.

[0050] In the embodiments of the present disclosure, the second processing submodule 212 can be configured with multiple counters, each of which is configured with a transaction identifier corresponding to the data source identifier, so as to count only when the counting signal with the respective exclusive transaction identifier is received. The obtained first counting value can represent the number of data messages of a certain data source sent to the on-chip storage module 240 via the on-chip network module 230. The first counting value is used for the second processing submodule to reset based on the first counting value in the case of receiving the first response signal, to generate a first reset signal. The first reset signal can represent that the first counter restores the initial state, for example, the counting value is zero.

[0051] Figure 2 The dashed arrow shown indicates that the on-chip storage module 240 sends the first response signal to the on-chip network module 230 in the case of completing writing the data message, and the first response signal is sent to the second processing submodule 212 via the on-chip network module 230. The second processing submodule 212 can reset based on the first counting value, to generate a first reset signal. And the first reset signal is sent to the first processing submodule 211. The first processing submodule 211 stores the identification message into the on-chip storage module 240 via the on-chip network module 230 in response to the first reset signal.

[0052] In the distributed system, the number of deployed computing nodes is large, and the number of processors deployed on each computing node can also include multiple. The data source identifier can be used to indicate the sending end of any message, which can be understood as the data source of any message, for example: the data source identifier of the message from the 0th processor of the first computing node and the message from the 1st processor of the first computing node are different. The data source identifier of the message from the first computing node and the data source identifier of the message from the third computing node are also different.

[0053] Based on the data source identifier, the first transaction identifier is determined as the unique identifier in data transmission, which realizes the traceability of communication between nodes, and establishes an association reference for subsequent consistency verification and control of synchronized data between nodes.

[0054] Since the messages sent by other computing nodes can be transmitted based on different protocols, in addition to being configured with the first processing submodule 211 and the second processing submodule 212, the inter-chip processing module 210 can also be configured with a preprocessor module 213 in communication connection with the first processing submodule 211, for parsing messages of different protocols from different computing nodes.

[0055] Figure 3 The circuit architecture diagram of the preprocessor module in any computing node is schematically shown. Figure 2 The circuit architecture diagram of the preprocessor module in any computing node is schematically shown.

[0056] As shown in Figure 3 The preprocessor submodule 213 can be configured with a protocol converter, a data alignment FIFO (First In, First Out, first-in first-out) unit and a message parsing FIFO unit connected in sequence.

[0057] The protocol converter is matched with the interconnection mechanism used for communication between computing nodes in the distributed system, to perform protocol conversion on the messages from other computing nodes, and output valid signals, start signals, end signals and data signals. Then, the valid signals, the start signals, the end signals and the data signals are input into the data alignment FIFO unit, and the data alignment FIFO unit performs data alignment according to the first-in first-out rule, and outputs the alignment signals and the valid signals after data alignment. Next, the alignment signals and the valid signals after data alignment are input into the message parsing FIFO unit, and the message parsing FIFO unit parses the message address, the data source identifier and the data signal in the message according to the first-in first-out rule and based on the message format defined by the transmission protocol. And the message address, the data source identifier, the data signal and the valid signal are input into the first processing submodule 211 for processing.

[0058] The following will be described in combination with Figures 4-6The specific circuit architecture of the first processing submodule is described in detail.

[0059] Figure 4 The circuit architecture of the first processing submodule in the inter-chip processing module is shown. Figure 2

[0060] As shown in the figure, the first processing submodule 211 can include a register 410, a first comparison unit 420, an identification determining unit 430, and a first sending unit 440. Figure 4

[0061] The register 410 is configured to store a predetermined address range. The predetermined address range indicates an available storage area in the first memory for storing identification packets. The first memory can be configured on the inter-chip processing module 210, for example, can be an on-chip static random-access memory (SRAM).

[0062] The first comparison unit 420 can be a logic circuit composed of a digital logic comparator, configured to read the predetermined address range from the register, and compare the packet address with the predetermined address range to obtain a first comparison result. The first comparison result can be a logic circuit output, for example, when outputting a high level, it indicates that the packet address is within the predetermined address range, at this time, the first comparison result indicates that the packet type is an identification packet. When outputting a low level, it indicates that the packet address is not within the predetermined address range, at this time, the first comparison result indicates that the packet type is a data packet.

[0063] The identification determining unit 430 is configured to determine the first transaction identification according to the data source identification, obtain a data packet with the first transaction identification, and send a first count signal to the second processing submodule 212.

[0064] The first sending unit 440 is configured to store the data packet with the first transaction identification to the on-chip storage module 240 via the on-chip network module 230 in the case that the first comparison result indicates that the packet type is a data packet. The first sending unit can be a multiplexer (MUX), for example, when the first comparison unit 420 outputs a low level, the data signal in the data packet and the first transaction identification output by the identification determining unit are input. It can be understood that the data signal includes the target data in the data packet. The data packet with the first transaction identification is sent to the on-chip storage module 240 via the on-chip network module 230. When the first comparison unit 420 outputs a high level, the synchronization identification in the identification packet and the first transaction identification output by the identification determining unit are input, and the identification packet with the first transaction identification is stored to the first memory. ​​

[0065] As Figure 4 indicated, the comparison result P1 output by the first comparison unit 420 can indicate that the message to be transmitted is a data message. The comparison result P1 is input to the first sending unit 440, so that the first sending unit 440 selects the path pointing to the network-on-chip module 230 as the transmission path of the data message based on the comparison result P1. Meanwhile, the comparison result P1 is sent to the second processing submodule 212, so that the second processing submodule 212 counts based on the comparison result P1 and the first count signal.

[0066] The comparison result output by the first comparison unit by comparing the message address with the predetermined address range is used as the basis for selecting the transmission path of the first sending unit, and the judgment of the message type is directly implemented from the hardware level, further reducing the occupation of the calculation resources by the judgment process.

[0067] Figure 5 The circuit architecture of the first processing submodule in the inter-chip processing module is schematically shown. Figure 2 The circuit architecture of the first processing submodule in the inter-chip processing module is schematically shown.

[0068] As Figure 5 indicated, the first processing submodule 211 adds the first memory 450 on the basis of the circuit architecture shown in Figure 4

[0069] The first memory is configured to store the identification message.

[0070] The first sending unit is further configured to, in the case where the first comparison result indicates that the message type is the identification message, store the identification message with the first transaction identification to the first memory according to the target address; and in response to the first reset signal, read the identification message from the first memory and store the identification message to the on-chip storage module via the network-on-chip module.

[0071] As Figure 5 indicated, the comparison result P2 output by the first comparison unit 420 can indicate that the message to be transmitted is an identification message. The comparison result P2 is sent to the second processing submodule 212, so that the second processing submodule 212 allocates the target address for storing the identification message in the first memory 450 for the identification message based on the comparison result P2, and the target address is returned to the first sending unit 440. Meanwhile, the comparison result P2, the data signal in the identification message and the first transaction identification are input to the first sending unit 440, so that the first sending unit 440 selects the path pointing to the first memory 450 as the transmission path of the identification message based on the comparison result P2. And the identification message is stored to the first memory 450 according to the target address.

[0072] ​When the first sending unit 440 receives the first reset signal, the identification message is read from the first memory 450, and a path pointing to the network-on-chip module 230 is selected as a transmission path of the identification message, so as to store the identification message to the on-chip storage module 240 via the network-on-chip module 230.

[0073] In the data synchronization process, the computing node directly writes the received data message in sequence to the corresponding on-chip storage module, and only blocks the identification message. In comparison, the storage area required by the identification message is much smaller than that of the data message. Therefore, it is not necessary to configure a storage area on the inter-chip processing module for buffering the data message before the identification message in the message sequence which has not been written, further improving the efficiency of data transmission between the computing nodes, while reducing the area occupied by the storage area on the computing node.

[0074] Figure 6 The circuit architecture of the identification determination unit in the data synchronization module 400 is shown in FIG. 4B. Figure 4 Or Figure 5 The circuit architecture of the identification determination unit in the data synchronization module 400 is shown in FIG. 4B.

[0075] As shown in FIG. 4B, the identification determination unit 430 can include a second memory 431, a second comparison unit 432, a first allocation component 433, and a first selector 434. The second comparison unit 432 is connected with the second memory 431 and the first allocation component 433 respectively. Figure 6

[0076] The second memory 431 is configured to store first mapping information between a data source identifier and a transaction identifier. The second memory can be a random access memory (RAM) or a register, which can support fast query and further improve the query efficiency.

[0077] The second comparison unit 432 is configured to compare the first mapping information with the data source identifier, and output a second comparison result. The second comparison unit 432 can be a logic circuit realized by a digital logic comparator, which is used to judge whether the message from the same data source has been processed.

[0078] ​For example, when the second comparison unit 432 outputs a high level, it can be indicated that the data source identifier is included in the first mapping information, and it can be understood that the previous packet in the same packet sequence from the same data source as the packet has been processed. For subsequent packets, the first transaction identifier can be used, so that the second processing submodule records the number of data packets before the identification packet in the packet sequence. When the second comparison unit 432 outputs a low level, it can be indicated that the data source identifier is not included in the first mapping information. When the second comparison unit 432 outputs a low level, it can be indicated that the data identifier is not included in the first mapping information, and it can be understood that the previous packet in the same packet sequence from the same data source as the packet has not been processed.

[0079] The first allocation component 433 is configured to, in a case where the second comparison result indicates that the first mapping information does not include the data source identifier, allocate the first transaction identifier to the data packet based on the data source identifier, to obtain a first allocation result; and store a mapping relationship between the first transaction identifier and the data source identifier to the second memory. The function of the first allocation component 433 can be realized by a combination logic circuit.

[0080] The first selector 434 is configured to, in a case where the second comparison result indicates that the first mapping information includes the data source identifier or the first allocation result indicates that the first transaction identifier is allocated to the data packet, select the first transaction identifier as the transaction identifier of the data packet according to the data source identifier, to obtain the data packet with the first transaction identifier.

[0081] As shown in Figure 6 When the first allocation component 433 receives the comparison result R2 from the second comparison unit 432 indicating that the first mapping information does not include the data source identifier, the first transaction identifier can be allocated to the data packet based on the data source identifier. And the first transaction identifier is sent to the first selector 434.

[0082] At the same time, the mapping relationship between the first transaction identifier and the data source identifier is stored to the second memory to update the first mapping information stored in the second memory. So that the second comparison unit 432 can compare the data source identifier of the subsequent packet based on the updated first mapping information. Thus, the fast update between the data source identifier and the transaction identifier is realized. In the case where the previous data packet has been written, for example, in the case where the first reset signal is received, the mapping relationship associated with the first reset signal can also be deleted from the first mapping information, so as to be dynamically released.

[0083] When the second comparison unit 432 outputs the comparison result R1, it indicates that the first mapping information includes the data source identifier, and then the transaction identifier corresponding to the data source identifier is directly determined as the first transaction identifier. And the comparison result R1 is sent to the first selector 434.

[0084] At this time, the initial transaction identifier in the data packet or the identifier packet is empty, and after receiving the first transaction identifier, the first selector 434 can select the first transaction identifier as the transaction identifier of the data packet based on the data source identifier, to obtain the data packet with the first transaction identifier.

[0085] The maximum number of concurrent transmission transactions supported by the on-chip network module is used for multi-layer dynamic mapping of data packets and identifier packets of different data sources, and through dynamic allocation and release of corresponding transaction identifiers, the storage resource overhead required by the computing node at the receiving end to complete data consistency cooperation is greatly reduced, thereby expanding the interconnection scale between the computing nodes in the distributed system.

[0086] Figure 7 An on-chip network module is schematically shown according to an embodiment of the present disclosure. Figure 2 A circuit architecture diagram of a second processing submodule in the inter-chip processing module is shown.

[0087] As shown in Figure 7 The second processing submodule 212 can include a plurality of counters, such as counter A, counter B, counter N, and a first counter 710.

[0088] When the second processing submodule 212 receives the first count signal, the comparison result P1, and the comparison result R1, it indicates that the previous packet from the same data source as the current data packet has been processed, and therefore, the first counter 710 can be controlled to count based on the first count signal to obtain a first count value.

[0089] The second processing submodule further includes a second allocation component 720 configured to allocate the first transaction identifier to the first counter 710 based on the data source identifier in a case where the second comparison result indicates that the first mapping information does not include the data source identifier.

[0090] The second allocation component 720 can be composed of a combination logic circuit. Since in the case where the second comparison result indicates that the first mapping information does not include the data source identifier, it indicates that the data packet with the same data source identifier as the current data packet has not been processed, it can be understood that no counter has been allocated to the current data packet in the second processing submodule 212. When the counter is reset, the second allocation component 720 also deletes the mapping information recording the allocation result between the transaction identifier and the counter.

[0091] Therefore, when the second allocation component 720 receives the first count signal, the comparison result P1, and the comparison result R2 from the first processing submodule 211, the second allocation component 720 can allocate the first transaction identifier to the first counter 710 based on the first transaction identifier carried by the first count signal, and control the first counter 710 to count to obtain a first count value.

[0092] The first counter 710 may be constructed from a programmable counter circuit for counting and tracking transaction identifiers, and is capable of counting upon receiving a first counting signal from the first processing submodule 211. Upon receiving a first response signal from the on-chip network module 230, it is reset based on the first count value.

[0093] By assigning counters based on data source identifiers, each counter is only responsible for recording the number of data packets from the same data source. This ensures that the corresponding identifier packet is written to the on-chip storage module only after all preceding data packets from the same data source have been written. This ensures dynamic consistency and coordination of data from various computing nodes, avoids mismatches between data sent by the sender and data read by the receiver, and ensures efficient, accurate transmission and synchronization of data between multiple computing nodes.

[0094] Figure 8 This illustration schematically shows another embodiment according to the present disclosure. Figure 2 The circuit architecture diagram of the second processing submodule in the inter-chip processing module is shown.

[0095] The first processing submodule 211 is also configured to send a synchronization signal to the second processing submodule when it is determined that the message type is an identification message.

[0096] like Figure 8 As shown, the comparison result P2 is output by the first comparison unit configured in the first processing submodule 211 as described above, indicating that the message type of the current message is an identification message. The signal output by the first comparison unit to characterize the comparison result P2 can be sent to the second processing submodule 212 as a synchronization signal.

[0097] The second processing submodule 212 is configured to synchronize a first count value to a synchronization unit associated with a first transaction identifier in response to a synchronization signal; so that the synchronization unit and the first counter are synchronized and reset based on the first count value in response to a first response signal associated with the first transaction identifier.

[0098] like Figure 8 As shown, the first counter 710 is composed of a programmable counter circuit. When the first counter 710 receives a synchronization signal, it sends the first count value in the first counter 710 to the synchronization unit 810 associated with the first transaction identifier.

[0099] In some embodiments, the second processing submodule 212 can include multiple synchronization units, the number of which can be the same as the number of counters, and a dedicated synchronization unit can be pre-configured for each counter, so that the second processing submodule 212 can synchronize the first count value in the first counter 710 to the synchronization unit 810 in response to the synchronization signal.

[0100] In some embodiments, the second processing submodule 212 further includes a third allocation component 820 configured to, in the case where the first comparison result indicates that the message type is an identification message, allocate a target address to the identification message based on the data source identifier and the synchronization identifier in the identification message; and send the target address to the first processing submodule.

[0101] As shown in Figure 8 , the third allocation component 820 can be composed of a sequential logic circuit, which allocates target addresses to identification messages in turn according to the time sequence of receiving comparison results P2. Then, the target addresses are sent to the first processing submodule 211, so that the first processing submodule 211 can store the identification messages into the first memory based on the target addresses.

[0102] This way of allocating storage addresses to identification messages in sequence ensures that the relative order between the data messages and the identification messages of the same data source read by the receiving computing node is consistent with the relative order between the data messages and the identification messages of the same data source sent by the sending computing node, further improving the dynamic cooperative consistency of the data read by the receiving computing node and the data sent by the sending computing node.

[0103] In a computing power expansion network (i.e., a distributed system), as the scale of the computing cluster expands, each computing node is likely to receive thousands of synchronization data sent by other data nodes.

[0104] Therefore, the second processing submodule further includes a first identification comparison unit for receiving the first response signal, comparing the transaction identifier in the first response signal with the first transaction identifier, and obtaining a third comparison result. This can accurately distinguish the transaction identifier of the data message that has been written, so as to accurately control the corresponding counter and synchronization unit to be reset.

[0105] Figure 9 schematically shows a circuit architecture diagram of the second processing submodule in the inter-chip processing module according to yet another embodiment of the present disclosure. Figure 2 schematically shows a circuit architecture diagram of the second processing submodule in the inter-chip processing module according to yet another embodiment of the present disclosure.

[0106] As shown in Figure 9 , the circuit architecture is the same as Figure 8Compared with the circuit architecture shown in the figure, a first identification comparison unit 910 is added, which is connected with the on-chip network module 230, and compares the transaction identification in the first response signal with the first transaction identification when the first response signal is received, to obtain a third comparison result.

[0107] In some embodiments, the first identification comparison unit can be composed of a logic circuit composed of digital logic comparators. It can be understood that the first identification comparison unit 910 outputs a comparison result signal when the first response signal matches the first transaction identification. The comparison result signal is input to the first counter 710 and the synchronization unit 810.

[0108] The first counter 710 and the synchronization unit 810 are also configured to perform a synchronous reset based on the first count value in the case that the third comparison result indicates that the transaction identification of the first response signal is the first transaction identification; and send a first reset signal to the first processing sub-module.

[0109] For example, the first count value can be 3, and the synchronization count value in the synchronization unit is also 3. When the first response signal is received, the count values in the first counter 710 and the synchronization unit 810 can be synchronized to decrease by 1. Until the count values in the first counter 710 and the synchronization unit 810 are synchronized to reset to 0, the first reset signal is sent to the first processing sub-module 211.

[0110] The first processing sub-module 211 is also configured to store the identification message to the on-chip storage module via the on-chip network module in response to the first reset signal.

[0111] In the embodiments of the present disclosure, the first processing sub-module 211 can first read the identification message from the first storage in response to the first reset signal, and then store the identification message to the on-chip storage module via the on-chip network module 230.

[0112] In some embodiments, the message sequence from the same data source can include multiple identification messages, for example, the message sequence can be: D1, D2, F1, D3, F2, wherein D1, D2 and D3 represent data messages, and F1 and F2 represent identification messages.

[0113] According to the foregoing description, the identification message F1 needs to wait until the data messages D1 and D2 are written and completed before being issued, and the identification message F2 needs to wait until D1, D2 and D3 are written and completed before being issued.

[0114] When the inter-chip processing module 210 receives the identification message F1, the count value in the first counter is 2, at this time, the count value associated with the identification message F1 synchronized by the synchronization unit is 2. When the inter-chip processing module 210 receives the identification message F2, and the previous sequence data message is not written to completion, the count value in the first counter is 3, at this time, the count value associated with the identification message F2 synchronized by the synchronization unit is 3.

[0115] When the first response signal is received, because the data sources are the same, the transaction identification is also the same, it can be understood that the count values associated with the identification message F1 and the identification message F2 are synchronized to decrease by 1 until the count value associated with the identification message F1 is zero, a reset signal is generated to control the identification message F1 to be issued. When the first response signal is received again, the count value associated with the identification message F2 is zero, a control signal for controlling the identification message F2 to be issued is generated.

[0116] Therefore, based on the response signal to control the synchronization reset of the synchronization unit and the counter, the order consistency of the synchronization identification in the message sequence of the same data source can be ensured, thereby improving the synchronization degree of the data observed by the computing node of the receiving end and the data sent by the computing node of the sending end.

[0117] In the embodiments of the present disclosure, the computing node of the sending end only needs to send the identification message with the synchronization identification, and the computing node of the receiving end monitors the synchronization identification after receiving the message, without any complex software intervention mechanism and without a cache clearing mechanism, so that the data synchronization consistency between the computing nodes can be realized. The data consistency at the hardware level avoids the data aging risk, and further improves the data synchronization efficiency and the operation accuracy.

[0118] In addition, the embodiments of the present disclosure also provide another scheme to ensure the dynamic collaborative consistency of data between the computing nodes in the case that the inter-chip processing module cannot accurately identify the identification message to block the identification message from being issued.

[0119] In the case that the inter-chip processing module cannot accurately identify the identification message to block the identification message from being issued, the messages can be sequentially stored to the on-chip storage module through the on-chip network module. Because the identification message sent by the computing node of the sending end is certainly after the data message associated with the identification message, sequentially issuing the messages can also ensure the dynamic collaborative consistency of data between the computing nodes.

[0120] The following will be described in detail Figures 10-12 The sequentially issued message scheme will be described in detail.

[0121] Figure 10A circuit architecture diagram of an inter-slice processing module in any computing node according to another embodiment of the present disclosure is schematically shown.

[0122] As shown in Figure 10 The computing node 1000 can include an inter-slice processing module 1010, a processor 220, an on-chip network module 230 and an on-chip storage module 240. The connection mode between the modules in the computing node 1000 is the same as that of the second computing node 200 described above, and will not be repeated here.

[0123] In the embodiments of the present disclosure, the packet sequence can include N packets; N is an integer greater than 1;

[0124] The inter-slice processing module 1010 further includes a third processing submodule 1011 and a fourth processing submodule 1012.

[0125] The third processing submodule 1011 is configured to determine a second transaction identifier according to the data source identifier of the nth packet, store the nth packet with the second transaction identifier to the on-chip storage module 240 via the on-chip network module 230, and send a second count signal to the fourth processing submodule 1012; n = 1, 2, 3, … N-1.

[0126] The fourth processing submodule 1012 includes a plurality of counters, and the fourth processing submodule is configured to control a second counter associated with the second transaction identifier to count in response to the second count signal, to obtain a second count value; and control the second counter to reset based on the second count value and send a second reset signal to the third processing submodule 1011 in a case where it is determined that the first response signal indicates that the nth packet has been written.

[0127] The third processing submodule 1011 is further configured to determine a third transaction identifier according to the data source identifier of the (n+1)th packet in response to the second reset signal, store the (n+1)th packet with the third transaction identifier to the on-chip storage module 240 via the on-chip network module 230, and send a third count signal to the fourth processing submodule 1012.

[0128] In the embodiments of the present disclosure, the inter-slice processing module 1010 can write all the received N packets to the storage area of the on-chip network module 230 according to the first-in-first-out mechanism, to form a storage queue in the storage area of the on-chip network module 230.

[0129] When the third processing submodule 1010 counts using the second counter, the second count value can be 1. When the third processing submodule receives the first response signal, the second counter is controlled to reset based on the second count value, at which time the second count value is reset to zero, and a second reset signal is generated.

[0130] When the third processing submodule 1010 receives the second reset signal, it is identified that the nth message has been written into the on-chip storage module 240, and the nth+1 message in the storage queue can be controlled to be stored into the on-chip storage module 240. And the third count signal is synchronously issued to control the counter associated with the third transaction identification to count.

[0131] Through the dynamic allocation of the transaction identification and the response of the counter to the reset in the case that the message has been written, the issuance of the next message is controlled, which can still guarantee the dynamic synchronization of data between the computing nodes in the case that the inter-chip processing module cannot identify the message type.

[0132] In order to realize the above-mentioned functions of the inter-chip processing module 1010, the circuit architecture of the third processing submodule 1011 and the fourth processing submodule 1012 will be described in detail below. Figure 11 and Figure 12 respectively.

[0133] Figure 11 The circuit architecture of the third processing submodule in the inter-chip processing module according to the embodiment of the present disclosure is schematically shown. Figure 10 The circuit architecture of the third processing submodule in the inter-chip processing module according to the embodiment of the present disclosure is schematically shown.

[0134] As shown in Figure 11 The third processing submodule 1011 includes a third memory 1110, a third comparison unit 1120, a fourth allocation component 1130, a second selector 1140 and a second sending unit 1150.

[0135] The third memory 1110 is connected with the third comparison unit 1120 and is configured to store the second mapping information between the data source identification and the transaction identification.

[0136] The second mapping information can be dynamically updated, and after the message of a certain transaction identification has been written, the mapping information associated with the transaction identification can be deleted from the third memory 1110 to release the transaction identification. The dynamic allocation and release of the transaction identification can reduce the storage resource overhead and be suitable for the interconnection requirements between larger-scale computing nodes.

[0137] The third comparison unit 1120 is configured to compare the second mapping information with the data source identification of the nth message and output a fourth comparison result.

[0138] For example, the third comparison unit 1120 can be composed of a logic circuit composed of a digital logic comparator. By comparing the second mapping information with the data source identification of the nth message, when the second mapping information includes the data identification of the nth message, a signal representing the comparison result L1 is output.

[0139] The second selector 1140 is configured to select the second transaction identifier as the transaction identifier of the nth message according to the data source identifier of the nth message in a case where the fourth comparison result indicates that the second mapping information includes the data source identifier of the nth message or the second allocation result indicates that the second transaction identifier is allocated to the nth message, to obtain the nth message with the second transaction identifier.

[0140] For example, the initial transaction identifiers in the nth message are all empty, and the second selector 1140 can select the second transaction identifier as the transaction identifier of the nth message based on the data source identifier of the nth message after receiving the comparison result L1, to obtain the nth message with the second transaction identifier.

[0141] The second sending unit 1150 is configured to store the nth message with the second transaction identifier to the on-chip storage module via the on-chip network module 230. For example, the second sending unit 1150 can also be composed of a multiplexer (MUX).

[0142] In a case where the third comparison unit 1120 determines that the second mapping information does not include the data source identifier of the nth message by comparing the second mapping information with the data source identifier of the nth message, a signal used to represent the comparison result L2 is output. The signal output by the third comparison unit 1120 can be sent as a second counting signal to the fourth processing sub-module, so that the fourth processing sub-module performs counting.

[0143] The fourth allocation component 1130 is configured to, in a case where the fourth comparison result indicates that the second mapping information does not include the data source identifier of the nth message, that is, the signal used to represent the comparison result L2 is received. Allocate the second transaction identifier to the nth message based on the data source identifier of the nth message, to obtain a second allocation result; and store the mapping relationship between the second transaction identifier and the data source identifier to the third memory.

[0144] For example, the second allocation result can indicate that the transaction identifier of the nth message is the second transaction identifier.

[0145] In the embodiments of the present disclosure, the fourth allocation component 1130 can be composed of the same digital circuit as the allocation component described above for allocating the transaction identifier, which will not be described here.

[0146] The embodiments of the present disclosure utilize the maximum transmission transaction concurrency limit supported by the on-chip network module, perform multi-layer dynamic mapping on the messages of different data sources, and greatly reduce the storage resource overhead required by the computing nodes at the receiving end to complete data consistency collaboration through dynamic allocation and release of the corresponding transaction identifiers, thereby expanding the interconnection scale between the computing nodes in the distributed system.

[0147] Figure 12Fig. 1 schematically illustrates a system according to an embodiment of the present disclosure; Figure 10 Fig. 2 schematically illustrates a circuit architecture diagram of a fourth processing submodule in the inter-chip processing module.

[0148] As shown in Fig. 2, the fourth processing submodule 1012 can include a plurality of counters and a fifth allocation component. Figure 12 As shown in Fig. 2, the fourth processing submodule 1012 can include a plurality of counters and a fifth allocation component. Figure 12 As shown, there is a second counter associated with the second transaction identification, and the rest of the counters have the same structure as the second counter, which is not described here.

[0149] When the fourth processing submodule 1012 receives the second count signal and the comparison result L1, it indicates that the previous packet from the same data source as the current data packet has been processed, and therefore, the second counter 1210 associated with the second transaction identification can be controlled to count based on the second count signal to obtain a second count value.

[0150] The fourth processing submodule further includes a fifth allocation component 1220 configured to allocate the second transaction identification to the second counter 1210 based on the data source identification of the nth packet in the case where the third comparison result indicates that the second mapping information does not include the data source identification of the nth packet.

[0151] The fifth allocation component 1220 can also be composed of combinational logic circuits, and since in the case where the third comparison result indicates that the second mapping information does not include the data source identification of the nth packet, it indicates that the data packet with the same data source identification as the current data packet has not been processed, it can be understood that no counter has been allocated to the current data packet in the fourth processing submodule 1212.

[0152] Therefore, when the fifth allocation component 1220 receives the second count signal and the comparison result L2 from the third processing submodule 1011, the fifth allocation component 1220 can allocate the second transaction identification to the second counter 1210 based on the second transaction identification carried by the second count signal, and control the second counter 1210 to count to obtain a second count value.

[0153] The second counter 1210 can be composed of a programmable counter circuit for counting and tracking transaction identifications, and can count when receiving the second count signal from the third processing submodule 1011. When receiving the first response signal from the on-chip network module 230, it is reset based on the second count value.

[0154] The data source identifier is used to assign the counter, so that each counter is responsible for recording the number of data packets from the same data source, thereby ensuring that the nth packet is written to the on-chip storage module, and then the n+1 packet is written to the on-chip storage module. The dynamic consistency of data from each computing node is ensured, and the phenomenon that the data sent by the sending end does not match the data read by the receiving end is avoided, thereby ensuring efficient and accurate transmission and synchronization of data among multiple computing nodes.

[0155] Based on the above two schemes for realizing dynamic consistency of data among computing nodes, the flexibility and robustness of the hardware circuit implementation are further improved at the hardware level.

[0156] Figure 13 A flowchart of a data transmission method according to an embodiment of the present disclosure is schematically shown.

[0157] As Figure 13 shown, the data transmission method 1300 can include operations S1310-S1330. The data transmission method can be applied to any computing node described above.

[0158] In operation S1310, in response to receiving a packet sequence from another computing node, the data packets in the packet sequence are stored in the on-chip storage module via the on-chip network module.

[0159] In operation S1320, in response to determining that the target data in the data packet has been written, the identification packet in the packet sequence is sent to the on-chip storage module via the on-chip network module.

[0160] In operation S1330, the processor reads the target data from the on-chip storage module via the on-chip network module after determining that the synchronization identifier in the identification packet has been written.

[0161] According to an embodiment of the present disclosure, the arrangement order of the data packet in the packet sequence is before the identification packet.

[0162] In an embodiment of the present disclosure, a plurality of computing nodes are deployed in a distributed system or a computing power expansion network, and the data transmission method can be applied to any computing node as a receiving end in the distributed system or the computing power expansion network.

[0163] For example, the distributed system is deployed with a computing node A and a computing node B as a sending end. In the data synchronization process, the computing node A as a sending end can first send target data to the on-chip network module on the computing node A, while carrying a data source identifier. The inter-chip processing module of the sending end computing node A packs the target data and attaches the data source identifier of the computing node A to generate a data packet. Based on the interconnection mechanism between the computing node A and the computing node B, such as an Ethernet or a PCIe protocol, the inter-chip processing module of the computing node B sends the data packet to the inter-chip processing module of the computing node B.

[0164] The sending process of the identification packet is similar to that of the data packet, except that the inter-chip processing module of the computing node A packs the synchronization identifier and attaches the data source identifier of the computing node A to generate the identification packet.

[0165] The inter-chip processing module of the computing node B stores the received data packet in the on-chip storage module of the computing node B via the on-chip network module of the computing node B in time. However, for the received identification packet, it needs to wait until the preceding data packet of the identification packet has been written into the on-chip storage module of the computing node B before being stored in the on-chip storage module of the computing node B via the on-chip network module of the computing node B.

[0166] It can be understood that the identification packet is issued after the preceding data packet has been written into the on-chip storage module of the computing node B, so when the processor of the computing node B determines that the identification packet has been written, the data read from the on-chip storage module is the same as the data sent by the sending end, thereby further improving the transmission accuracy and synchronization efficiency of data between multiple computing nodes.

[0167] The following will be described in detail Figure 14 An embodiment of the above data transmission method will be described in detail.

[0168] Figure 14 A logic block diagram of a data transmission method according to an embodiment of the present disclosure is schematically shown.

[0169] According to an embodiment of the present disclosure, in response to receiving a packet sequence from another computing node, storing data packets in the packet sequence into an on-chip storage module via an on-chip network module can include the following operations: in response to receiving any packet in the packet sequence, parsing the any packet to obtain a packet address of the any packet and a data source identifier of the any packet; determining a packet type of the any packet according to the first packet address; determining a first transaction identifier according to the data source identifier of the any packet; in response to determining that the packet type is a data packet, sending the data packet with the first transaction identifier to the on-chip storage module via the on-chip network module according to the first packet address.

[0170] As Figure 14As shown, the message 1400 can be any message in a message sequence from another computing node. First, the message 1400 is parsed to obtain the data source identifier 1401 and the message address 1402. Then, the message type is determined and the transaction identifier is matched. The message type determination and the transaction identifier matching can be performed in parallel.

[0171] As shown, the transaction identifier matching stage can include the following operations: first, operation S1410 can be performed based on the data source identifier 1401 and the identifier mapping information 1403. When the data source identifier 1401 hits the identifier mapping information 1403, it means that the data source identifier 1401 exists in the identifier mapping information 1403, then operation S1420 can be performed to determine the first transaction identifier. When the data source identifier 1401 does not hit the identifier mapping information 1403, it means that the data source identifier 1401 does not exist in the identifier mapping information 1403, then operation S1430 can be performed to assign the transaction identifier, i.e., assign the first transaction identifier to the message 1400. Figure 14 Based on the data source identifier, the transaction identifier uniquely associated with the message is assigned, which can ensure the traceability of the communication between the computing nodes, and establish an association basis for subsequent synchronization verification and synchronization control between nodes.

[0172] According to an embodiment of the present disclosure, the above method can further include the following operations: in response to determining that the message type is an identifier message, determining a target address for storing the identifier message based on the data source identifier; and storing the identifier message and the first transaction identifier in association according to the target address.

[0173] As shown, the message type determination stage can include the following operations: first, operation S1460 can be performed based on the message address 1402 and the predetermined address range 1404 to determine the message type. When the message address 1402 is within the predetermined address range 1404, it means that the message type of the message 1400 is an identifier message, then operation S1470 is performed to assign a storage address. Then, operation S1480 is performed to store the identifier message. When the message address 1402 is not within the predetermined address range 1404, it means that the message type of the message 1400 is a data message, then operation S1440 is performed to issue the data message.

[0174] Figure 14 Operation S1450 is performed to count the transaction identifier counter. After operation S1480 is performed, operation S1490 is performed to synchronize the count value in the transaction identifier counter by the synchronization unit.

[0175] Operation S1450 is performed to count the transaction identifier counter. After operation S1480 is performed, operation S1490 is performed to synchronize the count value in the transaction identifier counter by the synchronization unit.

[0176] ​The computing node as the receiving end feeds back a response signal in a case where the data message has been written, so as to determine the start point of entering the identification message transmission phase, and a closed-loop transmission verification mechanism is formed on the computing node as the receiving end.

[0177] According to an embodiment of the present disclosure, in response to determining that the target data in the data message has been written, sending, via the on-chip network module, the identification message in the message sequence to the on-chip storage module can include the following operations: obtaining response information from the on-chip storage module; in response to determining that the first transaction identifier is included in the response information, updating the count value associated with the first transaction identifier; and in response to determining that the updated count value is equal to a predetermined threshold value, determining that the target data in the data message has been written, and sending, via the on-chip network module, the identification message in the message sequence to the on-chip storage module.

[0178] As shown in Figure 14 Based on the response information 1405 associated with the first transaction identifier, operation S1410 is performed, and the counters of the transaction identifiers and the count values in the synchronization unit are updated synchronously.

[0179] Then, operation S1402 is performed to determine whether the updated count value is 0; if yes, operation S1404 is performed to issue the identification message. If no, operation S1403 is performed to wait for the next response signal associated with the first transaction identifier.

[0180] By judging the message type and issuing the data message in a timely manner, only the issuance of the identification message is blocked, and the identification message is issued only in a case where the previous data messages associated with the identification message have all been written. In the case of guaranteeing the dynamic consistency of the data of the receiving end and the sending end, the transmission efficiency of the data flow between the computing nodes is further improved, and the storage resources consumed by the computing nodes of the receiving end to achieve data synchronization are also reduced.

[0181] Figure 14 The embodiment shown blocks the issuance of the identification message, ensures the relative order between the data messages and the identification messages of the same data source for the computing node as the receiving end, and thus effectively avoids the problem that the data read by the computing node of the receiving end is inconsistent with the data sent by the computing node of the sending end.

[0182] The following will be described in detail Figure 15 Another embodiment of the above data transmission method will be described in detail.

[0183] According to an embodiment of the present disclosure, the above method can further include the following operations: storing the nth message to the on-chip storage module via the on-chip network module; and in response to determining that the nth message has been written, storing the (n+1)th message to the on-chip storage module via the on-chip network module.

[0184] Figure 15 A logic block diagram of a data transmission method according to an embodiment of the present disclosure is shown.

[0185] As shown in Figure 15 , first, operation S1510 is performed to parse the nth message to obtain the data source identifier 1501 of the nth message. Then, operation S1520 is performed to match the data source identifier 1501 of the nth message with the identifier mapping information 1502. When it is determined that the data source identifier 1501 of the nth message hits the identifier mapping information 1502, operation S1540 is performed to determine the second transaction identifier. When it is determined that the data source identifier 1501 of the nth message does not hit the identifier mapping information 1502, operation S1530 is performed to assign a transaction identifier to the nth message.

[0186] Then, operation S1550 is performed to deliver the nth message. And operation S1560 is performed to count the transaction counter.

[0187] Then, based on the response information 1503 associated with the second transaction identifier, operation S1501 is performed to update the count value of the transaction identifier counter.

[0188] Then, operation S1502 is performed to determine whether the updated count value is 0; if yes, operation S1510 is returned to parse the nth+1 message, assign a transaction identifier to the nth+1 message, and deliver the nth+1 message. If no, operation S1503 is performed to wait for the next response signal associated with the first transaction identifier.

[0189] Based on the first-in-first-out mechanism, the messages are delivered in order, and the next message is delivered after the response signal of the write completion is received. Since the computing node at the sending end sends the identifier message associated with the data message, the dynamic consistency of the data transmission across nodes can also be achieved.

[0190] Figure 16 An exemplary architecture diagram of the data transmission method according to an embodiment of the present disclosure is shown.

[0191] As shown in Figure 16 , four computing nodes are deployed in the exemplary architecture, and the third computing node is taken as the sending end and the second computing node is taken as the receiving end. The transmission process of the present disclosure is further explained in detail from the sending of the target data by the sending end to the reading of the target data by the receiving end. The process can include operations S1-S16.

[0192] In operation S1, the third computing node sends the target data carrying the identifier of the processor G31 to the network-on-chip module Noc3 by the processor G31.

[0193] During operation S2, the on-chip network module Noc3 sends the target data carrying the identifier of the processor G31 to the inter-chip processing module C3.

[0194] During operation S3, the inter-chip processing module C3 will assemble the target data carrying the identifier of processor G31 into packets, and attach the identifier of the third computing node and the message address to encapsulate the data packets.

[0195] During operation S4, the inter-chip processing module C3, based on the interconnection mechanism, sends data packets to the inter-chip processing module C2 of the second computing node according to the packet address.

[0196] The embodiments disclosed herein ensure dynamic consistency of data among multiple computing nodes during data synchronization through multi-level mapping operations, thereby further improving the effectiveness of the data read by the receiving computing node.

[0197] The above operations S1~S4 can be repeated multiple times until a predetermined number of data packets are sent to the second computing node. Then, operation S5 is executed, and the third computing node sends a synchronization identifier carrying the processor G31 identifier to the on-chip network module Noc3.

[0198] During operation S6, the on-chip network module Noc3 sends a synchronization identifier carrying the processor G31 identifier to the inter-chip processing module C3.

[0199] During operation S7, the inter-chip processing module C3 will assemble the synchronization identifier carrying the processor G31 identifier into a packet, and attach the identifier and message address of the third computing node to encapsulate it into an identifier message.

[0200] During operation S8, the inter-chip processing module C3, based on the interconnection mechanism, sends the identification message to the inter-chip processing module C2 of the second computing node according to the message address.

[0201] During operation S9, the inter-chip processing module C2 parses the packet, dynamically allocates a transaction identifier based on the data source identifier, and forwards the data packet with the transaction identifier to the on-chip network module Noc2. The inter-chip processing module C2 blocks the identified packets.

[0202] During operation S10, the on-chip network module Noc2 writes data packets one by one into the storage area on the on-chip storage module O2 for storing data.

[0203] In operation S11, the on-chip storage module O2 returns a response signal to the on-chip network module Noc2 after the data packet has been written.

[0204] During operation S12, the on-chip network module Noc2 forwards the response signals to the inter-chip processing module C2 one by one.

[0205] At operation S13, the inter-chip processing module C2 sends the identification message blocked in operation S9 to the on-chip network module Noc2, in a case where it is determined that all the preceding data messages associated with the identification message have been written to the on-chip storage module O2.

[0206] At operation S14, the on-chip network module Noc2 writes the identification message to a storage area for storing the identification on the on-chip storage module O2.

[0207] At operation S15, the processor G2 sends a query signal to the on-chip storage module O2 via the on-chip network module Noc2 based on a polling mechanism.

[0208] At operation S16, the on-chip storage module O2 returns the query result to the processor G2 via the on-chip network module Noc2, and reads the target data from the on-chip storage module O2 via the on-chip network module Noc2 in a case where it is determined that the synchronization identification has been written to the on-chip storage module O2.

[0209] It should be understood that the various forms of flow shown above can be used to reorder, add or delete steps. For example, the steps described in the present disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions of the present disclosure can be achieved, which are not limited herein.

[0210] The above detailed description does not constitute a limitation on the protection scope of the present disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A computing node, comprising: On-chip network module; An inter-chip processing module is configured to receive a message sequence from another computing node, store the data packets in the message sequence to an on-chip storage module via an on-chip network module, and, upon determining, based on a first response signal returned by the on-chip storage module via the on-chip network module that the target data in the data packets has been written, send an identification message from the message sequence to the on-chip storage module via the on-chip network module; wherein the data packets are arranged before the identification message in the message sequence. The processor is configured to send a query signal to the on-chip storage module via the on-chip network module, and, upon determining, based on a second response signal returned by the on-chip storage module via the on-chip network module that the synchronization identifier in the identifier message has been written, read the target data from the on-chip storage module via the on-chip network module.

2. The computing node according to claim 1, wherein, The inter-chip processing module includes: The first processing submodule is configured to: determine the message type of any message based on the message address of any message in the message sequence, and determine the first transaction identifier of any message based on the data source identifier of any message; if the message type is determined to be a data message, store the data message in the on-chip storage module via the on-chip network module according to the message address, and send a first counting signal to the second processing submodule. The second processing submodule includes multiple counters; the second processing submodule is configured to: in response to the first counting signal, control the first counter associated with the first transaction identifier to count, and obtain a first count value.

3. The computing node according to claim 2, wherein, The first processing submodule includes: A register is configured to store a predetermined address range; the predetermined address range indicates an available storage area in the first memory for storing identification messages; The first comparison unit is configured to read the predetermined address range from the register and compare the message address with the predetermined address range to obtain a first comparison result; The identifier determination unit is configured to determine the first transaction identifier based on the data source identifier, and obtain a data packet with the first transaction identifier; The first sending unit is configured to store the data packet with the first transaction identifier in the on-chip storage module via the on-chip network module when the first comparison result indicates that the message type is the data packet.

4. The computing node according to claim 3, wherein: The identifier determination unit includes: The second memory is configured to store the first mapping information between the data source identifier and the transaction identifier; The second comparison unit is configured to compare the first mapping information with the data source identifier and output a second comparison result. The first allocation component is configured to: when the second comparison result indicates that the first mapping information does not include the data source identifier, allocate the first transaction identifier to the data packet based on the data source identifier to obtain a first allocation result; and store the mapping relationship between the first transaction identifier and the data source identifier in the second memory. A first selector is configured to select the first transaction identifier as the transaction identifier of the data packet based on the data source identifier when the second comparison result indicates that the first mapping information includes the data source identifier or the first allocation result indicates that the first transaction identifier is allocated to the data packet, thereby obtaining a data packet with the first transaction identifier.

5. The computing node according to any one of claims 2-4, wherein, The second processing submodule also includes: The second allocation component is configured to allocate the first transaction identifier to the first counter based on the data source identifier when the second comparison result indicates that the first mapping information does not include the data source identifier.

6. The computing node according to any one of claims 2-5, wherein: The first processing submodule is further configured to: send a synchronization signal to the second processing submodule when it is determined that the message type is an identification message; The second processing submodule further includes multiple synchronization units, and the second processing submodule is configured to: synchronize the first count value to the synchronization unit associated with the first transaction identifier in response to the synchronization signal; and cause the synchronization unit and the first counter to be synchronously reset based on the first count value in response to the first response signal associated with the first transaction identifier.

7. The computing node according to claim 6, wherein, The second processing submodule also includes: The third allocation component is configured to, when the first comparison result indicates that the message type is the identified message, allocate the target address to the identified message based on the data source identifier and the synchronization identifier in the identified message; and send the target address to the first processing submodule.

8. The computing node according to claim 7, wherein, The first processing submodule further includes: A first memory is configured to store the identification message; The first sending unit is further configured to: when the first comparison result indicates that the message type is the identified message, store the identified message with the first transaction identifier into the first memory according to the target address; and in response to the first reset signal, read the identified message from the first memory and store the identified message into the on-chip storage module via the on-chip network module.

9. The computing node according to any one of claims 6-8, wherein, The second processing submodule also includes: The first identifier comparison unit is configured to receive the first response signal, compare the transaction identifier in the first response signal with the first transaction identifier, and obtain a third comparison result.

10. The computing node according to claim 9, wherein: The first counter and the synchronization unit are further configured to perform a synchronization reset based on the first counter value when the third comparison result indicates that the transaction identifier of the first response signal is the first transaction identifier; and to send a first reset signal to the first processing submodule. The first processing submodule is further configured to, in response to the first reset signal, store the identification message in the on-chip storage module via the on-chip network module.

11. The computing node according to claim 1, wherein, The message sequence includes N messages; N is an integer greater than 1; the inter-chip processing module further includes: The third processing submodule is configured to determine the second transaction identifier based on the data source identifier of the nth message, store the nth message with the second transaction identifier in the on-chip storage module via the on-chip network module, and send the second counting signal to the fourth processing submodule; n=1,2,3,…N-1; The fourth processing submodule includes multiple counters. The fourth processing submodule is configured to respond to the second counting signal, control the second counter associated with the second transaction identifier to count, and obtain a second count value; when it is determined that the first response signal indicates that the nth message has been written, control the second counter to reset based on the second count value, and send a second reset signal to the third processing submodule. The third processing submodule is further configured to, in response to the second reset signal, determine a third transaction identifier based on the data source identifier of the (n+1)th message, store the (n+1)th message with the third transaction identifier in the on-chip storage module via the on-chip network module, and send a third counting signal to the fourth processing submodule.

12. The computing node according to claim 11, wherein, The third processing submodule includes: The third memory is configured to store the second mapping information between the data source identifier and the transaction identifier; The third comparison unit is configured to compare the second mapping information with the data source identifier of the nth message and output a fourth comparison result; The fourth allocation component is configured to, when the fourth comparison result indicates that the second mapping information does not include the data source identifier of the nth message, allocate the second transaction identifier to the nth message based on the data source identifier of the nth message to obtain a second allocation result; and store the mapping relationship between the second transaction identifier and the data source identifier of the nth message in the third memory; The second selector is configured to select the second transaction identifier as the transaction identifier of the nth message based on the data source identifier of the nth message when the fourth comparison result indicates that the second mapping information includes the data source identifier of the nth message or the second allocation result indicates that the second transaction identifier is allocated to the nth message, thereby obtaining the nth message with the second transaction identifier. The second sending unit is configured to store the nth message with the second transaction identifier to the on-chip storage module via the on-chip network module.

13. The computing node according to claim 11, wherein, The fourth processing submodule also includes: The fifth allocation component is configured to allocate the second transaction identifier to the second counter based on the data source identifier of the nth message when the second comparison result indicates that the second mapping information includes the data source identifier of the nth message.

14. A data transmission method, applied to a computing node according to any one of claims 1 to 11, the method comprising: In response to receiving a message sequence from another computing node, the data packets in the message sequence are stored in the on-chip storage module via the on-chip network module; In response to determining that the target data in the data packet has been written, the identification packet in the packet sequence is sent to the on-chip storage module via the on-chip network module; and When the processor determines that the synchronization identifier in the identification message has been written, it reads the target data from the on-chip storage module via the on-chip network module. The data packets are arranged in the packet sequence before the identification packets.

15. The method according to claim 14, wherein, The step of responding to receiving a message sequence from another computing node and storing the data packets in the message sequence to the on-chip storage module via the on-chip network module includes: In response to receiving any message in the message sequence, the message is parsed to obtain the message address and the data source identifier of the message. The message type of any one of the messages is determined based on the first message address; The first transaction identifier is determined based on the data source identifier of any of the messages; In response to determining that the message type is a data message, the data message with the first transaction identifier is sent to the on-chip storage module via the on-chip network module according to the first message address, based on the first transaction identifier.

16. The method of claim 15, further comprising: In response to determining that the message type is an identification message, a target address for storing the identification message is determined based on the data source identifier; According to the target address, the identification message is associated with and stored with the first transaction identifier.

17. The method according to any one of claims 14-16, wherein, In response to determining that the target data in the data packet has been written, the identification packet in the packet sequence is sent to the on-chip storage module via the on-chip network module, including: Obtain response information from the on-chip storage module; In response to determining that the response information includes the first transaction identifier, the count value associated with the first transaction identifier is updated; and In response to determining that the updated count value is equal to a predetermined threshold, it is determined that the target data in the data packet has been written, and the identification packet in the packet sequence is sent to the on-chip storage module via the on-chip network module.

18. The method according to claim 1, wherein, The message sequence includes N messages, where N is an integer greater than 1; the method further includes: The nth message is stored in the on-chip storage module via the on-chip network module; In response to determining that the nth message has been written, the (n+1)th message is stored in the on-chip storage module via the on-chip network module.

Images