Multiple deep trench insulated pillar high conductivity insulated gate bipolar transistor and process thereof

Abstract

The application discloses a multiple deep-groove insulating column high-conductivity insulated gate bipolar transistor and a manufacturing method thereof, and relates to the technical field of power semiconductor manufacturing. The application discloses a multiple deep-groove insulating column high-conductivity insulated gate bipolar transistor and a manufacturing method thereof, and relates to the technical field of power semiconductor manufacturing. The emitter end comprises an emitting area, a base area and an insulating layer, and the base area is provided with groove type gates on both sides. The emitter end further comprises a potential floatable P type area and a plurality of deep-groove insulating columns in the P type area. The P type area is formed by doping P ions on the sidewalls and the bottom of the insulating column grooves, and the deep-groove insulating columns are filled with insulating materials. The emitting area comprises two N+ emitter areas and a P+ area between the N+ emitter areas. By increasing the number of insulating columns, performing sidewall ion implantation and backfilling insulating material process, the processing difficulty of the potential floatable P type area is reduced, and the process reliability is improved. The above structure changes the hole flow direction to realize low saturation voltage between the collector and the emitter end, reduces excessive carriers of the emitter end, shortens the switching time, reduces the switching loss, reduces the electric field intensity at the bottom of the gate, and improves the breakdown voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power semiconductor manufacturing, in particular to a multi-deep trench insulation column high-conductivity insulated gate bipolar transistor and a process thereof. BACKGROUND

[0002] In recent years, insulated gate bipolar transistors (IGBT) have been widely used, with application ranges extending from industrial motor drives, buses, high-speed rail passenger vehicles to household appliances, and have been mass-produced by many international manufacturers.

[0003] The structure of a conventional trench insulated gate bipolar transistor (Trench IGBT) is shown in Figure 2a , which mainly depends on the competitive relationship between the on-state loss P on and the off-state loss P off of the collector-emitter saturation voltage VCE sat under the rated current. When the transistor is in the on state, more carrier injection can increase the conductivity and thus reduce the on-state loss, but when the transistor is in the off state, it takes energy to empty the injected carriers, so more carrier injection will also produce higher off-state loss P off . Recently, researchers have proposed a structure that can reduce the collector-emitter saturation voltage VCE sat , as shown in Figure 2b . In this structure, isolated P-doped regions are provided on both sides of the main structure region, which are not connected to the electrodes and can freely float. Holes need to bypass these isolated P-doped regions to pass through the P-base region of the main structure region to reach the N+ emitter electrode, so the holes will accumulate in these isolated P-doped regions, thereby increasing the N-drift region conductivity modulation effect and reducing the on-state voltage drop. The P-doped region with floating potential extends the zero-potential region outside the gate region downward, reducing the electric field strength at the edge of the gate, which reduces the probability of tunneling effect at the lower corner of the gate, thereby improving the voltage resistance of the component.

[0004] The current method for making isolated P-type regions is to use high-energy injection and long-time diffusion doping technology, which requires special equipment or processes. Forming a large-volume P-type region takes a long time, and the annealing temperature is not easy to control, which has problems such as high process difficulty, expensive equipment requirements, and difficulty in accurately controlling the doping concentration. SUMMARY

[0005] In view of the above problems existing in actual production, one of the purposes of the present application is to provide a multiple deep trench insulating column high-conductivity insulated gate bipolar transistor, which, while achieving low on-state voltage drop and off-state loss by setting an isolated P-doped region, sets multiple deep trench insulating columns in the isolated P-doped region to optimize the production process to overcome the difficulty of large-volume doping. In order to produce the multiple deep trench insulating column high-conductivity insulated gate bipolar transistor, the second purpose of the present application also proposes a multiple deep trench insulating column high-conductivity insulated gate bipolar transistor process, which processes multiple deep trenches in the isolated P-doped region, performs P-type ion implantation through the sidewalls of the deep trenches, and backfills insulating material to form a P-type region with floating potential, i.e., a P-doped region, containing multiple insulating columns, thereby replacing the traditional high-energy implantation process, which can reduce the process difficulty and increase the process feasibility. The specific scheme is as follows:

[0006] A multiple deep trench insulating column high-conductivity insulated gate bipolar transistor, comprising an emitter end and a collector end, the emitter end comprising a main unit and auxiliary units on both sides of the main unit; wherein,

[0007] The main unit comprises an emission region, a base region, and an insulating layer, and the base region has a trench gate on both sides;

[0008] The auxiliary unit comprises a P-type region with floating potential and multiple deep trench insulating columns therein;

[0009] The P-type region with floating potential is formed by doping P-ions on the sidewalls and bottom of the insulating column trench, and the deep trench insulating column is filled with insulating material;

[0010] The emission region comprises N+ emitter regions on both sides of the top of the base region, and a P+ region between the two N+ emitter regions.

[0011] Further, the depth of the P-type region with floating potential is greater than the depth of the gate trench.

[0012] Further, the insulating columns are configured as independent insulating columns formed by mutually separated trenches.

[0013] Further, the number of insulating columns is 1-20; the spacing between two adjacent deep trench insulating columns on the same side can be set to be the same or different according to the specific structure design.

[0014] Further, the insulating material comprises oxides and nitrides.

[0015] Further, the oxides comprise silicon dioxide, aluminum oxide, hafnium oxide, or silicon oxynitride;

[0016] The nitrides comprise silicon nitride, aluminum nitride, or boron nitride.

[0017] A multiple deep trench insulation pillar high conductivity insulated gate bipolar transistor process for preparing a multiple deep trench insulation pillar high conductivity insulated gate bipolar transistor as described above, comprising the following steps:

[0018] Grinding the substrate to a set thickness according to the required thickness of the rated voltage;

[0019] Defining a trench on the substrate by photolithography and etching it to the required depth;

[0020] Sequentially generating an oxide and depositing N-type doped polysilicon and etching back to form a trench gate;

[0021] Fabricating a base region by photolithography and ion implantation;

[0022] Forming an N+ emitter region for an emitter electrode ohmic contact by photolithography and ion implantation;

[0023] Fabricating multiple trenches of a specific depth at specific locations of the auxiliary unit using a photolithography and etching process;

[0024] Forming a potential floatable P-type region by P-type ion implantation through the trench sidewall;

[0025] Backfilling an insulating material in the trench to form a deep trench insulation pillar, and polishing the emitter end surface to a set smoothness;

[0026] Depositing an insulating layer and defining an emitter end contact hole using photolithography;

[0027] Forming a P+ region by photolithography and ion implantation;

[0028] Forming a buffer region (N+) by ion implantation at the bottom of the substrate;

[0029] Forming a P+ collector end by ion implantation at the bottom of the substrate;

[0030] Depositing a metal as an emitter electrode on the emitter end;

[0031] Depositing a metal as a collector electrode on the collector end.

[0032] The present application at least includes the following beneficial effects:

[0033] (1) The zero potential region outside the gate extends downward, reducing the power line density at the edge of the component, which can reduce the electric field peak at the gate corner and slow down the occurrence of tunneling effect, thereby improving the voltage withstand performance of the component. The zero potential region outside the gate extends downward, reducing the potential line density at the edge of the component, which can reduce the electric field peak at the gate corner and slow down the occurrence of tunneling effect, thereby improving the voltage withstand performance of the component.

[0034] (2) Reduction of on-state voltage drop (VCEsat):

[0035] (3) The design of the potential floating P-type region structure containing multiple deep trench insulation pillars makes the component different from the traditional trench insulated gate bipolar transistor in terms of carrier flow. Holes need to bypass the potential floating P-type region, so that the holes accumulate under the trench gate, which can effectively change the conductivity of the region;

[0036] (4) The multiple deep trench insulation pillars are configured to form independent insulation pillars by separating the trenches from each other, which can retain the original high-conductivity IGBT advantage of changing the direction of hole flow, while reducing excessive carriers at the emitter end, thereby reducing the switching time and greatly reducing the switching loss of the component. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 is a structure schematic diagram of the multiple deep trench insulation pillar high-conductivity insulated gate bipolar transistor (MFTHC-IGBT) of the present application;

[0038] Figure 2a is a structure schematic diagram of the traditional trench insulated gate bipolar transistor (Trench IGBT);

[0039] Figure 2b is a structure schematic diagram of the high-conductivity trench insulated gate bipolar transistor (HC-IGBT);

[0040] Figure 2c is a structure schematic diagram of the advanced trench process high-conductivity insulated gate bipolar transistor (Advanced Trench HiGT);

[0041] Figure 3 is a method step schematic diagram for manufacturing the multiple deep trench insulation pillar high-conductivity insulated gate bipolar transistor (MFTHC-IGBT) of the present application;

[0042] Figure 4 (a), (b), (c), and (d) are potential distribution diagrams of Trench IGBT, HC-IGBT, Advanced Trench HiGT, and MFTHC-IGBT, respectively;

[0043] Figure 5 (a), (b), (c), and (d) are electric field distribution diagrams of Trench IGBT, HC-IGBT, Advanced Trench HiGT, and MFTHC-IGBT, respectively;

[0044] Figure 6Tangential plot of maximum electric field at the bottom of the gate trench for (a) HC-IGBT, (b) Advanced Trench HiGT, (c) MFTHC-IGBT;

[0045] Figure 7 Saturated current plot for (a) Trench IGBT, (b) HC-IGBT, (c) Advanced Trench HiGT, and (d) MFTHC-IGBT;

[0046] Figure 8 VCE-IC output characteristic plot for (a) Trench IGBT, (b) HC-IGBT, (c) Advanced Trench HiGT, and (d) MFTHC-IGBT;

[0047] Figure 9 Switching characteristic plot for HC-IGBT;

[0048] Figure 10 Switching characteristic plot for Advanced Trench HiGT;

[0049] Figure 11 Switching characteristic plot for MFTHC-IGBT;

[0050] Reference numerals: 101, emitter terminal; 102, N+ emitter region; 103, P+ region; 104, base region; 105, gate trench; 106, electrically floating P-type region; 107, deep trench insulating pillar; 108, trench gate; 109, insulating pillar trench; 200, collector terminal; 300, buffer region; 400, drift region; 500, mask. DETAILED DESCRIPTION

[0051] Embodiments of the present application are described below in detail, examples of which are shown in the accompanying drawings. Figures 1-11

[0052] In the description of the present specification, the description of the terms "certain embodiments", "one embodiment", "some embodiments", "illustrative embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily mean the same embodiment or example. Also, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0053] A multiple deep trench insulating pillar high conductivity insulated gate bipolar transistor, such as​Figure 1 As shown, it comprises an emitter end 101 and a collector end 200, between which a buffer region 300 (N+ Buffer) and a drift region 400 (N- Drift Region) are arranged. The emitter end 101 comprises a main unit and auxiliary units on both sides of the main unit.

[0054] As shown, the main unit comprises an emitter region, a base region 104 and an insulating layer, and a trench gate 108 on both sides of the base region 104. The emitter region comprises N+ emitter regions 102 on both sides of the top of the base region 104, and a P+ region 103 between the two N+ emitter regions 102. Figure 1 The auxiliary units comprise a floating potential P-type region 106 and a plurality of deep trench insulating columns 107 therein. The deep trench insulating columns 107 are filled with insulating material, and the floating potential P-type region 106 is formed by doping P- ions on the sidewalls and bottom of the insulating column trench 109. The depth of the floating potential P-type region 106 is greater than the depth of the gate trench 105.

[0055] The deep trench insulating columns 107 are configured as independent insulating columns separated by trenches. In the embodiments of the present application, the number of deep trench insulating columns 107 is 1-20 (two on each side as shown in the figure), and the spacing between the two adjacent deep trench insulating columns 107 on the same side can be the same or different according to the specific structural design, and is preferably arranged at equal intervals.

[0056] Figure 1 The insulating material filling the deep trench insulating columns 107 includes oxides and nitrides, wherein the oxides include but are not limited to silicon dioxide, aluminum oxide, hafnium oxide or silicon oxynitride, and the nitrides include silicon nitride, aluminum nitride or boron nitride.

[0057] In order to prepare the multiple deep trench insulating column high-conductivity insulated gate bipolar transistor based on the deep trench insulating column 107 structure as described above, the present application discloses a method for manufacturing an insulated gate bipolar transistor based on the deep trench insulating column 107 structure, and the specific process can be combined with the method for manufacturing an insulated gate bipolar transistor as shown in the figure.

[0058] First, the N-type doped substrate, i.e. the wafer, is ground to a set thickness according to the required thickness of the rated withstand voltage. Then, a trench of a specific depth is manufactured through a photoetching and etching process, Figure 3

[0059] First, the N-type doped substrate, i.e. the wafer, is ground to a set thickness according to the required thickness of the rated withstand voltage. Then, a trench of a specific depth is manufactured through a photoetching and etching process, Figure 3 ​​The middle top shaded area is a mask 500, and oxide and N-type doped polysilicon are sequentially deposited to form a trench gate 108. Subsequently, the base region 104 and N+emitter region 102 in ohmic contact with the emitter electrode are formed by photolithography and ion implantation. Then, a specific depth of multiple trench is formed at a specific location of the auxiliary cell by photolithography and etching process. After etching the trench, P-type ion implantation is performed through the sidewall to form a potential floating P-type region 106, and then the trench is filled with insulating material to form a deep trench insulating column 107. The surface of the emitter terminal 101 is polished to a certain smoothness by polishing process, and an insulating layer is deposited. Then, a connection hole is formed in the emitter terminal 101 by photolithography and etching process, and P+region 103 is formed by photolithography and ion implantation, and finally the emitter electrode is formed by metal evaporation. Then, N-type doped polysilicon is deposited on the back of the substrate to form a buffer region 300, and finally P-type polysilicon is deposited to form a P+collector terminal 200, and metal is deposited on the collector terminal 200 as a collector electrode.

[0060] The above manufacturing method steps are summarized as follows:

[0061] S1, define a trench on the substrate by photolithography, and etch it to the required depth;

[0062] S2, sequentially deposit oxide and N-type doped polysilicon and etch back to form a trench gate 108;

[0063] S3, form the base region 104 by photolithography and ion implantation;

[0064] S4, form N+emitter region 102 in ohmic contact with the emitter electrode by photolithography and ion implantation;

[0065] S5, a specific depth of multiple insulating column trench 109 is formed at a specific location of the auxiliary cell by photolithography and etching process;

[0066] S6, P-type ion implantation is performed through the sidewall of the trench to form a potential floating P-type region 106;

[0067] S7, fill the trench with insulating material to form a deep trench insulating column 107, and polish the surface of the emitter terminal 101 to a certain smoothness by polishing process;

[0068] S8, deposit an insulating layer and define a contact hole for the emitter terminal 101 by photolithography;

[0069] S9, form P+region 103 by photolithography and ion implantation;

[0070] S10, form a buffer region 300 by ion implantation at the bottom of the substrate;

[0071] S11, form a P+collector terminal 200 by ion implantation at the bottom of the substrate;

[0072] S13, depositing metal as the emitter electrode on the emitter end 101;

[0073] S14, depositing metal as the collector electrode on the collector end 200.

[0074] It should be noted that the above-mentioned step sequence is only a preferred implementation sequence, which can be adjusted as needed in actual application.

[0075] In combination Figure 1 and Figure 2a , Figure 2b , Figure 2c as shown in Figure 2a the traditional trench insulated gate bipolar transistor-Trench IGBT, Figure 2b high conductivity insulated gate bipolar transistor-HC-IGBT, Figure 2c advanced trench process high conductivity insulated gate bipolar transistor-Advanced Trench HiGT, Figure 1 the structure diagram of the multiple deep trench insulated column high conductivity insulated gate bipolar transistor-MFTHC-IGBT proposed in the present application.

[0076] First, compare the electrical characteristics of the multiple deep trench insulated column high conductivity insulated gate bipolar transistor (MFTHC-IGBT) with the high conductivity trench insulated gate bipolar transistor (HC-IGBT) and the advanced trench process high conductivity insulated gate bipolar transistor (Advanced Trench HiGT). The carrier concentration and thickness corresponding to a 650V IGBT are simulated and calculated. In the simulation calculation, the loaded voltage is the breakdown voltage value of the transistor, and the potential distribution in the transistor is calculated, and the results are shown in Figure 4 (a), (b), (c), (d) of FIG. 8, it can be seen that the use of multiple deep trench insulated column 107 can extend the zero potential area outside the gate downward. Correspondingly, the potential distribution of the multiple deep trench insulated column high conductivity insulated gate bipolar transistor proposed in the present application extends in a parallel manner. The amount of potential change will be reflected in the electric field, and the area with greater potential line density will have greater electric field strength. As shown in Figure 5 (a), (b), (c), (d) of FIG. 8, the potential floating P-type region structure containing multiple deep trench insulated column 107 can reduce the electric field strength at the edge of the gate, reduce the probability of avalanche breakdown, and improve the voltage withstand characteristics of the transistor.

[0077] The maximum transverse and vertical electric field tangents of the high conductivity trench insulated gate bipolar transistor, the advanced trench process high conductivity insulated gate bipolar transistor, and the multiple deep trench insulated column high conductivity insulated gate bipolar transistor are shown in Figure 6 .

[0078] The saturation current of conventional insulated-gate bipolar transistors (IGBTs), high-conductivity IGBTs, advanced trench process high-conductivity IGBTs, and multi-deep trench insulated-pillar high-conductivity IGBTs varies with voltage as follows: Figure 7 As shown, the saturation current of the latter three transistors is lower than that of traditional transistors, indicating a reduction in their on-state power consumption. Furthermore, the introduction of a potential-floating P-type region 106 extends the zero-potential region outside the trench gate 108 downwards, reducing the electric field strength at the gate edge and increasing the breakdown voltage to 730V. In contrast, the breakdown voltages of the Advanced Trench HiGT, HC-IGBT, and Trench IGBT insulated-gate bipolar transistors under the same conditions are 700V, 680V, ​​and 670V, respectively. This demonstrates that the introduction of the potential-floating P-type region 106 improves the device's breakdown resistance.

[0079] The VCE-IC output characteristics of Trench IGBT, HC-IGBT, Advanced Trench HiGT, and MFTHC-IGBT are as follows: Figure 8 As shown. The introduction of the potential-floating P-type region 106 alters the hole orientation, forcing it to bypass the region. This causes holes to accumulate below the gate trench, effectively increasing the device's conductivity and reducing the component's VCEsat.

[0080] The structure and manufacturing process of the potential-floating P-type region 106, comprising multiple deep trench insulating pillars 107, invented in this patent effectively reduces manufacturing difficulty and increases process feasibility while retaining this advantage. The turn-off characteristics of HC-IGBT, Advanced Trench HiGT, and MFTHC-IGBT are as follows: Figure 9 and Figure 10 As shown, the design of separating the floating potential P-type region 106 from the main structure region can maintain the high conductivity of the IGBT while changing the hole flow direction to reduce excessive charge carriers at the emitter 101. This can result in a larger slope of current drop during turn-off, thereby reducing the switching time and significantly reducing the switching losses of the component.

[0081] The simulation results above demonstrate that adjusting the potential-floating P-type region 106 can improve the device's turn-off time and power loss during turn-off. Finally, we compare the turn-off time of the Advanced Trench HiGT and MFTHC-IGBT by reducing the device gate voltage (VG) from 15V to -15V to transition the transistor from the on-state to the off-state, and observing the time required for the device current to drop to zero. The results are as follows... Figure 10 and Figure 11As shown, the multiple deep trench insulated pillar high conductivity insulated gate bipolar transistor has lower switching loss.

[0082] The following table is experimental data of different structural designs:

[0083]

[0084] Although the embodiments of the present application have been shown and described above, it should be understood by those having ordinary skill in the art that the above embodiments are exemplary and are not to be construed as limiting the present application, and those having ordinary skill in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present application.

Claims

1. A multiple deep trench insulated pillar high conductivity insulated gate bipolar transistor comprising an emitter terminal (101) and a collector terminal (200), characterized in that, The emitter (101) comprises a main unit and auxiliary units on both sides of the main unit, wherein, The main unit comprises an emitting region, a base region (104), and an insulating layer, and the base region (104) is flanked by a groove gate (108); The auxiliary unit comprises a P-type region (106) with a floating potential and a plurality of deep-groove insulating columns (107) therein; The P-type region (106) with a floating potential is formed by P-ion doping on the sidewalls and bottom of an insulating column groove (109), and the deep-groove insulating columns (107) are filled with insulating material; The emitting region comprises N+ emitter regions (102) on both sides of the top of the base region (104), and a P+ region (103) between the two N+ emitter regions (102).

2. The multiple deep trench isolated pillar high conductivity IGBT of claim 1, wherein, The depth of the P-type region (106) with a floating potential is greater than the depth of the gate groove (105).

3. The multiple deep trench isolated pillar high conductivity IGBT of claim 1, wherein, The plurality of deep-groove insulating columns are configured as independent deep-groove insulating columns (107) separated by grooves.

4. The multiple deep trench isolated pillar high conductivity IGBT of claim 1, wherein, The number of the deep-groove insulating columns (107) is 1-20; The spacing between two adjacent deep-groove insulating columns (107) on the same side is set to be the same or different according to specific structural design.

5. The multiple deep trench isolated pillar high conductivity IGBT of claim 1, wherein, The insulating material comprises an oxide and a nitride.

6. The multiple deep trench isolated pillar high conductivity IGBT of claim 5, wherein, The oxide comprises silicon dioxide, aluminum oxide, hafnium oxide, or silicon oxynitride; The nitride comprises silicon nitride, aluminum nitride, or boron nitride.

7. A process for manufacturing a multiple deep trench pillar high conductivity IGBT, for manufacturing a multiple deep trench pillar high conductivity IGBT according to any one of claims 1 to 6, characterized in that, The method comprises: Grinding the substrate to a set thickness according to the required thickness of the rated withstand voltage; Defining a groove on the substrate by photolithography and etching it to the required depth; Sequentially forming an oxide and depositing N-type doped polysilicon and etching back to form a groove gate (108); Fabricating a base region (104) by photolithography and ion implantation; Forming an N+ emitter region (102) for an emitter electrode ohmic contact by photolithography and ion implantation; Using a photolithography and etching process to fabricate a plurality of insulating column grooves (109) of a set depth at a set position of the auxiliary unit; Forming a P-type region (106) with a floating potential by P-type ion implantation through the sidewalls of the insulating column grooves (109); Forming deep-groove insulating columns (107) by backfilling insulating material in the grooves, and polishing the surface of the emitter (101) to a set smoothness by a polishing process; Depositing an insulating layer and defining an emitter terminal contact hole by photolithography; Forming a P+ region (103) by photolithography and ion implantation; Ion implantation at the bottom of the substrate to form a buffer region (300); Ion implantation at the bottom of the substrate to form a P+ collector terminal (200); Depositing metal on the emitter terminal (101) as an emitter electrode; Depositing metal on the collector terminal (200) as a collector electrode.

8. The multiple deep trench isolation pillar high conductivity IGBT process of claim 7, wherein, After backfilling insulating material to form deep-groove insulating columns (107), the method further comprises polishing the surface of the emitter terminal (101) to a set smoothness by a polishing process, and then depositing the insulating material.

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