Semiconductor device

Abstract

The application relates to a semiconductor device. The semiconductor device comprises: a semiconductor material layer; a gate trench and a gate structure, the gate trench extending from a top surface of the semiconductor material layer into the semiconductor material layer; the gate structure being located in the gate trench; a source region, the source region being located between adjacent gate trenches; the source region comprising a well region and a source contact region located above the well region; a punch-through prevention structure, the punch-through prevention structure being located in the well region, and a doping concentration of the punch-through prevention structure being greater than a doping concentration of the well region; a first electric field shielding structure, the first electric field shielding structure being located between adjacent gate trenches; wherein a depth of the first electric field shielding structure is greater than a depth of the gate trench. By arranging the punch-through prevention structure and the first electric field shielding structure with a greater doping concentration, the device can significantly improve the ability to withstand blocking voltage in the case of a short channel, improve the gate oxide reliability, and thus improve the stability and reliability of the device in long-term operation.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device. BACKGROUND

[0002] With the development of semiconductor technology, the performance of traditional silicon-based semiconductor devices has gradually approached the physical limit of the material, while the devices made of the third-generation semiconductor materials represented by silicon carbide have excellent working capabilities such as high frequency, high voltage, high temperature resistance, and radiation resistance, which can realize higher power density and higher efficiency. As a representative of silicon carbide (SiC) switching devices, Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) devices have the advantages of low switching loss, high working frequency, easy driving, and suitability for parallel use, and have been gradually popularized and used in electric vehicles, charging piles, new energy power generation, industrial control, flexible DC power transmission and other application scenarios.

[0003] At present, MOSFET devices can mainly be divided into two structures, planar gate MOSFET structure and trench gate MOSFET structure. Compared with the planar gate MOSFET structure, the trench gate MOSFET structure has higher channel mobility and smaller cell size, thereby reducing the specific on-resistance of the device and improving the on-current density and on-state performance of the device. However, with the reduction of the channel length, the trench gate MOSFET structure faces the short channel (0.3-0.5 μm) effect, which may cause premature punch-through when the device is in the blocking state, significantly affecting the blocking characteristics and threshold stability of the device. In addition, the trench gate MOSFET structure also faces the problem of gate oxide reliability. When the device is in the blocking state, the gate trench bottom is exposed to the high electric field region in the silicon carbide drift region. At this time, the gate oxide layer at the bottom of the gate trench bears high electric field intensity, which is easy to cause insulation performance degradation, reducing the stability and life of the device in long-term operation. SUMMARY

[0004] Therefore, it is necessary to provide a semiconductor device in view of the short channel effect and the problem of gate oxide reliability of the trench gate MOSFET structure.

[0005] A semiconductor device includes: a semiconductor material layer; gate trenches and gate structures, the gate trenches extending from the top surface of the semiconductor material layer into the semiconductor material layer, the gate trenches extending along a first direction and spaced apart along a second direction; wherein the first direction is perpendicular to the second direction; the gate structures are located in the gate trenches; source regions located between adjacent gate trenches, the source regions including a plurality of first sub-regions spaced apart along the first direction; the source regions including a well region and a source contact region located above the well region; a punch-through structure located in the well region, and the doping concentration of the punch-through structure is greater than the doping concentration of the well region; a first electric field shielding structure located between adjacent gate trenches and spaced apart between adjacent first sub-regions along the first direction; wherein the depth of the first electric field shielding structure in the semiconductor material layer is greater than the depth of the gate trenches in the semiconductor material layer.

[0006] In one embodiment, along the second direction, the distance between the anti-penetration structure and the adjacent gate trench is equal. This optimizes the electric field distribution, further enhancing the device's ability to withstand blocking voltages in short-channel conditions, reducing short-channel effects, and improving device uniformity and reliability.

[0007] In one embodiment, along the second direction, the ratio of the width of the anti-penetration structure to the width of the well region is 1:3 to 3:4. By setting the anti-penetration structure to have a smaller width, the doping concentration of the channel region can be maintained, thereby preventing premature device punch-through while ensuring a lower specific on-resistance and significantly improving the device's blocking voltage. In this way, the on-resistance of the device can be reduced while ensuring the protective effect of the first electric field shielding structure on the gate oxide layer.

[0008] In one embodiment, along the first direction, the spacing between two adjacent first electric field shielding structures is inversely proportional to the depth of the gate trench in the semiconductor material layer and directly proportional to the depth of the first electric field shielding structure in the semiconductor material layer. This allows for the reduction of the device's on-resistance while ensuring the protective effect of the first electric field shielding structure on the gate oxide layer.

[0009] In one embodiment, the source region further includes a plurality of second sub-regions located between the gate trench and the first electric field shielding structure, and the second sub-regions connect two first sub-regions spaced apart along the first direction. This further increases the channel occupancy and reduces the specific on-resistance of the device.

[0010] In one embodiment, the semiconductor device further includes a second electric field shielding structure located at the bottom of the gate structure, wherein the doping concentration of the second electric field shielding structure is the same as that of the first electric field shielding structure. By providing the second electric field shielding structure, a low specific on-resistance is achieved while further reducing the maximum electric field in the gate oxide layer, improving gate oxide reliability, and enhancing the long-term stability and reliability of the device.

[0011] In one embodiment, the depth of the second electric field shielding structure in the semiconductor material layer is greater than or equal to the depth of the first electric field shielding structure in the semiconductor material layer. This can simultaneously achieve the effects of low specific on-resistance, high breakdown voltage, and reduced gate oxide electric field strength.

[0012] In one embodiment, along the first direction, the ratio of the length of the first electric field shielding structure to the length of the second electric field shielding structure is 1:1 to 3:4. Thus, by increasing the length of the second electric field shielding structure, the bottom area of ​​the second electric field shielding structure can be increased, which in turn increases the body area and PN junction area of ​​the device's body diode. This is beneficial for improving the conduction performance of the device's body diode and its resistance to surge, avalanche, and short-circuit current impacts.

[0013] In one embodiment, the ratio of the depth of the source region in the semiconductor material layer to the depth of the gate trench in the semiconductor material layer is 3:4 to 9:10. Increasing the depth of the source region expands the depth of the well region, which in turn can adjust the increase of the specific on-resistance of the device, improve the lower threshold voltage due to the short-channel effect, and reduce the off-state leakage current.

[0014] In one embodiment, the semiconductor material layer includes a substrate, an epitaxial layer, and a current spreading layer stacked sequentially, wherein the depths of the first electric field shielding structure and the second electric field shielding structure within the current spreading layer are less than the thickness of the current spreading layer. Fusing a current spreading layer on the epitaxial layer can optimize the current distribution in the device, reduce on-resistance, and improve device reliability.

[0015] The aforementioned semiconductor device, on the one hand, by setting a punch-through prevention structure with a large doping concentration in the well region of the source region, avoids premature punch-through of the device, which can significantly improve the blocking voltage of the device and significantly enhance the device's ability to withstand the blocking voltage under short-channel conditions; on the other hand, by setting a first electric field shielding structure between adjacent gate trenches, the electric field strength in the gate oxide layer during blocking can be reduced, protecting the gate oxide layer in the gate structure, improving gate oxide reliability, and thus improving the stability and reliability of the device during long-term operation. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic cross-sectional structure diagram of a semiconductor device provided for related technologies;

[0018] Figure 2 A cross-sectional structural schematic diagram of another semiconductor device provided for related technologies;

[0019] Figure 3 This is a top view of a semiconductor device provided in an embodiment of this application;

[0020] Figure 4 for Figure 3 The three-dimensional structure diagram of the semiconductor device shown in the dashed box A;

[0021] Figure 5 for Figure 4 The diagram shows the three-dimensional structure of the semiconductor device after rotation.

[0022] Figure 6 for Figure 4 A schematic diagram of the cross-sectional structure of the semiconductor device shown;

[0023] Figure 7 A three-dimensional structural diagram of a semiconductor device provided in an embodiment of this application;

[0024] Figure 8 A top view of another semiconductor device provided in an embodiment of this application;

[0025] Figure 9 for Figure 8 The three-dimensional structure diagram of the semiconductor device shown in the dashed box B;

[0026] Figure 10 for Figure 9 A schematic diagram of the cross-sectional structure of the semiconductor device shown;

[0027] Figure 11 A three-dimensional structural diagram of another semiconductor device provided in the embodiments of this application;

[0028] Figure 12 for Figure 11 A top view of the semiconductor device shown.

[0029] Figure 13 for Figure 11A schematic diagram of the cross-sectional structure of the semiconductor device shown;

[0030] Figure 14 A cross-sectional structural diagram of a semiconductor device provided in an embodiment of this application;

[0031] Figure 15 A cross-sectional view of the conduction current distribution of a semiconductor device provided in an embodiment of this application;

[0032] Figure 16 for Figure 2 The diagram shows a cross-sectional view of the conduction current distribution of the semiconductor device.

[0033] Figure 17 A comparison chart of the output characteristic curves of drain current density and drain voltage of semiconductor devices provided in related technologies and embodiments of this application;

[0034] Figure 18 A comparison of the output characteristic curves of drain current density versus drain voltage for semiconductor devices with different cell parameters provided in the embodiments of this application;

[0035] Figure 19 A comparison of the transfer characteristic curves of drain current versus gate voltage for semiconductor devices with different doping concentrations of the punch-through structure provided in the embodiments of this application;

[0036] Figure 20 This is a schematic flowchart illustrating the method for fabricating a semiconductor device provided in an embodiment of this application.

[0037] In the figure: 10, semiconductor material layer; 11, substrate; 12, epitaxial layer; 13, current spreading layer; 14, first electric field shielding structure; 15, second electric field shielding structure; 16, anti-penetration structure; 21, first shielding structure; 22, second shielding structure; 30, gate structure; 31, gate oxide layer; 32, gate electrode; 40, source region; 401, first sub-region; 402, second sub-region; 41, well region; 42, source contact region; 50, channel region; 61, source electrode; 62, drain electrode. Detailed Implementation

[0038] To facilitate understanding of the present invention, it will be described in more detail below. However, it should be understood that the present invention can be implemented in many different forms and is not limited to the embodiments or examples described herein. Rather, these embodiments or examples are provided to make the disclosure of the present invention more thorough and complete.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments or examples only and is not intended to limit the invention. The optional scope of the term "and / or" as used herein includes any one of two or more of the related listed items, as well as any and all combinations of the related listed items, including any two related listed items, any more related listed items, or a combination of all related listed items.

[0040] In this invention, numerical ranges are involved. Unless otherwise specified, the numerical ranges are considered continuous and include the minimum and maximum values ​​of the range, as well as every value between the minimum and maximum values. Furthermore, when the range refers to integers, it includes every integer between the minimum and maximum values ​​of the range. Additionally, when multiple ranges are provided to describe features or characteristics, the ranges may be merged. In other words, unless otherwise specified, all ranges disclosed herein should be understood to include any and all subranges to which they are included.

[0041] Currently, SiC MOSFET devices offer lower conduction losses and faster switching frequencies compared to traditional silicon-based insulated-gate bipolar transistors (Si IGBTs), thus improving system efficiency. However, in the development of power electronic equipment technology, while pursuing efficiency and power density, system stability and reliability are crucial considerations. The reliability of SiC MOSFET devices is a key factor affecting their practical application in power electronic systems, and there is often a trade-off between device performance and reliability. In SiC MOSFET device design, it is necessary to simultaneously consider techniques to improve device performance and enhance reliability. The key challenge in SiC MOSFET device design is ensuring that the device meets the long-term operational stability and reliability requirements of the application system while reducing specific on-resistance and improving conduction performance.

[0042] Figure 1 A schematic cross-sectional structure diagram of a semiconductor device provided for related technologies; Figure 2 A cross-sectional structural diagram of another semiconductor device provided for related technologies.

[0043] Please refer to Figure 1 and Figure 2 , Figure 1 and Figure 2Each cell of a trench gate MOSFET device includes: a substrate 11; an epitaxial layer 12 located on the substrate 11; a gate trench T1 extending from the top surface of the epitaxial layer 12 into the epitaxial layer 12 and extending along a first direction X; a gate structure 30 including a gate oxide layer 31 covering the bottom and sidewalls of the gate trench T1 and a gate electrode 32 covering the gate oxide layer 31; a source region 40 located on both sides of the gate structure 30 and extending along the first direction X, the source region 40 including a well region 41 and a source contact region 42 located above the well region 41, the well region 41 can also be called a "base region"; and a channel region 50 located in the well region 41 and located at one end of the well region 41 near the sidewall of the gate trench T1; wherein, the depth of the gate trench T1 in the epitaxial layer 12 is greater than the depth of the source region 40 in the epitaxial layer 12.

[0044] in, Figure 1 The cell of the trench gate MOSFET device shown also includes: a first shielding structure 21, located on the side of the source region 40 away from the gate structure 30, the first shielding structure 21 and the gate trench T1 are separated by the source region 40, and the depth of the first shielding structure 21 in the epitaxial layer 12 is greater than the depth of the gate trench T1 in the epitaxial layer 12; the first shielding structure 21 and the gate structure 30 form a junction field-effect transistor (JFET) region below the source region 40; Figure 2 The cell of the trench gate MOSFET device shown also includes a second shielding structure 22, located below the gate structure 30, which partially or completely covers the bottom of the gate trench T1.

[0045] Here, the epitaxial layer 12 has a first N-type doping concentration, the source contact region 42 has a second N-type doping concentration, and the second N-type doping concentration is higher than the first N-type doping concentration; the well region 41 has a first P-type doping concentration, and the first shielding structure 21 has a second P-type doping concentration that is higher than the first P-type doping concentration.

[0046] It should be noted that, Figure 1The trench gate MOSFET device shown reduces the electric field strength of the gate oxide layer 31 at the bottom of the gate trench T1 by setting a first shielding structure 21. However, forming the pattern of the first shielding structure 21 and the gate trench T1 requires photolithographic alignment, and alignment deviations can occur, causing the first shielding structure 21 to deviate from its ideal position (the two closest gate trenches T1 are the same). If the distance from the gate trench T1 decreases, the on-resistance of the device increases, affecting its performance; if the distance from the gate trench T1 increases, the protective effect of the first shielding structure 21 on the gate oxide layer 31 decreases, leading to a decline in the long-term stability and reliability of the device. In summary, the conduction performance and reliability of the trench gate MOSFET device are affected by photolithographic alignment deviations during manufacturing, limiting the device's production yield.

[0047] It should also be noted that, Figure 2 As shown, the trench gate MOSFET device can significantly reduce the electric field strength of the gate oxide layer 31 by setting the second shielding structure 22. However, due to the presence of the second shielding structure 22 at the bottom of the gate trench T1, the conduction current needs to bypass the second shielding structure 22 after flowing down along the conductive channel instead of spreading downward along the bottom of the gate trench T1, which will lead to a significant increase in the on-resistance. Furthermore, in terms of process technology, when using non-self-aligned photolithography to form the gate trench T1 and the second shielding structure 22, the alignment deviation between the two photolithography processes will cause the second shielding structure 22 to fail to completely protect the bottom of the gate trench T1 and the two trench corners. At the same time, one side wall of the gate trench T1 is easily implanted with ions to form a P-region, thereby sacrificing the conductivity of this side channel. On the other hand, using self-aligned photolithography requires a high degree of steepness of the side wall of the gate trench T1. Due to the difficulty in controlling the etching morphology of SiC, the etched trench often has a tilt angle. When ion implantation forms the first shielding structure 21, implanted P-regions will be formed on both sides of the gate trench T1, which will cause the device to be completely unable to conduct current or to have poor conductivity.

[0048] Based on this, embodiments of this application provide a semiconductor device. Figure 3 This is a top view of a semiconductor device provided in an embodiment of this application; Figure 4 for Figure 3 The three-dimensional structure diagram of the semiconductor device shown in the dashed box A; Figure 5 for Figure 4 The diagram shows the three-dimensional structure of the semiconductor device after rotation. Figure 6 for Figure 4 The diagram shows a cross-sectional view of the semiconductor device. Please refer to it. Figure 3 to Figure 6 Semiconductor devices include:

[0049] Semiconductor material layer 10;

[0050] The gate trench T1 extends from the top surface of the semiconductor material layer 10 into the semiconductor material layer 10. The gate trench T1 extends along a first direction X and is spaced apart along a second direction Y. The first direction X is perpendicular to the second direction Y. The gate structure 30 is located in the gate trench T1.

[0051] Source region 40, located between adjacent gate trenches T1, source region 40 includes a plurality of first sub-regions 401 spaced apart along a first direction X; source region 40 includes well region 41 and source contact region 42 located above well region 41.

[0052] The anti-penetration structure 16 is located in the well region 41, and the doping concentration of the anti-penetration structure 16 is greater than the doping concentration of the well region 41.

[0053] The first electric field shielding structure 14 is located between adjacent gate trenches T1 and is spaced apart between adjacent first sub-regions 401 along the first direction X; wherein the depth of the first electric field shielding structure 14 in the semiconductor material layer 10 is greater than the depth of the gate trenches T1 in the semiconductor material layer 10.

[0054] Understandably, on the one hand, by setting a punch-through prevention structure 16 with a large doping concentration in the well region 41 of the source region 40, the blocking voltage of the device can be significantly improved, the device can be prevented from punching through prematurely, and the ability of the device to withstand the blocking voltage under short-channel conditions can be significantly improved. On the other hand, by setting a first electric field shielding structure 14 between adjacent gate trenches T1, the electric field strength in the gate oxide layer 31 during blocking can be reduced, the gate oxide layer 31 in the gate structure 30 can be protected, the gate oxide reliability can be improved, and thus the stability and reliability of the device during long-term operation can be improved.

[0055] It should be noted that in trench-gate MOSFET devices, the short-channel effect significantly impacts the device's blocking characteristics and threshold stability. As the channel length decreases, the intrusion of the drain electric field into the channel region intensifies, leading to premature punch-through under high-voltage blocking conditions. This occurs when the drain junction depletion region extends towards the source, weakening the source-drain barrier and significantly increasing the off-state leakage current. Experimental data show that leakage current can increase 3-8 times when the channel length is less than 0.5 μm. Simultaneously, the short-channel design induces a decrease in threshold voltage and a drain-induced barrier lowering (DIBL) effect. This threshold drift not only deteriorates subthreshold characteristics and increases static power dissipation but also worsens the device's stability under temperature variations. Although existing technologies can mitigate the problems through solutions such as P-shield structures, doping engineering, or high-k dielectric layers, they still face limitations such as increased on-resistance, introduction of lattice defects, and high interface state density, which in turn lead to problems such as increased leakage current, threshold voltage drift, decreased device reliability, degradation of subthreshold characteristics, and exacerbation of hot carrier effects.

[0056] In some embodiments, the semiconductor material layer 10 may include a substrate 11, an epitaxial layer 12, and a current spreading layer 13 stacked sequentially.

[0057] It should be noted that the center plane of the semiconductor material layer 10 in the thickness direction Z is defined as the plane of the semiconductor material layer 10. Two mutually perpendicular directions, a first direction X and a second direction Y, are defined in the plane direction of the semiconductor material layer 10. Here, the first direction X is the direction in which the gate trench T1 extends, and the second direction Y is the direction perpendicular to the first direction X in the plane direction of the semiconductor material layer 10.

[0058] The substrate 11 can be made of elemental semiconductor materials (e.g., silicon (Si) substrates, germanium (Ge) substrates, etc.), III-V compound semiconductor materials (e.g., silicon carbide (SiC) substrates, gallium nitride (GaN) substrates, gallium arsenide (GaAs) substrates, indium phosphide (InP) substrates, etc.), II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art. In this application, the substrate 11 is a silicon carbide substrate.

[0059] Epitaxial layer 12 is a single-crystal thin film layer deposited on the surface of substrate 11 by an epitaxial growth process, which has the same or similar crystal structure as the substrate 11 material.

[0060] The current spreading layer 13, located on the epitaxial layer 12, is typically obtained through ion implantation or high-concentration epitaxial processes. By setting the current spreading layer 13 on the epitaxial layer 12, the current distribution in the device can be optimized, the on-resistance reduced, and the device reliability improved.

[0061] In some embodiments, the semiconductor material layer 10 may have a first doping type. Specifically, the substrate 11, the epitaxial layer 12, and the current spreading layer 13 may have a first doping type. In the embodiments of this application, the substrate 11 may be an N+ type substrate, the epitaxial layer 12 may be an N- type drift region, and the current spreading layer 13 may be an N- type current spreading layer.

[0062] It should be noted that the first doping type and the second doping type described below have opposite conductivity types. The first doping type can be P-type or N-type, and the second doping type can be N-type or P-type. N-type impurity ions include phosphorus ions, arsenic ions, and antimony ions, while P-type impurity ions include boron ions, gallium ions, and indium ions. The doping types in the embodiments of this application can be changed to opposite doping types accordingly; for example, P-type doping can be changed to N-type doping while N-type doping is changed to P-type doping.

[0063] In some embodiments, please refer to Figure 4 The gate trench T1 can extend from the top surface of the current spreading layer 13 into the current spreading layer 13; and the depth of the gate trench T1 in the current spreading layer 13 is less than the thickness of the current spreading layer 13.

[0064] In some embodiments, please refer to Figure 4 The gate structure 30 may specifically include a gate oxide layer 31 covering the sidewalls and bottom of the gate trench T1, and a gate electrode 32 covering the bottom and side of the gate oxide layer 31 and filling the gate trench T1. The material of the gate oxide layer 31 may include silicon dioxide; the material of the gate electrode 32 may include polysilicon.

[0065] In some embodiments, please refer to Figure 4 The source region 40 may include a first sub-region 401. Along the first direction X, a plurality of first sub-regions 401 are discontinuous sub-regions of the source region 40, and the plurality of first sub-regions 401 are arranged alternately with a plurality of first electric field shielding structures 14; the first sub-region 401 may include a well region 41 and a source contact region 42 located on the well region 41, and may also include a channel region 50, which may be a region located inside the well region 41 near the gate oxide layer 31.

[0066] In some specific embodiments, the source contact region 42 may have a first doping type, and the well region 41 and the channel region 50 may have a second doping type. In this application, the source contact region 42 may be an N-type contact region, the well region 41 may be a P-type well region, and the channel region 50 may be a P-type channel region. The channel region 50 is the region of the dynamic conductive path formed when the device is operating; the doping concentration of the well region 41 determines the doping concentration of the channel region 50, and the depth and doping concentration can be changed by changing the ion implantation dose and energy to achieve different specific on-resistance and threshold voltage performance requirements.

[0067] In some embodiments, along the second direction Y, the anti-penetration structure 16 is spaced apart from the adjacent gate trench T1 by a well region 41. Alternatively, along the second direction Y, the anti-penetration structure 16 is spaced apart from the gate trench T1.

[0068] In some embodiments, please refer to Figure 6 Along the second direction Y, the distance between the anti-penetration structure 16 and the adjacent gate trench T1 is equal. The projection of the anti-penetration structure 16 onto the plane of the semiconductor material layer 10 can be a strip structure extending along the first direction X. Here, the anti-penetration structure 16 can also be referred to as an "early penetration protection zone", "early penetration protection structure", or "implantation protection zone".

[0069] It is understandable that the distance between the anti-penetration structure 16 and the adjacent gate trench T1 is not equal, and the electric field will be excessively concentrated in some areas, forming a non-uniform distribution. By adopting the setting method of this application, the electric field distribution can be optimized, further improving the device's ability to withstand blocking voltage under short-channel conditions, reducing short-channel effects, and improving device uniformity and reliability.

[0070] In some embodiments, the punch-through barrier structure 16 may have a second doping type; the punch-through barrier structure 16 may be a P-type punch-through barrier structure. Specifically, the punch-through barrier structure 16 can be formed by increasing the local doping concentration of the well region 41. When the punch-through barrier structure 16 is formed locally in the well region 41 by an additional ion implantation, the maximum ion implantation energy can be the same as the maximum ion implantation energy when the well region 41 is formed.

[0071] In some embodiments, please refer to Figure 6 Along the second direction Y, the ratio of the width of the anti-punch-through structure 16 to the width of the well region 41 can be 1:3 to 3:4. In this way, by setting the anti-punch-through structure 16 to have a small width, the doping concentration of the channel region 50 can be unaffected. This allows the device to avoid premature punch-through while maintaining a low specific on-resistance, thus significantly improving the device's blocking voltage.

[0072] It should be noted that if the increase in the doping concentration of the anti-penetration structure 16 affects the doping concentration of the channel region 50, it will lead to an increase in the specific on-resistance. During the fabrication of the anti-penetration structure 16, the width of the anti-penetration structure 16 along the second direction Y can be set to be relatively narrow. Considering the size linewidth of the photomask exposure window and to avoid alignment deviations in the second direction Y, a strip-shaped ion implantation window can be used to form the anti-penetration structure 16.

[0073] Figure 7 This is a three-dimensional structural diagram of a semiconductor device provided in an embodiment of this application.

[0074] In some embodiments, please refer toFigure 7 The ratio of the depth of the source region 40 in the semiconductor material layer 10 to the depth of the gate trench T1 in the semiconductor material layer 10 is 3:4 to 9:10. By limiting this ratio, the depth of the source region 40 in the semiconductor material layer 10 is increased, thereby expanding the depth of the well region 41. This allows for adjustment of the device's specific on-resistance, improving the lower threshold voltage due to the short-channel effect, and reducing the off-state leakage current.

[0075] Specifically, the thickness of the well region 41 is between 0.3 μm and 0.5 μm. It should be noted that the depth of the well region 41 in the semiconductor material layer 10 cannot be greater than the depth of the gate trench T1 in the semiconductor material layer 10, otherwise the device will not be able to conduct.

[0076] Additionally, increasing the doping concentration in well region 41 can improve the lower threshold voltage due to the short-channel effect and reduce the off-state leakage current. For example, increasing the doping concentration from 2e17cm can achieve a low specific on-resistance. -3 Increased to 4e17cm -3 .

[0077] In some embodiments, please refer to Figure 4 Along the first direction X, the spacing between two adjacent first electric field shielding structures 14 is inversely proportional to the depth of the gate trench T1 in the semiconductor material layer 10 and directly proportional to the depth of the first electric field shielding structure 14 in the semiconductor material layer 10.

[0078] It is understandable that along the first direction X, a small spacing between two adjacent first electric field shielding structures 14 will result in a larger on-resistance, while a large spacing will result in insufficient protection of the gate oxide layer 31. Therefore, the spacing between two adjacent first electric field shielding structures 14 can be determined based on the depth of the gate trench T1 and the depth of the first electric field shielding structure 14. In this way, the on-resistance of the device can be reduced while ensuring the protective effect of the first electric field shielding structure 14 on the gate oxide layer 31.

[0079] Figure 8 A top view of another semiconductor device provided in an embodiment of this application; Figure 9 for Figure 8 The three-dimensional structure diagram of the semiconductor device shown in the dashed box B; Figure 10 for Figure 9 The diagram shows a cross-sectional structure of the semiconductor device.

[0080] In some embodiments, please refer to Figure 8 to Figure 10The source region 40 further includes multiple second sub-regions 402, which are located between the gate trench T1 and the first electric field shielding structure 14, and connect two first sub-regions 401 spaced apart along the first direction X. Each second sub-region 402 may include a well region 41 and a source contact region 42 located on the well region 41. The well region 41 and source contact region 42 in the second sub-region 402 can be considered as extensions of the well region 41 and source contact region 42 of the first sub-region 401. This further increases the channel occupancy and reduces the specific on-resistance of the device.

[0081] In some embodiments, please refer to Figure 9 The first electric field shielding structure 14 extends along the second direction Y. The first electric field shielding structure 14 divides the source region 40 into multiple independent first sub-regions 401. In this way, the cell size of the device can be reduced, thereby reducing the on-resistance of the device, lowering the specific on-resistance of the device, and improving the conductivity of the device.

[0082] In some embodiments, please refer to Figure 10 The semiconductor device further includes a second electric field shielding structure 15, which is located at the bottom of the gate structure 30. The doping concentration of the second electric field shielding structure 15 is the same as that of the first electric field shielding structure 14. The first electric field shielding structure 14 can also be referred to as the "first electric field shielding region"; the second electric field shielding structure 15 can also be referred to as the "second electric field shielding region"; the first electric field shielding structure 14 and the second electric field shielding structure 15 have a second doping type.

[0083] It is understandable that by setting the second electric field shielding structure 15, the gate oxide electric field of the device can be further reduced on the basis of setting the first electric field shielding structure 14. While achieving a low specific on-resistance, the maximum electric field in the gate oxide layer 31 can be further reduced, thereby improving the gate oxide reliability problem and enhancing the stability and reliability of the device during long-term operation.

[0084] It should be noted that the second electric field shielding structure 15 can be formed by ion implantation at the bottom of the gate trench T1 after the gate trench T1 is formed, using a lower implantation energy. Typically, the highest ion implantation energy does not exceed 1500 keV, making it difficult to achieve an electric field shielding structure depth greater than 1.5 μm. However, ion implantation at the bottom of the gate trench T1 after etching can deepen the electric field shielding structure with lower energy, reducing lattice damage and further lowering the maximum electric field in the gate oxide layer 31. Compared to related technologies, the gate trench bottom implantation in this embodiment does not affect the path of current flow and diffusion along the channel region 50 to the bottom of the gate trench T1.

[0085] In some embodiments, please refer to Figure 8Along the first direction, the ratio of the length of the first electric field shielding structure 14 to the length of the second electric field shielding structure 15 is 1:1 to 3:4. Thus, by increasing the length of the second electric field shielding structure 15, the bottom area of ​​the second electric field shielding structure 15 can be increased, which in turn increases the body area and PN junction area of ​​the device's body diode. This is beneficial for improving the conduction performance of the device's body diode and its resistance to surge, avalanche, and short-circuit current impacts.

[0086] Figure 15 A cross-sectional view of the conduction current distribution of a semiconductor device provided in an embodiment of this application; Figure 16 for Figure 2 The diagram shows a cross-sectional view of the conduction current distribution of the semiconductor device.

[0087] Please refer to Figure 15 The working principle of the semiconductor device provided in this application embodiment is as follows: When the device is in the on state, a positive bias voltage is applied to the gate oxide layer 31, which induces an electron inversion layer in the well region 41. After applying a certain positive voltage between the drain electrode 62 and the source electrode 61, the current will pass through the substrate 11, the epitaxial layer 12, the current spreading layer 13, the channel region 50, and the source contact region 42 to reach the source electrode 61. The region through which the current passes during conduction is... Figure 15 The shaded area in the image. Compared to... Figure 16 The cross-sectional view of the conduction current distribution shown in the embodiment of this application shows that after the conduction current flows down along the channel region 50, it diffuses directly downward along the bottom of the gate trench T1, which can significantly reduce the conduction resistance.

[0088] In addition, when the device is in forward blocking, zero voltage is applied to the gate. As the positive voltage applied between the drain electrode 62 and the source electrode 61 increases, the electric field strength inside the device increases. Free electrons gain high energy under the acceleration of the high electric field. When the critical value is reached, a large number of electron-hole pairs are generated, resulting in a large increase in current. Avalanche breakdown occurs at the junction of the PN junction structure inside the device, namely the first electric field shielding structure 14 and the current spreading layer 13.

[0089] In some embodiments, please refer to Figure 10 The depth of the first electric field shielding structure 14 and the second electric field shielding structure 15 in the current spreading layer 13 is less than the thickness of the current spreading layer 13.

[0090] Figure 11 A three-dimensional structural diagram of another semiconductor device provided in the embodiments of this application; Figure 12 for Figure 11 A top view of the semiconductor device shown. Figure 13 for Figure 11 A schematic diagram of the cross-sectional structure of the semiconductor device shown; Figure 14This is a cross-sectional structural diagram of a semiconductor device provided in an embodiment of this application.

[0091] In some embodiments, please refer to Figure 11 to Figure 13 The depth of the first electric field shielding structure 14 in the semiconductor material layer 10 is greater than the depth of the second electric field shielding structure 15 in the semiconductor material layer 10. This further reduces the electric field strength in the gate oxide layer 31, protecting the gate oxide layer 31 and improving device reliability.

[0092] In some embodiments, please refer to Figure 14 The depth of the first electric field shielding structure 14 in the semiconductor material layer 10 is equal to the depth of the second electric field shielding structure 15 in the semiconductor material layer 10. It can be understood that by controlling the depths of the first and second electric field shielding structures 14 and 15 to be consistent, the body area and PN junction area of ​​the device's body diode can be increased. Based on the semiconductor device having a second sub-region 402, by increasing the channel ratio and reducing the specific on-resistance, the injection area at the bottom of the gate trench T1 can be adjusted and increased to achieve the purpose of protecting the gate oxide layer 31 at a lower specific on-resistance. Thus, the effects of low specific on-resistance, high breakdown voltage, and reduced electric field strength of the gate oxide layer 31 can be achieved simultaneously.

[0093] In some embodiments, Table 1 lists the key cell parameters of the device; where N epi The doping concentration of the epitaxial layer; N CSL The doping concentration of the current spreading layer (CSL doping); t CSL N represents the thickness of the current spreading layer (CSL). PPS The doping concentration of the P+ region is t. PPS L represents the thickness of the P+ region. PPS N is the length of region P+; NPS The doping concentration of the N+ region (N+ doping); L NPS W is the length of the N+ source region. NPS N + source width; t NPS The thickness of the N+ source region (N+ thickness); N PWL The doping concentration of the P-well region; t PWL W represents the thickness of the P-well region. PWPAdd the width of the impurity region to the P-well; W GT t is the width of the gate trench. GT This represents the depth of the gate trench. Here, the P+ region represents the area where the first electric field shielding structure 14 is located, the N+ region represents the area where the source contact region 42 is located, and the P-well additional impurity region represents the area where the anti-penetration structure 16 is located.

[0094] Table 1

[0095]

[0096] Figure 17 A comparison chart of the output characteristic curves of drain current density and drain voltage of semiconductor devices provided in related technologies and embodiments of this application; Figure 18 A comparison of the output characteristic curves of drain current density versus drain voltage for semiconductor devices with different cell parameters provided in the embodiments of this application; Figure 19 A comparison of the transfer characteristic curves of drain current versus gate voltage for semiconductor devices with different doping concentrations and punch-through structures provided in the embodiments of this application.

[0097] in, Figure 17 Curves 1 and 2 in the figure represent the output characteristic curves of semiconductor devices without and with the anti-penetration structure 16, respectively. Figure 17 As can be seen, by setting the anti-penetration structure 16 in this embodiment, the blocking voltage of the device can be greatly improved.

[0098] Combined with reference Table 1 and Figure 18 In this embodiment of the application, W NPS The value range is >0.7μm, specifically, W NPS The value range can be 0.8μm to 1.4μm; this is because when W NPS When the value of W is less than 0.7 μm, the ion implantation of the anti-penetration structure 16 will affect the doping concentration of the channel region 50, increasing the specific on-resistance. NPS As the value gradually increases, the width of the through-protection region can be appropriately increased, which can improve the blocking voltage of the device while ensuring that the resistance is smaller than the on-resistance.

[0099] In this embodiment of the application, L NPS The value range is <1.1μm, W NPSThe value range can be 0.7μm to 1.1μm. This is because when L... NPS When the value is greater than 1.1 μm, the distance between the first electric field shielding structures 14 increases, which leads to an increase in the maximum electric field in the gate oxide layer 31.

[0100] In addition, in the embodiments of this application, L PPS The value range can be 0.5μm to 1.0μm, because when L PPS When the value of is less than 0.5μm, the device can have a lower specific on-resistance, but the blocking voltage will be reduced due to the decrease in the area of ​​the PN junction inside the device.

[0101] In this embodiment of the application, by Figure 19 It can be seen that by appropriately increasing the channel length L channel and N PWL The value of can improve the lower threshold voltage V caused by the short-channel effect. th This improves the short-channel effect.

[0102] In some embodiments, the semiconductor device further includes a source electrode 61 and a drain electrode 62; the source electrode 61 covers the upper surface of the source contact region 42 of the source region 40 and the upper surface of the first electric field shielding structure 14; the leakage current is located on the bottom surface of the semiconductor material layer 10.

[0103] In some specific embodiments, when a positive voltage is applied between the source electrode 61 and the drain electrode 62, the sub-regions (first sub-region 401 and second sub-region 402) of each source region 40 form a channel region 50 adjacent to the sidewall of the gate trench T1. After the current flows in from the well region 41, it flows down along the sidewall of the gate trench T1 in the channel region 50, and through the part of the bottom of the gate trench T1 that is not covered by the second electric field shielding structure 15 to the area of ​​the current extension layer 13 without electric field shielding, and then flows out from the drain electrode 62.

[0104] Based on this, embodiments of this application also provide a method for fabricating a semiconductor device. Figure 20 A schematic flowchart of a method for fabricating a semiconductor device provided in this application embodiment is shown in the figure. The method for fabricating a semiconductor device includes:

[0105] Step S101: Provide a semiconductor material layer having a first doping type;

[0106] Step S102: A well region is formed in the semiconductor material layer, the well region having a second doping type;

[0107] Step S103: A punch-through barrier structure is formed in the well region. The punch-through barrier structure has a second doping type and the doping concentration of the punch-through barrier structure is greater than the doping concentration of the well region.

[0108] Step S104: A source contact region is formed above the well region; the source contact region and the well region are defined as a source region, and the source region includes a plurality of first sub-regions spaced apart along a first direction; the plurality of source regions are arranged spaced apart along a second direction; wherein, the first direction is perpendicular to the second direction.

[0109] Step S105: A first electric field shielding structure is formed in the semiconductor material layer. The first electric field shielding structure is disposed at intervals between adjacent first sub-regions along a first direction. The depth of the first electric field shielding structure in the semiconductor material layer is greater than the depth of the source region in the semiconductor material layer.

[0110] Step S106: A gate trench is formed in the semiconductor material layer; the gate trench extends from the top surface of the semiconductor material layer into the semiconductor material layer, the gate trench extends along the first direction, is located between two adjacent source regions, and is located between adjacent first electric field shielding structures; wherein, the depth of the gate trench in the semiconductor material layer is less than the depth of the first electric field shielding structure in the semiconductor material layer.

[0111] Step S107: Form a gate structure located in a gate trench.

[0112] In some embodiments, before forming the gate structure, the method for fabricating the semiconductor device further includes forming a second electric field shielding structure, the second electric field shielding structure being located at the bottom of the gate structure, and the doping concentration of the second electric field shielding structure being the same as the doping concentration of the first electric field shielding structure.

[0113] It is understandable that, through the above-mentioned semiconductor device fabrication method, on the one hand, compared to Figure 1 The related technologies shown can avoid the problem of alignment deviations in photolithography during the fabrication of the first shielding structure and the gate trench, which would cause the first shielding structure to deviate from its ideal position. On the other hand, they improve the insufficient protection of the gate oxide corners of the gate trench caused by alignment deviations in non-self-aligned photolithography processes, the increase in the gate oxide electric field caused by the expansion of the lateral distance of the JFET region, and the increase in resistance caused by the reduction of the lateral distance of the JFET region. Furthermore, the second electric field shielding structure injected perpendicular to the bottom of the gate trench also reduces the requirement for the steepness of the gate trench sidewalls when using self-aligned photolithography processes. The injection at the bottom of the gate trench has virtually no impact on the lateral length of the channel region. Compared with related technologies, the injection at the bottom of the gate trench in this embodiment does not affect the path of current flow and diffusion along the channel to the bottom of the gate trench.

[0114] It should also be understood that although the steps in the above flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Moreover, at least some of the steps in the above flowchart may include multiple steps or stages, and these steps or stages are not necessarily completed at the same time, nor are they necessarily performed sequentially.

[0115] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0116] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: Semiconductor material layer; A gate trench and a gate structure, wherein the gate trench extends from the top surface of the semiconductor material layer into the semiconductor material layer, the gate trench extends along a first direction and is spaced apart along a second direction; wherein the first direction is perpendicular to the second direction; and the gate structure is located in the gate trench. The source region is located between adjacent gate trenches, and includes a plurality of first sub-regions spaced apart along the first direction; the source region also includes a plurality of second sub-regions, the second sub-regions connecting two first sub-regions spaced apart along the first direction; the source region includes a well region and a source contact region located above the well region; A punch-through barrier structure is located in the well region, and the doping concentration of the punch-through barrier structure is greater than the doping concentration of the well region; A first electric field shielding structure is located between adjacent gate trenches and is spaced apart between adjacent first sub-regions along the first direction; second sub-regions are provided on both sides of the first electric field shielding structure along the second direction, and the second sub-regions are located between the gate trenches and the first electric field shielding structure; wherein, the depth of the first electric field shielding structure in the semiconductor material layer is greater than the depth of the gate trenches in the semiconductor material layer.

2. The semiconductor device according to claim 1, characterized in that, Along the second direction, the distance between the anti-penetration structure and the adjacent gate trench is equal.

3. The semiconductor device according to claim 2, characterized in that, Along the second direction, the ratio of the width of the anti-penetration structure to the width of the trap area is 1:3 to 3:

4.

4. The semiconductor device according to claim 1, characterized in that, Along the first direction, the spacing between two adjacent first electric field shielding structures is inversely proportional to the depth of the gate trench in the semiconductor material layer and directly proportional to the depth of the first electric field shielding structure in the semiconductor material layer.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, The semiconductor device further includes: A second electric field shielding structure is located at the bottom of the gate structure, and the doping concentration of the second electric field shielding structure is the same as that of the first electric field shielding structure.

6. The semiconductor device according to claim 5, characterized in that, The depth of the second electric field shielding structure in the semiconductor material layer is greater than or equal to the depth of the first electric field shielding structure in the semiconductor material layer.

7. The semiconductor device according to claim 5, characterized in that, Along the first direction, the ratio of the length of the first electric field shielding structure to the length of the second electric field shielding structure is 1:1 to 3:

4.

8. The semiconductor device according to claim 1, characterized in that, The ratio of the depth of the source region in the semiconductor material layer to the depth of the gate trench in the semiconductor material layer is 3:4 to 9:

10.

9. The semiconductor device according to claim 5, characterized in that, The semiconductor material layer includes a substrate, an epitaxial layer, and a current spreading layer stacked sequentially, wherein the depths of the first electric field shielding structure and the second electric field shielding structure in the current spreading layer are less than the thickness of the current spreading layer.

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