Techniques for generating new output value for inclusion within sequence of output values output in given representation

Abstract

An apparatus and method are provided for generating a new output value for inclusion within a sequence of output values output in a given representation. An input interface receives a target value, and a modification circuit determines a new output value in the sequence from a current output value in the sequence according to the target value such that the new output value satisfies the determined condition. The determined conditions simultaneously require that when the new output value and the current output value are expressed in a given representation, the new output value has a Hamming distance of 1 with respect to the current output value and the new output value lies between the current output value and the target value. The modification circuit is arranged to select, as a new output value, a possible new output value closest to the target value from among at least two possible new output values when there are the at least two possible new output values satisfying the determined condition.

Description

BACKGROUND

[0001] The present technology relates to generating a sequence of output values outputting in a given representation, and in particular to generating a new output value from a received target value to include in the sequence.

[0002] Such technology can be used in various situations, for example when generating a sequence of output values that seeks to follow changes in a corresponding sequence of received target values. By appropriately selecting the given representation, this can ensure that a receiving device more reliably detects changes in the output values in the sequence compared to situations where those receiving devices are configured to directly receive the corresponding sequence of target values and seek to detect changes in the target values. For example, the given representation can be selected such that when a default change in value occurs between a given output value and a next output value in the sequence, the given output value and the next output value will have a Hamming distance of 1 when expressed in the given representation. This can facilitate the receiving device reliably detecting a transition from the given output value to the next output value, even if the receiving device is operating asynchronously with the device sending the output values.

[0003] However, successive target values in the sequence can change by different amounts, and in particular will not always change by a default amount (e.g. a minimum adjustment amount). For example, the amount by which successive values of the target values change can depend on a clock frequency at which the circuit generating the target values is operating, and this clock frequency itself can vary over time. It is therefore desirable to be able to accommodate arbitrary changes in the target values, whilst still producing a corresponding sequence of output values that seeks to follow changes in the corresponding sequence of received target values, and whilst still ensuring that the sequence of output values can be reliably detected. SUMMARY

[0004] In a first example arrangement, there is provided an apparatus comprising: an output circuit arranged to output a sequence of output values in a given representation; an input interface for receiving a target value; and a modification circuit for determining a new output value in the sequence from a current output value in the sequence in dependence on the target value, such that the new output value satisfies a determined condition, wherein the determined condition simultaneously requires that: the new output value has a Hamming distance of 1 relative to the current output value when the new output value and the current output value are expressed in the given representation, and the new output value lies between the current output value and the target value; wherein the modification circuit is arranged to, when there are at least two possible new output values that satisfy the determined condition, select as the new output value the possible new output value that is closest to the target value from the at least two possible new output values.

[0005] In another example arrangement, there is provided a method of generating a new output value for inclusion within a sequence of output values outputting in a given representation, the method comprising: receiving a target value; employing a modification circuit to determine the new output value in the sequence from a current output value in the sequence in dependence on the target value such that the new output value satisfies a determined condition, wherein the determined condition simultaneously requires that: when the new output value and the current output value are expressed in the given representation, the new output value has a Hamming distance of 1 with respect to the current output value, and the new output value lies between the current output value and the target value; and in the event that there are at least two possible new output values that satisfy the determined condition, selecting as the new output value the possible new output value that is closest to the target value from among the at least two possible new output values.

[0006] In yet another example arrangement, there is provided a computer readable medium for storing computer readable code for manufacturing an apparatus, the apparatus comprising: an output circuit arranged to output a sequence of output values in a given representation; an input interface for receiving a target value; and a modification circuit for determining a new output value in the sequence from a current output value in the sequence in dependence on the target value such that the new output value satisfies a determined condition, wherein the determined condition simultaneously requires that: when the new output value and the current output value are expressed in the given representation, the new output value has a Hamming distance of 1 with respect to the current output value, and the new output value lies between the current output value and the target value; wherein the modification circuit is arranged to, in the event that there are at least two possible new output values that satisfy the determined condition, select as the new output value the possible new output value that is closest to the target value from among the at least two possible new output values. Such computer readable code can be provided in any known transitory computer readable medium, such as wired or wireless transmission of code over a network, or a non-transitory computer readable medium such as a semiconductor, magnetic or optical disk.

[0007] In yet another example arrangement, there is provided a system comprising: an apparatus according to the first example arrangement described above, implemented in at least one package chip; at least one system component; and a board, wherein the at least one package chip and the at least one system component are assembled on the board.

[0008] In still another example arrangement, there is provided a chip-inclusive product comprising a system as described above assembled with at least one other product component on a further board. BRIEF DESCRIPTION OF DRAWINGS

[0009] The technology will be further described, by way of example only, with reference to examples of the technology as illustrated in the following drawings in which:

[0010] Figure 1is a block diagram of an apparatus according to one example implementation;

[0011] Figure 2 is a flowchart illustrating steps performed by an apparatus according to one example implementation; Figure 1

[0012] Figure 3A and Figure 3B provides a flowchart illustrating steps that can be performed by an apparatus according to one example implementation in more detail;

[0013] Figures 4 to 6 schematically illustrates a particular example of how a new output value can be generated from a current output value according to a target value according to one example implementation;

[0014] Figure 7 schematically illustrates a system in which the apparatus described herein can be employed according to one example implementation; and

[0015] Figure 8 Examples of systems and chip-containing products are illustrated. DETAILED DESCRIPTION

[0016] In one example implementation, there is provided an apparatus having an output circuit for outputting a sequence of output values in a given representation. An input interface is arranged to receive a target value, and a modification circuit is arranged to determine a new output value in the sequence from a current output value in the sequence according to the target value. When determining the new output value, the modification circuit is arranged to ensure that the new output value satisfies a determined condition which simultaneously requires that: when the new output value and the current output value are expressed in the given representation, the new output value has a Hamming distance of 1 with respect to the current output value, and the new output value is between the current output value and the target value. The requirement for a Hamming distance of 1 ensures that there is only a single numerical change between adjacent output values in the sequence in the form of the given representation, which eliminates the need for any synchronisation circuitry and allows a receiving device to reliably detect a transition of a change of output value from the current output value to the new output value. Furthermore, the requirement that the new output value is between the current output value and the target value means that the new output value is enabled to be closer to the target value than the current output value (thus attempting to follow the target value), but not to exceed the target value.

[0017] Furthermore, the modification circuit is arranged to, when there are at least two possible new output values that satisfy the determined condition, select the possible new output value that is closest to the target value from the at least two possible new output values as the new output value.

[0018] ​The above-described technique takes advantage of the fact that while a given representation can always produce a Hamming distance of 1 between two consecutive output values that differ by a default amount (e.g., a minimum adjustment amount), in some instances there can be larger adjustments in consecutive output values that would also result in those consecutive output values having a Hamming distance of 1 when expressed in the given representation, and that can also satisfy the requirement to generate a new output value that lies between the current output value and the target value. By attempting to detect such instances, an apparatus can be produced that can accommodate arbitrary changes in a sequence of target values while producing a corresponding sequence of output values that can be adjusted in response to changes in the amount of change in the target values so as to accurately follow the sequence of target values and while always ensuring that consecutive output values in the sequence in the form of the given representation have a Hamming distance of 1 with respect to each other.

[0019] The target values received at the input interface can take various forms. However, by way of example, in one particular implementation the target values can take the form of global time values. The amount by which consecutive instances of the target values received at the input interface change can vary over time, e.g., due to changes in the clock frequency at which an entity generating the global time values is operating, and / or changes in the clock frequency at which the apparatus is sampling the global time values, and thus there can be arbitrary changes in the target values, some of which are larger than others. The above-described technique can accommodate these arbitrary changes by attempting to determine new output values that allow the sequence of output values to more quickly reflect changes in the corresponding sequence of target values and thus more accurately follow the target values while always ensuring that consecutive output values in the sequence have a Hamming distance of 1 when expressed in the given representation. Moreover, the described technique ensures that any new output values selected will not exceed the corresponding target values. In the context of global time values propagating, this ensures that the receiving device never receives an output value that indicates a global time value that exceeds the originally generated global time value provided as the target value.

[0020] In the above-described example of global time values, each consecutive instance of the target value is expected to identify a value that is increased relative to the previously observed target value, and thus the sequence of received target values can be monotonically, arbitrarily increasing values. However, the technique can also be used in association with a sequence of target values that are monotonically but arbitrarily decreasing values. Moreover, in one example implementation the apparatus can accommodate a sequence of target values that can increase or decrease by arbitrary amounts between consecutive target values in the sequence.

[0021] The given representation can vary depending on the particular implementation, but in one example implementation is a Gray code representation. This provides a particularly efficient representation for use, since the Gray code representation is unambiguously defined, and the transition between the Gray code representation of any given value and the equivalent binary representation is direct. Thus, this can simplify the functionality of the modification circuit when attempting to determine a potential output value that satisfies the previously mentioned determined condition.

[0022] The modification circuit can be arranged to indicate the new output value in a variety of ways. However, in one example implementation the output circuit has storage for storing the current output value in the given representation, and the modification circuit is arranged to output a modification value that identifies which bit of the current output value in the given representation needs to have its bit value flipped in order to generate the new output value in the given representation. The output circuit can then be arranged to use the modification value to update the storage to identify the new output value in the given representation.

[0023] The modification value can take a variety of forms. For example, the modification value can take the form of a binary value having enough bits so that any one of the individual bits making up the output value in the given representation can be identified. By way of a specific example only, if the output value in the given representation comprises a 32-bit value, a 5-bit binary value can be used as the modification value to identify which individual bit within the current output value in the given representation needs to have its bit value flipped in order to transition from the current output value to the new output value in the given representation. In an alternative implementation, the modification value can be expressed as a one-hot encoded value having the same number of bits as the number of bits within the output value in the given representation, and a single bit within the one-hot encoded value is set to identify the bit position within the output value whose bit value should be flipped.

[0024] In one example implementation, at least each time a new instance of the target value is received at the input interface, the modification circuit is arranged to determine the current output value from the output value in the given representation as currently stored in the storage, and to determine the new output value in the sequence from the determined current output value in dependence on the new instance of the target value. While the modification circuit can be arranged to perform the determination of the new output value each time the target value changes, in one example implementation the modification circuit can also be arranged to continue to redetermine the new output value each time it is assessed that the current output value has not yet matched the target value, and thus irrespective of whether the target value has been updated. For example, the modification circuit can be arranged to perform such redeterminations on each clock cycle of the apparatus, either because the sampled target value has changed from a previous target value, or because the current output value as stored by the output circuit has not yet matched the target value.

[0025] The modification circuit can take various forms. In one example implementation, the modification circuit comprises an analysis circuit for performing an analysis operation using both the target value in binary representation and the current output value in binary representation in order to determine one or more candidate bit positions at which a bit value within the current output value in the given representation can be flipped in order to generate the new output value in the given representation. The modification circuit further comprises an evaluation circuit arranged to, when at least two candidate bit positions are determined, evaluate which of the candidate bit positions will result in the new output value that is closest to the target value while also being located between the current output value and the target value in the given representation in case its bit value within the current output value in the given representation is flipped in order to generate the new output value in the given representation. Such an arrangement can provide a particularly simple and cost-effective arrangement for implementing the modification circuit, thereby providing a small area solution. In alternative implementations, such functionality of the modification circuit can be implemented by software running on a general purpose processing circuit, if desired.

[0026] As previously mentioned, in some example implementations, the output value is maintained in the given representation, and when the modification circuit is implemented in the manner discussed above, then in one example implementation a conversion circuit can be provided to convert the current output value in the given representation into the current output value in binary representation for providing to the modification circuit.

[0027] There are various ways in which the analysis circuit can be arranged to perform the previously mentioned analysis operation in order to determine one or more candidate bit positions. However, in one example implementation, the analysis circuit is arranged to detect the most significant bit position as a first candidate bit position X at which the bit value in the target value in binary representation differs from the bit value in the current output value in binary representation. Such a determination of the first candidate bit position can be readily determined using both the target value and the current output value in binary representation. For example, an XOR operation can be performed using both the target value and the current output value in binary representation as input, where the most significant bit position in the output has a logical 1 value indicating the first candidate bit position X. If desired, the output from the XOR operation can be converted into a thermometer code (where all bit positions from bit position X to bit position 0 are set to a logical 1 value).

[0028] Furthermore, the analysis circuit can be arranged to detect a next most significant bit position below the first candidate bit position X at which a bit value in the current output value in binary representation is a predetermined bit value as a second candidate bit position Y, provided that there is at least one bit position below the first candidate bit position X at which a bit value in the current output value in binary representation has a predetermined bit value. In one example implementation, the second candidate bit position Y can be determined using a right-shifted one-bit version of the previously mentioned thermometer encoding in combination with the current output value in binary representation.

[0029] In one example implementation, the evaluation circuit can then be arranged to generate a candidate new output value that would be formed if the bit value at the first candidate bit position X within the current output value in the given representation were to be flipped in order to generate the new output value in the given representation. If the evaluation circuit then determines that the candidate new output value lies between the current output value and the target value, the evaluation circuit can then be arranged to identify the first candidate bit position X as the bit position within its current output value in the given representation at which a bit value is to be flipped in order to generate the new output value in the given representation. In one example implementation, the above-mentioned candidate new output value can be readily generated from the existing output value. For example, in an example implementation in which a Gray code is used as the given representation, the previously mentioned thermometer encoding and the current output value can be subjected to an XOR operation, the output of which then represents the candidate new output value.

[0030] In one example implementation, when it is determined that the above-mentioned candidate new output value does not lie between the current output value and the target value, the evaluation circuit can be arranged to identify the second candidate bit position Y as the bit position within its current output value in the given representation at which a bit value is to be flipped in order to generate the new output value in the given representation. It has been found that, in the case that the above-mentioned candidate new output value does not lie between the current output value and the target value (i.e. is not within an acceptable range of values), there will always be a bit position Y detected by the analysis circuit, and thus this bit position can be used to indicate a bit value to be flipped in order to transition the current output value to the new output value in the given representation.

[0031] As previously mentioned, in one example implementation, the given representation is a Gray code representation. In such an implementation, the evaluation circuit can be arranged to calculate the candidate new output value (C new ) in binary representation from the current output value (C

[0032] C new= {C[N-1:X+1], ~ C[X;0]}

[0033] such that C new X to 0 in C new is the inverse of the corresponding bit X to 0 in C new is greater than or equal to the target value in binary form (for implementations where the consecutive target values are decreasing), the candidate new output value is determined to be between the current output value and the target value.

[0034] As previously mentioned, in one example implementation, the analysis circuit is arranged to determine the next most significant bit position below the first candidate bit position X as the second candidate bit position Y at which the bit value in the current output value in binary form is a predetermined bit value, provided that there is at least one bit position below the first candidate bit position X at which the bit value in the current output value in binary form has the predetermined bit value. The predetermined bit value will depend on whether the target values received at the input interface are increasing or decreasing. In one example implementation, the predetermined bit value is a logical 0 value when consecutive values of the target value as received at the input interface are monotonically increasing, and the predetermined bit value is a logical 1 value when consecutive values of the target value as received at the input interface are monotonically decreasing.

[0035] While in some example implementations the apparatus will be for the case where the consecutive target values are either monotonically increasing only or monotonically decreasing only, the techniques described herein can also be used for other cases. For example, when any given target value as received at the input interface is allowed to increase or decrease relative to a previous target value as received at the input interface, the modification circuit can be arranged to additionally comprise a direction detection circuit for determining whether a currently received target value is greater than or less than the current output value. The predetermined bit value is then set to a logical 0 value when the currently received target value is greater than the current output value, and the predetermined bit value is set to a logical 1 value when the currently received target value is less than the current output value.

[0036] Particular example implementations will now be discussed with reference to the accompanying drawings.

[0037] Figure 1is a block diagram of an apparatus according to one example implementation. A sequence of target values is received at an input interface 10, and the apparatus is for generating a sequence of output values from an output circuit 30 that seeks to follow the sequence of target values. The output values are output according to a given representation that is selected so as to seek to improve reliable detection of changes in the output values. In one particular example implementation, the given representation is a Gray code representation. The Gray code representation ensures that when a first value is adjusted by a minimum adjustment value to produce a second value, the first value and the second value will differ by only a single bit value when expressed in Gray code representation (i.e. one bit within the first value in Gray code representation will have its bit value flipped to create the second value in Gray code representation). Thus, by using a Gray code representation, transitions in the output values can be more reliably detected even if the component that receives those output values is operating asynchronously with the apparatus that generates those output values.

[0038] When two values differ by only a single bit value, the two values are said to have a Hamming distance of 1. However, in many practical situations, adjacent target values within the sequence of target values received at the input interface will not necessarily differ from each other by only the minimum possible adjustment, and thus two adjacent output values in Gray code representation can not have a Hamming distance of 1 if each target value is simply converted directly to an equivalent Gray code representation. It is an aim of the techniques described herein to ensure that adjacent output values generated by the apparatus do have a Hamming distance of 1, whilst still enabling the sequence of output values to be adjusted in response to changes in the amount of change in the target values, so as to seek to accurately follow the sequence of target values.

[0039] As shown in Figure 1 , the apparatus comprises a modification circuit that receives each target value as received at the input interface 10. The target values can be received in various forms, but in one example implementation the target values are received in binary form. If received in a different form, the input interface can convert the target values to binary form before forwarding the received target values to the modification circuit, in one example implementation. The target value in binary form is referred to in Figure 1 as the target value T.

[0040] The output circuit 30 is arranged to store a Gray code representation of the current output value within a storage apparatus 45. Under a reset condition, the current output value in the storage apparatus will be reset to a defined value, for example all zeros. The current output value in Gray code form is provided to the modification circuit 20 via a Gray code to binary converter circuit 50, so that the modification circuit 20 receives the current output value in binary form, which is referred to in Figure 1 as the current output value C.

[0041] The target value T and the current output value C are optionally provided to an analysis circuit 35 via a direction determination circuit 55, which will be described in more detail later. The analysis circuit 35 is arranged to perform an analysis operation in order to determine one or more candidate bit positions at which a bit value within the current output value in Gray code representation can be flipped in order to generate a new output value (i.e. the next output value in the sequence) in Gray code representation.

[0042] In particular, in one example implementation, the analysis circuit is arranged to detect the most significant bit position as a first candidate bit position X at which the bit value in the target value T in binary representation differs from the bit value in the current output value C in binary representation. In one example implementation, this is achieved by performing an XOR operation on the provided binary values T and C to produce a result value, where the most significant bit position in the result value has a logical 1 value indicating the first candidate bit position X. If desired, the result value from the XOR operation can be converted to a thermometer code (where all bit positions from bit position X to bit position 0 are set to a logical 1 value).

[0043] In addition, the analysis circuit is arranged to detect the next most significant bit position below the first candidate bit position X as a second candidate bit position Y at which the bit value in the current output value C in binary representation is a predetermined bit value, provided that there is at least one bit position below the first candidate bit position X at which the bit value in the current output value C in binary representation has the predetermined bit value. The predetermined bit value will depend on whether the target value in the sequence is increasing or decreasing. If the target value is monotonically increasing, the predetermined bit value will be a logical 0 value, whereas if the target value is monotonically decreasing, the predetermined bit value will be a logical 1 value. In one example implementation, the target value will be constrained to be monotonically increasing values, or in an alternative example implementation, the target value will be constrained to be monotonically decreasing values. However, the techniques described herein can also be used if the target value is not constrained in this way. In particular, in implementations where the target value can increase or decrease, the direction determination circuit 55 can be used to determine whether the newly received target value is greater than or less than the current output value, and the predetermined bit value identifier circuit 60 identifies the appropriate predetermined bit value accordingly (i.e. a logical 0 value if the target value is greater than the current output value, or a logical 1 value if the target value is less than the current output value).

[0044] There are various ways in which the analysis circuit 35 can be arranged to detect the second candidate bit position Y, but in one example implementation, a right-shifted by one version of the previously mentioned thermometer encoding can be used in conjunction with the current output value C in binary representation to determine the second candidate bit position Y. For example, assuming that the predetermined bit value is a logic 0 value, this can be achieved by inverting each bit of the current output value and ANDing the inverted bits with the corresponding bits from the right-shifted by one version of the thermometer encoding, and detecting the most significant bit of the result having a logic 1 value as the bit position Y.

[0045] As shown in Figure 1 the binary values T and C are provided from the analysis circuit 35 to the evaluation circuit 40 along with the first candidate bit position X and the second candidate bit position Y. The evaluation circuit is then arranged to generate a candidate new output value that would be formed if the bit value at the first candidate bit position X within the current output value in Gray code representation were to be flipped to generate the new output value in Gray code representation. The evaluation circuit 40 then determines whether the candidate new output value lies between the current output value and the target value, and if so, the evaluation circuit is arranged to identify the first candidate bit position X as the bit position within its current output value in Gray code representation whose bit value is to be flipped to generate the new output value in Gray code representation. Otherwise, the second candidate bit position Y is indicated as the bit position within its current output value in Gray code representation whose bit value is to be flipped to generate the new output value in Gray code representation. The evaluation circuit can generate the candidate new output value in various ways, but in one example implementation, the previously mentioned thermometer encoding and current output value C are subjected to an XOR operation to generate the new candidate new output value.

[0046] The bit position determined by the evaluation circuit is then provided as a modification value to the output circuit 30 in order to cause the output value in Gray code form stored within the storage 45 to be updated. The modification value can take various forms, but in one example implementation, the modification value is provided as a one-hot encoded value whose set bit identifies the bit position within the current output value in Gray code representation whose bit value is to be flipped to generate the new output value in Gray code representation.

[0047] Figure 2 is an illustration of a Figure 1The flowchart describes the operation of the device. At step 100, it is determined whether a new target value has been received; if not, at step 105, it is determined whether the current output value matches the target value. If a new target value is received, or if the current output value does not match the most recently provided target value, the process proceeds to step 110. It should be noted that in one example implementation, the target value presented to input interface 10 is sampled by the device during each clock cycle, and therefore at each clock cycle, a new target value can be considered received regardless of whether the currently sampled target value is actually different from the previously sampled target value. In such implementations, the evaluation at step 105 is not required, and it can be assumed that a new target value has been received simply at step 100.

[0048] At step 110, the modification circuit is arranged to determine a new output value from the current output value based on the provided target value, and specifically, the modification circuit is arranged to constrain the new output value such that it satisfies a determined condition. This determined condition first requires that when both the new output value and the current output value are expressed in Gray code representation (or more generally, when both values ​​are expressed in a given representation used by the device, where Gray code representation is an example implementation), there exists a Hamming distance of 1 between the two values. However, the determined condition also requires that the new output value lies between the current output value and the target value, such that the output value cannot be adjusted to exceed the target value, i.e., it will not exceed the corresponding target value.

[0049] As indicated at step 115, when two or more possible output values ​​satisfy the determined condition, the modification circuit 20 is arranged to select the possible output value that is closest to the target value among those possible output values, thereby allowing changes in the output value to be adjusted more quickly according to changes in the target value provided to the device. The modification circuit then generates a modification value to identify a bit position in the current output value in Gray code form, the bit value of which should be flipped to generate a new output value in Gray code form, and at step 120, the output circuit flips the desired bit to generate a new output value in Gray code form, and the process then returns to step 100 (as previously mentioned, in other embodiments, representations other than Gray code may be used, as long as an output value that satisfies the previously mentioned determined condition can be generated).

[0050] Figure 3A and Figure 3B More detailed examples of specific implementations are provided by Figure 1 The flowchart shows the steps performed by the device. Steps 150 and 155 correspond to... Figure 2steps 100 and 105, and so when it is determined that a new target value has been received or that the current output value does not match the currently provided target value, then the process proceeds to step 160, in which the current output value is converted from a Gray code representation to a binary representation, e.g. using a Gray code to binary converter circuit 50. Figure 1

[0051] As previously mentioned, if the target value can be increased or decreased (as opposed to being constrained to only monotonically increasing or only monotonically decreasing), then at step 165 a direction determination circuit 55 can be used to determine whether the target value is greater than or less than the current output value, and then cause a predetermined bit value identifier circuit 60 to identify the appropriate predetermined bit value accordingly (a logical 0 value if the target value is greater than the current output value, and a logical 1 value if the target value is less than the current output value).

[0052] At step 170, an analysis circuit 35 is arranged to detect the most significant bit position as a first candidate bit position X at which the bit value in the target value differs from the bit value in the current output value (both values being considered in binary form). Furthermore, at step 175, the analysis circuit 35 detects the next most significant bit position below bit position X as a second candidate bit position Y at which the bit value in the current output value in binary form has a predetermined bit value (if available, i.e. if there is at least one such bit position).

[0053] At step 180, an evaluation circuit is arranged to calculate a candidate new output value (C new ) in binary form from the current output value (C) in binary form as:

[0054] C new = {C[N-1:X+1], ~ C[X; 0]}

[0055] such that bit X to 0 in C new is the inverse of the corresponding bit X to 0 in C.

[0056] C new therefore represents the candidate new output value that would be formed if the bit value at the first candidate bit position X within the current output value in Gray code form was flipped in order to generate the new output value in Gray code form.

[0057] At step 185, it is determined whether C new lies between the value C and T, i.e. C new ​The new output value will cause the output value to shift toward the target value T, but will not exceed that target value. If this is determined to be the case, the process proceeds to step 190, where bit position X is selected as the bit position whose bit value is to be flipped in the current output value in Gray code form to produce the new output value in Gray code form. Conversely, if this is not the case, the process proceeds instead to step 195, where bit position Y is selected as the bit position whose bit value is to be flipped in the current output value in Gray code form to produce the new output value in Gray code form. Regardless of which of steps 190 and 195 is performed, the process then proceeds to step 197, where output circuitry 30 updates storage device 45 to identify the new output value in Gray code form (which becomes the updated current output value at this point). The process then returns to step 150.

[0058] Figures 4 to 6 This illustrative example illustrates how a new output value can be generated from the current output value based on a target value, according to a specific implementation of an example. Figure 4 In this example, assuming the received target value is monotonically increasing, it has the form 200, i.e., representing a value of 8, and the current output value in Gray code form has the form 205, i.e., representing a value of 2. Gray code representation 205 is converted to binary representation 210, and as indicated by representation 215, bit positions X and Y are determined by comparing values ​​C and T. Specifically, for the example value shown, the most significant bit position where the values ​​of T and C differ is bit position 3 (assuming bit positions are labeled as bit positions 0 to 4, where bit position 0 is the least significant bit position), and the first bit position below bit position 3 that has a predetermined value of 0 in the current output value C is bit position 2.

[0059] Candidate new output value C new As shown in Figure 220 (and as is evident from the previous discussion, created by inverting all bits of the current output value C between the least significant bit position and bit position X (inclusive)). This effectively represents a value of 13, which is greater than the target value, thus causing a failure to pass with respect to C. new The check is whether it is less than or equal to the target value T. Therefore, the bit position Y is flipped in the current output value in Gray code form to generate a new output value G' in Gray code form. Figure 4 As shown in the diagram, 225 represents a value of 5. Therefore, in this particular example, it is not possible to perform a flip at bit position X, as this would result in a new output value exceeding the target value. Instead, a flip is performed at bit position Y, causing the output value to increase from 2 to 5 in a single update, thus shifting towards the desired target value of 8.

[0060] Figure 5 A second example is illustrated, which also assumes that the target value is monotonically increasing, which shows a case where a flip can be performed at bit position X. In particular, the target value has a representation 250, thus indicating that the target value is 5, while the current output value in Gray code form has a representation 255, thus indicating that the current output value is 2 (as also shown by the current output value 260 in binary representation form).

[0061] The representation 265 indicates the bit positions X and Y identified based on the values of C and T, and the representation 270 indicates the determined candidate new output value C new This time, by considering C new whether it is less than or equal to T (which is found to be true), and thus the bit position X flips its value in the current output value in Gray code representation in order to produce a new output value G' (indicated by the representation 275 in Figure 5 and the representation value is 5). Thus, in this particular example, the current output value of 2 can be updated in one shot to produce a new output value that matches the target value of 5, while still ensuring that the Hamming distance between adjacent output values is 1.

[0062] Figure 6 A further example is illustrated, where in this case the target value is assumed to be monotonically decreasing, and thus the predetermined bit value considered in determining the bit position Y is a bit value of 1. As shown by the representation 300, the latest target value specifies a value of 7, while the current output value in Gray code form represents a value of 14, as shown by the representation 305. The representation 310 shows the equivalent binary representation of the current output value C, and the representation 315 indicates the bit positions X and Y identified within the current output value C.

[0063] As shown by the representation 320, the candidate new output value C new identifies a value of 1. Since the target value is assumed to be monotonically decreasing, the relevant check to be performed is whether C new is greater than or equal to the target value T, which in this case results in false, and thus the bit position Y that is flipped in the current output value in Gray code representation in order to produce a new output value in Gray code representation is Y, which is indicated by the representation 325 as shown. Figure 6 In this particular example, it will be seen that the current output value of 14 is changed to a new output value of 9, thus moving the output value towards the target value of 7, while ensuring that the Hamming distance observed between adjacent output values is 1.

[0064] The above technique makes use of the fact that while using a Gray code representation will always result in a Hamming distance of 1 between two output values that differ by the smallest adjustment amount (i.e. by a value of 1), in some instances there can be larger adjustments between consecutive output values that will also result in those consecutive output values having a Hamming distance of 1 when represented using a Gray code, and which can also satisfy the requirement to generate a new output value that lies between the current output value and the target value. By attempting to detect such instances, the described apparatus can adapt to any changes in the sequence of target values while generating a corresponding sequence of output values that can be adjusted in response to changes in the amount of change of the target values so as to accurately follow the sequence of target values, and while always ensuring that consecutive output values in the sequence in the form of a Gray code representation have a Hamming distance of 1 with respect to each other.

[0065] The techniques described herein can be used in a variety of circumstances. In one particular example implementation, however, it is assumed that the sequence of target values represents a global time value within a data processing system. The above described apparatus can be included within the system for generating a sequence of Gray code values that attempts to follow changes in the global time value. Since the target values represent a global time value, it is expected that each subsequently received global time value will be greater than the previous global time value, i.e. the target values are monotonically increasing.

[0066] Figure 7 Such a system is shown in which the Gray code current time generator circuit 350 can be arranged to include the previously described apparatus as shown in, for example, Figure 1 and thus generate a sequence of Gray code current time indications that attempts to follow a sequence of current time indications received as target values. By using a Gray code representation, this can ensure that various different processing devices 360, 370 within the system reliably detect an increase in the global time, even when those processing devices can operate at different frequencies with respect to each other, and indeed can operate at different frequencies with respect to the Gray code current time generator circuit 350. In particular, these different processing devices 360, 370 can operate asynchronously with respect to the Gray code current time generator 350, but due to the use of a Gray code representation, changes in the time value will be reliably detected, the Gray code representation ensuring that only a single bit will change its value between adjacent time indications output by the circuit 350.

[0067] The amount of successive instance changes of the current time value (as received at the input interface of the Gray code current time generator 350) can vary over time, for example due to changes in the clock frequency at which the entity generating the global time value is operating, and / or changes in the clock frequency at which the Gray code current time generator circuit 350 is sampling the global time value, and thus there can be arbitrary changes in the sampled global time value, some of which are larger than others. Such situations can arise in data processing systems, for example due to switching clock frequencies in response to requested performance and / or power levels. However, as will be apparent from the previous discussion, when implementing the techniques described herein within the Gray code current time generator 350, the Gray code current time generator 350 can accommodate such arbitrary changes in the received target values (i.e. the received indications of the current time) such that a sequence of Gray code current time indications can be output that satisfy the requirement that the Hamming distance between adjacent output values is 1, while allowing the output values to attempt to adjust quickly to arbitrary changes in the received indications of the current time.

[0068] The techniques described herein can be implemented within a dedicated circuit, with simple circuit components being used to perform the required calculations, thereby enabling a small area circuit to be produced, which in turn allows a low cost and low power solution to be developed. Alternatively, if desired, the techniques described herein can be implemented by suitable software executing on a general purpose data processing apparatus.

[0069] The concepts described herein can be embodied in computer readable code for manufacturing devices embodying the described concepts. For example, the computer readable code can be used at one or more stages of a semiconductor design and fabrication process, including electronic design automation (EDA) stages, to manufacture integrated circuits that include devices embodying these concepts. The aforementioned computer readable code can additionally or alternatively enable devices embodying the concepts described herein to be defined, modeled, simulated, verified, and / or tested.

[0070] For example, computer readable code for making an apparatus embodying the concepts described herein can be embodied in code that defines the hardware description language (HDL) representations of these concepts. For example, the code can define a register transfer level (RTL) abstraction of one or more logic circuits for defining an apparatus embodying these concepts. The code can define the HDL representations of one or more logic circuits embodying the apparatus in Verilog, SystemVerilog, Chisel, or VHDL (very high speed integrated circuit hardware description language), as well as intermediate representations such as FIRRTL. The computer readable code can provide definitions embodying the concepts using system level modeling languages such as SystemC and SystemVerilog, or other behavioral representations of the concepts that are interpretable by a computer to enable simulation, functional and / or formal verification, and testing of the concepts.

[0071] Additionally or alternatively, the computer readable code can define low level descriptions of integrated circuit components embodying the concepts described herein, such as one or more netlists or integrated circuit layout definitions, including representations such as GDSII. The one or more netlists or other computer readable representations of integrated circuit components can be generated by applying one or more logic synthesis processes to the RTL representations to generate definitions for making an apparatus embodying the invention. Alternatively or additionally, the one or more logic synthesis processes can generate bitstreams to be loaded into a field programmable gate array (FPGA) from the computer readable code to configure the FPGA to embody the described concepts. The FPGA can be deployed for the purposes of verifying and testing the concepts prior to manufacturing integrated circuits, or the FPGA can be deployed directly in a product.

[0072] The computer readable code can include a mix of code representations for making an apparatus, for example including a mix of one or more of RTL representations, netlist representations, or another computer readable definition used in the process of semiconductor design and manufacturing to make an apparatus embodying the invention. Alternatively or additionally, the concepts can be defined in a combination of a computer readable definition of an apparatus used in the process of semiconductor design and manufacturing to make the apparatus and computer readable code defining instructions to be executed by the defined apparatus once manufactured.

[0073] Such computer readable code can be disposed in any known transitory computer readable medium, such as wired or wireless transmission of the code over a network, or a non-transitory computer readable medium such as a semiconductor, magnetic or optical disk. An integrated circuit made using the computer readable code can include components such as one or more of a central processing unit, a graphics processing unit, a neural processing unit, a digital signal processor, or other components individually or collectively embodying the concepts.

[0074] The concepts described herein can be embodied in a system that includes at least one packaged chip. The earlier-described apparatus is implemented in the at least one packaged chip (in one particular chip of the system, or distributed across more than one packaged chip). The at least one packaged chip is assembled on a board with at least one system component. The chip-inclusive product can include the system assembled on a further board with at least one other product component. The system or chip-inclusive product can be assembled into a housing or onto a structural support such as a frame or blade.

[0075] As Figure 8 indicated, one or more packaged chips 400 are manufactured by a semiconductor chip manufacturer, with the above-described apparatus implemented on one chip or distributed across two or more chips in the chip. In some examples, the chip product 400 manufactured by the semiconductor chip manufacturer can be provided as a semiconductor package that includes a protective enclosure (e.g., made of metal, plastic, glass, or ceramic) that houses the semiconductor devices implementing the above-described apparatus, as well as connectors such as pads, balls, or pins for connecting the semiconductor devices to an external environment. In cases where more than one chip 400 is provided, these chips can be provided as separate integrated circuits (provided as separate packages), or can be packaged by the semiconductor provider into a multi-chip semiconductor package (e.g., using an interposer, or by providing a multi-layer chip product that includes two or more vertically stacked layers of integrated circuits using three-dimensional integration).

[0076] In some examples, a collection of small chips (i.e., small modular chips with particular functionality) can themselves be referred to as a chip. The small chips can be individually packaged in semiconductor packages and / or packaged together into a multi-small-chip semiconductor package (e.g., using an interposer, or by providing a multi-layer small-chip product that includes two or more vertically stacked layers of integrated circuits using three-dimensional integration).

[0077] The one or more packaged chips 400 are assembled on a board 402 with at least one system component 404 to provide a system 406. For example, the board can include a printed circuit board. The board substrate can be made of any of a variety of materials, e.g., plastic, glass, ceramic, or a flexible substrate material such as paper, plastic, or a textile material. The at least one system component 404 includes one or more external components that are not part of the one or more packaged chips 400. For example, the at least one system component 404 can include any one or more of, e.g., another packaged chip (e.g., provided by a different manufacturer or produced on a different process node), an interface module, a resistor, a capacitor, an inductor, a transformer, a diode, a transistor, and / or a sensor.

[0078] A chip-inclusive product 416 is manufactured that includes the system 406 (including the board 402, one or more chips 400, and at least one system component 404) and one or more product components 412. The product components 412 include one or more additional components that are not part of the system 406. As an example, non-exhaustive list, the one or more product components 412 can include user input / output devices such as keyboards, touch screens, microphones, speakers, display screens, haptic devices, etc.; wireless communication transmitters / receivers; sensors; actuators for actuating mechanical motion; thermal control devices; additional packaged chips; interface modules; resistors; capacitors; inductors; transformers; diodes; and / or transistors. The system 406 and the one or more product components 412 can be assembled on a further board 414.

[0079] The board 402 or the further board 414 can be disposed on or in a device housing or other structural support (e.g., a frame or a blade) to provide a product that can be handled by a user and / or that is intended for personal or corporate operational use.

[0080] The system 406 or the chip-inclusive product 416 can be at least one of an end-user product, a machine, a medical device, a computing or telecommunications infrastructure product, or an automation control system. For example, as an example, non-exhaustive list, the chip-inclusive product can be any of a telecommunications device, a mobile phone, a tablet, a laptop, a computer, a server (e.g., a rackmount or a blade server), an infrastructure device, networking equipment, a vehicle or other automotive product, an industrial machine, a consumer device, a smart card, a credit card, smart glasses, avionics, a robotic device, a camera, a television, a smart television, a DVD player, a set-top box, a wearable device, a household appliance, a smart meter, a medical device, a heating / lighting control device, a sensor, and / or a control system for controlling public infrastructure equipment such as smart highways or traffic lights.

[0081] In this application, the word "configured" is used to mean that an element of a device has the capability to carry out a defined operation. In this context, a "configuration" means an arrangement or manner of interconnection of hardware or software. For example, a device can be provided with dedicated hardware for providing the defined operation, or a processor or other processing device can be programmed to perform the function. "Configured" does not imply that an element of the device needs to be changed in any way in order to provide the defined operation.

[0082] While example embodiments of the application have been described herein with reference to the accompanying drawings, it is to be understood that the application is not limited to those precise embodiments, and that various changes, additions and modifications can be made without departing from the scope and spirit of the application as defined in the appended claims. For example, features of one claim can be combined with features of another claim while not departing from the scope of the application.

Claims

1. An apparatus comprising: an output circuit arranged to output a sequence of output values in a given representation; an input interface for receiving a target value; and a modification circuit for determining a new output value in the sequence from a current output value in the sequence in dependence on the target value, such that the new output value satisfies a determined condition, wherein the determined condition simultaneously requires that when the new output value and the current output value are expressed in the given representation, the new output value has a Hamming distance of 1 relative to the current output value, and the new output value lies between the current output value and the target value; wherein the modification circuit is arranged to select, when there are at least two possible new output values that satisfy the determined condition, the possible new output value that is closest to the target value from among the at least two possible new output values as the new output value.

2. The apparatus of claim 1, wherein the given representation is a Gray code representation.

3. The apparatus of claim 1 or claim 2, wherein: the output circuit has storage for storing the current output value in the form of the given representation; and the modification circuit is arranged to output a modification value that identifies which bit of the current output value in the form of the given representation needs to have its bit value flipped in order to generate the new output value in the form of the given representation; and the output circuit is arranged to use the modification value to update the storage to identify the new output value in the form of the given representation.

4. The apparatus of claim 3, wherein at least each time a new instance of the target value is received at the input interface, the modification circuit is arranged to determine the current output value from the output value in the form of the given representation as currently stored in the storage, and to determine the new output value in the sequence from the determined current output value in dependence on the new instance of the target value.

5. The apparatus of any preceding claim, wherein: the modification circuit comprises an analysis circuit for performing an analysis operation using both the target value in binary representation and the current output value in binary representation in order to determine one or more candidate bit positions within the current output value in the given representation whose bit value can be flipped in order to generate the new output value in the given representation; and the modification circuit further comprises an evaluation circuit arranged to, when at least two candidate bit positions are determined, evaluate which of the candidate bit positions, if its bit value within the current output value in the given representation is flipped in order to generate the new output value in the given representation, will result in the new output value that is closest to the target value while also lying between the current output value and the target value.

6. The apparatus of claim 5, further comprising: a conversion circuit for converting the current output value in the form of the given representation into the current output value in the form of binary representation to provide to the modification circuit.

7. The apparatus of claim 5 or claim 6, wherein: the analysis circuit is arranged to detect a most significant bit position as a first candidate bit position X at which a bit value in the target value in binary representation is different from a bit value in the current output value in binary representation.

8. The apparatus of claim 7, wherein the analysis circuit is arranged to detect a next most significant bit position below the first candidate bit position X as a second candidate bit position Y at which a bit value in the current output value in binary representation is a predetermined bit value, provided there is at least one bit position below the first candidate bit position X at which a bit value in the current output value in binary representation has the predetermined bit value.

9. The apparatus of claim 8, wherein the evaluation circuit is arranged to generate a candidate new output value that would be formed if the bit value in the current output value in the given representation at the first candidate bit position X were to be flipped in order to generate the new output value in the given representation; and to identify the first candidate bit position X as the bit position within its current output value in the given representation at which a bit value is to be flipped in order to generate the new output value in the given representation when the candidate new output value lies between the current output value and the target value.

10. The apparatus of claim 9, wherein when the candidate new output value does not lie between the current output value and the target value, the evaluation circuit is arranged to identify the second candidate bit position Y as the bit position within its current output value in the given representation at which a bit value is to be flipped in order to generate the new output value in the given representation.

11. An apparatus according to claim 9 or claim 10, wherein the given representation is a Gray code representation, and the evaluation circuitry is arranged to calculate the candidate new output value (C new ) in binary form from the current output value (C) in binary form as: C new = {C[N-1:X+1], ~ C[X;0]} such that C new X to 0 in C is the inverse of the corresponding X to 0 in C.

12. The apparatus of any one of claims 8 to 11, wherein the predetermined bit value is a logical 0 value when consecutive values of the target value as received at the input interface monotonically increase.

13. The apparatus of any one of claims 8 to 11, wherein the predetermined bit value is a logical 1 value when consecutive values of the target value as received at the input interface monotonically decrease.

14. The apparatus of any one of claims 8 to 11, wherein: when any given target value as received at the input interface is allowed to increase or decrease relative to a previous target value as received at the input interface, the modification circuit comprises a direction detection circuit for determining whether a currently received target value is greater than or less than the current output value; when the currently received target value is greater than the current output value, the predetermined bit value is a logical 0 value; and when the currently received target value is less than the current output value, the predetermined bit value is a logical 1 value. when the current received target value is less than the current output value, the predetermined bit value is a logical 1 value.

15. The apparatus of any preceding claim, wherein the target value represents a global time value.

16. A method of generating a new output value for inclusion in a sequence of output values output in a given representation, the method comprising: receiving a target value; employing a modification circuit to determine the new output value in the sequence from a current output value in the sequence in dependence on the target value such that the new output value satisfies a determined condition, wherein the determined condition simultaneously requires that: when the new output value and the current output value are expressed in the given representation, the new output value has a Hamming distance of 1 with respect to the current output value, and the new output value lies between the current output value and the target value; and in the presence of at least two possible new output values that satisfy the determined condition, selecting the possible new output value closest to the target value from the at least two possible new output values as the new output value.

17. A non-transitory computer readable medium for storing computer readable code for manufacturing an apparatus, the apparatus comprising: an output circuit arranged to output a sequence of output values in a given representation; an input interface for receiving a target value; and a modification circuit for determining a new output value in the sequence from a current output value in the sequence in dependence on the target value such that the new output value satisfies a determined condition, wherein the determined condition simultaneously requires that: when the new output value and the current output value are expressed in the given representation, the new output value has a Hamming distance of 1 with respect to the current output value, and the new output value lies between the current output value and the target value; wherein the modification circuit is arranged to, in the presence of at least two possible new output values that satisfy the determined condition, select the possible new output value closest to the target value from the at least two possible new output values as the new output value.

18. A system comprising: an apparatus according to any one of claims 1 to 15, the apparatus implemented in at least one package chip; at least one system component; and a board, wherein the at least one package chip and the at least one system component are assembled on the board.

19. A chip-inclusive product comprising a system according to claim 18, the system being assembled with at least one other product component on a further board.

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