Three-dimensional (3D) dual complementary circuit structures and related methods of manufacture

Abstract

A 3D dual complementary circuit structure includes a first forked sheet structure stacked on a first side of a second forked sheet structure in a first direction to provide two complementary circuits in a space of a single forked sheet structure. At least one semiconductor plate in the first fork sheet structure is equally divided into a first plate part with a first semiconductor type and a second plate part with a second semiconductor type by the partition wall; and at least one semiconductor plate in the second fork sheet structure is equally divided into a third plate part with a third semiconductor type and a fourth plate part with a fourth semiconductor type. One of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type may be the same semiconductor type as the first semiconductor type. Two complementary metal oxide semiconductor (CMOS) circuits may be formed in the region of a single forked sheet structure.

Description

Priority Application

[0001] This application claims priority to U.S. Patent Application Serial No. 18 / 314,245, filed May 9, 2023, entitled “THREE-DIMENSIONAL (3D) DUAL COMPLEMENTARY CIRCUIT STRUCTURES AND RELATED FABRICATION METHODS,” the entirety of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The technology of the present disclosure relates generally to transistors in integrated circuits, and more specifically to three-dimensional transistor circuitry. BACKGROUND

[0003] Consumer demand for higher electronic device performance has driven technological advances. For example, to meet consumer demand for devices with greater functionality and performance in smaller packages, there is currently a trend to increase the number of transistors in integrated circuits (ICs) in electronic devices such as cell phones, laptops, and tablet computers. Reducing the size of transistors allows more transistors to fit on a chip of the same area, or the same number of transistors to fit on a smaller chip. One method for reducing the area of individual transistors involves trading horizontal area for vertical height. This has led to the development of three-dimensional (3D) transistors and circuitry. For example, by vertically stacking a first type of transistor on a second type of transistor, complementary circuitry employing two different types of transistors can be reduced. However, in addition to the size of individual transistors, another contribution to the area of an IC is the minimum face-to-face spacing distance between transistors due to limitations of the manufacturing process. Because of this spacing distance, a large proportion of the area of an IC chip is wasted. What is needed is a method that can further reduce the area occupied by multiple transistors. SUMMARY

[0004] Aspects disclosed in the detailed description include three-dimensional (3D) dual-complementary circuit structures. Related methods of fabricating 3D dual-complementary circuit structures are also disclosed. An example 3D dual-complementary circuit structure includes a first fin structure stacked in a first direction on a first side of a second fin structure to provide two complementary circuits in a space in a single fin structure. The fin structure includes at least one semiconductor plate used as a transistor channel, which is bisected by a partition wall to form a first circuit device in a first plate portion and a second circuit device in a second plate portion to provide two circuit devices in an area less than two separate circuit device structures. The partition wall divides the at least one semiconductor plate in the first fin structure into a first plate portion having a first semiconductor type and a second plate portion having a second semiconductor type, and also divides the at least one semiconductor plate in the second fin structure into a third plate portion having a third semiconductor type and a fourth plate portion having a fourth semiconductor type. In this way, two CMOS circuits can be formed in one of a plurality of configurations within the area of a single fin structure to significantly increase circuit density and reduce the area of an integrated circuit.

[0005] Any of the second, third, and fourth semiconductor types can be the same semiconductor type as the first semiconductor type. In some examples, only one of the second, third, and fourth semiconductor types can be the same semiconductor type as the first semiconductor type, while the other semiconductor types can be opposite semiconductor types. In such examples, where the 3D dual-complementary circuit structure has two semiconductor devices of each semiconductor type, two complementary metal-oxide-semiconductor (CMOS) circuits can be formed in the area of the first fin structure that is less than the area of two separate device structures.

[0006] In this regard, in one aspect, a 3D dual-circuit structure is disclosed. The 3D dual-circuit structure includes a first fin structure including at least one first semiconductor plate, a second fin structure including at least one second semiconductor plate and disposed in a first direction on a first side of the first fin structure, and a partition wall bisecting the at least one first semiconductor plate in a second direction orthogonal to the first direction into a first plate portion including a first semiconductor type on a first side of the partition wall and a second plate portion including a second semiconductor type on a second side of the partition wall, and also bisecting the at least one second semiconductor plate in the second direction into a third plate portion including a third semiconductor type on the first side of the partition wall and a fourth plate portion including a fourth semiconductor type on the second side of the partition wall, where a first of the second, third, and fourth semiconductor types is the same semiconductor type as the first semiconductor type.

[0007] In another aspect, a method of fabricating a 3D dual-circuit structure is disclosed. The method of fabricating a 3D dual-circuit structure includes forming a first interdigitated structure including at least one first semiconductor plate; forming a second interdigitated structure including at least one second semiconductor plate and disposed on a first side of the first interdigitated structure in a first direction; and forming a partition wall bisecting the at least one first semiconductor plate in a second direction orthogonal to the first direction into a first plate portion including a first semiconductor type on a first side of the partition wall and a second plate portion including a second semiconductor type on a second side of the partition wall, and further bisecting the at least one second semiconductor plate in the second direction into a third plate portion including a third semiconductor type on the first side of the partition wall and a fourth plate portion including a fourth semiconductor type on the second side of the partition wall, wherein a first of the second, third, and fourth semiconductor types is a same semiconductor type as the first semiconductor type.

[0008] In another aspect, an integrated circuit (IC) is disclosed. The IC includes a complementary logic circuit including a plurality of 3D dual-circuit structures, each of the plurality of 3D dual-circuit structures including: a first interdigitated structure including at least one first semiconductor plate, a second interdigitated structure including at least one second semiconductor plate and disposed on a first side of the first interdigitated structure in a first direction, and a partition wall bisecting the at least one first semiconductor plate in a second direction orthogonal to the first direction into a first plate portion including a first semiconductor type on a first side of the partition wall and a second plate portion including a second semiconductor type on a second side of the partition wall, and bisecting the at least one second semiconductor plate in the second direction into a third plate portion including a third semiconductor type on the first side of the partition wall and a fourth plate portion including a fourth semiconductor type on the second side of the partition wall, wherein a first of the second, third, and fourth semiconductor types is a same semiconductor type as the first semiconductor type. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1A is a top view of an example of an exemplary three-dimensional (3D) dual-complementary circuit structure including stacked interdigitated structures in which two complementary metal-oxide-semiconductor (CMOS) circuits are formed in regions of the interdigitated structures;

[0010] Figure 1B is Figure 1A is a cross-sectional side view of the exemplary 3D dual-complementary circuit structure in

[0011] Figure 1C is Figure 1Ais a cross-sectional side view along a channel direction of a first tine and a second tine in an exemplary 3D dual-complementary circuit structure in

[0012] Figure 2 is a flowchart showing an exemplary fabrication procedure for fabricating an exemplary 3D dual-complementary circuit structure, the structure including a stacked tine structure in which two CMOS circuits are formed in a reduced area, including but not limited to Figures 1A-1C a dual-complementary circuit structure in

[0013] Figures 3A-3I is a flowchart showing another exemplary fabrication procedure for fabricating an exemplary dual-complementary circuit structure, the structure including a stacked tine structure in which two CMOS circuits are formed in a tine structure area, including but not limited to Figures 1A-1C a dual-complementary circuit structure in

[0014] Figures 4A-4I is an exemplary fabrication stage during fabrication of an exemplary 3D dual-complementary circuit structure according to Figures 1A-1C an exemplary fabrication procedure in

[0015] Figure 5 is a cross-sectional side view of another example of a 3D dual-complementary circuit structure, the structure including a stacked tine structure in which two CMOS circuits are formed in a tine structure area, gates in a first tine structure are coupled to gates in a second tine structure, and gate contacts are on only one face;

[0016] Figure 6 is a cross-sectional side view of another example of a 3D dual-complementary circuit structure, the structure including a stacked tine structure in which two CMOS circuits are formed in a tine structure area, gates in a first tine structure are coupled to gates in a second tine structure, and gate contacts are on two faces;

[0017] Figure 7 is a cross-sectional side view of another example of a 3D dual-complementary circuit structure, the structure including a stacked tine structure in which two CMOS circuits are formed in a tine structure area, gates in a first tine structure are coupled to gates in a second tine structure, and gate contacts are on two faces;

[0018] Figure 8 is a block diagram of an exemplary wireless communication device, the wireless communication device including a radio frequency (RF) assembly, the RF assembly can include a 3D dual-complementary circuit structure, the structure including a stacked tine structure in which two CMOS circuits are formed in a tine structure area, including but not limited to Figures 1A-1C and Figures 5-7a 3D dual circuit structure in Figure 2 and Figures 3A-3I any one of the exemplary fabrication procedures in

[0019] Figure 9 is a block diagram of an exemplary processor-based system that can include a 3D dual complementary circuit structure including stacked interdigitated structures in which two CMOS circuits are formed in a reduced area, including but not limited to Figures 1A-1C and Figures 5-7 a dual circuit structure in Figure 2 and Figures 3A-3I any one of the exemplary fabrication procedures in DETAILED DESCRIPTION

[0020] Several exemplary aspects of the disclosure are described with reference to the drawings. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0021] Aspects disclosed in the detailed description include three-dimensional (3D) dual complementary circuit structures. Related methods of fabricating 3D dual complementary circuit structures are also disclosed. An exemplary 3D dual complementary circuit structure includes a first interdigitated structure stacked in a first direction on a first side of a second interdigitated structure to provide two complementary circuits in a space in a single interdigitated structure. The interdigitated structures include at least one semiconductor plate used as a transistor channel that is bisected by a partition wall to form a first circuit device in a first plate portion and a second circuit device in a second plate portion to provide two circuit devices in an area less than two separate circuit device structures. The partition wall divides the at least one semiconductor plate in the first interdigitated structure into a first plate portion having a first semiconductor type and a second plate portion having a second semiconductor type, and also divides the at least one semiconductor plate in the second interdigitated structure into a third plate portion having a third semiconductor type and a fourth plate portion having a fourth semiconductor type. In this way, two CMOS circuits can be formed in one of a plurality of configurations within the area of a single interdigitated structure to significantly increase circuit density and reduce the area of an integrated circuit.

[0022] Any of the second, third, and fourth semiconductor types can be the same semiconductor type as the first semiconductor type. In some examples, only one of the second, third, and fourth semiconductor types can be the same semiconductor type as the first semiconductor type, while the other semiconductor types can be opposite semiconductor types. In such examples, where the 3D dual complementary circuit structure has two semiconductor devices of each semiconductor type, two complementary metal-oxide-semiconductor (CMOS) circuits can be formed in the area of the first interdigitated structure that is less than the area of the two separate device structures.

[0023] In this regard, Figure 1A is a top view of an example of an exemplary three-dimensional (3D) dual complementary circuit structure (“dual circuit structure”) 100 and a first interdigitated structure 102Y on an integrated circuit chip (IC) 101, the first interdigitated structure stacked in a first vertical direction (Z-axis direction) on a second interdigitated structure 102X (not shown in Figure 1A to provide a first complementary metal-oxide-semiconductor (CMOS) circuit 104A and a second CMOS circuit 104B extending in a second horizontal direction (X-axis direction) and a third horizontal direction (Y-axis direction) in an area A 100 of the interdigitated structure. A semiconductor slab is a thin layer having two opposite planes and two edges. A semiconductor slab bisected by a partition wall is divided or split into a first slab portion on a first side of the partition wall and a second slab portion on a second side of the partition wall separated from each other by the two faces. The first and second slab portions are electrically isolated from each other due to the bisecting, but can be coupled in other ways. The first and second portions can not be equal in size. The bisected semiconductor slab in the interdigitated structure provides two circuit devices in an area less than two circuit device structures having separately formed transistor channel regions. Features referred to herein are shown in Figure 1A , Figure 1B and Figure 1C , which are schematic diagrams of the dual circuit structure 100, respectively, and in some cases, features can be shown in only one of Figure 1A , Figure 1B and Figure 1C .

[0024] The second X-axis direction and the third Y-axis direction are both orthogonal to the first direction and to each other. The area A 100The area of two separate device structures (e.g., complementary field effect transistor (CFET) structures) that can be spaced less than a minimum separation distance dictated by fabrication program limitations can be less due to the corresponding portions of the stacked first and second fin structures 102Y and 102X being separated by the separation wall 106, which is narrower in width than the minimum separation distance. For example, a first CMOS circuit 104A can be formed on a first side SI of the separation wall 106, and a second CMOS circuit 104B can be formed on a second side S2 of the separation wall 106. However, other configurations are possible. CMOS circuits include first circuit devices having a first semiconductor type and second circuit devices having an opposite semiconductor type, as explained further below.

[0025] The first fin structure 102Y includes at least one first semiconductor plate (e.g., nanosheet) 108 that is split by the separation wall 106 into a first plate portion 110A and a second plate portion 110B, also referred to herein as a first portion 110A and a second portion 110B. The dual circuit structure 100 also includes a first gate 112A disposed around the first portion 110A of the at least one first semiconductor plate 108 and a second gate 112B disposed around the second portion 110B of the at least one first semiconductor plate 108. The first and second gates 112A and 112B can be initially formed as a single structure, but are split by the addition of the separation wall 106. The first gate 112A controls current in a second X-axis direction in a first channel region 114A in the first portion 110A of the first semiconductor plate 108. The second gate 112B controls current in the second portion 110B of the first semiconductor plate 108. Thus, circuit devices such as metal oxide semiconductor (MOS) transistors can be formed in the first and second portions 110A and 110B of the first fin structure 102Y. The dual circuit structure 100 also includes spacers 116 on each face of the first fin structure 102Y.

[0026] On both faces of the first gate 112A, in the second direction, the first portion 110A of the first semiconductor plate 108 is coupled to source / drain regions 118J and 118K, and the second portion 110B of the semiconductor plate 108 is coupled to source / drain regions 120J and 120K. Currents in the first portion 110A and the second portion 110B of the semiconductor plate 108 are based, in part, on voltage differences between source / drain regions 118J, 118K and source / drain regions 120J, 120K, respectively. The dual-circuit structure 100 also includes dummy gates 122J and 122K at either end (in the second direction) of the first portion 110A and the second portion 110B of the semiconductor plate 108. In some examples, the dummy gates 122J and 122K are non-active gates that isolate the dual-circuit structure 100 from other circuit structures, and can be active gates for controlling current in other channel regions.

[0027] Figure 1B is a cross-sectional side view of the dual-circuit structure 100 at a B-B' section in Figure 1A , which extends in the third Y-axis direction through the gates 112A and 112B and across (e.g., orthogonal to) the partition wall 106. The B-B' section is in a plane that extends along the third direction (Y-axis direction) and the first direction (Z-axis direction). Figure 1A is a top view of the dual-circuit structure 100 at the A-A' section shown in Figure 1B .

[0028] Figure 1B It is shown that, in this example, at least one first semiconductor plate 108 in the first interdigitated structure 102Y includes three first semiconductor sheets. The current driving capability of the first channel region 114A of the first portion 110A and the second channel region 114B of the second portion 110B is determined, at least in part, by the number of at least one first semiconductor plate 108, and can be greater than or less than the number shown here.

[0029] Figure 1B It is also shown that a second interdigitated structure 102X is disposed on (e.g., below) a first side of the first interdigitated structure 102Y in the first direction. The second interdigitated structure 102X is similar in many respects to the first interdigitated structure 102Y, but is inverted relative to the first interdigitated structure 102Y. In other words, in some structural aspects, the first interdigitated structure 102Y and the second interdigitated structure 102X can mirror each other in the first direction on opposite faces of the bonding layer 124 that separates them. In some examples, the bonding layer 124 can include a shallow trench isolation (STI) material layer.

[0030] The second interdigitated structure 102X includes at least one (e.g., three in this example) second semiconductor plate 126 that is divided into a third portion 128A and a fourth portion 128B that are electrically isolated from each other by the partition wall 106. The second interdigitated structure 102X includes a third gate 130A and a fourth gate 130B that are also electrically separated from each other by the partition wall 106. The first and second gates 112A and 112B and the third and fourth gates 130A and 130B are made of a conductive material such as metal.

[0031] The at least one first semiconductor plate 108 and the at least one second semiconductor plate 126 are formed of a semiconductor material such as silicon (Si). In the first portion 110A of the first interdigitated structure 102Y, the semiconductor material is doped with a first dopant DP1 to have a first semiconductor type PN1. In the third portion 128A of the second interdigitated structure 102X, the semiconductor material is doped with a third dopant DP3 to have a third semiconductor type PN3 that is opposite to the first semiconductor type PN1 in this example. For example, the first semiconductor type PN1 can be doped with a pentavalent dopant and the third semiconductor type PN3 can be doped with a trivalent dopant. In another example, the first semiconductor type PN1 is doped with a trivalent dopant and the third semiconductor type is doped with a pentavalent dopant. In other examples, the first semiconductor type PN1 in the first portion 110A and the third semiconductor type PN3 in the third portion 128A are the same semiconductor type.

[0032] Depending on the type of dopant, the semiconductor material in each of the at least one first semiconductor plate 108 in the first portion 110A and the at least one second semiconductor plate 126 in the third portion 128A is either an N-type semiconductor or a P-type semiconductor. Thus, in the example where the first semiconductor type PN1 of the first portion 110A and the third semiconductor type PN3 of the third portion 128A are opposite semiconductor types, a first CMOS circuit 104A can be formed. The at least one first semiconductor plate 108 in the second portion 110B of the first interdigitated structure 102Y is doped with a second dopant DP2 for a second semiconductor type PN2 that is opposite to the first semiconductor type PN1 in this example and also opposite to a fourth semiconductor type PN4 of the at least one second semiconductor plate 126B in the fourth portion 128B that is doped with a fourth dopant DP4. In this way, the second portion 110B and the fourth portion 128B can be employed to form a second CMOS circuit 104B.

[0033] In some examples, the first semiconductor type PN1 of the first portion 110A is the same as the second semiconductor type PN2 of the second portion 110B. In some examples, the first semiconductor type PN1 of the first portion 110A is the same as the third semiconductor type PN3 of the third portion 128A. In some examples, the first semiconductor type PN1 of the first portion 110A is the same as the fourth semiconductor type PN4 of the fourth portion 128B. In some examples, any two of the first semiconductor type PN1, the second semiconductor type PN2, the third semiconductor type PN3, and the fourth semiconductor type PN4 are P-type semiconductors, while the other two are N-type semiconductors, such that two CMOS circuits can be formed in the dual-circuit structure 100.

[0034] As can be seen from Figure 1B , the first gate 112A is disposed around the at least one first semiconductor plate 108 in the first portion 110A in a manner similar to a gate-all-around (GAA) type transistor, except for the portions where the spacer walls 106 abut the at least one first semiconductor plate 108. The second gate 112B, the third gate 130A, and the fourth gate 130B are also disposed around the respective faces of the at least one semiconductor plate 108 and 126, except for the portions where the spacer walls 106 abut. In addition, the work function metal layers 132 and 134 are disposed around the at least one first semiconductor plate 108 and 126. In particular, the work function metal layer 132 is of a type corresponding to the first semiconductor type PN1 and the fourth semiconductor type PN4 in the example of Figure 1B . Thus, the work function metal layer 132 is disposed between the at least one first semiconductor plate 108 in the first portion 110A and the first gate 112A. The work function metal layer 132 is also disposed between the at least one second semiconductor plate 126 in the fourth portion 128B and the fourth gate 130B. The work function metal layer 134 corresponds to the second semiconductor type PN2 and the third semiconductor type PN3, as shown in Figure 1B . Thus, the work function metal layer 134 is disposed between the at least one first semiconductor plate 108 in the second portion 110B and the second gate 112B, and also between the at least one second semiconductor plate 126 in the third portion 128A and the third gate 130A. The work function metal layers 132 and 134 are separated from the at least one semiconductor plate 108 and 126 by the dielectric layer 136.

[0035] In structure, the first and second fin structures 102Y and 102X are disposed in interlayer dielectric (ILD) layers 138 and 140 of ILD material 142 or other suitable material, respectively. The first and second gates 112A and 112B of the first fin structure 102Y and the third and fourth gates 130A and 130B of the second fin structure 102X are isolated from the ILD material 142 by spacers 116. For example, the separation walls 106 and spacers 116 can be formed of silicon nitride (SiN or SiO2). The materials for the work function metal layers 132 and 134 are selected according to whether the semiconductor types PN1, PN2, PN3, and PN4 are N-type or P-type.

[0036] For electrical coupling to / from external circuits, the dual circuit structure 100 includes vias 144 and contacts 146 in a first contact layer 148 to supply control voltages to control current in the first and second channel regions 114A and 114B, respectively. Vias 150 and contacts 152 in a second contact layer 154 are used to provide a supply voltage to control current in the third and fourth portions 128A and 128B. Thus, in this example, each of the first, second, third, and fourth gates 112A, 112B, 130A, and 130B is individually controlled by a separate control voltage provided at contacts 146 and 152. However, different configurations can be used to apply control voltages according to circuit requirements, as discussed below Figures 5-7 as shown in the examples of

[0037] Figure 1C is a cross-sectional side view of the cross-section C-C' in the dual circuit structure 100 of Figure 1A is a cross-sectional side view of the cross-section C-C' in the dual circuit structure 100 of Figure 1B and Figure 1C features common to the examples of Figure 1A or Figure 1B are shown.

[0038] Figure 1CThe second portion 110B is provided to show that the source / drain regions 120J and 120K in the second portion 110B extend in the first X-axis direction and are coupled to each of the at least one first semiconductor plate 108, and that the source / drain regions 156J and 156K in the second portion 110B extend in the first X-axis direction and are coupled to each of the at least one second semiconductor plate 126. It will be appreciated that the source / drain regions 120J, 120K, 156J, and 156K are in the first to fourth source / drain regions of the dual-circuit structure 100 on the second side S2 of the separation wall 106 (see Figure 1A ), and that there are fifth, sixth, seventh, and eighth source regions (not shown) similarly coupled to the at least one first semiconductor plate 108 in the first portion 110A and the at least one second semiconductor plate 126 in the third portion 128A. In this example, the fifth to eighth source / drain regions will also be coupled to fifth to eighth contacts in the first and second contact layers 148 and 154.

[0039] The source / drain regions 120J and 120K are on opposite faces of the channel region 114B to provide the source and drain of a transistor depending on the polarity of the voltage applied between the source / drain regions 120J and 120K. The source / drain regions 156J and 156K extend in the first direction in the fourth portion 128B and are coupled to each of the at least one second semiconductor plate 126. The source / drain regions 156J and 156K provide the source and drain on either of the channel regions 158B in a transistor (e.g., MOS transistor) depending on the polarity of the applied voltage.

[0040] The source / drain regions 120J and 120K are coupled to the metal via 160 and the metal contact 162, and the source / drain regions 156J and 156K are coupled to the metal via 164 and the metal contact 166. The dual-circuit structure 100 in this example includes a via 168 for electrically coupling the source / drain region 120K of the second portion 110B to the source / drain region 156K of the fourth portion 128B, which can be used to configure an inverter circuit or other circuit in which the source / drain regions of a first type of transistor are coupled to the source / drain regions of a second type of transistor.

[0041] A manufacturing procedure can be used to manufacture a dual-circuit structure including a 3D interdigitated structure in which two CMOS circuits are formed in a reduced area, including but not limited to Figures 1A-1C the dual-circuit structure 100 in FIG. 1. In this regard, Figure 2is a flowchart illustrating an exemplary fabrication procedure 200 to fabricate a dual complementary circuit structure including a 3D interdigitated stack in which two CMOS circuits are formed in a reduced area. Figure 2 The fabrication procedure 200 in Figures 1A-1C is discussed with respect to the dual circuit structure 100 in Figure 2 but note that the fabrication procedure 200 in Figures 1A-1C is not limited to fabricating the dual circuit structure 100 in

[0042] In this regard, exemplary steps to fabricate the dual circuit structure 100 include forming a first interdigitated structure 102Y including at least one first semiconductor plate 108 (block 202); forming a second interdigitated structure 102X including at least one second semiconductor plate 126 and disposed on a first side of the first interdigitated structure 102Y in a first direction (block 204). The method includes forming a partition wall 106 bisecting the at least one first semiconductor plate 108 and the at least one second semiconductor plate 126 in a second direction orthogonal to the first direction (block 206), wherein: the first semiconductor plate 108 bisected by the partition wall includes a first plate portion 110A including a first semiconductor type PN1 on a first side SI of the partition wall 106 and a second plate portion 110B including a second semiconductor type PN2 on a second side S2 of the partition wall 106; the second semiconductor plate 126 bisected by the partition wall includes a third plate portion 128A including a third semiconductor type PN3 on the first side SI of the partition wall 106 and a fourth plate portion 128B including a fourth semiconductor type PN4 on the second side S2 of the partition wall 106; a first one of the second semiconductor type PN2, the third semiconductor type PN3, and the fourth semiconductor type PN4 is a same semiconductor type as the first semiconductor type PN1.

[0043] Other fabrication procedures can also be employed to fabricate a dual circuit structure including a 3D interdigitated stack in which two CMOS circuits are formed in a reduced area, including but not limited to Figures 1A-1C the dual circuit structure 100 in

[0044] In this regard, Figures 3A-3I is a flowchart illustrating another exemplary fabrication procedure 300 to fabricate a dual circuit structure including a 3D interdigitated stack in which two CMOS circuits are formed in a reduced area, including but not limited to Figures 1A-1C the dual circuit structure 100 in Figures 4A-4I are exemplary fabrication stages 400A-400I during fabrication of a dual circuit structure including a 3D interdigitated stack in which two CMOS circuits are formed in a reduced area according to Figures 3A-3I the fabrication procedure 300 in

[0045] In this regard, as shown in fabrication stage 400A in FIG. 4A, a first step 302 in a fabrication procedure 300 includes forming a first tine structure 402 on a substrate 404, the first tine structure 402 including at least one first semiconductor plate 406 stacked in a first Z-axis direction and surrounded by a dummy poly gate 408, and forming spacers 410 on each face of the dummy poly gate 408. The at least one first semiconductor plate 406 is formed of a semiconductor material such as Si. The dummy poly gate 408 can be formed of a poly silicon material. The spacers 410 can be SiN, for example. Figure 4A As shown in fabrication stage 400B in FIG. 4B, a next step 304 in the fabrication procedure 300 includes forming a dielectric layer 412 around the first tine structure 402, forming a spacer wall shield 414 including an opening 416 on the first tine structure 402, and forming a trench 418 in the first tine structure 402 through the opening 416. The dielectric layer 412 can be an interlayer dielectric (ILD) material formed on the substrate 404 around the first tine structure 402, for example. The first tine structure 402 and the dielectric layer 412 can be planarized prior to forming the spacer wall shield 414 by chemical and / or mechanical polishing (CMP). The trench 418 corresponding to the opening 416 extends through the first tine structure 402 in the first Z-axis direction to the substrate 404.

[0046] Figure 4B As shown in fabrication stage 400C in FIG. 4C, a next step 306 in the fabrication procedure 300 includes forming a spacer wall 420 in the trench 418 of the first tine structure 402, and removing the spacer wall shield 414. The spacer wall 420 can be formed of SiN deposited into the trench 418 and chemical and / or mechanical polishing (CMP), for example.

[0047] As shown in fabrication stage 400D in FIG. 4D, a next step 308 in the fabrication procedure 300 includes removing the dummy poly gate 408, forming a high-K dielectric layer 422 on the at least one first semiconductor plate 406 on a first side SI and a second side S2 of the spacer wall 420, and forming a first type work function metal layer 424 on the high-K dielectric layer 422 on the first side SI and the second side S2 of the spacer wall 420. The dummy poly gate 408 can be removed by a chemical etching procedure. The first type work function metal 424 can be an N-type or a P-type work function metal. Figure 4C As shown in fabrication stage 400E in FIG. 4E, a next step 310 in the fabrication procedure 300 includes forming a second tine structure 430 on the substrate 404, the second tine structure 430 including at least one second semiconductor plate 432 stacked in the first Z-axis direction and surrounded by a second poly gate 434, and forming spacers 436 on each face of the second poly gate 434. The at least one second semiconductor plate 432 is formed of a semiconductor material such as Si. The second poly gate 434 can be formed of a poly silicon material. The spacers 436 can be SiN, for example.

[0048] Figure 4D As shown in fabrication stage 400F in FIG. 4F, a next step 312 in the fabrication procedure 300 includes forming a dielectric layer 438 around the second tine structure 430, forming a spacer wall shield 440 including an opening 442 on the second tine structure 430, and forming a trench 444 in the second tine structure 430 through the opening 442. The dielectric layer 438 can be an interlayer dielectric (ILD) material formed on the substrate 404 around the second tine structure 430, for example. The second tine structure 430 and the dielectric layer 438 can be planarized prior to forming the spacer wall shield 440 by chemical and / or mechanical polishing (CMP). The trench 444 corresponding to the opening 442 extends through the second tine structure 430 in the first Z-axis direction to the substrate 404.

[0049] As shown in fabrication stage 400G in FIG. 4G, a next step 314 in the fabrication procedure 300 includes forming a spacer wall 446 in the trench 444 of the second tine structure 430, and removing the spacer wall shield 440. The spacer wall 446 can be formed of SiN deposited into the trench 444 and chemical and / or mechanical polishing (CMP), for example. Figure 4E ​​As shown in fabrication stage 400E in FIG. 4, the next optional processing step 310 in the fabrication procedure 300 includes removing the first type work function metal 424 from the at least one first semiconductor plate 406 on the first side S1 of the separation wall 420, and forming a second type work function metal 426 on the high-K dielectric layer 422 on the at least one first semiconductor plate 406 on the first side S1 of the separation wall 420. The first type work function metal 424 can be removed by forming a shield on the second side S2 of the separation wall and performing a chemical etch.

[0050] As shown in fabrication stage 400D in FIG. 4, the next step 308 in the fabrication procedure 300 includes forming the first type work function metal 424 on the high-K dielectric layer 422 on the first side S1 of the separation wall 420, and forming the second type work function metal 426 on the high-K dielectric layer 422 on the second side S2 of the separation wall 420. Figure 4F As shown in fabrication stage 400F in FIG. 4, the next step 312 in the fabrication procedure 300 includes forming a first gate 428 on the work function metal 424, 426 on the first side S1 of the separation wall 420, and forming a second gate 430 on the first type work function metal 424 on the second side S2 of the separation wall 420. If the first type work function metal 424 is removed from the first side S1 and replaced with the second type work function metal 426, the first gate 428 is formed on the second type work function metal 426 on the face S1. Otherwise, the first gate 428 is formed on the first type work function metal 424 on the face S1.

[0051] As shown in fabrication stage 400D in FIG. 4, the next step 308 in the fabrication procedure 300 includes forming the first type work function metal 424 on the high-K dielectric layer 422 on the first side S1 of the separation wall 420, and forming the second type work function metal 426 on the high-K dielectric layer 422 on the second side S2 of the separation wall 420. Figure 4G As shown in fabrication stage 400G in FIG. 4, the next step 314 in the fabrication procedure 300 includes forming a first contact layer 432 on the first dielectric layer 412 and the first interdigitated structure 402, and forming a first gate contact 434 coupled to one of the first gate 428 and the second gate 430 through the first contact layer 432. The first contact layer 432 can be formed of an intermetallic dielectric material. The first gate contact 434 can be a metal, such as tungsten or copper.

[0052] As shown in fabrication stage 400D in FIG. 4, the next step 308 in the fabrication procedure 300 includes forming the first type work function metal 424 on the high-K dielectric layer 422 on the first side S1 of the separation wall 420, and forming the second type work function metal 426 on the high-K dielectric layer 422 on the second side S2 of the separation wall 420. Figure 4H As shown in fabrication stage 400H in FIG. 4, the step 316 in the fabrication procedure 300 includes mounting a carrier chip 436 on the first contact layer 432, removing the substrate 404 from the bottom surface BS of the first interdigitated structure 402, and forming a bonding layer 438 that optionally includes an inter-gate contact 440 coupled to the first gate 428 and the second gate 430 on the bottom surface BS of the first interdigitated structure 402. In examples in which the bonding layer 438 is formed without the inter-gate contact 440, the first gate contact 434 in the first contact layer 432 is coupled to one of the first gate 428 and the second gate 430, and the bonding layer 434 can also include a second gate contact (not shown) coupled to the other of the first gate 428 and the second gate 430.

[0053] As shown in fabrication stage 400D in FIG. 4, the next step 308 in the fabrication procedure 300 includes forming the first type work function metal 424 on the high-K dielectric layer 422 on the first side S1 of the separation wall 420, and forming the second type work function metal 426 on the high-K dielectric layer 422 on the second side S2 of the separation wall 420. Figure 4IAs shown in manufacturing stage 400I, step 318 in manufacturing process 300 includes bonding the bottom surface BS' of the second fork structure 402' manufactured according to steps 302-316 to the bonding layer 438 of the first fork structure, as shown in manufacturing stages 400A-400H. At this point, the second fork structure 402' is disposed on a first side (e.g., below) of the first fork structure 402 in a first Z-axis direction to form a 3D fork stack. The partition walls 420 and 420' of the first fork structure 402 are aligned with the second fork structure 402' to form a single partition wall 420 extending in a first direction from the first contact layer 432 of the first fork structure 402 to the first contact layer 432' of the second fork structure 402'.

[0054] Other examples of cross-sectional views of a two-circuit structure include Figures 5-7 As shown, the structure includes a 3D fork stack, in which two CMOS circuits are formed within a reduced area. Figures 5-7 Zhongyu Figures 1A-1C The same features are similarly labeled, and will not be elaborated further here.

[0055] Figure 5 This is an example of a 3D dual-circuit structure 500, which includes a 3D fork structure 502, wherein CMOS circuits 504A and 504B are formed in a reduced area. Figure 5 In this example, the first semiconductor type PN1 of the first portion 110A is opposite to the third semiconductor type PN3 of the third portion 128A. Furthermore, in this example, the second semiconductor type PN2 of the second portion 110B is opposite to the fourth semiconductor type PN4 of the fourth portion 128B. Therefore, transistors (not shown) formed in the first portion 110A and the third portion 128A can form a CMOS circuit 504A, and transistors formed in the second portion 110B and the fourth portion 128B can form a CMOS circuit 504B. On the first side S1 of the partition wall 106, the first gate 112A of the first portion 110A is coupled to the third gate 130A of the third portion 128A through the first inter-gate contact 506A in the bonding layer 124 to form the CMOS circuit 504A, and the second gate 112B of the second portion 110B is coupled to the fourth gate 130B of the fourth portion 128B through the second inter-gate contact 506B on the second side S2 of the partition wall 106 to form the CMOS circuit 504B.

[0056] As shown in this example, the inclusion of the inter-gate contacts 506A and 506B allows the control voltage for the CMOS circuits on each face S1 and S2 of the partition wall 106 to be provided by the inter-gate contacts 506A on the first contact layer 148 above (in the Z-axis direction) the first tine structure 102Y. This eliminates the need for a bottom contact or via to couple the third gate 130A in the third portion 128A and the fourth gate 130B in the fourth portion 128B to the control voltage.

[0057] As with the example in Figure 5 , Figure 6 the example of the dual-circuit structure 600 in includes inter-gate contacts 602A and 602B to couple the first gate 112A to the third gate 130A on the first side S1 and the second gate 112B to the fourth gate 130B in the fourth portion 128B. However, the first contact layer 148 only contains gate contacts 604A coupled to the first gate 112A and the third gate 130A to provide voltage to the CMOS circuits on the first side S1. The second contact layer 154 contains gate contacts 604B coupled to the fourth gate 130B and the second gate 112B to provide voltage to the CMOS circuits on the second side S2.

[0058] The second semiconductor type PN2 and the fourth semiconductor type PN4 are opposite each other as shown in Figure 5 , but in the dual-circuit structure 600, the second semiconductor type PN2 in the first tine structure 102Y and the first semiconductor PN1 have the same semiconductor type (the same as each other), and the fourth semiconductor type PN4 in the second tine structure 102X and the third semiconductor type PN3 have the same semiconductor type. Thus, Figure 6 the dual-circuit structure 600 in can provide the same CMOS circuits as the dual-circuit structure 500 in Figure 5 , but without the optional process step 310 in the process 300 to form opposite semiconductor types on different faces S1 and S2 of the partition wall 106.

[0059] Figure 7 Another example of a dual-circuit structure 700 is shown, which includes a 3D tine structure in which CMOS circuits 702A and 702B are formed in reduced areas. The first semiconductor type PN1 in the first portion 110A of the at least one semiconductor plate 108 is opposite the second semiconductor type PN2 in the second portion 110B. In addition, the first gate 112A and the second gate 112B are coupled to each other in the first contact layer 148 through a via 704 and a contact 706. Unlike Figure 5 and Figure 6 , in which CMOS circuits are formed on each face of the partition wall 106, Figure 7The dual-circuit structure in enables CMOS circuits 702A and 702B on each face of the bonding layer 124. For example, the first gate 112A and the second gate 112B are coupled to form a CMOS inverter. Similarly, the third semiconductor type PN3 is opposite the fourth semiconductor type PN4, and the gates 130A and 130B are coupled to each other through vias 708 and contacts 710 in the second contact layer 154.

[0060] It should be understood that in all examples in Figures 5-7 the source / drain regions can also be coupled to external circuits or another terminal through vias and contacts in the first contact layer 148 and the second contact layer 154.

[0061] An electronic device according to any of the aspects disclosed herein can be provided in or incorporated into any processor-based device, including a 3D dual-complementary circuit structure including a stacked-finger structure in which two CMOS circuits are formed in a reduced area, as shown in Figures 1A-1C and Figures 5-7 Examples include, but are not limited to, a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, an mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cell phone, a smartphone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a laptop computer, a wearable computer device (e.g., a smart watch, a health or fitness tracker, glasses, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.

[0062] In this regard, Figure 8 An example wireless communication device 800 is shown including radio frequency (RF) components formed by one or more ICs 802, where any of the ICs 802 can include an integrated circuit including a dual-complementary circuit structure according to any of the aspects disclosed herein, including a stacked-finger structure in which two CMOS circuits are formed in an area of a single finger, as shown in Figures 1A-1C and Figures 5-7 For example, the wireless communication device 800 can include or be provided in any of the devices described above. As Figure 8As shown, the wireless communication device 800 includes a transceiver 804 and a data processor 806. The data processor 806 can include memory for storing data and program codes. The transceiver 804 includes a transmitter 808 and a receiver 810 that support bi-directional communication. In general, the wireless communication device 800 can include any number of transmitters 808 and / or receivers 810 for any number of communication systems and frequency bands. All or a portion of the transceiver 804 can be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

[0063] The transmitter 808 or receiver 810 can be implemented with a super- heterodyne architecture or a direct-conversion architecture. In a super-heterodyne architecture, a signal is frequency converted between RF and baseband in multiple stages, e.g., from RF to an intermediate frequency (IF) in one stage, and then from IF to baseband in another stage. In a direct-conversion architecture, a signal is frequency converted between RF and baseband in one stage. The super-heterodyne and direct-conversion architectures can use different circuit blocks and / or have different requirements. In the exemplary wireless communication device 800, the transmitter 808 and receiver 810 are implemented with a direct-conversion architecture. Figure 8 In the wireless communication device 800, the transmitter 808 and receiver 810 are implemented with a direct-conversion architecture.

[0064] In the transmit path, the data processor 806 processes information to be transmitted and provides I and Q analog output signals to the transmitter 808. In the exemplary wireless communication device 800, the data processor 806 includes digital-to-analog converters (DACs) 812(1), 812(2) for converting digital signals produced by the data processor 806 to the I and Q analog output signals, e.g., I and Q output currents, for further processing.

[0065] Within the transmitter 808, lowpass filters 814(1), 814(2) filter the I and Q analog output signals, respectively, to remove undesired signals caused by previous digital-to-analog conversion. Amplifiers (AMPs) 816(1), 816(2) amplify the signals from the lowpass filters 814(1), 814(2), respectively, and provide I and Q baseband signals. An upconverter 818 upconverts the I and Q baseband signals with I and Q transmit (TX) local oscillator (LO) signals from a TX LO signal generator 822 through mixers 820(1), 820(2) to provide upconverted signals 824. A filter 826 filters the upconverted signals 824 to remove undesired signals caused by the upconversion and noise in the receive band. A power amplifier (PA) 828 amplifies the upconverted signals 824 from the filter 826 for a desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 830 and transmitted via an antenna 832.

[0066] In the receive path, the antenna 832 receives signals transmitted by base stations and provides a received RF signal, which is routed through the duplexer or switch 830 and provided to a low noise amplifier (LNA) 834. The duplexer or switch 830 is designed to operate at a particular receive (RX) to TX duplexer frequency separation, such that RX signals are isolated from TX signals. The received RF signal is amplified by the LNA 834 and filtered by a filter 836 to obtain a desired RF input signal. Down-mixers 838(1), 838(2) mix the output of the filter 836 with I and Q RX LO signals (i.e., LO I and LO Q) from an RX LO signal generator 840 to produce I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 842(1), 842(2) and further filtered by low pass filters 844(1) and 844(2) to obtain I and Q analog input signals, which are provided to the data processor 806. In this example, the data processor 806 includes analog-to-digital converters (ADCs) 846(1), 846(2) for converting the analog input signals to digital signals to be further processed by the data processor 806.

[0067] In Figure 8 In the wireless communication device 800, the TX LO signal generator 822 generates I and Q TX LO signals for up-conversion, and the RX LO signal generator 840 generates I or Q RX LO signals for down-conversion. Each LO signal is a periodic signal having a particular base frequency. A TX phase-locked loop (PLL) circuit 848 receives timing information from the data processor 806 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from the TX LO signal generator 822. Similarly, a RX PLL circuit 850 receives timing information from the data processor 806 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from the RX LO signal generator 840.

[0068] Figure 9 An example of a processor-based system 900 that can employ integrated circuits, including dual complementary circuit structures and stacked-die structures, in which two CMOS circuits are formed in the area of a single die, is shown in Figures 1A-1C and Figures 5-7The illustrated. In this example, the processor-based system 900 includes one or more central processing unit(s) (CPU(s)) 902, which can also be referred to as a CPU or processor core(s), each including one or more processor(s) 904. The CPU(s) 902 can have cache memory 906 coupled to the processor(s) 904 to provide temporary storage to accelerate the use of data by the processor(s) 904. The CPU(s) 902 is coupled to a system bus 908 and can be coupled among other primary and secondary devices comprised in the processor-based system 900. As is well known, the CPU(s) 902 communicates with these other devices by exchanging address, control, and data information over the system bus 908. For example, the CPU(s) 902 can transmit bus transaction requests to a memory controller 910 as an example of a slave device. Although Figure 9 Multiple system buses 908 can be provided, as is known, with each system bus 908 constituting a different fabric.

[0069] Other primary and secondary devices can be connected to the system bus 908. As Figure 9 illustrated, these devices can include, by way of example and not by way of limitation, a memory system 912 including the memory controller 910 and one or more memory arrays 914, one or more input devices 916, one or more output devices 918, one or more network interface devices 920, and one or more display controller(s) 922. The input device(s) 916 can include any type of input device, including, but not limited to, input keys, switches, voice processors, etc. The output device(s) 918 can include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. The network interface device(s) 920 can be any device configured to allow exchange of data to and from a network 924. The network 924 can be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a Bluetooth™ network, and the Internet. The network interface device(s) 920 can be configured to support any type of communications protocol desired.

[0070] The CPU(s) 902 can also be configured to access the display controller(s) 922 over the system bus 908 to control information sent to one or more displays 926. The display controller(s) 922, in turn, can control one or more displays 926 to which the display controller(s) 922 is connected. The displays 926 can include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, or a light emitting diode (LED) display, among others.

[0071] Those skilled in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein can be implemented as electronic hardware, instructions stored in memory or in another computer-readable medium, wherein any such instructions are executed by a processor or other processing device or combination thereof. As an example, devices and components described herein can be used in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. The memory disclosed herein can be any type of and size of memory and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such

[0072] The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein can be implemented or performed with any processor, digital signal processor (DSP), application specific integrated circuit (ASIC), field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor can be a microprocessor, but in the alternative, the processor can be any conventional processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0073] The aspects disclosed herein can be embodied in hardware and in instructions stored in hardware, and can reside, for example, in random access memory (RAM), flash memory, read only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium can be integral to the processor. The processor and the storage medium can reside in an ASIC. The ASIC can reside in a remote station. Alternatively, the processor and the storage medium can reside as discrete components in a remote station, a base station, or a server.

[0074] It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described can be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step can actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects can be combined. It is understood that the operational steps illustrated in the flowchart can be modified in a variety of different ways without departing from the spirit or scope of the present disclosure. It is also understood that the information and signals described herein can be represented using various technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0075] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be clear to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein and the designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0076] Implementation examples are described in the following numbered clauses: 1. A three-dimensional (3D) dual-circuit structure, comprising: a first interdigitated structure comprising at least one first semiconductor plate; a second interdigitated structure comprising at least one second semiconductor plate and disposed on a first side of the first interdigitated structure in a first direction; and a partition wall bisecting each of the at least one first semiconductor plate and the at least one second semiconductor plate in a second direction orthogonal to the first direction, wherein: the first semiconductor plate bisected by the partition wall includes a first plate portion on a first side of the partition wall comprising a first semiconductor type and a second plate portion on a second side of the partition wall comprising a second semiconductor type; the second semiconductor plate bisected by the partition wall includes a third plate portion on the first side of the partition wall comprising a third semiconductor type and a fourth plate portion on the second side of the partition wall comprising a fourth semiconductor type; and a first one of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type is a same semiconductor type as the first semiconductor type. 2. The 3D dual circuit structure of clause 1, wherein: a second one of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type is a same semiconductor type as a third one of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type. 3. The 3D dual circuit structure of clause 1 or 2, wherein the second semiconductor type is the first one of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type. 4. The 3D dual circuit structure of clause 1 or 2, wherein the third semiconductor type is the first one of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type. 5. The 3D dual circuit structure of clause 1 or 2, wherein the fourth semiconductor type is the first one of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type. 6. The 3D dual circuit structure of any one of clauses 1 to 5, the first interdigitated structure further comprising: a first gate; and a second gate; wherein: the first gate is disposed around the at least one first semiconductor plate in the first plate portion; the second gate is disposed around the at least one first semiconductor plate in the second plate portion; and the first gate is partitioned from the second gate by the partition wall. 7. The 3D dual circuit structure of clause 6, the second interdigitated structure further comprising: a third gate; and a fourth gate; wherein: the third gate is disposed around the at least one second semiconductor plate in the third plate portion; the fourth gate is disposed around the at least one second semiconductor plate in the fourth plate portion; and the third gate is separated from the fourth gate by the partition wall. 8. The 3D dual circuit structure of clause 6 or 7, further comprising: a first type work function metal disposed between the first gate and the at least one first semiconductor plate in the first plate portion; and the first type work function metal is disposed in a first one of the second plate portion, the third plate portion, and the fourth plate portion, the first one comprising the first one of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type. 9. The 3D dual circuit structure of clause 8, further comprising: a second type work function metal, different from the first type work function metal, disposed in a second one and a third one of the second plate portion, the third plate portion, and the fourth plate portion. 10. The 3D dual circuit structure of clause 7, further comprising a bonding layer, wherein: the first interdigitated structure is disposed in a first dielectric layer; the second interdigitated structure is disposed in a second dielectric layer; and the bonding layer is disposed between the first dielectric layer and the second dielectric layer. 11. The 3D dual circuit structure of clause 10, the bonding layer further comprising: a first gate-to-gate contact electrically coupling the first gate to the third gate; and a second gate-to-gate contact electrically coupling the second gate to the fourth gate. 12. The 3D dual circuit structure of clause 10 or 11, wherein the partition wall extends through the bonding layer. 13. The 3D dual circuit structure of any one of clauses 7 to 12, further comprising: a first contact layer disposed on the first interdigitated structure, the first contact layer comprising: a first gate contact coupled to the first gate; and a second gate contact coupled to the second gate; and a second contact layer disposed on the second interdigitated structure, the second contact layer comprising: a third gate contact coupled to the third gate; and a fourth gate contact coupled to the fourth gate. 14. The 3D dual circuit structure of clause 13, further comprising: a first source / drain coupled to each of the at least one first semiconductor plate in the first plate portion on a first side of the first gate; a second source / drain coupled to each of the at least one first semiconductor plate in the first plate portion on a second side of the first gate; a third source / drain coupled to each of the at least one first semiconductor plate in the second plate portion on a first side of the second gate; a fourth source / drain coupled to each of the at least one first semiconductor plate in the second plate portion on a second side of the second gate; a fifth source / drain coupled to each of the at least one second semiconductor plate in the third plate portion on a first side of the third gate; a sixth source / drain coupled to each of the at least one second semiconductor plate in the third plate portion on a second side of the third gate; a seventh source / drain coupled to each of the at least one second semiconductor plate in the fourth plate portion on a first side of the fourth gate; and an eighth source / drain coupled to each of the at least one second semiconductor plate in the fourth plate portion on a second side of the fourth gate. 15. The 3D dual circuit structure of clause 14, wherein: the first contact layer further comprises: a first source / drain contact coupled to the first source / drain; a second source / drain contact coupled to the second source / drain; a third source / drain contact coupled to the third source / drain; and a fourth source / drain contact coupled to the fourth source / drain; and the second contact layer further comprises: a fifth source / drain contact coupled to the fifth source / drain; a sixth source / drain contact coupled to the sixth source / drain; a seventh source / drain contact coupled to the seventh source / drain; and an eighth source / drain contact coupled to the eighth source / drain. 16. The 3D dual-circuit structure of clause 15, further comprising: a first via coupling the first source / drain contact to the fifth source / drain contact; and a second via coupling the third source / drain contact to the seventh source / drain contact. 17. The 3D dual-circuit structure of clause 10 or 12, wherein: the first gate is electrically isolated from the third gate through the bonding layer; and the second gate is electrically isolated from the fourth gate through the bonding layer. 18. The 3D dual-circuit structure of any of clauses 1-17, integrated into a device selected from a set consisting of: a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cell phone, a smartphone, a voice over internet protocol (VoIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computer, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter. 19. A method of fabricating a 3D dual-circuit structure, the method comprising: forming a first fin structure comprising at least one first semiconductor plate; forming a second fin structure comprising at least one second semiconductor plate and disposed on a first side of the first fin structure in a first direction; and forming a partition wall bisecting the at least one first semiconductor plate and the at least one second semiconductor plate in a second direction orthogonal to the first direction, wherein: the first semiconductor plate bisected by the partition wall comprises a first plate portion comprising a first semiconductor type on a first side of the partition wall and a second plate portion comprising a second semiconductor type on a second side of the partition wall; the second semiconductor plate bisected by the partition wall includes a third plate portion on the first side of the partition wall comprising a third semiconductor type and a fourth plate portion on the second side of the partition wall comprising a fourth semiconductor type; and a first one of the second semiconductor type, the third semiconductor type and the fourth semiconductor type is the same semiconductor type as the first semiconductor type. 20. An integrated circuit (IC) comprising: a complementary logic circuit comprising a plurality of 3D dual-circuit structures, each of the 3D dual-circuit structures comprising: a first fin structure comprising at least one first semiconductor plate; a second fin structure comprising at least one second semiconductor plate and disposed on a first side of the first fin structure in a first direction; and a partition wall bisecting the at least one first semiconductor plate on a second direction orthogonal to the first direction into a first plate portion on a first side of the partition wall comprising a first semiconductor type and a second plate portion on a second side of the partition wall comprising a second semiconductor type, and bisecting the at least one second semiconductor plate on the second direction into a third plate portion on the first side of the partition wall comprising a third semiconductor type and a fourth plate portion on the second side of the partition wall comprising a fourth semiconductor type, wherein: a first one of the second semiconductor type, the third semiconductor type and the fourth semiconductor type is the same semiconductor type as the first semiconductor type.

Claims

1. A three-dimensional (3D) dual-circuit structure, comprising: a first interdigitated structure comprising at least one first semiconductor plate; a second interdigitated structure comprising at least one second semiconductor plate and disposed on a first side of the first interdigitated structure in a first direction; and a partition wall bisecting each of the at least one first semiconductor plate and the at least one second semiconductor plate in a second direction orthogonal to the first direction, wherein: the first semiconductor plate bisected by the partition wall comprises a first plate portion on a first side of the partition wall comprising a first semiconductor type and a second plate portion on a second side of the partition wall comprising a second semiconductor type; the second semiconductor plate bisected by the partition wall comprises a third plate portion on the first side of the partition wall comprising a third semiconductor type and a fourth plate portion on the second side of the partition wall comprising a fourth semiconductor type; and a first one of the second, third, and fourth semiconductor types is a same semiconductor type as the first semiconductor type.

2. The 3D dual-circuit structure of claim 1, wherein: a second one of the second, third, and fourth semiconductor types is a same semiconductor type as a third one of the second, third, and fourth semiconductor types.

3. The 3D dual-circuit structure of claim 1, wherein the second semiconductor type is the first one of the second, third, and fourth semiconductor types.

4. The 3D dual-circuit structure of claim 1, wherein the third semiconductor type is the first one of the second, third, and fourth semiconductor types.

5. The 3D dual-circuit structure of claim 1, wherein the fourth semiconductor type is the first one of the second, third, and fourth semiconductor types.

6. The 3D dual-circuit structure of claim 1, the first interdigitated structure further comprising: a first gate; and a second gate; wherein: the first gate is disposed about the at least one first semiconductor plate in the first plate portion; the second gate is disposed about the at least one first semiconductor plate in the second plate portion; and the first gate is partitioned from the second gate by the partition wall.

7. The 3D dual-circuit structure of claim 6, the second interdigitated structure further comprising: a third gate; and a fourth gate; wherein: the third gate is disposed about the at least one second semiconductor plate in the third plate portion; the fourth gate is disposed about the at least one second semiconductor plate in the fourth plate portion; and the third gate is partitioned from the fourth gate by the partition wall.

8. The 3D dual-circuit structure of claim 6, further comprising: ​ ​ ​ a first type work function metal disposed in the first plate portion between the first gate and the at least one first semiconductor plate; and the first type work function metal is disposed in a first of the second plate portion, the third plate portion, and the fourth plate portion, the first of the second, third, and fourth semiconductor types.

9. The 3D dual circuit structure of claim 8, further comprising: a second type work function metal, different from the first type work function metal, disposed in a second and third of the second plate portion, the third plate portion, and the fourth plate portion.

10. The 3D dual circuit structure of claim 7, further comprising a bonding layer, wherein: the first interdigitated structure is disposed in a first dielectric layer; the second interdigitated structure is disposed in a second dielectric layer; and the bonding layer is disposed between the first dielectric layer and the second dielectric layer. a first gate-to-gate contact electrically coupling the first gate to the third gate; and 11. The 3D dual circuit structure of claim 10, the bonding layer further comprising: a second gate-to-gate contact electrically coupling the second gate to the fourth gate.

12. The 3D dual circuit structure of claim 10, wherein the partition wall extends through the bonding layer.

13. The 3D dual circuit structure of claim 7, further comprising: a first contact layer disposed on the first interdigitated structure, the first contact layer comprising: a first gate contact coupled to the first gate; and a second gate contact coupled to the second gate; and a second contact layer disposed on the second interdigitated structure, the second contact layer comprising: a third gate contact coupled to the third gate; and a fourth gate contact coupled to the fourth gate.

14. The 3D dual circuit structure of claim 13, further comprising: a first source / drain coupled to each of the at least one first semiconductor plate in the first plate portion on a first side of the first gate; a second source / drain coupled to each of the at least one first semiconductor plate in the first plate portion on a second side of the first gate; a third source / drain coupled to each of the at least one first semiconductor plate in the second plate portion on a first side of the second gate; a fourth source / drain coupled to each of the at least one first semiconductor plate in the second plate portion on a second side of the second gate; a fifth source / drain coupled to each of the at least one second semiconductor plate in the third plate portion on a first side of the third gate; a sixth source / drain coupled to each of the at least one second semiconductor plate in the third plate portion on a second side of the third gate; a seventh source / drain coupled to each of the at least one second semiconductor plate in the fourth plate portion on a first side of the fourth gate; and an eighth source / drain coupled to each of the at least one second semiconductor plate in the fourth plate portion on a second side of the fourth gate. and an eighth source / drain coupled to each of the at least one second semiconductor plate in the fourth plate portion on a second side of the fourth gate.

15. The 3D dual-circuit structure of claim 14, wherein: the first contact layer further comprises: a first source / drain contact coupled to the first source / drain; a second source / drain contact coupled to the second source / drain; a third source / drain contact coupled to the third source / drain; and a fourth source / drain contact coupled to the fourth source / drain; and the second contact layer further comprises: a fifth source / drain contact coupled to the fifth source / drain; a sixth source / drain contact coupled to the sixth source / drain; a seventh source / drain contact coupled to the seventh source / drain; and an eighth source / drain contact coupled to the eighth source / drain.

16. The 3D dual-circuit structure of claim 15, further comprising: a first via coupling the first source / drain contact to the fifth source / drain contact; and a second via coupling the third source / drain contact to the seventh source / drain contact.

17. The 3D dual-circuit structure of claim 10, wherein: the first gate is electrically isolated from the third gate through the bonding layer; and the second gate is electrically isolated from the fourth gate through the bonding layer.

18. The 3D dual-circuit structure of claim 1 integrated into a device selected from a set consisting of: a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cell phone, a smartphone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computer, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.

19. A method of fabricating a 3D dual-circuit structure, the method comprising: forming a first interdigitated structure comprising at least one first semiconductor plate; forming a second interdigitated structure comprising at least one second semiconductor plate and disposed on a first side of the first interdigitated structure in a first direction; and forming a partition wall bisecting the at least one first semiconductor plate and the at least one second semiconductor plate in a second direction orthogonal to the first direction, wherein: ​ ​ the first semiconductor plate bisected by the partition wall includes a first plate portion on a first side of the partition wall comprising a first semiconductor type and a second plate portion on a second side of the partition wall comprising a second semiconductor type; the second semiconductor plate bisected by the partition wall includes a third plate portion on the first side of the partition wall comprising a third semiconductor type and a fourth plate portion on the second side of the partition wall comprising a fourth semiconductor type; and a first one of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type is a same semiconductor type as the first semiconductor type.

20. An integrated circuit (IC) comprising: complementary logic circuitry comprising a plurality of 3D dual-circuit structures, each of the 3D dual-circuit structures comprising: a first fin structure comprising at least one first semiconductor plate; a second fin structure comprising at least one second semiconductor plate and disposed on a first side of the first fin structure in a first direction; and a partition wall bisecting the at least one first semiconductor plate into a first plate portion on a first side of the partition wall comprising a first semiconductor type and a second plate portion on a second side of the partition wall comprising a second semiconductor type in a second direction orthogonal to the first direction, and bisecting the at least one second semiconductor plate into a third plate portion on the first side of the partition wall comprising a third semiconductor type and a fourth plate portion on the second side of the partition wall comprising a fourth semiconductor type in the second direction, wherein: a first one of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type is a same semiconductor type as the first semiconductor type.

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