Printed circuit board wiring methods and electronic devices

Abstract

This application discloses a wiring method and electronic device for printed circuit boards, relating to the field of printed circuit technology. It can automatically partition the initial printed circuit board based on its size information and prioritize wiring according to the type label of each partition. This sequentially determines the number of clusters for the starting points of wiring in multiple partitions. By combining the clustering results with a cost function, it calculates a low-cost target wiring path plan, achieving wiring planning and automatic wiring for the printed circuit board. Therefore, it can solve the technical problems in related technologies, such as reliance on engineers' prior knowledge, high labor costs, low wiring efficiency, and significant risk of misjudgment during wiring, which affect the actual use of the printed circuit board. This method improves wiring efficiency, reduces the impact of human factors on wiring quality, and covers a wider range of printed circuit board sizes.

Description

Technical Field

[0001] This application relates to the field of printed circuit technology, and in particular to a wiring method for a printed circuit board and an electronic device. Background Technology

[0002] In related technologies, traditional algorithms are only applicable to simple printed circuit boards. There are also some machine learning-based solutions, which have solved some complex problems, but there is still room for optimization. They cannot fully adapt to the wiring requirements of ultra-high-rise and high-density printed circuit boards. They also rely on engineers' prior knowledge, resulting in high labor costs, low wiring efficiency, and are subject to human influence. There is a significant risk of misjudgment during the wiring process, which affects the actual use of printed circuit boards and urgently needs improvement. Summary of the Invention

[0003] This application provides a wiring method and electronic device for printed circuit boards, in order to at least solve the technical problems in the related art, such as reliance on engineers' prior knowledge, high labor costs, low wiring efficiency, and the risk of misjudgment during the wiring process due to human influence, which in turn affects the actual use of printed circuit boards.

[0004] This application provides a routing method for a printed circuit board, comprising the following steps: obtaining the size information of a target initial printed circuit board; inputting the size information into a pre-built circuit board partitioning model to divide the target initial printed circuit board into multiple partitions and matching the category labels of the multiple partitions; obtaining the priority coefficients of the multiple partitions according to the category labels, and sorting the multiple partitions based on the priority coefficients to obtain a routing priority sequence; determining the number of clusters of routing start points of the multiple partitions based on the routing priority sequence to obtain the clustering results of the multiple partitions; calculating the multiple inter-layer costs of the target initial printed circuit board under the constraints of the clustering results based on a pre-built cost function, and combining the preset design rules and the multiple inter-layer costs to obtain a target routing path plan that meets the preset cost optimization conditions, and routing the target initial printed circuit board based on the target routing path plan.

[0005] This application also provides a wiring apparatus for a printed circuit board, comprising: an acquisition module for acquiring the size information of a target initial printed circuit board; a classification module for inputting the size information into a pre-built circuit board partitioning model to divide the target initial printed circuit board into multiple partitions and matching the category labels of the multiple partitions; a sorting module for obtaining priority coefficients of the multiple partitions according to the category labels and sorting the multiple partitions based on the priority coefficients to obtain a wiring priority sequence; a clustering module for determining the number of clusters of the wiring start points of the multiple partitions based on the wiring priority sequence to obtain the clustering results of the multiple partitions; and a wiring module for calculating the inter-layer costs of the target initial printed circuit board under the constraints of the clustering results based on a pre-built cost function, and combining the preset design rules and the multiple inter-layer costs to obtain a target wiring path plan that meets the preset cost optimization conditions, so as to perform wiring on the target initial printed circuit board based on the target wiring path plan.

[0006] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the wiring method of any of the above-described printed circuit boards.

[0007] This application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of any of the above-described printed circuit board wiring methods.

[0008] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described printed circuit board wiring methods.

[0009] This application enables the automatic partitioning of a target initial printed circuit board (PCB) based on its size information. Routing priority is then prioritized according to the type label of each partition. Partitioning and priority ranking ensure that critical signals are routed first, improving signal integrity. Furthermore, the number of clusters for routing start points in multiple partitions is determined sequentially based on priority, thus determining the number of routing start points in each region. Through clustering, the complex routing problem is decomposed into multiple sub-problems, reducing computational complexity. Combining the clustering results with a cost function, low-cost target routing path planning is calculated, achieving routing planning and automatic routing for the PCB. Therefore, this application addresses the technical problems in related technologies, such as reliance on engineers' prior knowledge, high labor costs, low routing efficiency, and significant risk of misjudgment during routing, which negatively impact the actual use of the PCB. It achieves improved routing efficiency, reduced the impact of human factors on routing quality, and covers a wider range of PCB sizes. Attached Figure Description

[0010] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a flowchart illustrating a wiring method for a printed circuit board according to an embodiment of this application;

[0012] Figure 2 This is a flowchart of a wiring method for a printed circuit board according to an embodiment of this application;

[0013] Figure 3 This is a flowchart of an adaptive clustering method provided according to an embodiment of this application;

[0014] Figure 4 This is a schematic diagram of a wiring device for a printed circuit board according to an embodiment of this application. Detailed Implementation

[0015] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0016] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0017] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0018] It is understandable that printed circuit board wiring is the core step to achieve circuit functions, and components need to be interconnected through wires. As electronic devices develop towards "high density, multi-layer, and multi-signal types", traditional EDA (Electronic Design Automation) automatic wiring tools have three major difficulties when dealing with complex PCBs with "multi-layers (≥6 layers), multi-signal mixing (high-speed / analog / digital), and high-density pins": 1. High cost of manual intervention: Engineers need to spend weeks or even months adjusting wiring rules. Especially, the inter-layer interconnection planning of multi-layer boards (such as via positions and inter-layer signal distribution) depends on experience; 2. Low wiring efficiency: The module division, clustering parameters, etc. of existing solutions need to be set manually according to experience, and repeated debugging is required for different types of PCBs, resulting in poor adaptability; 3. Conflict between signal quality and routing completion rate: Too many vias in multi-layer boards easily lead to signal loss, while fixed restricted routing area rules easily waste routing space, resulting in some pins being unable to be routed.

[0019] In related technologies, traditional algorithms (Lee algorithm, A* algorithm) are only applicable to simple printed circuit boards. There are also some machine learning-based solutions, which, although solving some complex problems, still have room for optimization and cannot fully meet the wiring requirements of ultra-high-layer and high-density printed circuit boards.

[0020] Some automatic wiring solutions still rely on engineers' prior knowledge. When facing new types of printed circuit boards, manual rules cannot cover all scenarios, easily leading to classification errors;

[0021] Moreover, the clustering number n of kmeans needs to be calculated manually as "number of wiring starting points / 15 < n < number of wiring starting points / 5". When the pin density of the printed circuit board is uneven (such as dense pins in local areas and sparse pins in local areas), a fixed range of n will cause too large deviation in the number of points in subclasses, affecting the MAPF wiring efficiency;

[0022] The inter-layer wiring of multi-layer printed circuit boards depends on vias, without considering the "signal loss cost" (such as high-speed signal vias easily generating reflections) and "space cost" (vias occupying the area of the printed circuit board) of vias, easily leading to a decline in signal quality or waste of wiring resources;

[0023] Using "fixed boundary expansion in the up, down, left, and right directions" for the already wired area, without distinguishing signal types (such as high-speed signals requiring a wider isolation distance and low-speed signals allowing a smaller isolation), results in some areas having excessive occupation of wiring space and a reduction in the routing completion rate.

[0024] To solve the above technical problems, the wiring method of the printed circuit board proposed in the embodiments of this application can improve wiring efficiency, reduce the influence of human factors on wiring quality, and increase the range of size specifications of printed circuit boards that can be covered.

[0025] Such as Figure 1 As shown, an embodiment of this application provides a wiring method for a printed circuit board, including the following steps:

[0026] In step S101, the size information of the target initial printed circuit board is obtained.

[0027] Printed circuit boards are substrates used to support and connect electronic components.

[0028] The embodiments of this application can obtain the physical dimensions of the target initial printed circuit board that needs to be automatically routed, and then partition the target initial printed circuit board according to the physical dimensions.

[0029] In step S102, the size information is input into the pre-built circuit board partition model to divide the target initial printed circuit board into multiple partitions and match the category labels of the multiple partitions.

[0030] This application embodiment can use a circuit board partitioning model to partition the target initial printed circuit board, so that after dividing the target initial printed circuit board into multiple partitions, the corresponding partition types are matched, such as high-speed signal modules, analog signal modules, digital signal modules, etc.

[0031] Optionally, in one embodiment of this application, before dividing the target initial printed circuit board into regions using a pre-built circuit board partitioning model, the method further includes: acquiring wiring data of the sample printed circuit board; dividing the sample printed circuit board into multiple sample sub-regions that meet preset size conditions; extracting data features from the multiple sample sub-regions based on the wiring data; determining sample category labels for the multiple sample sub-regions based on the data features; and training the pre-built initial circuit board partitioning model using the sample category labels to obtain a circuit board partitioning model.

[0032] In actual implementation, the embodiments of this application can obtain two types of data from the already laid-out printed circuit board (sample printed circuit board):

[0033] Basic data: component location coordinates, initial coordinates of the keep-out area, coordinates of the wiring pair (start point / end point);

[0034] Enhanced data: Signal type of each wiring pair (high-speed / analog / digital, such as DDR5 signal is high-speed, sensor signal is analog), PCB interlayer parameters (dielectric thickness of each layer, via signal loss factor, interlayer wiring bandwidth).

[0035] Furthermore, embodiments of this application can achieve automatic classification of printed circuit board areas based on enhanced data, without the need for manual rule setting:

[0036] This application embodiment can divide the sample printed circuit board into 10mm×10mm sub-regions, and extract the "component type distribution (e.g., chip / resistor / capacitor ratio), signal type ratio (high-speed signal wiring pair ratio), and pin density (per mm)" of each sub-region. 2 Pin count) is used as an input feature;

[0037] The algorithm employs 3 convolutional layers (for extracting local features), 2 pooling layers (for dimensionality reduction), and 2 fully connected layers (for classification output) to output category labels for sub-regions (such as "high-speed signal module", "analog signal module", and "digital signal module").

[0038] Train a convolutional model by obtaining labeled data of printed circuit boards of different types. The training objective is to minimize the classification cross-entropy loss, and the model accuracy needs to be ≥95% to obtain a circuit board partitioning model.

[0039] This application embodiment, by training a circuit board partitioning model, can automatically partition and classify new printed circuit boards, reducing manual intervention. This improves the accuracy of partitioning and classification, thus providing a reliable foundation for subsequent prioritization and routing.

[0040] In step S103, priority coefficients of multiple partitions are obtained according to category labels, and the multiple partitions are sorted based on priority coefficients to obtain a wiring priority sequence.

[0041] As one possible implementation method, embodiments of this application can automatically set priorities based on category labels, with rules determined by signal characteristics. For example, high-speed signal modules (such as DDR, PCIe) have the highest priority; analog signal modules (such as sensors, amplifiers) have the next highest priority; and digital signal modules (such as MCUs, logic chips) have the lowest priority.

[0042] The priority can be quantified by the "signal sensitivity coefficient". The sensitivity coefficient for high-speed signals is 0.8, for analog signals it is 0.6, and for digital signals it is 0.4. Signals with higher coefficients are processed first.

[0043] The embodiments of this application can use partitioning and priority sorting to ensure that critical signals are routed first, thereby improving signal integrity.

[0044] In step S104, based on the routing priority sequence, the number of clusters of routing start points for multiple partitions is determined, and the clustering results of multiple partitions are obtained.

[0045] In this context, the routing start point refers to the beginning and end points of the routing, which are usually the pins of components, and the number of clusters is the number of clusters.

[0046] In actual implementation, the embodiments of this application can perform clustering calculations on the starting points of the wiring in each partition according to the order of wiring priority, so as to facilitate subsequent wiring planning.

[0047] Optionally, in one embodiment of this application, the clustering number of routing start points for multiple partitions is determined based on the routing priority sequence to obtain the clustering results of multiple partitions, including: assigning any number of routing start points to multiple partitions; calculating the sum of squares of the distances from any number of routing start points to the cluster centers of the corresponding partitions to construct a number curve based on the any number and the sum of squares; and determining the target number of multiple partitions as the clustering number based on the number curve.

[0048] The embodiments of this application can dynamically determine the number of clusters n for each partition without manual calculation:

[0049] Calculate the sum of squared errors (SSE) within the cluster: For the routing start point of each submodule, try n=2, 3, ..., 20 in sequence, and calculate the SSE for different n (SSE = Σ(Euclidean distance from each point to its cluster center)). 2 ));

[0050] The elbow rule determines the optimal n. In this embodiment, an "SSE-n" curve can be plotted, and the n corresponding to the inflection point of the curve can be used as the optimal number of clusters to ensure that the number of wiring start points in each partition is between 8 and 12.

[0051] For example, if a high-speed module has 90 wiring start points, the SSE-n curve will reach an inflection point when n=9. At this point, each subclass has about 10 start points, which is within the optimal range.

[0052] The embodiments of this application can automatically determine the number of clusters, avoiding deviations caused by manual settings. The elbow rule is used to find a balance between clustering effectiveness and computational efficiency, ensuring that the number of starting points for each sub-cluster is within a reasonable range, facilitating subsequent wiring.

[0053] In step S105, the inter-layer costs of the target initial printed circuit board under the constraints of clustering results are calculated based on the pre-built cost function. Combined with the preset design rules and the multiple inter-layer costs, a target routing path plan that meets the preset cost optimization conditions is obtained, and the target initial printed circuit board is routed based on the target routing path plan.

[0054] The cost function can be used to evaluate the quality of a routing path, and it can take into account factors such as path length, number of vias, and signal integrity.

[0055] The embodiments of this application can transform the cabling problem into a "MAPF problem considering inter-layer costs" based on clustering results and cost functions, thereby obtaining a low-cost cabling path plan that meets design rule constraints while ensuring a reasonable range of cabling starting points.

[0056] Optionally, in one embodiment of this application, the inter-layer cost of the target initial printed circuit board under the constraints of clustering results is calculated based on a pre-constructed cost function. Combined with preset design rules and multiple inter-layer costs, a target routing path plan that meets preset cost optimization conditions is obtained. This includes: treating multiple sets of routing pairs as multiple agents to transform the routing path plan into an agent path plan; calculating the cost function with collision constraints of multiple agents to obtain the path plan of multiple agents, and using the path plan as the target routing path plan.

[0057] In this embodiment, each wiring pair is positioned as a start and end point of a wiring. In path planning, each wiring pair can be considered a smart agent, whose range of motion includes all layers of the printed circuit board. Multiple smart agents simultaneously plan paths in a shared environment, ensuring that the paths do not conflict, thus achieving path planning. Furthermore, during planning, collision constraints are required to ensure that the paths between smart agents do not overlap.

[0058] Under collision constraints, the embodiments of this application can calculate the cost function (including path length, via cost, etc.), transform the wiring problem into a "MAPF problem considering inter-layer cost", realize inter-layer interconnection optimization, and simultaneously satisfy "no collision (paths of different agents do not overlap)" and "minimum inter-layer cost", and finally output the path plan for each agent.

[0059] Using the MAPF framework, this application embodiment can plan multiple paths simultaneously, avoid path conflicts, and improve deployment efficiency. Combined with a cost function, path quality (such as signal integrity and manufacturing cost) can be optimized while avoiding conflicts.

[0060] Optionally, in one embodiment of this application, before calculating the cost function based on collision constraints of multiple intelligent agents, the method further includes: obtaining the interlayer combination of the target initial printed circuit board; determining the interlayer via loss coefficient of the target initial printed circuit board based on the interlayer combination, the material of the target initial printed circuit board, and via parameters, and calculating the via space cost; calculating the via signal loss cost during interlayer switching based on the via loss coefficient and via parameters; and constructing a cost function based on the via signal loss cost, via space cost, and corresponding weighting coefficients.

[0061] It is understandable that interlayer combination refers to the arrangement of different layers in a printed circuit board; via is a conductive hole used to connect different layers; via loss factor represents the parameter of signal loss caused by via; via space cost represents the cost corresponding to the space area occupied by the via; and via signal loss cost represents the cost of signal loss caused by the via.

[0062] In actual implementation, the via cost in this application embodiment can be defined as C = α × C1 + β × C2, where:

[0063] C1 is the signal loss cost of the via, which is determined by the interlayer parameters of the printed circuit board. For example, if the via loss coefficient from the 2nd layer to the 3rd layer is 0.1, then C1 = 0.1.

[0064] C2 is the via space cost. When the via diameter is 0.3mm, C2 = 0.3. The larger the diameter, the higher the cost.

[0065] α=0.6, β=0.4, which can be finely adjusted according to the requirements of the printed circuit board, but α+β=1 must be satisfied;

[0066] The cost function in this embodiment can be used in MAPF, and the cost will be accumulated when the agent needs to switch layers.

[0067] The embodiments of this application can quantify the cost of vias, including signal loss and space occupation, making path planning more in line with electrical and manufacturing requirements, and flexibly emphasizing signal integrity or space utilization according to design needs by adjusting the weighting coefficients.

[0068] Optionally, in one embodiment of this application, routing a target initial printed circuit board based on a target routing path plan includes: calculating a no-wiring area of ​​the target initial printed circuit board based on the target routing path plan; optimizing the target routing path plan based on the no-wiring area to obtain a new path plan, so as to use the new path plan to route the target initial printed circuit board.

[0069] The no-wiring zone is an area where wiring is not allowed, in order to prevent signal interference.

[0070] In actual implementation, embodiments of this application can extract features of the already routed paths, such as signal type, line width, signal frequency, routing layer information, and path geometry. Based on these features, embodiments of this application can calculate the dynamic ban width, thereby generating ban regions.

[0071] After generating the no-wiring zone, this embodiment of the application can detect whether there is a conflict between the target wiring path plan and the no-wiring zone. Then, if there is a conflict, the target wiring path plan is optimized based on the no-wiring zone to obtain a new path plan, so that the new path plan can bypass the conflicting no-wiring zone.

[0072] The no-closing zones in this application embodiment can avoid interference between signals and improve signal integrity; by dynamically generating no-closing zones, this application embodiment can make more effective use of space and avoid wasting space.

[0073] Optionally, in one embodiment of this application, calculating the keep-out area of ​​the target initial printed circuit board based on the target wiring path planning includes: obtaining the signal type of the wiring on the target initial printed circuit board; calculating the keep-out width based on the signal type; expanding the preset width area on both sides of the wiring into a buffer zone to generate a keep-out strip; calculating the corresponding via keep-out area based on the via parameters and via signal type of the target initial printed circuit board; and combining the keep-out strip and the via keep-out area to obtain the keep-out area.

[0074] The width of the restricted area (restricted area width) is calculated as follows: d = w + k × f.

[0075] Where w is the width of the routed trace, such as 0.2mm for high-speed signals; f is the signal frequency, such as 3200MHz for DDR5 signals; and k is the signal isolation coefficient, with k=0.05×10 for high-speed signals. -6 The analog signal k = 0.03 × 10 -6 The digital signal k = 0.01 × 10 -6 .

[0076] For example, the kill width d of a high-speed signal line (w=0.2mm, f=3200MHz) is 0.2 + 0.05 × 10 -6 ×3200×10 6 =0.2 + 0.16 = 0.36 mm; d = 0.1 + 0.01 × 10 for digital signal line (w = 0.1 mm, f = 100 MHz). -6 ×100×10 6 =0.1+0.01=0.11mm, which significantly saves space.

[0077] In this embodiment, the existing wiring can be extended to both sides by d / 2 to form a cloth hold strip. Simultaneously, for vias, the cloth hold area around the via is calculated based on its signal type and parameters (such as diameter). Finally, the cloth hold strip and the via cloth hold area are merged to obtain a complete cloth hold area.

[0078] The embodiments of this application can clearly define the no-distribution area through accurate calculation, so as to ensure the safe isolation between different signal types, avoid signal crosstalk and interference, and improve circuit performance.

[0079] Optionally, in one embodiment of this application, optimizing the target wiring path planning based on the no-wiring area to obtain a new path plan includes: marking the no-wiring area as impassable; checking whether the agent's current path intersects with the no-wiring area; if they intersect, marking the current path as needing rewiring to obtain a path to be processed; and using a preset path search algorithm, under the constraints of the no-wiring area and preset design rules, correcting the path to be processed to obtain a new path plan.

[0080] The design rules can include multiple aspects such as electrical, physical, manufacturing, signal integrity, power integrity, and thermal management.

[0081] For example, determine the width of the conductors based on the current magnitude and temperature rise requirements; the minimum distance between conductors, between conductors and vias, and between vias to prevent electrical short circuits; the minimum distance between conductors, vias, etc., and the board edge; provide sufficient heat dissipation measures for heat-generating components, such as heat dissipation holes, heat dissipation copper sheets, etc.; pad size; for high-speed differential lines or parallel buses, require signal line length matching to maintain timing consistency; for high-speed signals, limit the number of vias to reduce impedance discontinuities and signal reflections; stack-up order, etc.

[0082] Design rules can be set according to different application scenarios of printed circuit boards, and can be used as routing constraints for subsequent planning.

[0083] It is understood that the no-closing area is a non-overlapping area. The embodiments of this application can check whether the path of the agent intersects with any no-closing area and calculate the severity of the conflict (overlapping area / length). The embodiments of this application can correct the unprocessed path with conflict based on the severity of the conflict.

[0084] For example, in scenarios where the severity of the conflict is relatively minor, such as when the conflict length is less than 10% of the total length, embodiments of this application can insert detour points before and after the conflict area and use a path search algorithm to find alternative paths outside the restricted area under the constraints of the restricted area and preset design rules.

[0085] For scenarios with a high degree of conflict severity, such as conflict length being greater than or equal to 10% of the total length but less than 30% of the total length, or involving sensitive signals, the embodiments of this application can assess the cost of switching to an adjacent layer and use the inter-layer cost function to calculate the switching point with the lowest cost, thereby planning a new path, such as a planar path-via-adjacent layer planar path.

[0086] For scenarios with extremely severe conflicts, such as when the conflict length is greater than or equal to 30% of the total length, or when multiple paths conflict and block each other, this application embodiment can delete all conflicting paths, then re-cluster, adjust the wiring starting point, and re-plan the path.

[0087] The embodiments of this application can ensure that the final wiring avoids restricted areas to prevent signal interference; and automatically rewiring is performed according to the severity of the problem to reduce the workload of manual adjustments and obtain an appropriate optimization solution.

[0088] Optionally, in one embodiment of this application, optimizing the target cabling path planning based on the no-cable zone to obtain a new path plan includes: determining whether the path to be processed meets the preset correction conditions under the constraints of the no-cable zone and preset design rules; if the preset correction conditions are not met, optimizing the range of the no-cable zone under the constraints of the preset design rules, or generating a cabling error reminder.

[0089] It is understandable that there are paths that are difficult to bypass the restricted area, and there are situations where the path cannot avoid the restricted area. In this application embodiment, if a path that meets the design rules (i.e., does not meet the preset correction conditions) cannot be found when attempting to rewire, the scope of the restricted area can be optimized (e.g., the width of the restricted area can be reduced if allowed) or a wiring error reminder can be generated to prompt the designer to make manual adjustments.

[0090] The embodiments of this application can improve the success rate of wiring and ensure wiring quality.

[0091] Optionally, in one embodiment of this application, the method further includes: routing the target initial printed circuit board based on the target routing path planning to obtain the actual printed circuit board, and extracting the area of ​​the routed region from the actual printed circuit board; calculating the corresponding routing space utilization rate based on the area of ​​the routed region and the total area of ​​the actual printed circuit board; and optimizing the no-route area based on the routing space utilization rate until the routing space utilization rate reaches the preset utilization standard.

[0092] This application embodiment can calculate the ratio between the area of ​​the wired area and the total area of ​​the actual printed circuit board to obtain the wired space utilization rate and determine whether a certain space utilization standard (e.g., 80%) has been reached. If not, this application embodiment can adjust k in the calculation formula of the wired area width to optimize the wired area while ensuring signal integrity, and then rewire to determine whether the wired space utilization rate has reached the utilization standard.

[0093] In practical implementation, embodiments of this application can prioritize optimizing the exclusion zone that has a smaller impact on signal integrity, such as the exclusion zone for low-frequency digital signals. For high-speed signals, reducing their exclusion zone is prohibited.

[0094] The embodiments of this application can improve the space utilization efficiency of printed circuit boards, avoid overly conservative layout settings, and save space while ensuring quality.

[0095] Optionally, in one embodiment of this application, the method further includes: extracting the routed wiring and total wiring from the actual printed circuit board; calculating the corresponding routing rate based on the routed wiring and total wiring; using the via and conductor loss of the actual printed circuit board as the average signal loss; determining whether the actual printed circuit board meets the preset optimization conditions based on the routing rate and / or the average signal loss; if the preset optimization conditions are met, optimizing the clustering range of the routing starting point based on the routing rate and / or the average signal loss, or optimizing the weight of the cost function until the preset optimization conditions are no longer met.

[0096] The routing completion rate is the proportion of completed routing pairs to the total number of routing pairs, and the average signal loss is the total loss of vias and conductors. This application embodiment can establish a feedback optimization mechanism for routing quality. Routing quality is evaluated through routing completion rate and signal loss; if it does not meet the standards, the clustering parameters or cost function weights are adjusted, and routing optimization is performed again.

[0097] If the coverage rate is less than 98%, the clustering range of the adaptive k-means is readjusted and the above steps are repeated; if the average signal loss is greater than 0.2 dB, the weight of C1 in the inter-layer cost function is increased (α=0.7), and the inter-layer path is replanned.

[0098] The embodiments of this application can realize closed-loop control of wiring quality to adaptively adjust and optimize parameters.

[0099] Optionally, in one embodiment of this application, the method further includes: acquiring the signal waveform of the high-speed signal passing through the actual printed circuit board; determining whether the actual printed circuit board meets the preset signal integrity conditions based on the signal waveform; and, if the preset signal integrity conditions are not met, using the signal waveform as a wiring constraint to optimize the target wiring path planning.

[0100] In this embodiment of the application, after the wiring is completed, the actual printed circuit board can be tested to obtain multiple sets of waveform data of key test points (such as clock lines, data buses, etc.).

[0101] Analyzing waveform data reveals waveform problems to determine the cause of signal incompleteness, such as insufficient line spacing or excessively long parallel traces. Based on these causes, embodiments of this application can adjust the routing path planning for similar printed circuit boards to enable mass production after determining a reasonable planning method.

[0102] The embodiments of this application can optimize the design based on actual test data to improve the actual performance of the product. The optimized design can be mass-produced to improve wiring efficiency.

[0103] Combination Figure 2 and Figure 3 As shown, a wiring method for a printed circuit board according to an embodiment of this application will be described in detail.

[0104] Step S201, data input. This embodiment of the application can obtain two types of data from a pre-laid-out printed circuit board (sample printed circuit board):

[0105] Basic data: component location coordinates, initial coordinates of the keep-out area, coordinates of the wiring pair (start point / end point);

[0106] Enhanced data: Signal type of each wiring pair (high-speed / analog / digital, such as DDR5 signal is high-speed, sensor signal is analog), PCB interlayer parameters (dielectric thickness of each layer, via signal loss factor, interlayer wiring bandwidth).

[0107] Step S202, intelligent classification. This embodiment of the application can achieve automatic classification of printed circuit board areas based on augmented data, without the need for manual rule setting:

[0108] This application embodiment can divide the sample printed circuit board into 10mm×10mm sub-regions, and extract the "component type distribution (e.g., chip / resistor / capacitor ratio), signal type ratio (high-speed signal wiring pair ratio), and pin density (per mm)" of each sub-region. 2 Pin count) is used as an input feature;

[0109] The algorithm employs 3 convolutional layers (for extracting local features), 2 pooling layers (for dimensionality reduction), and 2 fully connected layers (for classification output) to output category labels for sub-regions (such as "high-speed signal module", "analog signal module", and "digital signal module").

[0110] Train a convolutional model by obtaining labeled data of printed circuit boards of different types. The training objective is to minimize the classification cross-entropy loss, and the model accuracy must be ≥95%.

[0111] This application embodiment can automatically set priorities based on classification results, with the rules determined by signal characteristics:

[0112] High-speed signal modules (such as DDR and PCIe) have the highest priority;

[0113] Analog signal modules (such as sensors and amplifiers) are of secondary priority;

[0114] Digital signal modules (such as MCUs and logic chips) have the lowest priority.

[0115] Priority can be quantified by the "signal sensitivity coefficient". The sensitivity coefficient for high-speed signals is 0.8, for analog signals it is 0.6, and for digital signals it is 0.4. Signals with higher coefficients are processed first.

[0116] This application embodiment can extract features such as component type distribution, signal type ratio, and pin density of the target initial printed circuit board partition to construct a convolutional neural network model of "3 convolutional layers + 2 pooling layers + 2 fully connected layers," achieving automatic classification of the target initial printed circuit board without the need for manual setting of prior rules. This allows for automatic adaptation to different types of printed circuit boards, with a classification accuracy of ≥95%, reducing manual intervention.

[0117] Step S203, adaptive clustering. For example... Figure 3 As shown in the embodiment of this application, the number of clusters n for each partition can be dynamically determined without manual calculation:

[0118] Calculate the sum of squared errors (SSE) within a cluster: For the routing start point of each partition, try n=2, 3, ..., 20 in sequence, and calculate the SSE for different n (SSE = Σ(Euclidean distance from each point to its cluster center)). 2 ));

[0119] The elbow rule determines the optimal n: Plot the "SSE-n" curve, find the n corresponding to the inflection point of the curve as the optimal number of clusters, and ensure that the number of wiring start points for each subclass is between 8 and 12.

[0120] For example, if a high-speed module has 90 wiring start points, the SSE-n curve will have an inflection point when n=9. At this point, each subclass has about 10 start points, which is within the optimal range.

[0121] This application embodiment can first calculate the sum of squared errors (SSE) within clusters corresponding to different numbers of clusters n (n=2 to 20) for the routing start point of each partition, and then dynamically determine the optimal number of clusters n through the "elbow rule" (finding the inflection point where the SSE decrease rate suddenly changes), without manual calculation. This automatically determines the optimal n, stabilizing the number of sub-cluster points at 8-12, thus improving the routing efficiency of MAPF.

[0122] Step S204, optimize routing. Transform the partitioned routing problem into a "MAPF problem considering inter-layer costs," achieving inter-layer interconnection optimization:

[0123] Multi-agent modeling: Each wiring pair is considered as an "agent", and the agent's range of motion includes all layers of the printed circuit board;

[0124] Interlayer cost function: Define via cost C = α × C1 + β × C2, where:

[0125] C1 is the signal loss cost of the via, which is determined by the interlayer parameters of the PCB. For example, if the via loss coefficient from the 2nd layer to the 3rd layer is 0.1, then C1 = 0.1.

[0126] C2 is the via space cost. When the via diameter is 0.3mm, C2 = 0.3. The larger the diameter, the higher the cost.

[0127] α=0.6, β=0.4, which can be finely adjusted according to the requirements of the printed circuit board, but α+β=1 must be satisfied;

[0128] When searching for paths, the agent must simultaneously satisfy "no collision (paths of different agents do not overlap)" and "minimum inter-layer cost", and finally output each agent's "inter-layer path + planar path" (such as "2nd layer planar routing → via to 3rd layer → 3rd layer planar routing").

[0129] The embodiments of this application can prioritize the inter-layer path with the lowest cost in multi-agent path planning, reduce via signal loss, and improve the space utilization of printed circuit boards.

[0130] Step S205: Dynamic ban zone generation. This embodiment of the application can adjust the ban zone range based on the signal type of the existing cabling, avoiding wasted space.

[0131] Calculation of the width of the restricted area: d = w + k × f, where:

[0132] w represents the width of the wired trace, such as 0.2mm for high-speed signal traces.

[0133] f is the signal frequency, such as DDR5 signal frequency = 3200MHz;

[0134] k is the signal isolation coefficient; for high-speed signals, k = 0.05 × 10⁻⁶. -6 The analog signal k = 0.03 × 10 -6 The digital signal k = 0.01 × 10 -6 ;

[0135] For example, the allowable width d for a high-speed signal line (w=0.2mm, f=3200MHz) is 0.2 + 0.05 × 10 -6 ×3200×10 6 =0.2 + 0.16 = 0.36 mm; d = 0.1 + 0.01 × 10 for digital signal line (w = 0.1 mm, f = 100 MHz). -6 ×100×10 6 =0.1+0.01=0.11mm, which significantly saves space.

[0136] The embodiments of this application can differentiate and adjust the no-clothing range to avoid wasting space caused by fixed no-clothing rules.

[0137] Step S206, Dynamic Effect Feedback. After all partition routing is completed, evaluate the routing effect:

[0138] Evaluation metrics: Route completion rate = Route pairs completed / Total route pairs; Average signal loss is the total loss of vias and conductors; Route space utilization rate = Route area / Total printed circuit board area.

[0139] Feedback adjustment: If the coverage rate is <98%, then readjust the clustering range of the adaptive k-means and repeat steps S204-S206; if the average signal loss is >0.2dB, then increase the weight of C1 in the inter-layer cost function (α=0.7) and replan the inter-layer path.

[0140] Step S207, cabling complete. Repeat the above steps until all zones are cabled and the cabling performance meets the evaluation criteria, specifically: cabling completion rate ≥ 98%, average signal loss ≤ 0.2dB, and space utilization ≥ 80%.

[0141] In summary, compared to related technologies, which suffer from drawbacks such as reliance on manual module classification, unreasonable clustering parameters, high inter-layer interconnection losses, and wasted wiring space, and are difficult to adapt to scenarios involving "ultra-high-rise printed circuit boards" and "mixed-signal printed circuit boards (high-speed + analog + digital coexistence)," this invention, through the aforementioned improvements and optimizations, reduces manual intervention costs, improves wiring efficiency and signal quality, and fills the technological gap in automated wiring for ultra-high-rise and mixed-signal printed circuit boards, providing a reliable solution for the automated design of high-density, complex types of printed circuit boards.

[0142] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0143] like Figure 4 As shown, embodiments of this application also provide a wiring device 10 for a printed circuit board, including: a first acquisition module 100, a classification module 200, a sorting module 300, a clustering module 400, and a wiring module 500.

[0144] Specifically, the first acquisition module 100 is used to acquire the size information of the target initial printed circuit board.

[0145] The classification module 200 is used to input size information into a pre-built circuit board partition model to divide the target initial printed circuit board into multiple partitions and match the category labels of the multiple partitions.

[0146] The sorting module 300 is used to obtain the priority coefficients of multiple partitions based on the category labels, and to sort the multiple partitions based on the priority coefficients to obtain the wiring priority sequence.

[0147] Clustering module 400 is used to determine the number of clusters for the starting points of multiple partitions based on the routing priority sequence, and to obtain the clustering results for multiple partitions.

[0148] The routing module 500 is used to calculate the inter-layer cost of the target initial printed circuit board under the constraints of the clustering results based on the pre-built cost function. Combined with the preset design rules and the multiple inter-layer costs, a target routing path plan that meets the preset cost optimization conditions is obtained, and the target initial printed circuit board is routed based on the target routing path plan.

[0149] Optionally, in one embodiment of this application, the wiring device 10 of the printed circuit board further includes: a second acquisition module, a division module, a first extraction module, a determination module, and a training module.

[0150] The second acquisition module is used to acquire the wiring data of the sample printed circuit board.

[0151] The partitioning module is used to divide the sample printed circuit board into multiple sample sub-regions that meet preset size conditions.

[0152] The first extraction module is used to extract data features from multiple sample sub-regions based on wiring data.

[0153] The determination module is used to determine the sample category label of multiple sample sub-regions based on data features.

[0154] The training module is used to train the pre-built initial circuit board partitioning model using sample category labels to obtain the circuit board partitioning model.

[0155] Optionally, in one embodiment of this application, the clustering module 400 includes: an assignment unit, a first calculation unit, and a determination unit.

[0156] The assignment unit is used to assign any number of wiring start points to multiple partitions.

[0157] The first calculation unit is used to calculate the sum of squares of the distances from any number of wiring start points to the cluster center of the corresponding partition, so as to construct a quantity curve based on any number and the sum of squares.

[0158] The unit is determined based on the quantity curve to determine the target number of multiple partitions as the number of clusters.

[0159] Optionally, in one embodiment of this application, the wiring module 500 includes: a conversion unit and a second computing unit.

[0160] The conversion unit is used to treat multiple sets of wiring pairs as multiple agents to convert wiring path planning into agent path planning.

[0161] The second computing unit is used to calculate the cost function with collision constraints of multiple agents to obtain the path planning of multiple agents, and to use the path planning as the target wiring path planning.

[0162] Optionally, in one embodiment of this application, the wiring module 500 further includes: an acquisition unit, a third calculation unit, a fourth calculation unit, and a construction unit.

[0163] The acquisition unit is used to acquire the interlayer combination of the target initial printed circuit board.

[0164] The third calculation unit is used to determine the interlayer via loss coefficient of the target initial printed circuit board based on the interlayer combination, the material of the target initial printed circuit board, and the via parameters, and to calculate the via space cost.

[0165] The fourth calculation unit is used to calculate the via signal loss cost during interlayer switching based on the via loss coefficient and via parameters.

[0166] The construction unit is used to construct a cost function based on the via signal loss cost, via space cost, and corresponding weighting coefficients.

[0167] Optionally, in one embodiment of this application, the wiring module 500 includes a fifth computing unit and an optimization unit.

[0168] The fifth calculation unit is used to calculate the no-wiring area of ​​the target initial printed circuit board based on the target wiring path planning.

[0169] The optimization unit is used to optimize the target wiring path planning based on the restricted area to obtain a new path plan, so as to use the new path plan to route the target initial printed circuit board.

[0170] Optionally, in one embodiment of this application, the fifth calculation unit includes: a first acquisition subunit, a first calculation subunit, a generation subunit, a second calculation subunit, and a second acquisition subunit.

[0171] The first acquisition subunit is used to acquire the signal types that have been wired on the target initial printed circuit board.

[0172] The first calculation subunit is used to calculate the ban width based on the signal type.

[0173] The generated sub-unit is used to expand the preset width area on both sides of the already wired area into a buffer zone to generate a no-wiring strip.

[0174] The second calculation subunit is used to calculate the corresponding via-cancellation area based on the via parameters and via signal type of the target initial printed circuit board.

[0175] The second acquisition subunit is used to combine the fabric-blocking tape and the through-hole fabric-blocking area to obtain the fabric-blocking area.

[0176] Optionally, in one embodiment of this application, the optimization unit includes: a first marking subunit, a checking subunit, a second marking subunit, and a correction subunit.

[0177] The first marking subunit is used to mark the restricted area as impassable.

[0178] The inspection sub-unit is used to check whether the agent's current path intersects with the no-closing zone.

[0179] The second marking sub-unit is used to mark the current path as needing rerouting in the case of intersection, so as to obtain the path to be processed.

[0180] The correction subunit is used to correct the path to be processed under the constraints of the restricted area and the preset design rules by using a preset path search algorithm to obtain a new path plan.

[0181] Optionally, in one embodiment of this application, the optimization unit includes a judgment subunit and an optimization subunit.

[0182] The judgment subunit is used to determine whether the path to be processed meets the preset correction conditions under the constraints of the restricted area and the preset design rules.

[0183] The optimization sub-unit is used to optimize the range of the restricted area or generate wiring error alerts when the preset correction conditions are not met, based on preset design rules.

[0184] Optionally, in one embodiment of this application, the wiring device 10 of the printed circuit board further includes: a second extraction module, a calculation module, and a first optimization module.

[0185] The second extraction module is used to perform routing on the target initial printed circuit board based on the target routing path planning to obtain the actual printed circuit board, and extract the area of ​​the routed region from the actual printed circuit board.

[0186] The first calculation module is used to calculate the corresponding wiring space utilization rate based on the area of ​​the wired area and the total area of ​​the actual printed circuit board.

[0187] The first optimization module is used to optimize the no-cable zone based on the cabling space utilization rate until the cabling space utilization rate reaches the preset utilization standard.

[0188] Optionally, in one embodiment of this application, the wiring device 10 of the printed circuit board further includes: a third extraction module, a second calculation module, a third acquisition module, a first judgment module, and a second optimization module.

[0189] The third extraction module is used to extract the routed wiring and the total wiring from the actual printed circuit board.

[0190] The second calculation module is used to calculate the corresponding routing rate based on the already routed cabling and the total cabling.

[0191] The third acquisition module is used to take the via and wire loss of the actual printed circuit board as the average signal loss.

[0192] The first judgment module is used to determine whether the actual printed circuit board meets the preset optimization conditions based on the routing rate and / or average signal loss.

[0193] The second optimization module is used to optimize the clustering range of the wiring start point based on the routing rate and / or average signal loss, or to optimize the weight of the cost function, until the preset optimization conditions are no longer met, provided that the preset optimization conditions are met.

[0194] Optionally, in one embodiment of this application, the wiring device 10 of the printed circuit board further includes: a data acquisition module, a second judgment module, and a third optimization module.

[0195] The acquisition module is used to acquire the signal waveform of high-speed signals passing through the actual printed circuit board.

[0196] The second judgment module is used to determine whether the actual printed circuit board meets the preset signal integrity conditions based on the signal waveform.

[0197] The third optimization module is used to optimize the target wiring path planning by using the signal waveform as a wiring constraint when the preset signal integrity conditions are not met.

[0198] For a description of the features of the wiring device of the printed circuit board in the corresponding embodiment, please refer to the relevant description of the wiring method of the printed circuit board in the corresponding embodiment, which will not be repeated here.

[0199] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above-described printed circuit board wiring method embodiments.

[0200] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described printed circuit board wiring method embodiments when it is run.

[0201] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0202] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described printed circuit board wiring method embodiments.

[0203] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps in any of the above-described printed circuit board wiring method embodiments.

[0204] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0205] The foregoing has provided a detailed description of a printed circuit board wiring method and electronic device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A wiring method of a printed circuit board, characterized by, The method comprises the following steps: obtaining size information of a target initial printed circuit board; inputting the size information into a pre-constructed circuit board partition model to extract enhanced data of multiple partitions by using the circuit board partition model, classify the multiple partitions by using the enhanced data, divide multiple partitions of the target initial printed circuit board, and match the category labels of the multiple partitions; obtaining priority coefficients of the multiple partitions according to the category labels, and sorting the multiple partitions based on the priority coefficients to obtain a wiring priority sequence; assigning any number of wiring starting points to the multiple partitions based on the wiring priority sequence; calculating the sum of squares of distances from any number of wiring starting points to corresponding cluster centers of the multiple partitions to construct a number curve based on any number and the sum of squares; determining a balance point of clustering effect and calculation efficiency of the number curve by using an elbow rule, and determining the clustering number of the wiring starting points of the multiple partitions by using the balance point to obtain a clustering result of the multiple partitions; calculating multiple interlayer costs of the target initial printed circuit board under the constraint of the clustering result based on a pre-constructed cost function, combining a preset design rule and the multiple interlayer costs to obtain a target wiring path planning that meets a preset cost optimization condition, and wiring the target initial printed circuit board based on the target wiring path planning; The wiring of the target initial printed circuit board based on the target wiring path planning comprises: acquiring a wired signal type on the target initial printed circuit board; calculating a forbidden wiring width based on the signal type; expanding a pre-set width region on both sides of the wired signal type into a buffer zone to generate a forbidden wiring zone; calculating a corresponding via forbidden wiring region based on a via parameter and a via signal type of the target initial printed circuit board; combining the forbidden wiring zone and the via forbidden wiring region to obtain a forbidden wiring region; optimizing the target wiring path planning based on the forbidden wiring region to obtain a new path planning, and wiring the target initial printed circuit board by using the new path planning; wherein the width calculation expression of the forbidden wiring region is: wherein w represents a wired line width, f represents a signal frequency, and k represents a signal isolation coefficient.

2. The printed circuit board wiring method according to claim 1, wherein before dividing the target initial printed circuit board into regions by using the pre-constructed circuit board partition model, the method further comprises: obtaining wiring data of a sample printed circuit board; dividing the sample printed circuit board into multiple sample sub-regions that meet a preset size condition; extracting data features in the multiple sample sub-regions based on the wiring data; determining sample category labels of the multiple sample sub-regions based on the data features; training a pre-constructed initial circuit board partition model by using the sample category labels to obtain the circuit board partition model.

3. The printed circuit board wiring method according to claim 1, wherein The method of calculating multiple interlayer costs of the target initial printed circuit board under the constraint of the clustering result based on a pre-constructed cost function, combining a preset design rule and the multiple interlayer costs, comprises: taking multiple groups of wiring pairs as multiple agents to convert the wiring path planning into an agent path planning; obtaining an interlayer combination of the target initial printed circuit board; determining an interlayer via loss coefficient of the target initial printed circuit board based on the interlayer combination, a material of the target initial printed circuit board, and via parameters, and calculating a via space cost; calculating a via signal loss cost when switching between layers based on the via loss coefficient and the via parameters; constructing the cost function based on the via signal loss cost, the via space cost, and corresponding weight coefficients; calculating the cost function with collision constraints of the multiple agents to obtain a path planning of the multiple agents, and taking the path planning as the target wiring path planning.

4. The printed circuit board wiring method according to claim 3, wherein The method of optimizing the target wiring path planning based on the forbidden wiring area to obtain a new path planning comprises: marking the forbidden wiring area as impassable. checking whether a current path of the intelligent agent intersects with the forbidden area; if intersecting, marking the current path as needing to be rewired to obtain a to-be-processed path; correcting the to-be-processed path under the constraints of the forbidden area and the preset design rule by using a preset path search algorithm to obtain the new path planning.

5. The printed circuit board wiring method according to claim 4, wherein The method for optimizing the target routing path planning based on the forbidden area to obtain a new path planning comprises: under the constraints of the forbidden area and the preset design rule, judging whether the to-be-processed path meets a preset correction condition; if not meeting the preset correction condition, optimizing the range of the forbidden area or generating a routing error prompt under the constraint of the preset design rule.

6. The printed circuit board wiring method according to Claim 1, wherein Further comprising: routing the target initial printed circuit board based on the target routing path planning to obtain an actual printed circuit board, extracting an area of a routed region from the actual printed circuit board; calculating a corresponding routing space utilization rate based on the area of the routed region and a total area of the actual printed circuit board; optimizing the forbidden area based on the routing space utilization rate until the routing space utilization rate reaches a preset utilization standard.

7. The printed circuit board wiring method according to claim 6, wherein Further comprising: extracting a routed via and a total via from the actual printed circuit board; calculating a corresponding via utilization rate based on the routed via and the total via; regarding a via and a wire loss of the actual printed circuit board as an average signal loss; judging whether the actual printed circuit board meets a preset optimization condition based on the via utilization rate and / or the average signal loss; if meeting the preset optimization condition, optimizing a clustering range of the routing starting point based on the via utilization rate and / or the average signal loss, or optimizing a weight of the cost function until not meeting the preset optimization condition; collecting a signal waveform of a high-speed signal passing through the actual printed circuit board; judging whether the actual printed circuit board meets a preset signal integrity condition based on the signal waveform; under the condition of not meeting the preset signal integrity condition, regarding the signal waveform as a routing constraint to optimize the target routing path planning.

8. An electronic device, comprising: comprise: a memory for storing a computer program; a processor for implementing the steps of the method for routing a printed circuit board according to any one of claims 1 to 7 when executing the computer program.

Images