Picosecond pulse generator and picosecond pulse generation method based on amplitude and phase dual compensation

Abstract

The invention relates to a picosecond pulse generator and a picosecond pulse generation method based on amplitude and phase dual compensation, and belongs to the technical field of pulse generators. The picosecond pulse generator comprises a first-order amplitude compensation module which is used for generating multi-stage pulse signals with compensated amplitudes under the trigger of a trigger signal, and fixed phase differences exist among the pulse signals; the phase compensation module is used for receiving the multi-stage pulse signal, performing phase compensation and pulse compression on the multi-stage pulse signal through a multi-dimensional nonlinear transmission network, aligning the phase of each stage of pulse signal, and compressing the pulse width to a set picosecond-stage width; and the second-order amplitude compensation module is used for receiving the multi-stage pulse signals after phase compensation and pulse compression, carrying out phase alignment on the multi-stage pulse signals again, carrying out amplitude superposition on the aligned pulse signals, and outputting picosecond-stage pulse signals meeting the expected amplitude. According to the picosecond pulse generator, generation of high-amplitude picosecond pulses can be achieved at low cost.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of pulse generators, and particularly relates to a picosecond-level pulse generator based on amplitude and phase double compensation and a generating method. BACKGROUND

[0002] In the ultra-wideband wireless communication system, semiconductor circuit testing, and security testing and analysis of fault attack resistance of cryptographic chips, the design of a pulse generator with high amplitude and extremely short rising / falling edge is a very important research content.

[0003] In the late 19th century, Italian inventor Guglielmo Marchese Marconi used long / short pulses to form a modulated envelope, forming the prototype of pulse technology. In the late 1940s, with the development of radio technology and semiconductor technology, pulse technology has been continuously developed and widely applied in the fields of communication, digital systems, radio frequency and microwave systems, semiconductor characteristic testing, etc. Pulse technology has developed from the initial discrete silicon radio frequency tube fast edge technology to the technology of special structure devices (step recovery diode, tunnel diode, avalanche tube, etc.), and then to the nonlinear transmission line and microwave integration technology.

[0004] However, the pulse generation technology based on special structure devices is limited by factors such as turn-off speed and device voltage threshold, and the pulse rise / fall time and pulse amplitude are often difficult to consider simultaneously, so that the picosecond-level pulse generator with high pulse amplitude (greater than 200V) cannot be widely applied in practical applications. SUMMARY

[0005] In view of the above analysis, the application aims to disclose a picosecond-level pulse generator based on amplitude and phase double compensation, which solves the problems of the picosecond-level pulse generator based on commercial devices in reality, such as the limited voltage threshold of a single device leading to the pulse amplitude failing to meet the design requirements, and the limited turn-off speed of the device leading to the pulse duration and rise / fall time failing to meet the design requirements.

[0006] The application discloses a picosecond-level pulse generator based on amplitude and phase double compensation, comprising:

[0007] A first-order amplitude compensation module is configured to generate a multi-stage pulse signal with compensated amplitude under the triggering of a trigger signal, and each stage of the pulse signal has a fixed phase difference between stages;

[0008] A phase compensation module is configured to receive the multi-stage pulse signal and perform phase compensation and pulse compression on the multi-stage pulse signal through a multi-dimensional nonlinear transmission network, align the phases of the pulse signals of each stage, and compress the pulse width to a set picosecond-level width;

[0009] The second-order amplitude compensation module is configured to receive the multi-stage pulse signal after phase compensation and pulse compression, perform phase alignment of the multi-stage pulse signal again, superimpose amplitudes of the aligned multi-stage pulse signals, and output a picosecond-level pulse signal meeting an expected amplitude.

[0010] Further, the first-order amplitude compensation module comprises:

[0011] The energy storage capacitor part comprises N energy storage capacitors, each of which is connected between the high-voltage power supply and the ground.

[0012] The time delay path part comprises N time delay paths, and the number of time delay devices in each time delay path forms an arithmetic sequence, so that the time delay difference between adjacent two time delay paths is a fixed time difference Δt0. The time delay path part performs time delay processing on the input external trigger signal to generate N-stage trigger signals with a fixed phase difference.

[0013] The device cascade part comprises N stages of parallel switch circuits, and each stage of switch circuit comprises p series-connected field effect transistors.

[0014] The corresponding connection relationship between each stage of switch circuit and one time delay path and one energy storage capacitor is that the output end of the time delay path is connected to the gate of the p series-connected field effect transistors in the switch circuit, and the series circuit of the p series-connected field effect transistors is connected between the positive and negative poles of the energy storage capacitor.

[0015] The control relationship is that after the energy storage capacitor is pre-charged, the switch circuit establishes a discharge path for the energy storage capacitor under the trigger of the trigger signal output by the time delay path, the energy storage capacitor discharges, and a discharge pulse is output.

[0016] The N energy storage capacitors discharge in sequence to output multi-stage pulse signals with a fixed phase difference.

[0017] Further, the multi-dimensional nonlinear transmission network of the phase compensation module comprises N nonlinear transmission lines.

[0018] Each nonlinear transmission line corresponds to a stage of pulse signal; a reverse-biased varactor diode is connected across the nonlinear transmission line, and the capacitance of the varactor diode changes linearly with the signal level, so as to compress and compensate the phase of the pulse.

[0019] After each nonlinear transmission line respectively compresses and compensates the input pulse, the phases of the multi-stage pulse signals are aligned, and the pulse width is compressed to a set picosecond-level width.

[0020] Further, the design process of the multi-dimensional nonlinear transmission network of the phase compensation module comprises:

[0021] Step S1: determining the high-end cutoff frequency of the pulse signal according to the rising edge time of the expected output pulse.

[0022] Step S2, selecting a varactor diode meeting the cutoff frequency requirement;

[0023] Step S3, calculating the capacitance and inductance of the unit length lossless transmission line according to the dielectric constant of the PCB material;

[0024] Step S4, setting the embedding interval of the varactor diode, and calculating the capacitance and inductance of the single-section lossless transmission line;

[0025] Step S5, calculating the rising edge compression time of the single-section nonlinear transmission line;

[0026] Step S6, determining the number of nonlinear transmission lines meeting the phase compensation and pulse compression.

[0027] Further, in step S1, the high-end cutoff frequency f h ≈0.45 / tr out ; tr out is the expected output pulse rising edge time;

[0028] In step S2, the cutoff frequency f c of the selected varactor diode, the cutoff frequency f g of the nonlinear transmission line, and the high-end cutoff frequency f h of the pulse signal meet:

[0029]

[0030] In step S3, when the load is 50Ω, the capacitance and inductance of the unit length lossless transmission line C0 are respectively:

[0031]

[0032] Wherein, ε r is the dielectric constant of the selected PCB material;

[0033] In step S4, the capacitance C d and inductance L d of the single-section lossless transmission line are respectively:

[0034] C d =C0*d, L d =L0*d

[0035] Wherein, d is the embedding interval of the varactor diode on the PCB;

[0036] In step S5, the rising edge compression time of the single-section nonlinear transmission line is:

[0037]

[0038] Wherein, vA , v B respectively represent the level values of the top and bottom of the compressed signal; b is a constant factor, C j0 is the zero-bias junction capacitance of the varactor;

[0039] In step S6, the time difference between the pulse signal of the current stage entering the nonlinear transmission line and the pulse signal of the previous stage, plus the time difference between the rising edge of the pulse signal of the current stage entering the nonlinear transmission line and the desired output pulse signal, is divided by the rising edge compression time of the single-stage nonlinear transmission line, and then rounded off; the number of nonlinear transmission lines that satisfy phase compensation and pulse compression is determined.

[0040] Further, the second-order amplitude compensation module comprises a carrier delay module and a delay capacitor pairing module.

[0041] The carrier delay module comprises N carrier delay branches, and each carrier delay branch is connected to a corresponding nonlinear transmission line in the phase compensation module through a lossless transmission line.

[0042] The delay capacitor pairing module comprises N capacitor units, and each capacitor unit is connected to a corresponding carrier delay branch.

[0043] Further, in the carrier delay module, each carrier delay branch has a corresponding inductance value for re-aligning the phase of each stage of pulse signals.

[0044] In the delay capacitor pairing module, each capacitor unit has the same capacitance value for generating a final pulse output through pulse time-varying electric field induction and carrier superposition.

[0045] Further, in the delay capacitor pairing module, the capacitance value of the capacitor unit is:

[0046]

[0047] where V D is the expected amplitude; t r is the rise time of the field effect transistor in the first-order amplitude compensation module; N is the number of stages of the switching circuit in the first-order amplitude compensation module, and p is the number of field effect transistors included in each stage of the switching circuit; V B is the breakdown threshold voltage of each group of field effect transistors after cascading; and R is the impedance of the load.

[0048] Further, in the carrier delay module, the inductance values L i and L j in the i-th and j-th carrier delay branches satisfy the following relationship:

[0049]

[0050] wherein C is the capacitance value of the capacitive unit, L b , C b respectively represent the inductance and capacitance values corresponding to the length difference of the lossless transmission lines connected to the i-th and j-th carrier delay branches.

[0051] The application also discloses a pulse generating method using the picosecond-level pulse generator.

[0052] Step 1: Under the action of a reference high voltage, the energy storage capacitor part of the first-order amplitude compensation module starts pre-charging.

[0053] Step 2: An external trigger signal flows through the time delay path part of the first-order amplitude compensation module, and reaches the base of each group of cascade field effect transistors in the device cascade part with a fixed phase difference under the action of the time delay device in each time delay path.

[0054] Step 3: Under the action of the trigger signal, each group of cascade field effect transistors is instantaneously turned on, and the pre-charged carriers in the energy storage capacitor part are instantaneously introduced into the power ground plane through the collector-emitter path of the cascade field effect transistors, thereby generating multi-stage pulse signals with a fixed phase difference.

[0055] Step 4: After receiving the pulse signals output by the first-order amplitude compensation module, the phase compensation module makes each stage of pulse signals flow through a multi-dimensional nonlinear transmission network, and performs phase compensation and pulse compression of each stage of pulse signals under the action of the nonlinear transmission network, aligns the phases of each stage of pulse signals, and compresses the pulse width to a set picosecond-level width.

[0056] Step 5: The multi-stage pulse signals after phase compensation reach the second-order amplitude compensation module and enter the carrier delay module of the second-order amplitude compensation module.

[0057] Step 6: The carrier delay module aligns the phases of each stage of pulse signals flowing therethrough again by selecting the inductance parameters of each branch path.

[0058] Step 7: Each stage of pulse signals flowing through the carrier delay module simultaneously reaches the delay capacitor pairing module of the second-order amplitude compensation module, and under the induction of the pulse time-varying electric field and the superposition of carriers, a picosecond-level pulse signal meeting the expected amplitude is generated at the output end of the second-order amplitude compensation module.

[0059] The application can achieve at least one of the following beneficial effects:

[0060] The present application fully considers the problems that the pulse amplitude cannot reach the design requirement due to the limited voltage withstand value of a single device, and the pulse duration and rise / fall time cannot reach the design requirement due to the limited turn-off speed of the device in the design of a picosecond pulse generator based on a commercial device, and establishes a picosecond pulse generation method combining amplitude compensation and phase compensation, which can realize the generation of a picosecond pulse with a higher amplitude at a smaller cost.

[0061] The present application establishes a dual compensation mechanism of amplitude and phase, which can be compatible with current pulse generation systems with low amplitude and long duration, and avoids the capital and time cycle pressure caused by redesign during the upgrading process of the current pulse generation system.

[0062] Through two-stage pulse amplitude enhancement and pulse phase adjustment, a pulse signal with an amplitude greater than 200V, a pulse duration less than 600ps and a rise / fall time less than 120ps can be well generated, which greatly improves the pulse generation efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0063] The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application, and, together with the description, to specify the application.

[0064] Figure 1 The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application, and, together with the description, to specify the application.

[0065] Figure 2 The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application, and, together with the description, to specify the application.

[0066] Figure 3 The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application, and, together with the description, to specify the application.

[0067] Figure 4 The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application, and, together with the description, to specify the application.

[0068] Figure 5 The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application, and, together with the description, to specify the application.

[0069] Figure 6 The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application, and, together with the description, to specify the application. DETAILED DESCRIPTION

[0070] The preferred embodiments of the present application will be specifically described below in conjunction with the accompanying drawings, wherein the drawings constitute a part of this application and are used to illustrate the principles of the embodiments of the present application.

[0071] This invention discloses a picosecond-level pulse generator based on dual amplitude and phase compensation, such as... Figure 1 As shown, it includes:

[0072] A first-order amplitude compensation module is used to generate multi-level pulse signals with compensated amplitudes when triggered by a trigger signal, wherein each level of the pulse signal has a fixed phase difference.

[0073] The phase compensation module is used to receive the multi-level pulse signal and perform phase compensation and pulse compression on the multi-level pulse signal through a multi-dimensional nonlinear transmission network, align the phase of each level of pulse signal, and compress the pulse width to a set picosecond level width.

[0074] The second-order amplitude compensation module is used to receive multi-level pulse signals after phase compensation and pulse compression, perform phase alignment of the multi-level pulse signals again, and superimpose the amplitudes of the aligned pulse signals to output a picosecond-level pulse signal that meets the expected amplitude.

[0075] Specifically, the first-order amplitude compensation module includes:

[0076] The energy storage capacitor section consists of N energy storage capacitors, each of which is connected between the high-voltage power supply and ground.

[0077] The delay path section consists of N delay paths, with the number of delay devices in each delay path arranged in an arithmetic sequence, so that the delay difference between two adjacent delay paths is a fixed time difference Δt0. The delay path section performs delay processing on the input external trigger signal to generate an N-level trigger signal with a fixed phase difference.

[0078] The cascaded device section consists of N parallel switching circuits, each of which includes p series-connected field-effect transistors.

[0079] like Figure 2 As shown, the corresponding connection relationship between each stage of the switching circuit, a time delay path, and an energy storage capacitor is as follows: the output terminal of the time delay path is connected to the gate of p series-connected field-effect transistors in the switching circuit, and the series circuit of the p series-connected field-effect transistors is connected between the positive and negative terminals of the energy storage capacitor.

[0080] The control relationship is as follows: after the energy storage capacitor is pre-charged, the switching circuit establishes a discharge path for the energy storage capacitor under the trigger signal output by the time delay path, the energy storage capacitor discharges, and a discharge pulse is output.

[0081] N energy storage capacitors discharge sequentially, outputting multi-stage pulse signals with a fixed phase difference.

[0082] In the embodiment, the p field effect transistors are connected in series to increase the breakdown threshold voltage of each stage, so as to increase the pulse amplitude and compensate the pulse amplitude of each stage; N time delay paths are adopted to output the trigger signals of the fixed time difference Δt0 of each stage of switch circuit in turn, so as to generate the multi-stage pulse signals with the fixed phase difference.

[0083] Specifically, the multi-dimensional nonlinear transmission network of the phase compensation module is composed of N nonlinear transmission lines;

[0084] As shown in Figure 3 , each nonlinear transmission line corresponds to one stage of pulse signals; the reverse bias varactor diode is connected across the nonlinear transmission line; the capacitance of the varactor diode changes linearly with the signal level, so as to compress and compensate the phase of the pulse,

[0085] After each nonlinear transmission line compresses and compensates the input pulse respectively, the phases of the pulse signals of each stage are aligned, and the pulse width is compressed to the set picosecond level.

[0086] In the embodiment, the delay time characteristics of each state point of the signal are utilized by the N nonlinear transmission lines, so as to compress the input pulse and make the pulse width reach the set picosecond level; on the other hand, the phases of the pulse signals of each stage are aligned during the pulse compression; so as to facilitate the second-order compensation of the pulse.

[0087] For the first aspect: the reverse bias varactor diode connected across the nonlinear transmission line is controlled by the signal level on the transmission line, and inversely affects the transmission speed of different state points of the signal on the transmission line. Among them, the capacitance of the reverse bias varactor diode decreases with the increase of the input signal level v, and can be considered as linear change in a certain range, so the relationship between the capacitance C(v) of the varactor diode and the signal level v(t) can be expressed as:

[0088] C(v)=C j0 -bv(t)

[0089] Among them, C j0 is the zero-bias junction capacitance of the varactor diode, b is a constant factor, and v(t) represents the transient signal level changing with time t; accordingly, the capacitance per unit length of the nonlinear transmission line inductance can be expressed as

[0090]

[0091] Among them, L0 and C0 represent the inductance and capacitance per unit length of the uniform lossless transmission line; L d represents the inductance of the lossless transmission line with a length of d. Then the delay time per unit length of the nonlinear transmission line at each state point is:

[0092]

[0093] For the second aspect: as Figure 4 shown,

[0094] In the figure, Δt0 represents the phase delay of the two input signals A, B, Δt1, Δt2 and Δt3, Δt4 represent the propagation delay time of the bottom state point and the top state point of the signal A, B waveform respectively, in order to achieve the purpose of pulse compression and phase compensation at the same time, the following conditions need to be met at the same time:

[0095]

[0096] In order to meet the first two conditions in the above conditions, it is necessary to match the cutoff frequency f c of the varactor itself, the cutoff frequency f g of the nonlinear transmission line and the high end cutoff frequency f h of the pulse signal to meet the following conditions:

[0097]

[0098] When the solid phase difference Δγ = Δt0 generated under the action of the delay device in each path branch, the phases of the pulse signals of each stage are aligned.

[0099] Specifically, the design process of the multi-dimensional nonlinear transmission network of the phase compensation module includes:

[0100] Step S1, determining the high end cutoff frequency of the pulse signal according to the rising edge time of the expected output pulse;

[0101] In one scheme of the embodiment, the high end cutoff frequency of the pulse signal is f h ≈0.45 / tr out ; tr out is the expected output pulse rising edge time.

[0102] Step S2, selecting a varactor that meets the cutoff frequency requirement;

[0103] Specifically, the cutoff frequency f c of the selected varactor, the cutoff frequency f g of the nonlinear transmission line and the high end cutoff frequency f h of the pulse signal meet:

[0104]

[0105] In one scheme of the embodiment, the expected tr out is less than 1 nanosecond, and the cutoff frequency f c of the selected varactor isShould be greater than 5 times f h ≈0.45 / tr out That is, 2.25GHz, the nonlinear transmission line cutoff frequency f g Should be greater than 450MHz.

[0106] Step S3, according to the dielectric constant of PCB material, the capacitance and inductance of the unit length lossless transmission line are calculated;

[0107] In one scheme of the embodiment, when the load is 50Ω, the capacitance and inductance of the unit length lossless transmission line C0 are respectively L0:

[0108]

[0109] Wherein, ε r is the dielectric constant of the selected PCB material;

[0110] Step S4, set the embedded spacing of varactor diode, calculate the capacitance and inductance of single section lossless transmission line;

[0111] Specifically, the capacitance C d and inductance L d of single section lossless transmission line are respectively:

[0112] C d =C0*d, L d =L0*d

[0113] Wherein, d is the embedded spacing of varactor diode on PCB;

[0114] Step S5, calculate the rising edge compression time of single section nonlinear transmission line;

[0115] Specifically, the rising edge compression time of single section nonlinear transmission line is:

[0116]

[0117] Wherein, v A , v B respectively represent the level value of the top and bottom of the compressed signal; b is a constant factor, C j0 is the zero bias junction capacitance of varactor diode;

[0118] Step S6, determine the number of nonlinear transmission lines that meet the phase compensation and pulse compression.

[0119] Specifically, the time difference between the current stage pulse signal entering the nonlinear transmission line and the last stage pulse signal, plus the time difference between the rising edge of the current stage pulse signal entering the nonlinear transmission line and the desired output pulse signal, is divided by the rising edge compression time of the single nonlinear transmission line, and then rounded.

[0120] The multi-dimensional nonlinear transmission network designed by the above design process can achieve phase alignment of the input pulse signals of each stage and compress the pulse width to a set picosecond level.

[0121] Specifically, as shown in Figure 5 , the second-order amplitude compensation module includes a carrier delay module and a delay capacitor pairing module.

[0122] The carrier delay module includes N carrier delay branches, and each carrier delay branch is connected to a nonlinear transmission line in the phase compensation module through a lossless transmission line.

[0123] The delay capacitor pairing module includes N capacitor units, and each capacitor unit is connected to a carrier delay branch.

[0124] In the carrier delay module, each carrier delay branch has a corresponding inductance value for re-aligning the phase of each pulse signal.

[0125] In the delay capacitor pairing module, the capacitance values of each capacitor unit are the same, and are used to generate the final pulse output through pulse time-varying electric field induction and carrier superposition.

[0126] In order to make the final output pulse signal reach the expected amplitude V D , the capacitance value of the capacitor unit in the delay capacitor pairing module should be matched with the device cascade part.

[0127] The capacitance value of the matched capacitor unit is:

[0128]

[0129] Where V D is the expected amplitude; t r is the rise time of the field effect transistor in the first-order amplitude compensation module; N is the number of stages of the switch circuit in the first-order amplitude compensation module, and p is the number of field effect transistors in each stage of the switch circuit; V B is the breakdown threshold voltage of each group of field effect transistors after cascading; and R is the impedance of the load.

[0130] The re-phase alignment in the carrier delay module is mainly used to eliminate the time delay difference caused by the different lengths of the lossless transmission lines connected to each stage. Since the capacitance values of the capacitors in the delay capacitor matching module are the same, the time delay can be controlled by adjusting the inductance values of the carrier delay branches in the carrier delay module, so as to realize the re-phase alignment of the pulses in each stage.

[0131] In the carrier delay module, the inductance values L i and L j satisfy the following relationship:

[0132]

[0133] wherein C is the capacitance value of the capacitor, L b , C b respectively represent the inductance and capacitance values corresponding to the length difference of the lossless transmission lines connected to the i-th and j-th carrier delay branches.

[0134] The embodiment also discloses a method for generating high-amplitude picosecond pulses by using the picosecond pulse generator, as shown in the figure, comprising the following steps: Figure 6

[0135] Step 1: Under the action of the reference high voltage, the energy storage capacitor part of the first-order amplitude compensation module starts pre-charging.

[0136] Step 2: The external trigger signal flows through the time delay path part of the first-order amplitude compensation module, and reaches the bases of the groups of cascode field effect transistors in the device cascade part with fixed phase difference under the action of the time delay devices in each time delay path.

[0137] Step 3: Under the action of the trigger signal, each group of cascode field effect transistors is turned on instantaneously, and the pre-charged carriers in the energy storage capacitor part are instantaneously introduced into the power ground plane through the collector-emitter path of the cascode field effect transistors, thereby generating multi-stage pulse signals with fixed phase difference.

[0138] Step 4: After receiving the pulse signals output by the first-order amplitude compensation module, the phase compensation module makes the pulse signals in each stage flow through the multi-dimensional nonlinear transmission network, and performs phase compensation and pulse compression on the pulse signals in each stage under the action of the nonlinear transmission network, aligns the phases of the pulse signals in each stage, and compresses the pulse width to a set picosecond level.

[0139] Step 5: The multi-stage pulse signals after phase compensation reach the second-order amplitude compensation module and enter the carrier delay module of the second-order amplitude compensation module.

[0140] ​Step 6, the carrier delay module re-aligns the phases of the pulse signals passing through each branch path by selecting the inductance parameters of each branch path;

[0141] Step 7, the pulse signals passing through the carrier delay module simultaneously reach the delay capacitance pairing module of the second-order amplitude compensation module, and under the induction of the pulse time-varying electric field and the superposition of the carriers, a picosecond-level pulse signal meeting the expected amplitude is generated at the output end of the second-order amplitude compensation module.

[0142] In summary, the scheme disclosed in the embodiment of the application uses device cascading, time delay matching, pulse compression, carrier delay, carrier superposition and other means in combination, establishes a picosecond pulse generator design method based on dual compensation of amplitude and phase under the premise of fully considering the implementation cost and design difficulty, avoids the limitations of relying on a single device in terms of turn-off speed and device voltage threshold, can greatly compress the pulse signal width while improving the pulse amplitude, achieves the purpose of generating a high-amplitude picosecond pulse signal, and can adapt to individualized needs for pulse signal generation in different scenarios, and has very good scene adaptability.

[0143] The above merely describes a preferred specific embodiment of the application, but the protection scope of the application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the application, which should be covered within the protection scope of the application.

Claims

1. A picosecond-level pulse generator based on dual amplitude and phase compensation, characterized in that, include: A first-order amplitude compensation module is used to generate multi-level pulse signals with compensated amplitudes when triggered by a trigger signal, wherein each level of the pulse signal has a fixed phase difference. The phase compensation module is used to receive the multi-level pulse signal and perform phase compensation and pulse compression on the multi-level pulse signal through a multi-dimensional nonlinear transmission network, align the phase of each level of pulse signal, and compress the pulse width to a set picosecond level width. The second-order amplitude compensation module is used to receive multi-level pulse signals after phase compensation and pulse compression, perform phase alignment of the multi-level pulse signals again, and superimpose the amplitudes of the aligned pulse signals to output a picosecond-level pulse signal that meets the expected amplitude.

2. The picosecond-level pulse generator with dual amplitude and phase compensation according to claim 1, characterized in that, The first-order amplitude compensation module includes: The energy storage capacitor section consists of N energy storage capacitors, each of which is connected between the high-voltage power supply and ground. The delay path section consists of N delay paths, with the number of delay devices in each delay path arranged in an arithmetic sequence, so that the delay difference between two adjacent delay paths is a fixed time difference Δt0. The delay path section performs delay processing on the input external trigger signal to generate an N-level trigger signal with a fixed phase difference. The cascaded device section consists of N parallel switching circuits, each of which includes p series-connected field-effect transistors. The corresponding connection relationship between each stage of the switching circuit, a time delay path, and an energy storage capacitor is as follows: the output terminal of the time delay path is connected to the gate of p series-connected field-effect transistors in the switching circuit, and the series circuit of the p series-connected field-effect transistors is connected between the positive and negative terminals of the energy storage capacitor. The control relationship is as follows: after the energy storage capacitor is pre-charged, the switching circuit establishes a discharge path for the energy storage capacitor under the trigger signal output by the time delay path, the energy storage capacitor discharges, and a discharge pulse is output. N energy storage capacitors discharge sequentially, outputting multi-stage pulse signals with a fixed phase difference.

3. The picosecond-level pulse generator with dual amplitude and phase compensation according to claim 1 or 2, characterized in that, The multidimensional nonlinear transmission network of the phase compensation module consists of N nonlinear transmission lines; Each nonlinear transmission line corresponds to a single-stage pulse signal; A reverse-biased varactor diode is connected across the nonlinear transmission line. The capacitance of the varactor diode changes linearly with the signal level, thus compressing the pulse and compensating for its phase. Each nonlinear transmission line compresses and compensates the phase of the input pulse, aligns the phase of each pulse signal, and compresses the pulse width to a set picosecond level.

4. The picosecond-level pulse generator with dual amplitude and phase compensation according to claim 3, characterized in that, The design process of the multidimensional nonlinear transmission network of the phase compensation module includes: Step S1: Determine the high-end cutoff frequency of the pulse signal based on the expected rise time of the output pulse; Step S2: Select a varactor diode that meets the cutoff frequency requirements; Step S3: Calculate the capacitance and inductance per unit length of the lossless transmission line based on the dielectric constant of the PCB board. Step S4: Set the varactor diode embedding spacing and calculate the capacitance and inductance of a single section of lossless transmission line; Step S5: Calculate the rise time compression time of a single nonlinear transmission line; Step S6: Determine the number of nonlinear transmission segments that satisfy phase compensation and pulse compression.

5. The picosecond-level pulse generator with dual amplitude and phase compensation according to claim 4, characterized in that, In step S1, the high-end cutoff frequency f of the pulse signal h ≈0.45 / tr out ;tr out The expected rise time of the output pulse; In step S2, the cutoff frequency f of the selected varactor diode is... c The cutoff frequency f of a nonlinear transmission line g and the high-end cutoff frequency f of the pulse signal h satisfy: In step S3, when the load is 50Ω, the capacitance and inductance per unit length of the lossless transmission line C0 are respectively L0: Where, ε r The dielectric constant of the selected PCB material; In step S4, the capacitance C of a single section of lossless transmission line d and inductor L d They are respectively: C d =C0*d,L d =L0*d Where d is the embedding spacing of the varactor diode on the PCB; In step S5, the rise time compression time of a single-section nonlinear transmission line is: Among them, v A v B These represent the voltage levels at the top and bottom of the compressed signal, respectively; b is a constant factor, and C... j0 This is the zero-bias junction capacitance of the varactor diode; In step S6, the time difference between the current stage pulse signal and the previous stage pulse signal entering the nonlinear transmission line is added to the time difference between the rising edge of the current stage pulse signal entering the nonlinear transmission line and the rising edge compression time of the desired output pulse signal. This is then divided by the rising edge compression time of a single nonlinear transmission line and rounded down to determine the number of nonlinear transmission lines that satisfy phase compensation and pulse compression.

6. The picosecond-level pulse generator with dual amplitude and phase compensation according to claim 3, characterized in that, The second-order amplitude compensation module includes: a carrier delay module and a delay capacitor pairing module; The carrier delay module includes N carrier delay branches, and each carrier delay branch is connected to a nonlinear transmission line in the phase compensation module through a lossless transmission line. The delay capacitor pairing module includes N capacitor units; each capacitor unit is connected to a corresponding carrier delay branch.

7. The picosecond-level pulse generator with dual amplitude and phase compensation according to claim 6, characterized in that, In the carrier delay module, each carrier delay branch has a corresponding inductance value, which is used to re-phase align the pulse signals at each stage. In the delay capacitor pairing module, each capacitor unit has the same capacitance value, which is used to generate the final pulse output through pulse time-varying electric field induction and carrier superposition.

8. The picosecond-level pulse generator with dual amplitude and phase compensation according to claim 7, characterized in that, In the delay capacitor pairing module, the capacitance value of the capacitor unit is: Among them, V D The expected range; t r V is the rise time of the field-effect transistor in the first-order amplitude compensation module; N is the number of stages in the switching circuit of the first-order amplitude compensation module, and p is the number of field-effect transistors in each stage of the switching circuit; B R is the breakdown threshold voltage of each cascaded MOSFET; R is the impedance of the load.

9. The picosecond-level pulse generator with dual amplitude and phase compensation according to claim 8, characterized in that, In the carrier delay module, the inductance value L in the i-th and j-th carrier delay branches i and L j The following relationship must be satisfied: Where C is the capacitance value of the capacitor unit, L b C b These represent the inductance and capacitance values ​​corresponding to the length difference of the lossless transmission lines connected to the i-th and j-th carrier delay branches, respectively.

10. A pulse generation method using a picosecond-level pulse generator as described in any one of claims 1 to 9, characterized in that, Includes the following steps: Step 1: Under the action of the reference high voltage, the energy storage capacitor of the first-order amplitude compensation module begins to pre-charge. Step 2: The external trigger signal flows through the time delay path of the first-order amplitude compensation module, and under the action of the delay devices in each time delay path, it reaches the base of each group of cascaded field-effect transistors in the device cascade section with a fixed phase difference. Step 3: Under the action of the trigger signal, each group of cascaded field-effect transistors is turned on instantly. The pre-charged carriers in the energy storage capacitor section are introduced to the power supply ground plane through the collector-emitter path of the cascaded field-effect transistors, thereby generating multiple pulse signals with fixed phase differences. Step 4: After receiving the pulse signal output by the first-order amplitude compensation module, the phase compensation module makes each level of pulse signal flow through the multi-dimensional nonlinear transmission network, and performs phase compensation and pulse compression on each level of pulse signal under the action of the nonlinear transmission network, aligns the phase of each level of pulse signal, and compresses the pulse width to the set picosecond level width. Step 5: The multi-stage pulse signal after phase compensation arrives at the second-order amplitude compensation module and enters the carrier delay module of the second-order amplitude compensation module; Step 6: The carrier delay module re-aligns the phases of the pulse signals flowing through each branch path by selecting the inductance parameters of each branch path; Step 7: The pulse signals of each stage flowing through the carrier delay module simultaneously arrive at the delay capacitor matching module of the second-order amplitude compensation module, and under the induction of the pulse time-varying electric field and the superposition of carriers, a picosecond-level pulse signal with the expected amplitude is generated at the output of the second-order amplitude compensation module.

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