A CT sigma-delta modulator based on a ring VCO quantizer

Abstract

The application relates to a Sigma-Delta modulator, in particular to a CT type Sigma-Delta modulator based on a ring VCO quantizer. The Sigma-Delta modulator comprises a filtering module, a VCO quantizer module and a current steering feedback DAC module; the input positive end and the input negative end of the filtering module are respectively connected with external upper devices; the input positive end and the input negative end of the VCO quantizer module are respectively connected with the output positive end and the output negative end of the filtering module, and the output end of the VCO quantizer module is respectively connected with the input end of the current steering feedback DAC module and external lower devices; the VCO quantizer module converts an analog voltage signal into a digital signal and then respectively outputs the digital signal to the current steering feedback DAC module and the external lower devices; and the output positive end and the output negative end of the current steering feedback DAC module are respectively connected with the feedback positive end and the feedback negative end of the filtering module. The modulator disclosed by the application has low power consumption and small chip area.

Description

TECHNICAL FIELD

[0001] The present application relates to a Sigma-Delta modulator, in particular to a CT type Sigma-Delta modulator based on a ring VCO quantizer. BACKGROUND

[0002] With the continuous progress of medical technology, various medical sensors have become increasingly important in the fields of medical diagnosis, health monitoring, and personalized treatment. For example, sensors that detect bioelectric signals (such as electrocardiogram, electroencephalogram), sensors that detect biochemical indicators (such as blood glucose, blood oxygen, etc.), and sensors for medical imaging (such as ultrasonic imaging, nuclear magnetic resonance imaging) and other sensors. These medical sensors often need to capture weak analog signals and convert them into digital signals for processing through an analog-to-digital converter.

[0003] Analog-to-digital converters (ADCs) are mainly divided into two types according to the sampling method: one is the Nyquist ADC, mainly including Flash structure, Pipeline structure and SAR structure, and the sampling frequency of this type of ADC is usually twice the signal bandwidth; the other is the oversampling ADC, mainly the Sigma-Delta ADC, and its sampling frequency is usually M times the signal bandwidth. Sigma-Delta ADCs can also be divided into discrete-time (DT) and continuous-time (CT) types according to the sampling position. The DT type samples before the loop, while the CT type samples before the quantizer in the loop. The DT type has higher precision, but the CT type is faster, has wider signal bandwidth, and has built-in anti-aliasing filter characteristics. In addition, modern medical instruments emphasize low power consumption, which makes the Nyquist ADC face not small challenges in meeting these requirements, while the Sigma-Delta ADC can accurately capture the small changes of weak signals in medical sensors while providing high-resolution digital output and maintaining low power consumption.

[0004] The medical sensor system realizes high-precision acquisition and intelligent analysis of bioelectric signals through a multi-stage cooperative processing mechanism. The technical architecture includes five core modules: biophysical signal capture, analog front-end preprocessing (upper device), high-precision analog-to-digital conversion, digital signal processing (lower device), and human-computer interaction. The system workflow strictly follows the design guidelines of the medical electronic signal chain, and the specific implementation process is as follows: first, after the analog bioelectric signal is captured, it is preliminarily amplified by a low-noise amplifier (LNA) while minimizing noise introduction. The signal amplified by the LNA enters the programmable gain amplifier (PGA) module to complete further gain adjustment. Subsequently, the gain-adjusted signal enters the Sigma-Delta ADC and is converted into a digital signal. The converted digital signal is then input into the digital signal processor (DSP) to run various signal processing algorithms to extract valid information. Finally, the signal output by the DSP can be visually presented to the user through image display and other modules.

[0005] The Sigma-Delta modulator, as the core component of the Sigma-Delta ADC, has a significant impact on the performance of the Sigma-Delta ADC. However, in traditional Sigma-Delta modulators, the quantizer often uses a Flash structure based on a comparator, which can significantly increase the power consumption and area of multi-bit quantization structure Sigma-Delta modulators, thereby increasing the power consumption and area of Sigma-Delta ADCs. Therefore, in the medical sensor field, designing a high-bandwidth, low-power Sigma-Delta modulator has important value. SUMMARY

[0006] The purpose of the present application is to solve the technical problems of low bandwidth and high power consumption of existing modulators, and to provide a CT-type Sigma-Delta modulator based on a ring VCO quantizer.

[0007] To achieve the above purpose, the technical solution adopted by the present application is:

[0008] A CT-type Sigma-Delta modulator based on a ring VCO quantizer, characterized in that:

[0009] It includes a filter module, a VCO quantizer module, and a current steering feedback DAC module.

[0010] The input positive and negative terminals of the filter module are respectively connected to the external upper device for receiving the analog voltage signal input by the external upper device and performing filtering.

[0011] The input positive end and the input negative end of the VCO quantizer module are connected to the output positive end and the output negative end of the filter module respectively, and the output end of the VCO quantizer module is connected to the input end of the current steering feedback DAC module and an external lower device respectively; the VCO quantizer module is used for converting an analog voltage signal into a digital signal and outputting to the current steering feedback DAC module and the external lower device respectively;

[0012] The output positive end and the output negative end of the current steering feedback DAC module are connected to the feedback positive end and the feedback negative end of the filter module respectively, so as to form a cascaded resonant feedback structure.

[0013] Further, the filter module is a three-stage loop filter structure, comprising three-stage RC integrator circuits and two resonant resistors ;

[0014] The input positive end and the input negative end of the first-stage RC integrator circuit are connected to an external upper device respectively, so as to receive an analog voltage signal input by the external upper device, and the output positive end and the output negative end are connected to the input positive end and the input negative end of the second-stage RC integrator circuit respectively; the output positive end and the output negative end of the second-stage RC integrator circuit are connected to the input positive end and the input negative end of the third-stage RC integrator circuit respectively; and the output positive end and the output negative end of the third-stage RC integrator circuit are connected to the input positive end and the input negative end of the VCO quantizer module respectively.

[0015] One end of the two resonant resistors is connected to the input positive end and the input negative end of the second-stage RC integrator circuit respectively, and the other end is connected to the output negative end and the output positive end of the third-stage RC integrator circuit respectively.

[0016] The current steering feedback DAC module comprises a feedback DAC unit and a zero-order feedback DAC unit.

[0017] The input end of the feedback DAC unit and the input end of the zero-order feedback DAC unit are connected to the output end of the VCO quantizer module respectively.

[0018] The three output positive ends of the feedback DAC unit are connected to the feedback positive ends of the three-stage RC integrator circuits respectively, and the three output negative ends are connected to the feedback negative ends of the three-stage RC integrator circuits respectively.

[0019] The output positive end and the output negative end of the zero-order feedback DAC unit are connected to the zero-order feedback positive end and the zero-order feedback negative end of the third-stage RC integrator circuit respectively.

[0020] Further, the first-stage RC integrator circuit comprises a resistor R1, a resistor R2, a capacitor C1, a capacitor C2 and a first operational amplifier.

[0021] The second-stage RC integrator circuit comprises a resistor R3, a resistor R4, a capacitor C3, a capacitor C4 and a second operational amplifier.

[0022] The third-stage RC integrator circuit comprises resistors R7, R8, capacitors C5, C6, a third operational amplifier, resistor R9 and resistor R10;

[0023] two resonant resistors respectively resistor R5 and resistor R6;

[0024] One end of resistor R1 and resistor R2 is respectively the input positive terminal and the input negative terminal of the first-stage RC integrator circuit, for connecting external upper devices, and the other end is respectively connected to the non-inverting input terminal and the inverting input terminal of the first operational amplifier, and serves as the feedback positive terminal and the feedback negative terminal of the first-stage RC integrator circuit, and is respectively connected to the first output positive terminal and the first output negative terminal of the feedback DAC unit;

[0025] The other end of resistor R1 and one end of capacitor C1 are connected, and the other end of resistor R2 and one end of capacitor C2 are connected; the other end of capacitor C1 and capacitor C2 is respectively connected to the output negative terminal and the output positive terminal of the first operational amplifier, and the two nodes connected serve as the output negative terminal and the output positive terminal of the first-stage RC integrator circuit;

[0026] One end of resistor R3 and resistor R4 is respectively the input positive terminal and the input negative terminal of the second-stage RC integrator circuit, and is respectively connected to the output positive terminal and the output negative terminal of the first-stage RC integrator circuit;

[0027] The other end of resistor R3 and one end of capacitor C3 and resistor R5 are respectively connected to the non-inverting input terminal of the second operational amplifier, and the other end of resistor R4 and one end of capacitor C4 and resistor R6 are respectively connected to the inverting input terminal of the second operational amplifier, and the non-inverting input terminal and the inverting input terminal of the second operational amplifier are respectively the feedback positive terminal and the feedback negative terminal of the second-stage RC integrator circuit, and are respectively connected to the second output positive terminal and the second output negative terminal of the feedback DAC unit;

[0028] The other end of capacitor C3 and capacitor C4 is respectively connected to the output negative terminal and the output positive terminal of the second operational amplifier, and the two nodes connected serve as the output negative terminal and the output positive terminal of the second-stage RC integrator circuit;

[0029] One end of resistor R7 and resistor R8 is respectively the input positive terminal and the input negative terminal of the third-stage RC integrator circuit, and is respectively connected to the output positive terminal and the output negative terminal of the second-stage RC integrator circuit, and the other end is respectively connected to the non-inverting input terminal and the inverting input terminal of the third operational amplifier, and simultaneously serves as the feedback positive terminal and the feedback negative terminal of the third-stage RC integrator circuit, and is respectively connected to the third output positive terminal and the third output negative terminal of the feedback DAC unit;

[0030] The other end of the resistor R7 and one end of the capacitor C5 are connected, and the other end of the resistor R8 and one end of the capacitor C6 are connected;

[0031] The other end of the capacitor C5 and the resistor R5 is connected to the output negative terminal of the third operational amplifier, and one end of the resistor R9 is connected;

[0032] The other end of the resistor R10 and the resistor R9 is connected to the output positive terminal and the output negative terminal of the filter module, respectively, and is connected to the input positive terminal and the input negative terminal of the VCO quantizer module, and is connected to the zero-order feedback positive terminal and the zero-order feedback negative terminal of the third RC integrator circuit, and is connected to the output positive terminal and the output negative terminal of the zero-order feedback DAC unit, respectively.

[0033] Further, the VCO quantizer module includes a V-I conversion circuit, a VCO oscillation circuit, and a VCO quantization circuit;

[0034] The input positive terminal and the input negative terminal of the V-I conversion circuit are connected to the output positive terminal and the output negative terminal of the filter module, respectively, for converting an analog voltage signal into a current signal;

[0035] The current input terminal of the VCO oscillation circuit is connected to the current output terminal of the V-I conversion circuit, and the voltage input terminal is connected to an external for generating an oscillation signal;

[0036] The input positive terminal and the input negative terminal of the VCO quantization circuit are connected to the output positive terminal and the output negative terminal of the VCO oscillation circuit, respectively, the clock interface is connected to an external clock circuit, and the output terminal is connected to the input terminal of the current steering feedback DAC module and an external lower device, respectively; the VCO quantization circuit is used to receive a reference clock with a period of input by the clock circuit, and generate a digital signal according to the oscillation signal and the reference clock , and output to the current steering feedback DAC module and the external lower device, respectively.

[0037] Further, the V-I conversion circuit includes MOS tubes M a1 , M a2 , M a3 , M a4 , M a5 , M a6 , M a7 , M a8 , M a9 , M a10 , M a11 and a negative feedback resistor ;

[0038] MOS transistor M a1 MOS transistor M a4 MOS transistor M a9 MOS transistor M a11 MOS transistor M a5 MOS transistor M a8 MOS transistor M

[0039] MOS transistor M a5 MOS transistor M a8 MOS transistor M MOS transistor M a3 MOS transistor M a4 MOS transistor M a9 MOS transistor M a11 MOS transistor M

[0040] MOS transistor M a7 MOS transistor M a5 MOS transistor M a7 MOS transistor M a9 MOS transistor M a5 MOS transistor M a1 MOS transistor M a5 MOS transistor M

[0041] MOS transistor M a8 MOS transistor M a6 MOS transistor M a8 MOS transistor M a10 MOS transistor M a6 MOS transistor M a2 MOS transistor M a6 MOS transistor M

[0042] MOS transistor M a1 MOS transistor M a1 MOS transistor M a3 MOS transistor M a2 MOS transistor M a2 MOS transistor M a4 MOS transistor M

[0043] MOS transistor M a3 MOS transistor M a4 MOS transistor M ;

[0044] a negative feedback resistor the source of the MOS transistor M a1 and the source of the MOS transistor M a2 ;

[0045] the gate of the MOS transistor M a9 and the gate of the MOS transistor M a10 are connected to an external bias voltage V1 respectively, while the gate of the MOS transistor M a9 is connected to the drain of itself;

[0046] the gate of the MOS transistor M a11 is connected to the drain of itself, and the node of the connection is connected to the drain of the MOS transistor M a10 , which is used as the current output terminal of the V-I conversion circuit and the current input terminal of the VCO oscillation circuit, for outputting the converted current signal to the VCO oscillation circuit.

[0047] Further, the VCO oscillation circuit comprises N delay units connected in sequence in a head-to-tail manner; N is an odd number greater than or equal to 3;

[0048] The VCO quantization circuit comprises N quantization units;

[0049] The output positive terminal and the output negative terminal of the 1st delay unit are connected to the input positive terminal and the input negative terminal of the 2nd delay unit respectively; the output positive terminal and the output negative terminal of the 2nd delay unit are connected to the input positive terminal and the input negative terminal of the 3rd delay unit respectively; and so on, the output positive terminal and the output negative terminal of the Nth delay unit are connected to the input positive terminal and the input negative terminal of the 1st delay unit respectively;

[0050] The current input terminals of the N delay units are connected to the current output terminals of the V-I conversion circuit respectively, and the voltage input terminals are connected to the external bias voltage V1 respectively; ;

[0051] The output positive terminals and the output negative terminals of the N delay units are connected to the input positive terminals and the input negative terminals of the N quantization units respectively.

[0052] Further, the N delay units each comprise a MOS transistor M b1 , a MOS transistor M b2 , a MOS transistor M b3 , a MOS transistor M b4 , a MOS transistor M b5 , a MOS transistor M b6 , a MOS transistor M b7 , and a MOS transistor M b8 ;

[0053] The MOS transistor M b1 , the MOS transistor M b4are PMOS transistors, MOS transistor M b5 MOS transistor M b8 are NMOS transistors;

[0054] MOS transistor M b1 gate of MOS transistor M b5 gate, as the positive input terminal of the nth delay unit, n = 1, 2, …, N, MOS transistor M b1 drain of MOS transistor M b5 drain, constituting a first inverter structure;

[0055] MOS transistor M b2 gate of MOS transistor M b6 gate, MOS transistor M b2 drain of MOS transistor M b6 drain, constituting a second inverter structure;

[0056] MOS transistor M b3 gate of MOS transistor M b7 gate, MOS transistor M b3 drain of MOS transistor M b7 drain, constituting a third inverter structure;

[0057] MOS transistor M b4 gate of MOS transistor M b8 gate, as the negative input terminal of the nth delay unit, MOS transistor M b4 drain of MOS transistor M b8 drain, constituting a fourth inverter structure;

[0058] MOS transistor M b1 MOS transistor M b4 source, and MOS transistor M b5 MOS transistor M b8 source, respectively, connect the current output terminal of the V-I conversion circuit, and receive the current signal output by the V-I conversion circuit; and MOS transistor M b1 MOS transistor M b4 source, as the voltage input terminal of the delay unit, connects the external ;

[0059] MOS transistor M b1 and MOS transistor M b5 drain of MOS transistor M b2 gate of MOS transistor M b6 gate of MOS transistor M b2 and MOS transistor M b6 gate of MOS transistor M b3 and MOS transistor Mb7 The drain of the MOSFET is located at the M. b2 and MOSFET M b6 The connection node between the gates serves as the positive output terminal of the nth delay unit;

[0060] MOSFET M b4 and MOSFET M b8 The drain of the MOSFET M b3 and MOSFET M b7 The gate of the MOSFET, and at the same time, the MOSFET M b2 and MOSFET M b6 The drain of the MOSFET M b3 and MOSFET M b7 The gate of the MOSFET, and located in the MOSFET M b3 and MOSFET M b7 The connection node between the gates serves as the negative output terminal of the nth delay unit.

[0061] Furthermore, each of the N quantization units includes a buffer unit, two D flip-flop units, and an XOR unit;

[0062] The positive and negative input terminals of the buffer unit are respectively connected to the positive and negative output terminals of the corresponding delay unit. The output terminal is connected to the D terminal of the first D flip-flop unit. The Q terminal of the first D flip-flop unit is connected to the D terminal of the second D flip-flop unit and the first input terminal of the XOR unit. The Q terminal of the second D flip-flop unit is connected to the second input terminal of the XOR unit.

[0063] The CLK terminals of the two D flip-flop units are connected to an external clock circuit to receive the clock circuit input with a period of [missing information]. Reference clock ;

[0064] The output of the XOR unit serves as the output of the VCO quantizer module and is connected to the input of the current-steering feedback DAC module.

[0065] Furthermore, the feedback DAC unit includes three feedback circuits;

[0066] The N input terminals of each feedback circuit are connected to the output terminals of the N quantization units respectively. The positive output terminal is connected to the positive feedback terminal of the three-stage RC integrator circuit respectively, and the negative output terminal is connected to the negative feedback terminal of the three-stage RC integrator circuit respectively.

[0067] Furthermore, all three feedback circuits include a current source I. REF01 Current source I REF02 MOSFET M c1 MOSFET M c2 MOSFET M c3 MOSFET Mc4 MOSFET M c5 MOSFET M c6 RC noise reduction components, N switching transistors, and N cascaded current sources;

[0068] All N switching transistors include MOSFETs M c7 and MOSFET M c8 All N cascaded current sources include MOSFETs M c9 and MOSFET M c10 ;

[0069] MOSFET M c1 ~MOS transistor M c3 and MOSFET M c7 ~MOS transistor M c10 All are NMOS transistors; MOS transistor M c4 ~MOS transistor M c6 All are PMOS transistors;

[0070] MOSFET M c1 The gate of the MOSFET M c2 The gate of the MOSFET, and the connected node is connected to the MOSFET M c1 The drains of the two electrodes are connected to the current source I. REF01 The output terminal;

[0071] MOSFET M c1 and MOSFET M c3 The sources are all grounded;

[0072] MOSFET M c2 The source of the MOSFET is connected to the M c3 The drain of the MOSFET; c2 The drain of the MOSFET M c3 The gate of the RC noise reduction component is connected to one end of the RC noise reduction component; the other end of the RC noise reduction component is grounded.

[0073] MOSFET M c4 The gate of the MOSFET M c5 The gate of the MOSFET, and the connected node is connected to the MOSFET M c4 The drains of the two electrodes are connected to the current source I. REF02 The output terminal;

[0074] MOSFET M c4 MOSFET M c5 and MOSFET M c6 The sources are respectively connected to external... ;

[0075] MOSFET M c6 The gate of the MOSFET M c5 The gate of the MOSFET; c5The drains of the transistors are respectively connected to the MOSFET M in the N switching transistors. c7 The drain of the MOSFET M c6 The drains of the transistors are respectively connected to the MOSFET M in the N switching transistors. c8 The drain of the MOSFET; at the same time, the MOSFET M c5 and MOSFET M c6 The drains of the circuit are used as the negative and positive output terminals of the feedback circuit, respectively, and are connected to the negative and positive feedback terminals of the three-stage RC integrator circuit.

[0076] Among the N switching transistors, M is the MOSFET. c7 and MOSFET M c8 The gates of the transistors serve as the two input terminals of the feedback circuit, connected to the output terminals of N quantization units; among the N switching transistors, MOSFET M... c7 and MOSFET M c8 The source is connected, and each is connected to one of the N cascaded current sources, specifically to the MOSFET M. c9 The drain electrode;

[0077] Among the N cascaded current sources, MOSFET M c9 The gates of all are connected to MOSFETs M c2 The gate of the MOSFET; MOSFET M in N cascaded current sources c10 The gates of all are connected to MOSFETs M c3 The gate of the MOSFET; MOSFET M in N cascaded current sources c10 The sources of all transistors are grounded; in the same cascaded current source, the MOSFET M c9 The source connection corresponds to the MOSFET M c10 The drain electrode;

[0078] The zero-order feedback DAC unit includes MOSFET M d1 MOSFET M d2 Current source I ref1 Current source I ref2 Capacitor C a Capacitor C b And N current rudders;

[0079] Each of the N current-controlled transistors includes a MOSFET M. d3 MOSFET M d4 MOSFET M d5 MOSFET M d6 MOSFET M d7 and MOSFET M d8 ;

[0080] MOSFET M d1 and MOSFET M d3 ~MOS transistor M d5 All are PMOS transistors; MOS transistor M d2 and MOSFET Md6 ~MOS transistor M d8 All are NMOS transistors;

[0081] MOSFET M d1 The source is connected to the external MOS transistor M d1 The gate and MOSFET M d1 The source is connected, and a capacitor C is connected. a One end, current source I ref1 The output terminal; capacitor C a The other end is grounded;

[0082] MOSFET M d2 The drain and MOSFET M d2 The gate is connected, and capacitor C is connected. b One end, current source I ref2 Output terminal; MOSFET M d2 The source and capacitor C b The other end is grounded;

[0083] Among the N current-controlled transistors: MOSFET M d3 The gate of the MOSFET M d1 The gate of the MOSFET; d3 The source is connected to the external ; MOS transistor M d8 The gate of the MOSFET M d2 The gate of the MOSFET; d8 The source of the MOSFET is grounded; d4 The gate connection corresponds to the MOSFET M d6 The gate of the MOSFET is used as the first input of the zero-order feedback DAC unit and connected to the output of the corresponding quantization unit; the MOSFET M d5 The gate of the MOSFET M d7 The gate of the MOSFET is connected to the output of the corresponding quantization unit, serving as the second input of the zero-order feedback DAC unit; d4 The drain of the MOSFET M d6 The drain of the MOSFET serves as the negative output terminal of the zero-order feedback DAC unit, connected to the negative zero-order feedback terminal of the third-stage RC integrator circuit; MOSFET M d5 The drain connection corresponds to the MOSFET M d7 The drain of the circuit is used as the positive output terminal of the zero-order feedback DAC unit and connected to the positive zero-order feedback terminal of the third-stage RC integrator circuit.

[0084] In the same current-controlled circuit: MOSFET M d4 and MOSFET M d5 The sources are respectively connected to MOSFETs M d3 The drain of the MOSFET;d6 and MOSFET M d7 The sources are respectively connected to MOSFETs M d8 The drain electrode.

[0085] The beneficial effects of this invention are:

[0086] 1. This invention designs a differential single-channel high-linearity VCO quantizer module. On the one hand, it minimizes the impact of the VCO quantizer module's nonlinearity on the overall modulator, and further reduces the modulator's power consumption and chip area to a certain extent. On the other hand, the output of this VCO quantizer module is directly connected to the input of the current-following feedback DAC module, providing an implicit DEM (Dynamic Component Matching) for the current-following feedback DAC module. Furthermore, the implicit DEM provided by the VCO quantizer module does not consume additional power or occupy additional circuit area.

[0087] 2. This invention employs a cascaded resonant feedback structure (CRFB) composed of a filter module and a current-rudder feedback DAC module, which adds a resonant circuit (i.e., a resonant resistor) to the cascaded resonant feedforward structure (CRFF). The zero point of the modulator is adjusted by the circuit in which it is located, making the in-band noise suppression effect of the modulator more obvious. This structure does not require an additional adder module at the input of the VCO quantizer module, so there is no additional power consumption or circuit area increase.

[0088] 3. The present invention adopts a differential structure in the third-order loop filter structure, which improves the oversampling rate and thus improves the accuracy of the modulator, meeting the requirements of high oversampling rate and high accuracy of the overall modulator.

[0089] 4. The full-scale range of the current-following feedback DAC module designed in this invention, as well as the full-scale range of the modulator, can be achieved by adjusting the bias circuit. Furthermore, a single-channel path is maintained from the output of the VCO quantizer module to the input of the current-following feedback DAC module to reduce circuit power consumption. Attached Figure Description

[0090] Figure 1 This is a schematic diagram of the overall circuit structure of an embodiment of the present invention;

[0091] Figure 2 This is a circuit schematic diagram of the filtering module in an embodiment of the present invention;

[0092] Figure 3 This is a circuit schematic diagram of the VCO quantizer module in an embodiment of the present invention;

[0093] Figure 4 This is a circuit diagram of the VI conversion circuit in an embodiment of the present invention;

[0094] Figure 5 This is a circuit diagram of the VCO oscillation circuit in an embodiment of the present invention;

[0095] Figure 6 This is a circuit diagram of the VCO quantization circuit in an embodiment of the present invention;

[0096] Figure 7 The VI conversion circuit in the embodiment of the present invention and Actual simulation relationship diagram;

[0097] Figure 8 This is a diagram showing the frequency relationship between VF in an embodiment of the present invention;

[0098] Figure 9 This is a diagram showing the output of the XOR unit in an embodiment of the invention;

[0099] Figure 10 This is the overall circuit diagram of the zero-order feedback DAC unit in the embodiment of the invention;

[0100] Figure 11 This is the overall circuit diagram of the feedback DAC unit in the embodiment of the invention;

[0101] Figure 12 This is a diagram showing the feedback current results of the first feedback circuit in the embodiment of the invention. Detailed Implementation

[0102] To make the objectives, advantages, and features of the present invention clearer, the following detailed description of a CT-type Sigma-Delta modulator based on a ring VCO quantizer, in conjunction with the accompanying drawings and specific embodiments, will further clarify the advantages and features of the present invention. The advantages and features of the present invention will become clearer from the following specific embodiments.

[0103] Reference Figure 1 This embodiment presents a CT-type Sigma-Delta modulator based on a ring VCO quantizer, which mainly includes a filter module, a VCO quantizer module, and a current-steering feedback DAC module.

[0104] A cascaded resonant feedback structure, consisting of a filter module and a current-steering feedback DAC module, is widely used due to its single-loop structure, which is less prone to defects. The single-loop structure includes two typical architectures: feedforward and feedback. These two main structures can be further divided into four types based on the presence or absence of a resonant loop: cascaded integrator with distributed feedback (CIFB), integrator with weighted feedforward summation (CIFF), cascaded resonant feedback structure (CRFB), and cascaded resonant feedforward structure (CRFF).

[0105] Through a detailed analysis of the four structures (CIFB, CIFF, CRFB, CRFF), the advantages and disadvantages of each structure are understood. The most significant drawback of the feedforward structures (CIFF, CRFF) is the need for an adder module at the input of the VCO quantizer module, increasing the complexity of the circuit design. The distributed feedback cascaded integrator (CIFB) is also unsuitable for this embodiment due to its unfavorable zero-point location for in-band noise suppression. Therefore, in this embodiment, the cascaded resonant feedback structure (CRFB) is selected. Similar to the cascaded resonant feedforward structure (CRFF), it adds a resonant circuit to adjust the zero point of the overall modulator, resulting in more significant in-band noise suppression. Furthermore, this structure does not require an additional adder module at the input of the VCO quantizer module, thus avoiding additional power consumption and circuit area increases.

[0106] The main function of the filtering module is to filter the externally input analog voltage signal.

[0107] See Figure 1 and Figure 2 In this embodiment, the filtering module adopts a third-order loop filtering structure, including a three-stage RC integrator circuit and two resonant resistors. .

[0108] The positive and negative input terminals of the first-stage RC integrator circuit are connected to an external host device to receive the analog voltage signal from the host device. The positive and negative output terminals are connected to the positive and negative input terminals of the second-stage RC integrator circuit, respectively. The positive and negative output terminals of the second-stage RC integrator circuit are connected to the positive and negative input terminals of the third-stage RC integrator circuit, respectively. The positive and negative output terminals of the third-stage RC integrator circuit are connected to the positive and negative input terminals of the VCO quantizer module, respectively. Two resonant resistors... One end is connected to the positive and negative input terminals of the second-stage RC integrator circuit, and the other end is connected to the negative and positive output terminals of the third-stage RC integrator circuit.

[0109] The first-stage RC integrator circuit includes resistors R1 and R2, capacitors C1 and C2, and a first operational amplifier; the second-stage RC integrator circuit includes resistors R3 and R4, capacitors C3 and C4, and a second operational amplifier; the third-stage RC integrator circuit includes resistors R7 and R8, capacitors C5 and C6, a third operational amplifier, resistors R9 and R10; and two resonant resistors. Resistors R5 and R6 are respectively.

[0110] One end of resistors R1 and R2 serves as the positive and negative input terminals of the first-stage RC integrator circuit, respectively, for connecting to external higher-level devices. The other ends of resistors R1 and R2 are connected to the non-inverting and inverting input terminals of the first operational amplifier, respectively, and also serve as the positive and negative feedback terminals of the first-stage RC integrator circuit, respectively, connecting to the first positive and first negative output terminals of the current-steering feedback DAC module. The other end of resistor R1 is connected to one end of capacitor C1, and the other end of resistor R2 is connected to one end of capacitor C2. The other ends of capacitors C1 and C2 are connected to the negative and positive output terminals of the first operational amplifier, respectively, and the two connected nodes serve as the negative and positive output terminals of the first-stage RC integrator circuit.

[0111] One end of resistors R3 and R4 serves as the positive and negative input terminals of the second-stage RC integrator circuit, respectively, and is connected to the positive and negative output terminals of the first-stage RC integrator circuit. The other end of resistor R3, along with one end of capacitor C3 and resistor R5, is connected to the non-inverting input terminal of the second operational amplifier. The other end of resistor R4, along with one end of capacitor C4 and resistor R6, is connected to the inverting input terminal of the second operational amplifier. Simultaneously, the non-inverting and inverting input terminals of the second operational amplifier serve as the positive and negative feedback terminals of the second-stage RC integrator circuit, respectively, and are connected to the second positive and second negative output terminals of the current-steering feedback DAC module. The other ends of capacitors C3 and C4 are connected to the negative and positive output terminals of the second operational amplifier, respectively, and the two connected nodes serve as the negative and positive output terminals of the second-stage RC integrator circuit.

[0112] One end of resistors R7 and R8 serves as the positive and negative input terminals of the third-stage RC integrator circuit, respectively, and is connected to the positive and negative output terminals of the second-stage RC integrator circuit. The other ends of resistors R7 and R8 are connected to the non-inverting and inverting input terminals of the third operational amplifier, respectively, and also serve as the positive and negative feedback terminals of the third-stage RC integrator circuit, respectively, and are connected to the third positive and third negative output terminals of the current-steering feedback DAC module. The other end of resistor R7 is connected to one end of capacitor C5, and the other end of resistor R8 is connected to one end of capacitor C6. The other ends of capacitor C5 and resistor R5 are connected to the negative output terminal of the third operational amplifier and to one end of resistor R9. The other ends of capacitor C6 and resistor R6 are connected to the positive output terminal of the third operational amplifier and to one end of resistor R10. The other ends of resistors R10 and R9 serve as the positive and negative output terminals of the filter module, respectively, and are connected to the positive and negative input terminals of the VCO quantizer module. They also serve as the positive and negative zero-order feedback terminals of the third-stage RC integrator circuit, and are connected to the fourth positive and fourth negative output terminals of the current-steering feedback DAC module, respectively.

[0113] In this embodiment, the transfer function of the third-order loop filter structure is as follows:

[0114]

[0115] in: It is the Laplace transform form of the transfer function. It is a complex variable. Let be the integration constant. The sampling frequency; It is the resistance value; It is the capacitance value.

[0116] The main function of the VCO quantizer module is to convert analog voltage signals into digital signals.

[0117] The VCO quantizer module is essentially a feedback amplifier structure, characterized by its ability to generate periodic oscillating signals even without input. If the phase shift of the feedback amplifier structure in the modulator is large enough, the feedback in the modulator will become positive feedback, thus inducing oscillation.

[0118] See Figure 1 and Figure 3 In this embodiment, the VCO quantizer module includes a VI conversion circuit, a VCO oscillation circuit, and a VCO quantization circuit.

[0119] The positive and negative input terminals of the VI converter circuit are connected to the positive and negative output terminals of the filter module, respectively, to convert the analog voltage signal into a current signal. The current input terminal of the VCO oscillation circuit is connected to the current output terminal of the VI converter circuit, and the voltage input terminal is connected to an external... The main function of the VCO oscillation circuit is to generate an oscillation signal. The positive and negative input terminals of the VCO quantization circuit are connected to the positive and negative output terminals of the VCO oscillation circuit, respectively. The clock interface is connected to an external clock circuit, and the output terminals are connected to the input terminal of the current feedback DAC module and an external lower-level device, respectively. The VCO quantization circuit receives the clock circuit input with a period of... Reference clock And based on the oscillation signal and reference clock Digital signals are generated and output to the current-steering feedback DAC module and external lower-level devices, respectively.

[0120] See Figure 3 and Figure 4 In this embodiment, the VI conversion circuit mainly includes a MOS transistor M a1 MOSFET M a2 MOSFET M a3 MOSFET M a4 MOSFET M a5MOSFET M a6 MOSFET M a7 MOSFET M a8 MOSFET M a9 MOSFET M a10 MOSFET M a11 and negative feedback resistor .

[0121] Among them, MOS transistor M a1 ~MOS transistor M a4 and MOSFET M a9 ~MOS transistor M a11 All are NMOS transistors; MOS transistor M a5 ~MOS transistor M a8 All are PMOS transistors.

[0122] The VI conversion circuit in this embodiment adopts a differential structure, which can eliminate the influence of even-order harmonics, while the negative feedback resistor... It can improve the linearity of the VI conversion circuit.

[0123] Specifically, MOSFET M a5 ~MOS transistor M a8 The sources are all connected to external sources. MOS transistor M a3 MOSFET M a4 and MOSFET M a9 ~MOS transistor M a11 The sources of all transistors are grounded; MOSFET M a7 The gate of the MOSFET M a5 The gate of the MOSFET M a7 The drain of the MOSFET M a9 The drain of the MOSFET M a5 The drain of the MOSFET M a1 The drain of the MOSFET M a5 The drain of the MOSFET is connected to its own gate; MOSFET M a8 The gate of the MOSFET M a6 The gate of the MOSFET M a8 The drain of the MOSFET M a10 The drain of the MOSFET M a6 The drain of the MOSFET M a2 The drain of the MOSFET, and the MOSFET M a6 The drain of the MOSFET is connected to its own gate; MOSFET M a1 The gate of the MOSFET is connected to the positive output terminal of the filter module. a1 The source of the MOSFET is connected to the M a3 The drain of the MOSFET M a2The gate of the MOSFET is connected to the negative output terminal of the filter module. a2 The source of the MOSFET is connected to the M a4 The drain of the MOSFET; a3 The gate and MOSFET M a4 The gates are respectively connected to external bias voltages. negative feedback resistor The two ends are respectively connected to MOSFET M a1 The source and MOSFET M a2 The source of the MOSFET; a9 The gate and MOSFET M a10 The gates of the MOSFETs are connected to an external bias voltage V1, and the gates of the MOSFETs are connected to the external bias voltage V1. a9 The gate of the MOSFET is connected to its own drain; a11 The gate is connected to its own drain, and the node of this connection is connected to the MOSFET M. a10 The drain of the circuit also serves as the current output terminal of the VI conversion circuit, connecting to the current input terminal of the VCO oscillation circuit, and outputting the converted current signal to the VCO oscillation circuit.

[0124] By changing the negative feedback resistor The magnitude of this variable can change the conversion ratio between voltage and current, thus amplifying or reducing the current. Furthermore, it passes through a negative feedback resistor. There will be a certain voltage drop, which is helpful in improving the linearity of the VI conversion circuit. Figure 4 The medium current I1 passes through the NMOS current mirror (MOS transistor M). a9 MOSFET M a10 This forms a mirror current, which is then subtracted from the current I2 to obtain the current signal. Current signal It has a linear relationship with the differential currents (current I1, current I2).

[0125] For the VI conversion circuit designed in this embodiment, small-signal analysis yields the following results:

[0126]

[0127] in: The equivalent transconductance of the VI conversion circuit, The output resistance of the MOSFET. For analog voltage signals and The difference, For MOSFET M a11 The voltage difference between the drain and source, This is the inherent gain.

[0128] if and If the value is large enough, then The expression is as follows:

[0129]

[0130] Current signal The expression is as follows:

[0131]

[0132] In this embodiment, the common-mode voltage input to the VI conversion circuit is 650mV, its swing is set to ±350mV, and the output current signal... The voltage ratings are 0.297μA to 22.847μA, respectively. This VI conversion circuit... and The actual simulation relationship is as follows Figure 7 As shown.

[0133] See Figure 3 and Figure 5 In this embodiment, the VCO oscillation circuit includes N delay units; N is an odd number greater than or equal to 3; in this embodiment, 7 delay units are used as an example.

[0134] Figure 3 The VCO oscillation circuit shown has 7 Figure 5 The delay units shown have two inputs and two outputs per unit, and there are 7 delay units in total. Figure 5 The delay units shown are connected end to end to form a ring structure. Figure 3 In and That is, the differential current signal output by the VI conversion circuit. , and It is the input of a single delay unit. and It is the output of a single delay unit.

[0135] The current-starved delay unit designed in this embodiment is a positive-negative complementary delay unit. The advantages of this structure are: 1. It can achieve a wider range of frequency adjustment; 2. The self-excited oscillation generated by the positive feedback structure is more stable and the phase noise is smaller; 3. This structure has lower power consumption; 4. This structure has a faster response speed.

[0136] The positive and negative outputs of the first delay unit are connected to the positive and negative inputs of the second delay unit, respectively; the positive and negative outputs of the second delay unit are connected to the positive and negative inputs of the third delay unit, and so on. The positive and negative outputs of the seventh delay unit are connected to the positive and negative inputs of the first delay unit, respectively. The current inputs of the seven delay units are connected to the current output of the VI conversion circuit, and the voltage inputs are connected to external circuits. The positive and negative output terminals of the seven delay units are connected to the positive and negative input terminals of the VCO quantization circuit, respectively.

[0137] All seven delay units employ a positive feedback complementary CMOS inverter pair structure, specifically including MOS transistors M b1 MOSFET M b2 MOSFET M b3 MOSFET M b4 MOSFET M b5 MOSFET M b6 MOSFET M b7 MOSFET M b8 .

[0138] Among them, MOS transistor M b1 ~MOS transistor M b4 All are PMOS transistors, MOS transistor M b5 ~MOS transistor M b8 All are NMOS transistors.

[0139] MOSFET M b1 The gate of the MOSFET M b5 The gate of the MOSFET is used as the positive input of the nth delay unit, where n = 1, 2, ..., 7. b1 The drain of the MOSFET M b5 The drain of the MOSFET forms the first inverter structure; b2 The gate of the MOSFET M b6 The gate of the MOSFET M b2 The drain of the MOSFET M b6 The drain of the MOSFET forms the second inverter structure; b3 The gate of the MOSFET M b7 The gate of the MOSFET M b3 The drain of the MOSFET M b7 The drain of the MOSFET forms the third inverter structure; MOSFET M b4 The gate of the MOSFET M b8 The gate of the MOSFET serves as the negative input terminal of the nth delay unit. b4 The drain of the MOSFET M b8The drain of the first inverter forms the fourth inverter structure.

[0140] MOSFET M b1 ~MOS transistor M b4 The source and MOSFET M b5 ~MOS transistor M b8 The sources of the transistors are connected to the current output terminals of the VI conversion circuit, respectively, to receive the current signal output by the VI conversion circuit; and the MOSFET M... b1 ~MOS transistor M b4 The source of the delay unit serves as its voltage input, connected to an external... ; MOS transistor M b1 and MOSFET M b5 The drain of the MOSFET M b2 and MOSFET M b6 The gate of the MOSFET, and at the same time, the MOSFET M b2 and MOSFET M b6 The gate of the MOSFET M b3 and MOSFET M b7 The drain of the MOSFET is located at the M. b2 and MOSFET M b6 The connection node between the gates serves as the positive output terminal of the nth delay unit; MOSFET M b4 and MOSFET M b8 The drain of the MOSFET M b3 and MOSFET M b7 The gate of the MOSFET, and at the same time, the MOSFET M b2 and MOSFET M b6 The drain of the MOSFET M b3 and MOSFET M b7 The gate of the MOSFET, and located in the MOSFET M b3 and MOSFET M b7 The connection node between the gates serves as the negative output terminal of the nth delay unit.

[0141] In the VCO quantizer module, the oscillation frequency of the output digital signal is controlled by the delay unit. Specifically, the longer the delay of the delay unit, the lower the oscillation frequency. Conversely, the shorter the delay of the delay unit, the higher the oscillation frequency.

[0142] See Figure 6 In this embodiment, the VCO quantization circuit includes seven quantization units, namely Q1 to Q7. Each of the seven quantization units includes a buffer unit, two D flip-flop units (DFF) and an XOR unit, and all of them adopt a standard digital unit design.

[0143] In each quantization unit, the positive and negative input terminals of the buffer unit are connected to the positive and negative output terminals of the corresponding delay unit, respectively. The output terminal is connected to the D terminal of the first D flip-flop unit. The Q terminal of the first D flip-flop unit is connected to the D terminal of the second D flip-flop unit and the first input terminal of the XOR unit. The Q terminal of the second D flip-flop unit is connected to the second input terminal of the XOR unit. The CLK terminals of the two D flip-flop units are connected to an external clock circuit to receive an external clock signal with a period of... Reference clock The output of the XOR unit serves as the output of the VCO quantizer module, connected to the input of the current-steering feedback DAC module. This outputs the digital signal D<7:1> to the current-steering feedback DAC module, which contains D... <1> To D <7> Simultaneously, the digital signal DOUT<7:1> is output to the external lower-level device. It should be noted that the digital signal D<7:1> and the digital signal DOUT<7:1> here are the same signal; they are only used to distinguish between external output and feedback.

[0144] The core of the VCO quantization circuit lies in the need to calculate the reference clock. cycle The internal oscillation signal passes through 7 delay units. The counting method involves feeding the output of each delay unit into the corresponding D flip-flop unit sampled by clock CLK, then XORing the quantized phase value sampled at that moment with the quantized phase value sampled at the previous moment. The XOR output represents the number of delay units the oscillation signal passes through per unit period, thus solving the mismatch problem of the current-steering feedback DAC module. The VCO quantization circuit designed in this embodiment also has a subtle advantage because the XOR output has a Barrel-Shift characteristic, such as... Figure 9 As shown in the figure, V tune The input of the VCO quantization circuit is represented by D1 and D2, which represent the outputs of the two D flip-flop units, respectively. `out` represents the XOR output of the VCO quantization circuit. Connecting the XOR output of the VCO quantization circuit directly to the input of the current-following feedback DAC module provides an implicit DEM (Dynamic Component Matching) for the current-following feedback DAC module, thus helping to address the performance degradation caused by mismatch in the current-following feedback DAC module. Furthermore, the implicit DEM provided by the VCO quantization circuit does not consume additional power or occupy additional circuit area.

[0145] In summary, the working principle of a VCO quantization circuit is essentially the statistical analysis of the number of delay units the oscillation signal passes through within a unit cycle. Since the number of delay units in a VCO oscillation circuit is generally odd, and its structure is a loop connected end-to-end, when the oscillation signal propagates within this loop, there must be a delay unit in an unstable state. This instability manifests as the input and output being identical. In the next cycle, the oscillation signal will begin propagating from the output of this delay unit. The successful propagation is determined by whether the output of the D flip-flop unit has changed between the previous and current cycles. Conversely, if the output of the D flip-flop unit has not changed, the propagation has failed. The XOR unit is used to determine whether the propagation was successful. The final digital signal output by the VCO quantization circuit is in thermometer code format. This encoding method directly reflects the number of delay units through which the oscillation signal is propagated and directly affects the subsequent current-driven feedback DAC module.

[0146] For the VCO quantization circuit in this embodiment, the quantization voltage range is 300mV~1V. Figure 8 The frequency of its output digital signal within this voltage range The correspondence between voltage and voltage. Figure 8 The lowest voltage of 0.3V (300mV) corresponds to an output digital signal frequency of 9.73MHz, and the maximum voltage of 1V corresponds to a digital signal frequency of 238.91MHz, which meets the requirement that the maximum output frequency of a general modulator should not exceed half of the sampling frequency of 500MHz.

[0147] See Figure 1 In this embodiment, the current steering feedback DAC module mainly includes a feedback DAC unit and a zero-order feedback DAC unit.

[0148] The input terminals of the feedback DAC unit and the zero-order feedback DAC unit are respectively connected to the output terminals of the VCO quantizer module; the three positive output terminals of the feedback DAC unit are the first to third positive output terminals of the current-rudder feedback DAC module, respectively connected to the positive feedback terminals of the three-stage RC integrator circuit, and the three negative output terminals are the first to third negative output terminals of the current-rudder feedback DAC module, respectively connected to the negative feedback terminals of the three-stage RC integrator circuit; the positive and negative output terminals of the zero-order feedback DAC unit are the fourth positive and fourth negative output terminals of the current-rudder feedback DAC module, respectively connected to the zero-order feedback positive and zero-order feedback negative terminals of the third-stage RC integrator circuit.

[0149] Specifically, the feedback DAC unit includes three feedback circuits; the seven input terminals of each feedback circuit are connected to the output terminals of the seven VCO quantizer modules respectively, the positive output terminal is connected to the positive feedback terminal of the three-stage RC integrator circuit respectively, and the negative output terminal is connected to the negative feedback terminal of the three-stage RC integrator circuit respectively.

[0150] See Figure 11 All three feedback circuits include a current source I. REF01 Current source I REF02 MOSFET M c1 MOSFET M c2 MOSFET M c3 MOSFET M c4 MOSFET M c5 MOSFET M c6 RC noise reduction components, 7 switching transistors and 7 cascaded current sources.

[0151] All 7 switching transistors include MOSFETs M c7 and MOSFET M c8 All seven cascaded current sources include MOSFETs. c9 and MOSFET M c10 Among them, MOS transistor M c1 ~MOS transistor M c3 and MOSFET M c7 ~MOS transistor M c10 All are NMOS transistors; MOS transistor M c4 ~MOS transistor M c6 All are PMOS transistors.

[0152] MOSFET M c1 The gate of the MOSFET M c2 The gate of the MOSFET, and the connected node is connected to the MOSFET M c1 The drains of the two electrodes are connected to the current source I. REF01 Output terminal; MOSFET M c1 and MOSFET M c3 The sources of all transistors are grounded; MOSFET M c2 The source of the MOSFET is connected to the M c3 The drain of the MOSFET; c2 The drain of the MOSFET M c3 The gate of the MOSFET and one end of the RC noise reduction component; the other end of the RC noise reduction component is grounded; the MOSFET M c4 The gate of the MOSFET M c5 The gate of the MOSFET, and the connected node is connected to the MOSFET M c4 The drains of the two electrodes are connected to the current source I. REF02 Output terminal; MOSFET M c4 MOSFET M c5 and MOSFET Mc6 The sources are respectively connected to external... ; MOS transistor M c6 The gate of the MOSFET M c5 The gate of the MOSFET; c5 The drains of the transistors are connected to the MOSFETs M in the seven switching transistors. c7 The drain of the MOSFET M c6 The drains of the transistors are connected to the MOSFETs M in the seven switching transistors. c8 The drain of the MOSFET; at the same time, the MOSFET M c5 and MOSFET M c6 The drains of the transistors serve as the negative and positive output terminals of the feedback circuit, respectively, connecting to the negative and positive feedback terminals of the three-stage RC integrator circuit; among the seven switching transistors, the MOSFET M... c7 and MOSFET M c8 The gates of the transistors serve as the two input terminals of the feedback circuit, connecting to the output terminals of the seven quantization units; among the seven switching transistors, the MOSFET M... c7 and MOSFET M c8 The source is connected, and each is connected to one of the N cascaded current sources, specifically to the MOSFET M. c9 The drain of the MOSFET; 7 cascaded current sources in the MOSFET M c9 The gates of all are connected to MOSFETs M c2 The gate of the MOSFET; 7 cascaded current sources in the MOSFET M c10 The gates of all are connected to MOSFETs M c3 The gate of the MOSFET; 7 cascaded current sources in the MOSFET M c10 The sources of all transistors are grounded; in the same cascaded current source, the MOSFET M c9 The source connection corresponds to the MOSFET M c10 The drain electrode.

[0153] Among them, current source I REF01 MOSFET M c1 MOSFET M c2 MOSFET M c3 To form a bias circuit.

[0154] MOSFET M c7 and MOSFET M c8 This forms a switching circuit. It uses a MOSFET M... c7 and MOSFET M c8 The received digital signals (D and DN, which are two inverted signals) control the on / off state of the current, i.e., whether the feedback current flows to the positive and negative feedback terminals of the filter module, forming a feedback loop. The common-mode component of the current flowing through the cascaded current sources is through current source I. REF01 and current source I REF02In principle, this feedback DAC unit does not add a virtual ground point, meaning it does not add load to the positive and negative feedback terminals of the filter module. This ensures that the noise-to-output gain of the operational amplifier is 1, thus guaranteeing the linearity of the filter module and further enhancing the overall modulator performance. Furthermore, the full-scale range of both the feedback DAC unit and the modulator can be adjusted by regulating the gate voltage at the cascaded current source, i.e., by adjusting the current source I. REF01 The bias circuit is adjusted. In some modulators requiring dynamic range, variable gain operational amplifiers are typically used to improve the dynamic range; however, this embodiment only requires adjusting the bias voltage. Noise generated in the bias circuit can be removed using a simple RC noise reduction component. Furthermore, in the feedback DAC unit designed in this embodiment, a single-channel path is maintained from the output of the VCO quantizer module to the input of the feedback DAC unit to reduce circuit power consumption.

[0155] Current source I of the feedback DAC unit REF02 Current with a single cascaded current source It's a subtraction operation relationship. To ensure the feedback current of the differential output exhibits a symmetrical relationship, the following formula must be strictly satisfied:

[0156]

[0157] Right now:

[0158] .

[0159] Reference Figure 12 , for the first feedback circuit (example) in the modulator, the feedback current (I) OUTP I OUTN From this, we can see the feedback current (I) of the differential output. OUTP I OUTN They are exactly the same, only the flow direction is different.

[0160] See Figure 10 In this embodiment, the zero-order feedback DAC unit includes a MOS transistor M d1 MOSFET M d2 Current source I ref1 Current source I ref2 Capacitor C a Capacitor C b And 7 electric rudders.

[0161] All 7 current steering elements include MOSFETs M d3 MOSFET M d4 MOSFET M d5 MOSFET M d6 MOSFET M d7and MOSFET M d8 Among them, MOS transistor M d1 and MOSFET M d3 ~MOS transistor M d5 All are PMOS transistors; MOS transistor M d2 and MOSFET M d6 ~MOS transistor M d8 All are NMOS transistors.

[0162] MOSFET M d1 The source is connected to the external MOS transistor M d1 The gate and MOSFET M d1 The source is connected, and a capacitor C is connected. a One end, current source I ref1 The output terminal; capacitor C a The other end is grounded; MOSFET M d2 The drain and MOSFET M d2 The gate is connected, and capacitor C is connected. b One end, current source I ref2 Output terminal; MOSFET M d2 The source and capacitor C b The other end is grounded.

[0163] Of the 7 current rudders:

[0164] MOSFET M d3 The gate of the MOSFET M d1 The gate of the MOSFET; d3 The source is connected to the external ; MOS transistor M d8 The gate of the MOSFET M d2 The gate of the MOSFET; d8 The source of the MOSFET is grounded; d4 The gate connection corresponds to the MOSFET M d6 The gate of the MOSFET is used as the first input of the zero-order feedback DAC unit and connected to the output of the corresponding quantization unit; the MOSFET M d5 The gate of the MOSFET M d7 The gate of the MOSFET is connected to the output of the corresponding quantization unit, serving as the second input of the zero-order feedback DAC unit; d4 The drain of the MOSFET M d6 The drain of the MOSFET serves as the negative output terminal of the zero-order feedback DAC unit, connected to the negative zero-order feedback terminal of the third-stage RC integrator circuit; MOSFET M d5 The drain connection corresponds to the MOSFET M d7The drain of the circuit is used as the positive output terminal of the zero-order feedback DAC unit and connected to the positive zero-order feedback terminal of the third-stage RC integrator circuit.

[0165] In the same current rudder:

[0166] MOSFET M d4 and MOSFET M d5 The sources are respectively connected to MOSFETs M d3 The drain of the MOSFET; d6 and MOSFET M d7 The sources are respectively connected to MOSFETs M d8 The drain electrode.

[0167] In this embodiment, the zero-order feedback DAC unit adopts a complementary structure, and the current flowing from the zero-order feedback DAC unit to the filter module is ± This current is controlled by the digital signals (D and DN) output from the VCO quantizer module, which control the MOSFET M. d4 MOSFET M d6 and MOSFET M d5 MOSFET M d7 The switching on and off of the MOSFET is used for control. D and DN are a set of opposite signals; when D is 1, DN is 0. d4 MOSFET M d6 Turn off, MOSFET M d5 MOSFET M d7 When turned on, the feedback current (I) flowing to the filter module... OUTP I OUTN ( ) represents a set of opposite currents. Noise in a current-controlled zero-order feedback DAC unit can be reduced through a complementary structure, namely the complementary sub-current rudder with an upper and lower symmetrical structure shown in this invention.

Claims

1. A CT type Sigma-Delta modulator based on a ring VCO quantizer, comprising: a filter module, a VCO quantizer module, and a current steering feedback DAC module; input positive and negative terminals of the filter module are connected to external upper devices respectively, for receiving analog voltage signals input by the external upper devices and performing filtering; input positive and negative terminals of the VCO quantizer module are connected to output positive and negative terminals of the filter module respectively, and an output terminal of the VCO quantizer module is connected to an input terminal of the current steering feedback DAC module and an external lower device; the VCO quantizer module is configured to convert the analog voltage signals into digital signals and output the digital signals to the current steering feedback DAC module and the external lower device respectively; output positive and negative terminals of the current steering feedback DAC module are connected to feedback positive and negative terminals of the filter module respectively, to form a cascaded resonant feedback structure; input positive and negative terminals of a first-stage RC integrator circuit are connected to external upper devices respectively, for receiving analog voltage signals input by the external upper devices, and output positive and negative terminals of the first-stage RC integrator circuit are connected to input positive and negative terminals of a second-stage RC integrator circuit respectively; output positive and negative terminals of the second-stage RC integrator circuit are connected to input positive and negative terminals of a third-stage RC integrator circuit respectively; output positive and negative terminals of the third-stage RC integrator circuit are connected to input positive and negative terminals of the VCO quantizer module; the current steering feedback DAC module comprises a feedback DAC unit and a zero-order feedback DAC unit; input terminals of the feedback DAC unit and the zero-order feedback DAC unit are connected to an output terminal of the VCO quantizer module respectively; three output positive terminals of the feedback DAC unit are connected to feedback positive terminals of the third-stage RC integrator circuit respectively, and three output negative terminals of the feedback DAC unit are connected to feedback negative terminals of the third-stage RC integrator circuit respectively; output positive and negative terminals of the zero-order feedback DAC unit are connected to zero-order feedback positive and negative terminals of the third-stage RC integrator circuit respectively; the feedback DAC unit comprises three feedback circuits; N input terminals of each feedback circuit are connected to the output terminal of the VCO quantizer module, output positive terminals of each feedback circuit are connected to the feedback positive terminals of the third-stage RC integrator circuit, and output negative terminals of each feedback circuit are connected to the feedback negative terminals of the third-stage RC integrator circuit. 2.The CT type Sigma-Delta modulator based on the ring VCO quantizer according to claim 1, wherein: the first-stage RC integrator circuit comprises a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, and a first operational amplifier; the second-stage RC integrator circuit comprises a resistor R3, a resistor R4, a capacitor C3, a capacitor C4, and a second operational amplifier; and the third-stage RC integrator circuit comprises a resistor R7, a resistor R8, a capacitor C5, a capacitor C6, a third operational amplifier, a resistor R9, and a resistor R10. ​ ​ ​ The filter module is a third-order loop filter structure, including a three-stage RC integrator circuit and two resonant resistors R F ; ​ One end of each of the two resonance resistors R F is connected to the input positive terminal and the input negative terminal of the second-stage RC integrator circuit, respectively, and the other end is connected to the output negative terminal and the output positive terminal of the third-stage RC integrator circuit, respectively; ​ ​ ​ ​ ​ ​ Three of the feedback circuits each comprise a current source I REF01 , a current source I REF02 , a MOS transistor M c1 , a MOS transistor M c2 , a MOS transistor M c3 , a MOS transistor M c4 , a MOS transistor M c5 , a MOS transistor M c6 , an RC noise reduction component, N switches and N cascaded current sources N of said switching tubes each comprise a MOS transistor M c7 and a MOS transistor M c8 ; N of said cascaded current sources each comprise a MOS transistor M c9 and a MOS transistor M c10 ; The MOS transistor M c1 The MOS transistor M c3 The MOS transistor M c7 The MOS transistor M c10 The MOS transistor M c4 The MOS transistor M c6 The MOS transistor M the gate of the MOS transistor M c1 the gate of the MOS transistor M c2 the gate of the MOS transistor M c1 the drain of the MOS transistor M REF01 the output of the MOS transistor M The MOS transistor M c1 and the source of the MOS transistor M c3 are grounded. the source of the MOS transistor M c2 the drain of the MOS transistor M c3 the gate of the MOS transistor M c2 the drain of the MOS transistor M c3 the gate of the MOS transistor M, and one end of an RC noise reduction component; the other end of the RC noise reduction component is grounded; the gate of the MOS transistor M c4 the gate of the MOS transistor M c5 the gate of the MOS transistor M c4 the drain of the MOS transistor M REF02 the output of the MOS transistor M The source of the MOS transistor M c4 , the MOS transistor M c5 , and the MOS transistor M c6 is connected to an external V DD ; The drain of the MOS transistor M c6 is connected to the gate of the MOS transistor M c5 ; the drain of the MOS transistor M c5 is connected to the drain of the MOS transistor M c7 ; the drain of the MOS transistor M c6 is connected to the drain of the MOS transistor M c8 ; and the drain of the MOS transistor M c5 and the drain of the MOS transistor M c6 are connected to the feedback negative terminal and the feedback positive terminal of the three-stage RC integrator circuit respectively as the output negative terminal and the output positive terminal of the feedback circuit. MOS transistor M c7 and MOS transistor M c8 whose gates are connected to the output of the VCO quantizer module as two inputs of the feedback circuit; the sources of MOS transistors M c7 and MOS transistor M c8 are connected and the drains of MOS transistors M c9 are connected respectively. The gate of MOS transistor M c9 of the Nth cascade current source is connected to the gate of MOS transistor M c2 of the (N-1)th cascade current source; the gate of MOS transistor M c10 of the (N-2)th cascade current source is connected to the gate of MOS transistor M c3 of the (N-3)th cascade current source; the gate of MOS transistor M c10 of the (N-4)th cascade current source is connected to the gate of MOS transistor M c9 of the (N-5)th cascade current source; the source of MOS transistor M c10 of the same cascade current source is connected to the drain of corresponding MOS transistor M The zero-order feedback DAC unit comprises MOS transistor M d1 , MOS transistor M d2 , current source I ref1 , current source I ref2 , capacitor C a , capacitor C b , and N current steering units; N of said current steered each comprise a MOS transistor M d3 , a MOS transistor M d4 , a MOS transistor M d5 , a MOS transistor M d6 , a MOS transistor M d7 , and a MOS transistor M d8 ; MOS transistor M d1 and MOS transistor M d3 ~ MOS transistor M d5 are PMOS transistors; MOS transistor M d2 and MOS transistor M d6 ~ MOS transistor M d8 are NMOS transistors; The source of the MOS transistor M d1 is connected to an external V DD . The gate of the MOS transistor M d1 is connected to the source of the MOS transistor M d1 , and to one end of a capacitor C a , the output of a current source I ref1 ; the other end of the capacitor C a is grounded. The drain of the MOS transistor M d2 is connected to the gate of the MOS transistor M d2 , and to one end of the capacitor C b , the output of the current source I ref2 ; the source of the MOS transistor M d2 is grounded and the other end of the capacitor C b . Nth current steering DAC cell: the gate of MOS M d3 is connected to the gate of MOS M d1 ; the source of MOS M d3 is connected to the external V DD ; the gate of MOS M d8 is connected to the gate of MOS M d2 ; the source of MOS M d8 is connected to ground; the gate of MOS M d4 is connected to the gate of corresponding MOS M d6 , and is the first input of the zero-order feedback DAC cell, and is connected to the output of the VCO quantizer module; the gate of MOS M d5 is connected to the gate of MOS M d7 , and is the second input of the zero-order feedback DAC cell, and is connected to the output of the VCO quantizer module; the drain of MOS M d4 is connected to the drain of MOS M d6 , and is the negative output of the zero-order feedback DAC cell, and is connected to the zero-order feedback negative terminal of the third-stage RC integrator circuit; the drain of MOS M d5 is connected to the drain of corresponding MOS M d7 , and is the positive output of the zero-order feedback DAC cell, and is connected to the zero-order feedback positive terminal of the third-stage RC integrator circuit; In the same current steering: MOS transistor M d4 and MOS transistor M d5 The source of MOS transistor M d3 is connected to the drain of MOS transistor M d6 and MOS transistor M d7 The source of MOS transistor M d8 is connected to the drain of MOS transistor M ​ ​ ​ ​ two resonance resistors R F respectively resistor R5 and resistor R6; One end of the resistor R1 and the resistor R2 is the input positive terminal and the input negative terminal of the first RC integrator circuit respectively, which is used to connect the external upper device, and the other end is connected to the non-inverting input terminal and the inverting input terminal of the first operational amplifier respectively, and is used as the feedback positive terminal and the feedback negative terminal of the first RC integrator circuit, and is connected to the first output positive terminal and the first output negative terminal of the feedback DAC unit respectively; The other end of the resistor R1 and one end of the capacitor C1 are connected, and the other end of the resistor R2 and one end of the capacitor C2 are connected; the other end of the capacitor C1 and the capacitor C2 is connected to the output negative terminal and the output positive terminal of the first operational amplifier respectively, and the two nodes are used as the output negative terminal and the output positive terminal of the first RC integrator circuit respectively; One end of the resistor R3 and the resistor R4 is used as the input positive terminal and the input negative terminal of the second RC integrator circuit respectively, and is connected to the output positive terminal and the output negative terminal of the first RC integrator circuit respectively; The other end of the resistor R3 and one end of the capacitor C3 and the resistor R5 are connected to the non-inverting input terminal of the second operational amplifier respectively, and the other end of the resistor R4 and one end of the capacitor C4 and the resistor R6 are connected to the inverting input terminal of the second operational amplifier respectively, and the non-inverting input terminal and the inverting input terminal of the second operational amplifier are used as the feedback positive terminal and the feedback negative terminal of the second RC integrator circuit respectively, and are connected to the second output positive terminal and the second output negative terminal of the feedback DAC unit respectively; The other end of the capacitor C3 and the capacitor C4 is connected to the output negative terminal and the output positive terminal of the second operational amplifier respectively, and the two nodes are used as the output negative terminal and the output positive terminal of the second RC integrator circuit respectively; One end of the resistor R7 and the resistor R8 is used as the input positive terminal and the input negative terminal of the third RC integrator circuit respectively, and is connected to the output positive terminal and the output negative terminal of the second RC integrator circuit respectively, and the other end is connected to the non-inverting input terminal and the inverting input terminal of the third operational amplifier respectively, and is used as the feedback positive terminal and the feedback negative terminal of the third RC integrator circuit respectively, and is connected to the third output positive terminal and the third output negative terminal of the feedback DAC unit respectively; The other end of the resistor R7 and one end of the capacitor C5 are connected, and the other end of the resistor R8 and one end of the capacitor C6 are connected; The other end of the capacitor C5 and the resistor R5 is connected to the output negative terminal of the third operational amplifier, and one end of the resistor R9 is connected; the other end of the capacitor C6 and the resistor R6 is connected to the output positive terminal of the third operational amplifier, and one end of the resistor R10 is connected; The other end of the resistor R10 and the resistor R9 is used as the output positive terminal and the output negative terminal of the filter module respectively, and is connected to the input positive terminal and the input negative terminal of the VCO quantizer module respectively, and is used as the zero-order feedback positive terminal and the zero-order feedback negative terminal of the third RC integrator circuit respectively, and is connected to the output positive terminal and the output negative terminal of the zero-order feedback DAC unit respectively.

3. The CT type Sigma-Delta modulator based on the ring VCO quantizer according to claim 2, characterized in that: The VCO quantizer module comprises a V-I conversion circuit, a VCO oscillation circuit and a VCO quantization circuit; The input positive terminal and the input negative terminal of the V-I conversion circuit are connected to the output positive terminal and the output negative terminal of the filter module respectively, for converting the analog voltage signal into a current signal. The current input end of the VCO oscillation circuit is connected with the current output end of the V-I conversion circuit, and the voltage input end is connected with the external V DD , for generating an oscillation signal; The input positive terminal and the input negative terminal of the VCO quantization circuit are connected with the output positive terminal and the output negative terminal of the VCO oscillation circuit respectively, the clock interface is connected with the external clock circuit, and the output terminals are connected with the input terminals of the current steering feedback DAC module and the external lower-level device respectively; the VCO quantization circuit is used for receiving the reference clock F S with a period of T S input by the clock circuit, and generating digital signals according to the oscillation signal and the reference clock F S , and outputting the digital signals to the current steering feedback DAC module and the external lower-level device respectively.

4. The CT type Sigma-Delta modulator based on the ring VCO quantizer according to claim 3, wherein: The V-I conversion circuit comprises MOS transistor M a1 , MOS transistor M a2 , MOS transistor M a3 , MOS transistor M a4 , MOS transistor M a5 , MOS transistor M a6 , MOS transistor M a7 , MOS transistor M a8 , MOS transistor M a9 , MOS transistor M a10 , MOS transistor M a11 and negative feedback resistor R S ; The MOS transistor M a1 The MOS transistor M a4 The MOS transistor M a9 The MOS transistor M a11 The MOS transistor M a5 The MOS transistor M a8 The MOS transistor M The source of the MOS transistor M a5 The source of the MOS transistor M a8 is connected to an external V DD The source of the MOS transistor M a3 , the MOS transistor M a4 , and the MOS transistor M a9 The source of the MOS transistor M a11 is grounded. the gate of the MOS transistor M a7 the gate of the MOS transistor M a5 the gate of the MOS transistor M a7 the drain of the MOS transistor M a9 the drain of the MOS transistor M a5 the drain of the MOS transistor M a1 the drain of the MOS transistor M a5 the drain of the MOS transistor M the gate of the MOS transistor M a8 the gate of the MOS transistor M a6 the gate of the MOS transistor M a8 the drain of the MOS transistor M a10 the drain of the MOS transistor M a6 the drain of the MOS transistor M a2 the drain of the MOS transistor M a6 the gate of the MOS transistor M The gate of the MOS transistor M a1 connects the positive output end of the filter module, the source of the MOS transistor M a1 connects the MOS transistor M a3 the drain of the MOS transistor M a2 connects the negative output end of the filter module, the source of the MOS transistor M a2 connects the MOS transistor M a4 the drain of the MOS transistor M The gate of the MOS transistor M a3 is connected to an external bias voltage V a4 ; and the gate of the MOS transistor M B is connected to an external bias voltage V The negative feedback resistor R S is connected between the source of the MOS transistor M a1 and the source of the MOS transistor M a2 . The gate of the MOS transistor M a9 is connected to an external bias voltage V1, while the gate of the MOS transistor M a10 is connected to an external bias voltage V2, and the gate of the MOS transistor M a9 is connected to the drain of the MOS transistor M The gate of the MOS transistor M a11 is connected to its drain, and the node of the connection is connected to the drain of the MOS transistor M a10 , and simultaneously as the current output end of the V-I conversion circuit, and the current input end of the VCO oscillation circuit, for outputting the converted current signal to the VCO oscillation circuit.

5. The CT type Sigma-Delta modulator based on the ring VCO quantizer according to claim 4, wherein: The VCO oscillation circuit comprises N delay units connected in sequence and end to end; N is an odd number greater than or equal to 3; The VCO quantization circuit comprises N quantization units; The output positive terminal and the output negative terminal of the first delay unit are connected to the input positive terminal and the input negative terminal of the second delay unit respectively; the output positive terminal and the output negative terminal of the second delay unit are connected to the input positive terminal and the input negative terminal of the third delay unit respectively; and the output positive terminal and the output negative terminal of the Nth delay unit are connected to the input positive terminal and the input negative terminal of the first delay unit respectively. The current input end of each of the N delay units is connected to the current output end of a V-I conversion circuit, and the voltage input end is connected to the external V DD ; The output positive terminal and the output negative terminal of the N delay units are connected to the input positive terminal and the input negative terminal of the N quantization units respectively.

6. The CT type Sigma-Delta modulator based on the ring VCO quantizer according to claim 5, wherein: N of said delay units each comprise a MOS transistor M b1 , a MOS transistor M b2 , a MOS transistor M b3 , a MOS transistor M b4 , a MOS transistor M b5 , a MOS transistor M b6 , a MOS transistor M b7 , a MOS transistor M b8 ; MOS transistor M b1 ~ MOS transistor M b4 are all PMOS transistors, the MOS transistor M b5 ~ MOS transistor M b8 are all NMOS transistors; The drain of the MOS transistor M b1 The gate of the MOS transistor M b5 The gate of the MOS transistor M b1 The drain of the MOS transistor M b5 The drain of the MOS transistor M The gate of the MOS transistor M b2 The gate of the MOS transistor M b6 The gate of the MOS transistor M b2 The drain of the MOS transistor M b6 The drain of the MOS transistor M the gate of the MOS transistor M b3 the gate of the MOS transistor M b7 the gate of the MOS transistor M b3 the drain of the MOS transistor M b7 the drain of the MOS transistor M The drain of the MOS transistor M b4 is connected to the gate of the MOS transistor M b8 , the input negative terminal of the nth delay unit, the drain of the MOS transistor M b4 is connected to the gate of the MOS transistor M b8 , the fourth inverter structure is formed. The source of the MOS transistor M b1 The source of the MOS transistor M b4 The source of the MOS transistor M b5 The source of the MOS transistor M b8 The source of the MOS transistor M b1 The source of the MOS transistor M b4 The source of the MOS transistor M DD ​ The drain of the MOS transistor M b1 The gate of the MOS transistor M b5 The drain of the MOS transistor M b2 The gate of the MOS transistor M b6 The gate of the MOS transistor M b2 The gate of the MOS transistor M b6 The drain of the MOS transistor M b3 The drain of the MOS transistor M b7 The drain of the MOS transistor M b2 The gate of the MOS transistor M b6 The drain of the MOS transistor M the drain of the MOS transistor M b4 and the gate of the MOS transistor M b8 the drain of the MOS transistor M b3 and the gate of the MOS transistor M b7 the drain of the MOS transistor M b2 and the gate of the MOS transistor M b6 the drain of the MOS transistor M b3 and the gate of the MOS transistor M b7 the drain of the MOS transistor M b3 and the gate of the MOS transistor M b7 the drain of the MOS transistor M 7. The CT type Sigma-Delta modulator based on the ring VCO quantizer according to claim 6, wherein: Each of the N quantization units comprises a buffer unit, two D flip-flop units and an XOR unit; The input positive terminal and the input negative terminal of the buffer unit are connected to the output positive terminal and the output negative terminal of the corresponding delay unit respectively, and the output terminal is connected to the D terminal of the first D flip-flop unit; the Q terminal of the first D flip-flop unit is connected to the D terminal of the second D flip-flop unit and the first input terminal of the XOR unit respectively; and the Q terminal of the second D flip-flop unit is connected to the second input terminal of the XOR unit. The CLK terminals of the two D flip-flop units are respectively connected with external clock circuits for receiving a period T S of reference clock F S ; The output terminal of the XOR unit serves as the output terminal of the VCO quantizer module and is connected to the input terminal of the current steering feedback DAC module.

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