Ethercat master station synchronization control method and system based on microkernel operating system

Abstract

The application discloses an EtherCAT master station synchronization control method and system based on a microkernel operating system, and belongs to the technical field of industrial automation fieldbus control. The system adopts a microkernel architecture, deploys an EtherCAT protocol stack and a general network protocol stack as two independent user state processes, and carries out data interaction through an inter-process communication and shared memory mechanism provided by the microkernel. The method combines static compensation in the system initialization stage and dynamic compensation in the running stage through a bidirectional dynamic clock compensation mechanism, adopts a dynamic task scheduling strategy based on load sensing, dynamically adjusts the task execution order according to the real-time monitored CPU usage and task priority, introduces a hardware redundancy design of double clock sources and double communication links, and adopts a gradual synchronization recovery strategy during switching. The application can realize nanosecond-level synchronization accuracy and microsecond-level fault switching, and is suitable for industrial control scenes with extremely high real-time and reliability requirements.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of industrial automation field bus control, and in particular to an EtherCAT master station synchronization control method and system based on a microkernel operating system. BACKGROUND

[0002] EtherCAT (Ethernet for Control Automation Technology) is a mainstream real-time field bus technology in the industrial field, and its core advantages lie in high bandwidth, low latency and precise distributed synchronization control. As the control core of the bus system, the EtherCAT master station needs to realize real-time data interaction and clock synchronization with slave devices (such as servo drives, sensors and actuators), which is a key component for ensuring the consistency of collaborative action of industrial devices and is widely used in high-precision control scenarios such as numerical control machines, mechanical arms and automated production lines.

[0003] The existing synchronization control scheme of the EtherCAT master station is limited by the architecture design and technical implementation, and it is difficult to meet the stringent requirements of high-precision industrial scenarios. The main technical defects are as follows:

[0004] Lack of real-time performance: Traditional EtherCAT master stations are mostly developed based on macrokernel operating systems (such as Linux). In the macrokernel, kernel modules such as process management, memory management and device drivers are highly coupled with the application layer, and the context switching overhead is large, which causes the cycle control latency of the EtherCAT master station to fluctuate frequently by more than 100 μs, and cannot meet the real-time requirements of high-precision scenarios such as mechanical arm trajectory control, which require a latency fluctuation of ≤20 μs. Although some schemes attempt to introduce a microkernel operating system, there are still problems of redundant protocol call levels and delayed real-time response.

[0005] Synchronization accuracy is easily disturbed: Most master station synchronization controls rely on a single hardware clock source, lack of redundancy design and dynamic compensation mechanism. In industrial environments, factors such as electromagnetic interference, power fluctuations and temperature changes easily lead to clock drift error accumulation, causing the synchronization deviation of the master station and the slave station to exceed 50 ns, affecting the consistency of the collaborative action of multiple devices.

[0006] Poor coordination between task scheduling and synchronization control: The task scheduling mechanism of the macrokernel operating system is not optimized for EtherCAT synchronization tasks, and synchronization control tasks (such as clock calibration and PDO data interaction) and non-real-time tasks (such as log recording and UI display) share system resources, which easily leads to "task preemption delay", causing unstable synchronization frame sending period.

[0007] Weak fault redundancy capability: Existing schemes generally lack a perfect hardware redundancy and abnormal recovery mechanism. Some master stations only achieve communication link redundancy through ring topology, and when the master clock source fails or the communication link is interrupted, the master station needs to be restarted to recover synchronization, which seriously affects the continuity of the production line.

[0008] In view of the above problems, there is an urgent need for an EtherCAT master station synchronization control scheme based on a microkernel operating system, which can improve real-time performance, synchronization accuracy and anti-interference capability. SUMMARY

[0009] The purpose of the present application is to provide an EtherCAT master station synchronization control method and system based on a microkernel operating system, to realize the deep integration of high-precision clock synchronization, high-real-time dynamic task scheduling and high-reliability redundant control, and to meet the harsh requirements of high-precision industrial control scenarios.

[0010] To achieve the above purpose, the technical solution adopted by the present application is:

[0011] The EtherCAT master station synchronization control method based on the microkernel operating system comprises the following steps:

[0012] (1) System architecture deployment: In the microkernel operating system, the EtherCAT protocol stack and the general network protocol stack are deployed as two independent user-mode processes, and data interaction is performed through the inter-process communication and shared memory mechanism provided by the microkernel, and the EtherCAT protocol stack process is configured to have the highest scheduling priority;

[0013] (2) Clock synchronization: In the EtherCAT protocol stack process, slave clock synchronization is performed, including: in the system initialization phase, static compensation is performed, and the clock offset is pre-compensated by calculating the transmission delay between the master station and the slave station; in the system running phase, dynamic compensation is performed, the master station periodically collects the slave clock value, and the frequency and phase of the slave clock are adjusted in real time based on the clock deviation;

[0014] (3) Dynamic task scheduling: the system tasks are divided into real-time tasks, periodic tasks and background tasks of different priorities, and the time slice and execution order of the tasks are dynamically adjusted based on real-time monitoring of the system load;

[0015] (4) Redundant control: the working state of the master clock source and the master communication link is monitored in real time, and when a fault is detected, the standby clock source or the standby communication link is automatically switched to, and a gradual synchronization recovery strategy is adopted during the switching process.

[0016] Further, the system architecture deployment step specifically comprises:

[0017] The EtherCAT protocol stack process is configured to be bound to a dedicated CPU core for exclusive running;

[0018] The scheduling priority of the general network protocol stack process is configured as a dynamically adjustable mode, and is set as a high priority when performing an EtherCAT communication task and is set as a lower priority when performing a non-real-time network task;

[0019] The inter-process communication and shared memory mechanism provided by the micro-kernel operating system is used to realize zero-copy data frame interaction between the EtherCAT protocol stack process and the general network protocol stack process.

[0020] Further, the zero-copy data frame interaction realized through the inter-process communication and shared memory mechanism specifically includes:

[0021] A shared memory region is pre-allocated in a system initialization stage, and is mapped to the virtual address space of the EtherCAT protocol stack process and the general network protocol stack process, respectively;

[0022] The EtherCAT data frame received by the general network protocol stack process is directly written into the shared memory;

[0023] The EtherCAT protocol stack process directly reads and processes the EtherCAT data frame from the shared memory.

[0024] Further, the dynamic compensation specifically includes: the master periodically sends an ARMW frame to the slave to obtain the slave clock information and calculate the clock deviation; the deviation is input into a PI controller to calculate a clock adjustment amount, and the adjustment amount is applied to the slave through EtherCAT communication to adjust the frequency and phase of the slave clock in real time, thereby realizing closed-loop control.

[0025] Further, in the dynamic task scheduling process, the basis for dynamic adjustment is real-time monitoring of CPU usage and task response time; when the CPU usage is higher than a set threshold, the CPU resources of the real-time task are guaranteed, and the time slice of the non-real-time task is compressed.

[0026] Further, in the dynamic task scheduling process, the priority of the real-time task is higher than that of the periodic task, and the priority of the periodic task is higher than that of the background task;

[0027] The real-time task includes clock calibration, periodic synchronization frame transmission and reception, and synchronization deviation detection operation, and adopts a pre-emptive scheduling mechanism, and the execution period of the real-time task is at least 125μs;

[0028] The periodic task includes service data object configuration and process data object transmission, and is executed only when the real-time task is idle;

[0029] The background task includes log recording, state monitoring, UI display, time slice round-robin scheduling, time slice is 500 mu s by default, when real-time task load is greater than 80%, time slice is compressed to 125 mu s.

[0030] Further, in the microkernel dynamic task scheduling, the memory protection mechanism of the microkernel is used to allocate independent memory spaces for the real-time task, the periodic task and the background task, to prohibit low-priority tasks from accessing the memory area of high-priority tasks, and to allow the real-time task and the periodic task to transmit data through a shared memory pool allowing only read and write operations.

[0031] Further, the progressive synchronization strategy sequentially performs frequency coarse adjustment, phase fine adjustment and stable tracking operation, and gradually converges the deviation between the standby clock and the master clock to within the set threshold through phase progressive adjustment.

[0032] The application also provides an EtherCAT master station synchronization control system based on a microkernel operating system, which is used to execute the EtherCAT master station synchronization control method based on the microkernel operating system.

[0033] The microkernel operating system module is used to provide task scheduling, inter-process communication and memory management services.

[0034] The EtherCAT protocol stack module is used to realize EtherCAT master station communication and clock synchronization functions.

[0035] The clock synchronization module includes a static compensation unit and a dynamic compensation unit, the static compensation unit is used to calculate transmission delay and pre-compensate clock offset in the system initialization stage, and the dynamic compensation unit is used to real-time adjust the frequency and phase of the slave station clock in the system running stage.

[0036] The dynamic task scheduling module is used to dynamically adjust the task execution order according to system load and task priority.

[0037] The redundancy control module is used to realize automatic switching and recovery of double clock sources and double communication links, and to use the progressive synchronization strategy during switching.

[0038] Further, the microkernel core layer of the microkernel operating system module provides real-time scheduling support, interacts with the user state EtherCAT protocol stack process through inter-process communication; the hardware abstraction layer uniformly encapsulates the dual EtherCAT communication module, the dual clock module and the interrupt controller; the microkernel operating system supports hardware timestamp function, and the timestamp accuracy is better than ±1 ns; the clock stability of the dual clock module is better than 0.1 ppm; the redundant control module is connected with the hardware interrupt pin through the hardware abstraction layer, and supports switching of the clock source or the communication link within 100 microseconds.

[0039] The above scheme has the beneficial effects of:

[0040] 1. The microkernel architecture of the application is deeply integrated with the protocol stack, so that the key communication tasks can bypass the complex scheduling and network protocol stack of the traditional macrokernel, and are directly scheduled and resource allocated by the microkernel with the highest priority. This eliminates the coupling interference between the kernel module and the application layer from the architecture level, makes the system response to synchronous tasks more direct and the time delay more stable, significantly reduces the delay and jitter of task scheduling, and provides a stable and reliable running foundation for high real-time control. The scheme can fully adapt to scenes such as numerical control machine tools and mechanical arms that have strict real-time requirements.

[0041] 2. The bidirectional dynamic clock synchronization mechanism proposed in the application eliminates fixed delay through static compensation in the system startup stage, and continuously performs dynamic compensation to track and suppress clock drift in the running process. This method can effectively cope with the influence of factors such as temperature change, electromagnetic interference and load fluctuation. Moreover, this mechanism covers the whole life cycle of clock synchronization, compared with the scheme that only relies on single frequency adjustment, it can more comprehensively cope with interference factors in industrial environment, ensure that the synchronization deviation of master and slave stations always maintains at a very low level, and guarantee the consistency of multi-device cooperative action, so as to realize and long-term maintain the extremely high synchronization accuracy of nanosecond level.

[0042] 3. The dynamic task scheduling strategy based on load sensing can monitor the system resource state in real time, and dynamically adjust the task execution order and time slice allocation according to the task priority. This not only guarantees the real-time response of synchronous control and other key tasks, but also intelligently compresses the resource occupation of non-key tasks under high load. This strategy realizes "core task priority guarantee, resource allocation on-demand adaptation", which not only avoids the problem of unstable synchronization frame sending period in high load scene, but also fully utilizes system resources, realizes the best balance between system resource utilization efficiency and real-time task performance.

[0043] 4. The hardware redundancy design of double clock sources and double communication links, combined with the progressive synchronization recovery strategy, can realize seamless switching when a fault is detected, and through gradually adjusting the frequency of the standby clock during the switching process, the deviation converges within the threshold, avoiding the device jitter caused by sudden synchronization. This design avoids system interruption caused by single point failure, greatly enhances the fault tolerance and continuous operation reliability of the system, and makes it adapt to long-term stable operation in harsh industrial environments. BRIEF DESCRIPTION OF DRAWINGS

[0044] Figure 1 The system architecture diagram of the present application is shown in Figure 1.

[0045] Figure 2 The clock synchronization flowchart in the embodiment of the present application is shown in Figure 2.

[0046] Figure 3 The dynamic task scheduling flowchart in the embodiment of the present application is shown in Figure 3.

[0047] Figure 4 The redundancy switching control flowchart in the embodiment of the present application is shown in Figure 4.

[0048] Figure 5 The experimental synchronization deviation curve in the embodiment of the present application is shown in Figure 5. DETAILED DESCRIPTION

[0049] The present application will be further described in detail below in combination with the drawings and specific embodiments.

[0050] It should be noted that, unless otherwise specified, all technical and scientific terms used herein have the same meaning as generally understood by those skilled in the art to which the present application belongs.

[0051] Embodiment 1

[0052] The EtherCAT master station synchronization control method based on the microkernel operating system comprises the following steps:

[0053] System architecture deployment: in the microkernel operating system, the EtherCAT protocol stack and the general network protocol stack are deployed as two independent user state processes, and data interaction is carried out through the inter-process communication and shared memory mechanism provided by the microkernel, and the EtherCAT protocol stack process is configured to have the highest scheduling priority;

[0054] Clock synchronization: in the EtherCAT protocol stack process, slave clock synchronization is performed, including: in the system initialization stage, static compensation is performed, and the clock offset is pre-compensated by calculating the transmission delay between the master station and the slave station; in the system running stage, dynamic compensation is performed, the master station periodically collects the slave clock value, and the frequency and phase of the slave clock are adjusted in real time based on the clock deviation;

[0055] Dynamic task scheduling: divide system tasks into real-time tasks, periodic tasks and background tasks of different priorities, and dynamically adjust the time slice and execution order of the tasks based on real-time monitoring of system load;

[0056] Redundancy control: real-time monitoring of the working state of the main clock source and the main communication link, automatic switching to the backup clock source or backup communication link when a fault is detected, and using a gradual synchronization recovery strategy during the switching process.

[0057] The implementation process of each step is described in detail as follows:

[0058] (1) System architecture deployment

[0059] The EtherCAT master station synchronization control system based on the microkernel operating system adopts a five-layer architecture, including a hardware abstraction layer, a microkernel core layer, an EtherCAT protocol layer, a synchronization control layer and an application layer. The system architecture block diagram is shown in Figure 1 .

[0060] The hardware abstraction layer is responsible for encapsulating hardware resources, including EtherCAT communication interfaces, clock modules and interrupt controllers. Specifically, dual EtherCAT communication modules and dual clock modules are used. The dual EtherCAT communication module uses two LAN9252 chips, the main clock source is the CPU crystal oscillator, and the backup clock source is the DS3231 RTC. This layer provides standardized interfaces, such as rk3588_nsleep() for nanosecond-level delay and HAL_EtherCAT_SendFrame() for sending EtherCAT frames.

[0061] The microkernel core layer only retains the core functions of process scheduling, memory protection and inter-process communication. The kernel provides high-priority IPC mechanisms, including event flags and semaphores, for inter-process synchronization.

[0062] The EtherCAT protocol layer is developed based on the SOEM open-source protocol stack, which implements the EtherCAT master station function, including slave station scanning, PDO mapping and SYNC frame sending. This layer runs as an independent user-mode process, is configured as the highest scheduling priority of the system, and is bound to a dedicated CPU core for exclusive operation to avoid context switching overhead.

[0063] The synchronization control layer includes a clock synchronization module, a dynamic task scheduling module and a redundancy control module, which are responsible for clock synchronization, task scheduling and fault recovery respectively. The clock synchronization module provides Clock_CalcDeviation() and Clock_Compensate() interfaces for calculating master-slave clock deviation and performing clock compensation respectively; the dynamic task scheduling module provides pthread_attr_setschedparam(), pthread_create() and Sched_SetPriority() interfaces for setting task scheduling parameters, creating tasks and adjusting task priorities respectively; and the redundancy control module provides Redundancy_DetectError(), ec_check_slave_config() and Redundancy_Switch() interfaces for detecting errors, checking slave configuration state and performing redundancy switching respectively.

[0064] The application layer provides API interfaces such as Sync_StartControl() for starting synchronization control, Sync_GetDeviation() for obtaining synchronization deviation, and Sync_SetCycle() for setting synchronization cycle, to support secondary development of users.

[0065] The general network protocol stack (such as TCP / IP stack) is run as another independent user mode process, and its scheduling priority can be dynamically adjusted. When performing EtherCAT communication tasks, the network stack priority is set to high priority; and when performing non-real-time network tasks (such as data log uploading), the priority is adjusted to sub-high priority.

[0066] The EtherCAT protocol stack process and the network stack process interact through microkernel IPC and shared memory mechanism. In the system startup phase, an 8KB physically contiguous shared memory region is pre-allocated through the mem_alloc_contiguous() interface and mapped to the virtual address space of the two processes. The network stack process directly maps the EtherCAT frame received by the network card DMA to the shared memory, and the EtherCAT protocol stack process directly reads the data in the shared memory, realizing zero-copy data transmission.

[0067] (2) Clock synchronization process

[0068] The specific implementation of clock synchronization includes static compensation and dynamic compensation, and the clock synchronization flow is as shown in Figure 2

[0069] ​The static compensation is performed in the system initialization stage. The master station first enumerates the slave stations through the APRD frame, filters the slave stations supporting distributed clock and having hardware timestamp to mark as "synchronization node", and automatically identifies the first slave station supporting DC function as the reference clock source. The master station constructs the network topology graph by analyzing the port state of the slave station, and sends the test frame to calculate the round-trip delay (RTT). According to the RTT and the topology structure, the master station writes the one-way delay compensation value into the corresponding register of the slave station, and completes the initial offset pre-compensation.

[0070] The dynamic compensation is performed in the system running stage. The master station periodically sends the ARMW (Auto Increment Read Multiple Write) frame to the slave station, reads the absolute time of the reference slave station, and performs real-time deviation compensation. The master station calculates the real-time deviation: ΔT = T_slave - (T_master + static compensation value). The deviation is input into the PI controller to calculate the clock adjustment amount. The adjustment amount is sent to the slave station through the ARMW frame, and the slave station corrects the local clock frequency and phase in real time according to the adjustment amount, forming a closed-loop control.

[0071] The frequency adjustment amount calculation formula of the PI controller is: frequency adjustment amount = Kp x Δf + Ki x ∫Δfdt, wherein Kp is the frequency proportional coefficient, Ki is the frequency integral coefficient, and Δf is the frequency deviation. The value range of Kp is generally 0.01-0.5, and the value range of Ki is generally 0.001-0.05.

[0072] The phase adjustment amount calculation formula of the PI controller is: phase adjustment amount = Kp' x Δφ + Ki' x ∫Δφdt, wherein Kp' is the phase proportional coefficient, Ki' is the phase integral coefficient, and Δφ is the phase deviation. The value range of Kp' is generally 0.1-1.0, and the value range of Ki' is generally 0.005-0.1.

[0073] In this embodiment, Kp = 0.1, Ki = 0.01, Kp' = 0.5, and Ki' = 0.02. In actual application, adaptive adjustment can be made within or near the above ranges according to the network size, slave station performance, and specific requirements for synchronization dynamic performance.

[0074] The clock synchronization between slave stations is realized through the PLL controller. The reference slave station returns the calibrated clock to the master station as a reference through periodic communication frames, and the master station sends the system time to all slave stations through the broadcast write function of the LRW frame. Each slave station inputs the received system time into the local PLL controller to update the local synchronization counter, ensuring that the clock deviation between slave stations does not exceed 10 ns.

[0075] (3) Dynamic task scheduling

[0076] The implementation process of dynamic task scheduling includes:

[0077] The system tasks are divided into three priority levels:

[0078] Real-time tasks: including clock calibration, periodic synchronization frame transmission and reception, and synchronization deviation detection, with the highest priority (P1) and preemptive scheduling, and the lowest execution period of 125μs.

[0079] Periodic tasks: including service data object configuration and process data object transmission, with the second highest priority (P2) and periodic scheduling, and only executed when the real-time task is idle.

[0080] Background tasks: including log recording, state monitoring, and UI display, with the lowest priority (P3) and time slice round-robin scheduling, with a default time slice of 500μs.

[0081] The microkernel real-time monitoring system load and dynamically adjusts task resources through the Sched_AdjustTimeSlice() function. When the CPU usage is higher than 80% or the real-time task load exceeds 80%, the system compresses the background task time slice to 125μs and suspends the time slice allocation of non-real-time tasks to ensure the real-time task is executed without delay.

[0082] Through the memory protection mechanism of the microkernel, independent memory spaces are allocated for the three types of tasks, and low-priority tasks are prohibited from accessing high-priority task memory areas. Real-time tasks and periodic tasks transmit data through a shared memory pool (size 4KB, only read and write operations are allowed) to avoid IPC communication delay. The dynamic task scheduling process is shown in Figure 3 .

[0083] The microkernel real-time monitors the execution time of real-time tasks, and when the execution time of three consecutive periods is greater than the set communication period, it automatically suspends the time slice allocation of non-real-time tasks, releases CPU resources to high-priority tasks, and ensures real-time tasks without delay.

[0084] (4) Redundancy control

[0085] The implementation process of redundancy control includes:

[0086] The system real-time monitors two types of exceptions:

[0087] Clock source exception: when the clock drift exceeds 5ns / ms, it is determined that the main clock source is abnormal.

[0088] Communication link exception: when the master station does not receive a response from the slave station for three consecutive periods or the number of failed SYNC frame transmissions exceeds three times, it is determined that the communication is abnormal.

[0089] After detecting the exception, the redundancy control module triggers the switch, and the redundancy switching control process is as followsFigure 4 as shown.

[0090] Clock source switching: The microkernel triggers a clock switch interrupt through the hardware abstraction layer, switching to the backup clock source (DS3231 RTC) within 100 μs. The master station sends a "clock source switching notification frame" to all slaves, and the slaves switch the clock reference synchronously.

[0091] Link redundancy switching: The master station automatically enables the backup EtherCAT communication interface (LAN9252 chip) and reestablishes the connection through a "link switching instruction" within 500 μs.

[0092] Fault recovery adopts a gradual synchronization strategy, including three steps:

[0093] Frequency coarse adjustment: Adjust the backup clock frequency at a rate of 100 ns / ms to quickly reduce the deviation from the master clock.

[0094] Phase fine adjustment: Make subtle adjustments to the backup clock phase to further reduce the phase difference.

[0095] Stable tracking: The backup clock continuously tracks the system's desired clock frequency and phase until the deviation converges within a set threshold, such as stabilizing the final deviation at ≤10 ns.

[0096] In implementation, frequency coarse adjustment adjusts the backup clock frequency at a rate of 100 ns / ms until the frequency deviation is less than 50 ns; phase fine adjustment converges the phase difference to within 20 ns through the controller; and the stable tracking stage maintains a deviation of ≤10 ns.

[0097] Embodiment 2

[0098] This embodiment provides an EtherCAT master station synchronization control system based on a microkernel operating system, including:

[0099] A microkernel operating system module for providing task scheduling, inter-process communication, and memory management services;

[0100] An EtherCAT protocol stack module running as an independent user-mode process, used to implement EtherCAT master station communication and clock synchronization functions;

[0101] A clock synchronization module including a static compensation unit and a dynamic compensation unit, the static compensation unit is used to calculate the transmission delay and pre-compensate the clock offset during the system initialization phase, and the dynamic compensation unit is used to adjust the slave clock frequency and phase in real time during the system running phase;

[0102] A dynamic task scheduling module dynamically adjusts the task execution order according to system load and task priority;

[0103] A redundancy control module is configured to realize automatic switching and recovery of the dual clock source and the dual communication link, and to employ a gradual synchronization strategy during the switching.

[0104] The microkernel core layer of the microkernel operating system module provides real-time scheduling support, interacts with an EtherCAT protocol stack process in a user state through inter-process communication, and a hardware abstraction layer uniformly encapsulates a dual EtherCAT communication module, a dual clock module and an interrupt controller; the system supports a hardware timestamp function, and the timestamp precision is better than ±1 ns; the clock stability of the dual clock module is better than 0.1 ppm; the redundancy control module is connected with a hardware interrupt pin through the hardware abstraction layer, and supports switching of a clock source or a communication link within 100 μs.

[0105] In the embodiment, the system hardware and software are configured as follows:

[0106] Hardware layer:

[0107] Microkernel operating system module: RK3588 (ARM Cortex-A53 / A73 architecture, 4-core 2.4 GHz+4-core 1.8 GHz) is adopted, and hardware floating point operation and high-speed interrupt response are supported.

[0108] EtherCAT communication module: dual LAN9252 chips are adopted, are connected with a microprocessor through an SPI interface, support 100 Mbps full-duplex communication, and the hardware timestamp precision is better than ±1 ns.

[0109] Dual clock module: the main clock source is a CPU crystal oscillator (2.4 GHz), and the standby clock source is a DS3231 RTC, and the clock stability is less than or equal to 0.1 ppm.

[0110] Power module: 220V DC input, supports overvoltage and overcurrent protection.

[0111] Software layer:

[0112] Microkernel operating system: real-time indicators include context switching time ≤0.7 μs, real-time task response ≤3 μs, and interrupt delay ≤2 μs.

[0113] Hardware abstraction layer: LAN9252 driver, OSAL_Timer driver and DS3231 driver are provided, and frame sending / receiving, clock configuration and RTC reading and writing are realized.

[0114] EtherCAT protocol layer: developed based on a SOEM protocol stack, supports slave station scanning ec_config_init(), PDO mapping pdo_config() and SYNC frame sending ec_send_processdata().

[0115] Synchronization control layer:

[0116] Clock synchronization module: provides Clock_CalcDeviation() for calculating clock deviation, Clock_Compensate() responsible for executing the output of the PI controller, completing the adjustment of the slave clock.

[0117] Dynamic task scheduling module: provides Sched_CreateTask() for creating tasks, Sched_SetPriority() for adjusting priority.

[0118] Redundancy control module: provides Redundancy_DetectError() for monitoring errors, Redundancy_Switch() for performing redundancy switching.

[0119] Application layer API: provides interfaces such as Sync_StartControl(), Sync_GetDeviation(), Sync_SetCycle(), etc., supporting user configuration of synchronization period and reading of synchronization deviation.

[0120] Experimental results

[0121] Under typical industrial environment (temperature -10℃~60℃, electromagnetic interference level 3), continuous testing was carried out, 10000 groups of data were collected, the average synchronization deviation was 6.3ns, the standard deviation was 1.8ns, the maximum value was 9.7ns, and the system performance met:

[0122] Synchronization deviation: ≤10ns (standard deviation ≤2ns);

[0123] Master-slave station switching time: ≤500μs;

[0124] System CPU load: ≤80% under peak scenario;

[0125] Task response time jitter: ≤5μs.

[0126] Test platform configuration:

[0127] Master CPU: ARM Cortex-A53 @1.2GHz;

[0128] Slave device: 10 EtherCAT servo drives;

[0129] Communication cycle: 1ms.

[0130] The synchronization deviation test curve is shown in Figure 5 .

[0131] The EtherCAT protocol stack of the application is completely decoupled from the general network stack, and the two interact through the IPC mechanism provided by the microkernel, rather than directly depending on each other. The network stack can be flexibly enabled, disabled or modified according to the scene, and the function thereof can be quickly customized according to the user demand without touching the kernel core logic. Meanwhile, combined with the bidirectional clock compensation, dynamic task scheduling and hardware redundancy mechanism, high-precision and high-reliability EtherCAT master station synchronous control is realized, and the application has strong industrial application value and innovation.

[0132] Finally, it should be noted that the parts of the application not described in detail are all prior art. Those skilled in the art can understand that the above description is only a preferred example of the application and is not used to limit the application, although the application has been described in detail with reference to the foregoing examples. However, those skilled in the art can modify the technical solutions recorded in the foregoing examples or make equivalent replacement for part of the technical features. Any modification, equivalent replacement, etc. within the spirit and principles of the application shall be included in the protection scope of the application.

Claims

1. An EtherCAT master station synchronization control method based on a microkernel operating system, characterized in that, The method includes the following steps: (1) System architecture deployment: In the microkernel operating system, the EtherCAT protocol stack and the general network protocol stack are deployed as two independent user-mode processes, and the EtherCAT protocol stack process is configured to run exclusively on a dedicated CPU core; data interaction is carried out through the inter-process communication and shared memory mechanism provided by the microkernel, specifically including: pre-allocating a shared memory region during the system initialization phase and mapping it to the virtual address spaces of the EtherCAT protocol stack process and the general network protocol stack process respectively; the general network protocol stack process directly writes the received EtherCAT data frames into the shared memory; the EtherCAT protocol stack process directly reads and processes the EtherCAT data frames from the shared memory to achieve zero-copy data frame interaction; the EtherCAT protocol stack process is configured to have the highest scheduling priority; (2) Clock synchronization: In the EtherCAT protocol stack process, slave clock synchronization is performed, including: in the system initialization phase, static compensation is performed to pre-compensate the clock offset by calculating the transmission delay between the master station and the slave station; in the system operation phase, dynamic compensation is performed, specifically including: the master station periodically sends ARMW frames to the slave station to obtain the slave station clock information and calculates the clock offset; the offset is input into the PI controller to calculate the clock adjustment amount, and the adjustment amount is applied to the slave station through EtherCAT communication to adjust the frequency and phase of the slave station clock in real time, thereby realizing closed-loop control; (3) Dynamic task scheduling: The system tasks are divided into real-time tasks, periodic tasks and background tasks with different priorities, and the time slices and execution order of tasks are dynamically adjusted based on the real-time monitoring of the system load. (4) Redundancy control: Real-time monitoring of the working status of the master clock source and the master communication link. When a fault is detected, the system automatically switches to the backup clock source or backup communication link and adopts a gradual synchronization recovery strategy during the switching process.

2. The EtherCAT master station synchronization control method based on a microkernel operating system according to claim 1, characterized in that, The system architecture deployment steps specifically include: Configure the scheduling priority of the general network protocol stack process to a dynamically adjustable mode, setting it to high priority when executing EtherCAT communication tasks and lower priority when executing non-real-time network tasks; Zero-copy data frame interaction between the EtherCAT protocol stack process and the general network protocol stack process is achieved through the inter-process communication and shared memory mechanisms provided by the microkernel operating system.

3. The EtherCAT master station synchronization control method based on a microkernel operating system according to claim 1, characterized in that, During the dynamic task scheduling process, the dynamic adjustment is based on real-time monitoring of CPU utilization and task response time; when CPU utilization is higher than a set threshold, CPU resources for real-time tasks are guaranteed, and time slices for non-real-time tasks are compressed.

4. The EtherCAT master station synchronization control method based on a microkernel operating system according to claim 3, characterized in that, During dynamic task scheduling, real-time tasks have a higher priority than periodic tasks, and periodic tasks have a higher priority than background tasks. The real-time tasks include clock calibration, periodic synchronization frame transmission and reception, and synchronization deviation detection operations. They adopt a preemptive scheduling mechanism, and their execution cycle is as low as 125μs. The periodic tasks include service data object configuration and process data object transmission, and are executed only when the real-time tasks are idle. The background tasks include log recording, status monitoring, and UI display. They are scheduled using a time-slice round-robin system, with a default time slice of 500μs. When the real-time task load exceeds 80%, the time slice is compressed to 125μs.

5. The EtherCAT master station synchronization control method based on a microkernel operating system according to claim 4, characterized in that, In microkernel dynamic task scheduling, the microkernel's memory protection mechanism allocates independent memory spaces for real-time tasks, periodic tasks, and background tasks, prohibits low-priority tasks from accessing the memory areas of high-priority tasks, and real-time tasks and periodic tasks transfer data through a shared memory pool that only allows read and write operations.

6. The EtherCAT master station synchronization control method based on a microkernel operating system according to claim 1, characterized in that, The progressive synchronization strategy sequentially performs frequency coarse adjustment, phase fine adjustment, and stable tracking operations. Through progressive phase adjustment, the deviation between the backup clock and the master clock gradually converges to within a set threshold.

7. An EtherCAT master station synchronization control system based on a microkernel operating system, characterized in that, For executing the EtherCAT master station synchronization control method based on a microkernel operating system as described in any one of claims 1-6, the EtherCAT master station synchronization control system comprises: The microkernel operating system module provides services for task scheduling, inter-process communication, and memory management. The EtherCAT protocol stack module runs as an independent user-space process and is used to implement EtherCAT master station communication and clock synchronization functions. The clock synchronization module includes a static compensation unit and a dynamic compensation unit. The static compensation unit is used to calculate the transmission delay and pre-compensate the clock offset during the system initialization phase, and the dynamic compensation unit is used to adjust the slave clock frequency and phase in real time during the system operation phase. The dynamic task scheduling module dynamically adjusts the task execution order based on system load and task priority. The redundancy control module is used to realize the automatic switching and recovery of dual clock sources and dual communication links, and adopts a progressive synchronization strategy during the switching.

8. The EtherCAT master station synchronization control system based on a microkernel operating system according to claim 7, characterized in that, The microkernel operating system module's microkernel core layer provides real-time scheduling support and interacts with the user-space EtherCAT protocol stack process through inter-process communication. The hardware abstraction layer provides unified encapsulation for the dual EtherCAT communication module, dual clock module, and interrupt controller. The microkernel operating system supports hardware timestamp functionality with a timestamp accuracy better than ±1ns. The clock stability of the dual clock module is better than 0.1ppm. The redundancy control module is connected to the hardware interrupt pin through the hardware abstraction layer, supporting the switching of clock source or communication link within 100μs.

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