Semiconductor material and preparation method thereof

Abstract

The embodiment of the invention provides a semiconductor material and a preparation method thereof, and the semiconductor material comprises a first silicon carbide layer; the first silicon carbide layer comprises a twin crystal structure and a non-twin crystal structure; the twin crystal structure is embedded into the non-twin crystal structure; the projection of the growth direction of the twin crystal structure in the thickness extension direction of the first silicon carbide layer is greater than zero; the size of the twin structure is greater than the grain size of the non-twin structure; the non-twin crystal structure comprises polycrystalline silicon carbide.

Description

[0001] The present disclosure is a divisional application of a Chinese patent application with the application date of June 19, 2025, the application number of 202510837051.8, and the title of "Semiconductor Material and Preparation Method Thereof". TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor material and a preparation method thereof. BACKGROUND

[0003] Semiconductor materials, such as silicon carbide (SiC), as an important third-generation semiconductor material, have characteristics such as wide band gap, high critical electric field, high thermal conductivity, and high carrier saturation drift speed, and have broad application prospects in the fields of semiconductor lighting, new-generation mobile communication, smart grid, high-speed rail transportation, new energy vehicles, and consumer electronics, and are key new materials supporting the development of information, energy, transportation, and national defense industries.

[0004] In practical applications, the performance of silicon carbide, such as etch resistance, directly affects the service life of semiconductor devices. Therefore, how to improve the etch resistance of silicon carbide has become a problem that needs to be solved at present. SUMMARY

[0005] Embodiments of the present disclosure provide a semiconductor material and a preparation method thereof. The semiconductor material provided by the embodiments of the present disclosure comprises: a first silicon carbide layer; the first silicon carbide layer comprises a twin structure and a non-twin structure; the twin structure is embedded in the non-twin structure; the projection of the growth direction of the twin structure on the thickness extension direction of the first silicon carbide layer is greater than zero; and the size of the twin structure is greater than the grain size of the non-twin structure.

[0006] In some embodiments, the twin structure comprises a plurality of twin crystals; and adjacent twin crystals contact each other.

[0007] In some embodiments, the plurality of twin crystals are symmetrically arranged in a direction perpendicular to the thickness extension direction.

[0008] In some embodiments, the porosity between the plurality of twin crystals is less than the porosity between a plurality of grains in the non-twin structure.

[0009] In some embodiments, the atomic density of the twin structure is greater than the atomic density of the non-twin structure.

[0010] In some embodiments, the first silicon carbide layer comprises a plurality of substructure layers stacked along the thickness extension direction; and the plurality of twin structures in each substructure layer are uniformly arranged in a direction perpendicular to the thickness extension direction.

[0011] In some embodiments, the first silicon carbide layer includes a plurality of substructure layers stacked along the thickness extension direction; wherein the plurality of twin structures in each substructure layer are randomly arranged in a direction perpendicular to the thickness extension direction.

[0012] In some embodiments, in the plurality of said substructure layers, a portion of the twin structure extends from one substructure layer to another along the thickness extension direction.

[0013] In some embodiments, at least some of the twin structures in each of the substructure layers have different sizes.

[0014] In some embodiments, the sizes of the multiple twin structures in each of the multiple substructure layers are randomly distributed.

[0015] In some embodiments, the semiconductor material further includes: a second silicon carbide layer; the second silicon carbide layer is composed of the non-twinned structure; the second silicon carbide layer and the first silicon carbide layer are alternately stacked along the thickness extension direction.

[0016] This disclosure provides a method for preparing a semiconductor material, the method comprising: forming a first silicon carbide layer by a chemical vapor deposition process to form the semiconductor material; wherein the first silicon carbide layer comprises a twinned structure and a non-twinned structure; the twinned structure is embedded in the non-twinned structure; the projection of the growth direction of the twinned structure onto the thickness extension direction of the first silicon carbide layer is greater than zero; and the size of the twinned structure is larger than the grain size of the non-twinned structure.

[0017] This disclosure provides a semiconductor material and its preparation method. The semiconductor material includes a first silicon carbide layer; the first silicon carbide layer includes a twinned structure and a non-twinned structure; the twinned structure is embedded in the non-twinned structure; the projection of the growth direction of the twinned structure onto the thickness extension direction of the first silicon carbide layer is greater than zero; the size of the twinned structure is larger than the grain size of the non-twinned structure. In this disclosure, on one hand, by adding a highly etch-resistant twinned structure to the first silicon carbide layer, the etch resistance of the first silicon carbide layer can be increased. Furthermore, the twinned structure enables the first silicon carbide layer to distribute stress more evenly during deformation, avoiding stress concentration and thus improving the overall deformation capability of the first silicon carbide layer. On the other hand, when the growth direction of the twinned structure is consistent with or intersects (excluding perpendicular) the thickness direction of the first silicon carbide layer, the twinned interface can effectively hinder the movement of dislocations, thereby improving the strength of the first silicon carbide layer and extending the lifespan of the device. On the other hand, when the growth direction of the twin structure is consistent with or intersects (excluding perpendicular) the thickness direction of the first silicon carbide layer, the size of the twin structure in that thickness extension direction can be precisely controlled, thereby optimizing the strength and toughness of the twin structure. In this way, the high strength and high plasticity characteristics of the first silicon carbide layer can be improved simultaneously, thereby improving the stability of the device. Attached Figure Description

[0018] Figure 1 This is an exemplary cross-sectional schematic diagram of a semiconductor material provided in an embodiment of this disclosure;

[0019] Figure 2 This is a schematic cross-sectional view of a semiconductor material provided in an embodiment of the present disclosure;

[0020] Figure 3 for Figure 2 A magnified view of a local area in the diagram;

[0021] Figure 4 This is a schematic diagram of a process flow for forming semiconductor materials, provided in an embodiment of the present disclosure.

[0022] Figure 5 This is a schematic diagram illustrating the principle of forming a silicon carbide semiconductor material according to an embodiment of the present disclosure.

[0023] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The figures illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed Implementation

[0024] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0025] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0026] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0027] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0028] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0029] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0030] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0031] Silicon carbide (SiC) is a wide-bandgap semiconductor material with advantages such as high voltage resistance, high thermal conductivity, and high electron mobility, making it suitable for harsh environments such as high temperature, high pressure, and high frequency. SiC exists in various crystal structures, such as hexagonal (α-SiC), cubic (β-SiC), and rhombic structures. Different crystal structures of SiC have different physical and chemical properties, leading to different applications. Cubic structures (such as 3C-SiC) possess characteristics such as high temperature resistance, high pressure resistance, and high electron mobility, making them suitable for high-frequency, high-power, high-temperature resistant, and corrosion-resistant power electronic devices. Hexagonal structures (such as 4H-SiC and 6H-SiC) have characteristics such as high hardness and high thermal conductivity, and are widely used in the semiconductor field, such as in high-power electronic devices and optoelectronic devices. Rhombic structures (such as 15R-SiC) have good thermal stability and mechanical properties, making them suitable for aerospace, nuclear energy development, and other fields.

[0032] In some embodiments, silicon carbide can be further classified into monocrystalline silicon carbide and polycrystalline silicon carbide. Monocrystalline silicon carbide can be used in mechanical structural materials, semiconductor devices, power electronics, and optoelectronics at high temperatures; polycrystalline silicon carbide can be used in semiconductor devices, thin film coatings, and magnetic materials. In some possible embodiments, polycrystalline silicon carbide can be widely used in components of plasma etching machines, for example, in the fabrication of focusing rings and upper electrodes (which simultaneously provide entry points for various etching gases) in plasma etching machines.

[0033] In practical applications, the etching resistance of polycrystalline silicon carbide directly affects the service life of these components. Higher etching resistance leads to longer component lifespan. More uniform etching resistance in polycrystalline silicon carbide results in better etching stability of the components. Therefore, improving the etching resistance and uniformity of polycrystalline silicon carbide is a pressing issue that needs to be addressed.

[0034] In view of this, to solve one or more of the above problems, this disclosure provides a semiconductor material that can improve the etching resistance and etching uniformity of polycrystalline silicon carbide. Reference is made to... Figure 1 and Figure 2 , Figure 1 This is an exemplary cross-sectional schematic diagram of a semiconductor material provided in this disclosure; Figure 2 This is a schematic cross-sectional view of a semiconductor material provided in this disclosure; the semiconductor material includes a first silicon carbide layer 102; the first silicon carbide layer 102 includes a twin structure 100, and the projection of the growth direction of the twin structure 100 onto the thickness extension direction of the first silicon carbide layer is greater than zero.

[0035] It should be noted that twin structures, due to their high strength, high toughness, and high stability, exhibit superior etching resistance. Therefore, in this embodiment, on the one hand, by adding a highly etching-resistant twin structure to the first silicon carbide layer, the etching resistance of the first silicon carbide layer can be increased. Furthermore, the twin structure enables a more uniform distribution of stress during deformation of the first silicon carbide layer, avoiding stress concentration and thus improving the overall deformation capability of the first silicon carbide layer. On the other hand, when the growth direction of the twin structure is consistent with or intersects (excluding perpendicularity) the thickness direction of the first silicon carbide layer, the twin interface can effectively hinder dislocation movement, thereby increasing the strength of the first silicon carbide layer and extending the device's lifespan. Moreover, when the growth direction of the twin structure is consistent with or intersects (excluding perpendicularity) the thickness direction of the first silicon carbide layer, the dimensions of the twin structure in that thickness extension direction can be precisely controlled, thereby optimizing the strength and toughness of the twin structure. This allows for the simultaneous improvement of the high strength and high plasticity characteristics of the first silicon carbide layer, enhancing the stability of the device.

[0036] In this embodiment, the projection of the growth direction of the twin structure 100 onto the thickness extension direction of the first silicon carbide layer is greater than zero. That is, the growth direction of the twin structure 100 can be the same as / consistent with the thickness extension direction of the first silicon carbide layer 102, or it can intersect with the thickness extension direction of the first silicon carbide layer 102. It should be emphasized that this intersection does not include perpendicularity. In other words, in some embodiments, the growth direction of the twin structure 100 can be parallel to the thickness extension direction of the first silicon carbide layer 102. This allows the twin structure to guide dislocations to extend in a certain direction, preventing their lateral expansion and improving the reliability of the semiconductor material. In other embodiments, the growth direction of the twin structure 100 forms an acute angle with the thickness extension direction of the first silicon carbide layer 102, rather than being completely perpendicular; that is, the twin structure grows at an angle. In this angled twin structure, grain boundaries can effectively intercept penetrating dislocations (such as screw dislocations and edge dislocations), reducing defect density and improving the reliability of the semiconductor material. In addition, the tilted twin structure can release lattice mismatch stress through shear components, that is, release epitaxial stress, reduce cracks and stacking faults in the first silicon carbide layer, and improve the quality of semiconductor materials.

[0037] The semiconductor materials and twin structures provided in the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Here, the twin structure 100 can be, for example, a silicon carbide twin.

[0038] In some embodiments, reference Figure 3 , Figure 3 for Figure 2 The diagram shows a magnified view of a local area. The twin structure 100 can include multiple twin crystals; adjacent twin crystals are in contact with each other. This can suppress grain boundary migration and crack propagation, enhance the strength and hardness of the twin structure, and improve its stability.

[0039] In some embodiments, reference Figure 3 Multiple twin crystals are symmetrically arranged along a direction perpendicular to the thickness extension direction. It should be understood that symmetrical arrangement helps improve the stability of the twin structure. Here, the thickness extension direction of the first silicon carbide layer is, for example, the Z-axis direction, and the direction perpendicular to the thickness extension direction is, for example, the X-axis direction or the Y-axis direction. In some possible embodiments, the multiple twin crystals can form a mirror-symmetric orientation relationship along a common twin interface in their arrangement direction (X-axis direction or Y-axis direction). Thus, on the one hand, by introducing a high density of twin interfaces, the strength and hardness of the twin structure can be significantly improved without sacrificing the material's ductility. On the other hand, the twin interface has a low interface energy, making the multiple twin crystals very stable, thereby allowing the twin structure to maintain good stability even under high temperature or high stress environments.

[0040] In some embodiments, reference Figure 1 and Figure 2 The first silicon carbide layer 102 further includes a non-twinned structure 200; the twinned structure 100 is embedded in the non-twinned structure 200; here, the area of ​​the non-twinned structure 200 is larger than the area of ​​the twinned structure 100. The non-twinned structure 200 is, for example, polycrystalline silicon carbide. Polycrystalline silicon carbide may include multiple crystal orientations, for example... <111> Crystal orientation <100> Crystal orientation, etc., are not limited in the specific crystal orientation of polycrystalline silicon carbide in the embodiments of this disclosure.

[0041] In some possible embodiments, the size of the twinned structure 100 is larger than the grain size of the non-twinned structure 200. This can limit crack propagation when the first silicon carbide layer is subjected to stress, thereby improving the toughness and crack resistance of the first silicon carbide layer.

[0042] In some embodiments, the porosity between multiple twin crystals is less than the porosity between multiple grains in a non-twinned structure. In other words, the arrangement of multiple twin crystals is more compact, resulting in a higher density in the twinned structure. This improves the mechanical properties, durability, corrosion resistance, and thermal stability of the twinned structure.

[0043] In some embodiments, the atomic density of the twin structure 100 is greater than that of the non-twin structure 200. This reduces the defect density of the twin structure and improves the stability and etching resistance of both the twin structure and the first silicon carbide layer.

[0044] In some embodiments, multiple twin structures are uniformly distributed in the first silicon carbide layer. This improves the etching resistance uniformity (i.e., etching resistance uniformity) of the first silicon carbide layer. Further, in embodiments of this disclosure, the etching resistance uniformity of the first silicon carbide layer can be improved by adjusting the distribution position of the twin structures within the first silicon carbide layer.

[0045] In some embodiments, the first silicon carbide layer may include a plurality of substructure layers stacked along the thickness extension direction; wherein, in each substructure layer, a plurality of twin structures are uniformly arranged in a direction perpendicular to the thickness extension direction. This improves the etching resistance and etching uniformity of each substructure layer.

[0046] In some possible embodiments, reference Figure 1The first silicon carbide layer 102 may include a first substructure layer 1021, a second substructure layer 1022, and a third substructure layer 1023 stacked along the Z-axis direction. Each of the first substructure layer 1021, the second substructure layer 1022, and the third substructure layer 1023 includes multiple twin structures. The multiple twin structures in each substructure layer are uniformly arranged along the X-axis / Y-axis direction, which improves the etching resistance and etching uniformity of each substructure layer.

[0047] In some embodiments, the first silicon carbide layer includes a plurality of substructure layers stacked along the thickness extension direction; wherein, in each substructure layer, a plurality of twin structures are randomly arranged in a direction perpendicular to the thickness extension direction. Here, the randomly arranged twin structures can hinder dislocation movement in multiple directions, achieving a more uniform strengthening effect, avoiding the mechanical property shortcomings of a single orientation, and thus improving the overall strength, toughness, and stability of the semiconductor material.

[0048] In some embodiments, among the plurality of substructure layers, a portion of the twin structure extends from one substructure layer to another along the thickness extension direction. This can improve the adhesion between the two substructure layers, thereby enhancing the stability of the first silicon carbide layer in its thickness extension direction.

[0049] In some possible embodiments, reference Figure 1 The twin structure (such as the twin structure labeled 100a) extends from the first substructure layer 1021 into the second substructure layer 1022 along the Z-axis direction. This can improve the bonding performance of the first substructure layer 1021 and the second substructure layer 1022, thereby improving the stability of the first silicon carbide layer in the Z-axis direction.

[0050] In some embodiments, at least some of the twin structures in each substructure layer have different sizes. This can further improve the etching resistance uniformity of the first silicon carbide layer.

[0051] In some possible embodiments, reference Figure 1 The third substructure layer 1023 contains multiple twin structures, including a first twin structure 100b, a second twin structure 100c, and a third twin structure 100d. The sizes of the first twin structure 100b, the second twin structure 100c, and the third twin structure 100d are all different. In this way, stress can be dispersed inside the third substructure layer 1023 to form a gradient distribution or a non-uniform distribution, thereby improving the overall strength and toughness of the third substructure layer 1023.

[0052] In some other possible embodiments, the second twin structure 100c in the third substructure layer 1023 may have the same size as the fourth twin structure 100e in the first substructure layer 1021. This allows for a more uniform distribution of damage across different substructure layers, preventing rapid propagation of localized damage. In other words, having some twin structures of the same size and others of different sizes in the first silicon carbide layer reduces stress concentration and further improves the etching resistance uniformity of the first silicon carbide layer.

[0053] In some embodiments, the sizes of multiple twin structures in each of the multiple substructure layers are randomly distributed. In other words, the sizes of multiple twin structures in the first silicon carbide layer are randomly distributed. This can reduce the generation of internal defects, thereby improving the fatigue resistance of the first silicon carbide layer, reducing the concentration of local stress in the first silicon carbide layer, and enhancing the crack resistance and etching uniformity of the first silicon carbide layer.

[0054] In some possible embodiments, among the multiple twin structures in each substructure layer, the larger twin structures are uniformly distributed, while the smaller twin structures are randomly arranged. This can further improve the etching resistance uniformity of the substructure layer and the semiconductor material, and reduce particle generation.

[0055] In some embodiments, the semiconductor material further includes: a second silicon carbide layer; the second silicon carbide layer is composed of a non-twinned structure; the second silicon carbide layer and the first silicon carbide layer are alternately stacked along the thickness extension direction. This reduces the probability of cracking in the semiconductor material along its thickness extension direction and enhances the etching resistance of the semiconductor material in the horizontal direction (i.e., perpendicular to the thickness extension direction).

[0056] In some possible embodiments, reference Figure 1 The semiconductor material may include two second silicon carbide layers, namely a bottom second silicon carbide layer 101 and a top second silicon carbide layer 103. A first silicon carbide layer 102 is located between the bottom second silicon carbide layer 101 and the top second silicon carbide layer 103. The bottom second silicon carbide layer 101 and the top second silicon carbide layer 103 may be made of the same material, such as both being composed of a non-twinned structure, that is, both the bottom second silicon carbide layer 101 and the top second silicon carbide layer 103 are polycrystalline silicon carbide.

[0057] It should be noted that processes such as grinding and polishing, which may be used in the later stages of semiconductor material processing, can easily create cracks along the growth direction (i.e., the thickness extension direction). In such cases, forming a second silicon carbide layer on at least one side of the first silicon carbide layer can reduce the elastic degradation of the semiconductor material in the horizontal direction (i.e., perpendicular to the thickness extension direction) and improve the etching resistance of the semiconductor material in the growth direction. In other words, forming a second silicon carbide layer on at least one side of the first silicon carbide layer can both improve the etching resistance of the semiconductor material in the growth direction and prevent cracks extending along the growth direction from forming during processing.

[0058] In other embodiments, the semiconductor material may also consist of only one second silicon carbide layer, which is stacked with the first silicon carbide layer along the Z-axis. Specifically, this second silicon carbide layer may be... Figure 1 The bottom second silicon carbide layer 101 can also be Figure 1 The top second silicon carbide layer 103 in the structure reduces the probability of longitudinal cracks caused by excessive size of the twin structure in the Z-axis direction, thus improving the quality and reliability of the semiconductor material.

[0059] Based on this, in this embodiment, on the one hand, by adding a highly etch-resistant twin structure to the first silicon carbide layer, the etch resistance of the first silicon carbide layer can be increased. Furthermore, the twin structure enables a more uniform distribution of stress during deformation of the first silicon carbide layer, avoiding stress concentration and thus improving the overall deformation capability of the first silicon carbide layer. On the other hand, when the growth direction of the twin structure is consistent with the thickness direction of the first silicon carbide layer, the twin interface can effectively hinder dislocation movement, thereby improving the strength of the first silicon carbide layer and extending the device's lifespan. Furthermore, when the growth direction of the twin structure is consistent with the thickness direction of the first silicon carbide layer, the size of the twin structure in that thickness extension direction can be precisely controlled, thereby optimizing the strength and toughness of the twin structure. This allows for the simultaneous improvement of the high strength and high plasticity characteristics of the first silicon carbide layer, enhancing the device's stability. Moreover, by adjusting the distribution position of the twin structure in the first silicon carbide layer, the etch resistance uniformity of the first silicon carbide layer can be improved. This operation can extend the device's lifespan and improve its stability.

[0060] Based on the above-mentioned semiconductor materials, this disclosure provides a method for preparing semiconductor materials, referring to... Figure 4 , Figure 4 This is a schematic diagram of a process flow for forming a semiconductor material, provided as an embodiment of the present disclosure; wherein the method includes the following steps:

[0061] Step S401: A first silicon carbide layer is formed by chemical vapor deposition to form a semiconductor material; wherein the first silicon carbide layer includes a twinned structure and a non-twinned structure; the twinned structure is embedded in the non-twinned structure; the projection of the growth direction of the twinned structure onto the thickness extension direction of the first silicon carbide layer is greater than zero; the size of the twinned structure is larger than the grain size of the non-twinned structure. Here, the twinned structure includes silicon carbide twins.

[0062] It should be noted that the fabrication processes for semiconductor materials may include, for example, solid-phase methods, such as carbothermal reduction and direct silicon-carbon reaction; liquid-phase methods (LPE), such as sol-gel and polymer thermal decomposition; and gas-phase methods, such as chemical vapor deposition (CVD), physical vapor transport (PVT), high-temperature chemical vapor deposition (HTCVD), thermal decomposition, plasma methods, and laser-induced vapor deposition, etc. This disclosure does not limit these methods.

[0063] In this embodiment, the formation of a semiconductor material by chemical vapor deposition (CVD), specifically a silicon carbide structure, is described as an example. The process of depositing the silicon carbide structure may include the following steps: providing a substrate and a CVD reaction apparatus; and placing the substrate on a base within the CVD reaction chamber. The substrate may include, but is not limited to, a graphite substrate.

[0064] A specific reaction pressure and temperature are set in the CVD reaction chamber. While maintaining these specific reaction pressure and temperature, a main reactant gas and a carrier gas are mixed and injected into the chamber for deposition. The main reactant gas can include unary and binary reactant gases. Unary reactant gases include, for example, methyltrichlorosilane (MTS), dimethyldichlorosilane (DDS), and trimethylchlorosilane (TCS). Binary reactant gases can include, for example, silane-based and carbon-based gases. The carrier gas can be, for example, hydrogen and argon.

[0065] For clarity, the following description uses trichloromethylsilane (MTS) as the main reactant gas. It should be understood that the description of the reactant gas in the following text is for illustrative purposes only and is not intended to limit the scope of this disclosure.

[0066] In some possible implementations, the process of forming silicon carbide structures on graphite substrates using a system with MTS as the main reactant gas and hydrogen as the carrier gas involves a series of complex chain reactions between diluted gaseous MTS and excess hydrogen near the substrate surface, and the gradual condensation and growth of gaseous particles on the substrate surface. This process mainly includes intermediate phase reactions based on multi-component, multi-phase free radicals, decomposition, surface adsorption, and catalysis. During deposition, excessively high or low process parameters such as deposition temperature and partial pressure of each gaseous reactant can cause variations in the reaction rates of intermediate reactions, altering the slowest step of the reaction process and leading to changes in the reaction products and deposition structures. Therefore, different semiconductor materials can be obtained by adjusting specific reaction pressures and temperatures.

[0067] In the deposition process of preparing silicon carbide structures from MTS, Equation 1 provides the overall deposition reaction formula. The overall deposition reaction can include three steps. In the first step, MTS is thermally decomposed sequentially into groups containing silicon, carbon, and chlorine, as shown in Equations 2 and 3. In the second step, the SiCl2 / CH2 groups formed in the first thermal decomposition are adsorbed onto the substrate and undergo a second thermal decomposition, as shown in Equations 4 and 5. In the third step, the groups adsorbed on the substrate react with each other, as shown in Equation 6. Of course, silicon and carbon can react with each other to form silicon carbide, or silicon carbide and silicon, or silicon carbide and carbon.

[0068] CH3SiCl3→SiC+3HCl (Equation 1)

[0069] CH3SiCl3→SiCl2+CH2+HCl (Equation 2)

[0070] CH3SiCl3→SiCl3+CH3 (Equation 3)

[0071] SiCl2 + H2 → Si + 2HCl (Equation 4)

[0072] CH2→C+H2 (Equation 5) Si + C → SiC (Equation 6)

[0073] Specifically, such as Figure 5As shown, the steps for forming a silicon carbide structure may include: (1) transport of reactants, i.e., transporting gaseous reactants to a chemical vapor deposition reactor (i.e., a reaction chamber); (2) precursor reaction, i.e., the reaction gas undergoes a first thermal decomposition reaction to form groups containing silicon, carbon and chlorine elements; (3) gas molecule diffusion, i.e., the groups formed in the first thermal decomposition reaction diffuse; (4) precursor adsorption, i.e., the groups formed in the first thermal decomposition reaction adsorb onto the substrate; (5) precursor diffusion into the substrate; (6) surface reaction, i.e., the mutual reaction between the groups adsorbed on the substrate to form a continuous silicon carbide structure; (7) desorption of by-products, i.e., desorption of by-products adsorbed onto the substrate; (8) removal of by-products, i.e., the discharge of by-products from the reaction chamber through the outlet.

[0074] Here, the silicon carbide structure may include a first silicon carbide layer; in other words, the first silicon carbide layer can be formed by the above method.

[0075] In some embodiments, the crystal orientation type of a semiconductor material can be adjusted by controlling different reaction parameters (such as specific reaction pressure and specific reaction temperature).

[0076] In some embodiments, the twin structure may include a plurality of twin crystals; adjacent twin crystals are in contact with each other.

[0077] In some embodiments, a plurality of twin crystals are symmetrically arranged along a direction perpendicular to the thickness extension direction.

[0078] In some possible embodiments, the non-twinned structure includes polycrystalline silicon carbide.

[0079] In some embodiments, the porosity between multiple twinned crystals is less than the porosity between multiple grains in a non-twinned structure.

[0080] In some embodiments, the atomic density of a twinned structure is greater than that of a non-twinned structure.

[0081] In some embodiments, the first silicon carbide layer includes a plurality of substructure layers stacked along the thickness extension direction; wherein, a plurality of twin structures in each substructure layer are uniformly arranged in a direction perpendicular to the thickness extension direction.

[0082] In some embodiments, the first silicon carbide layer includes a plurality of substructure layers stacked along the thickness extension direction; wherein, a plurality of twin structures in each substructure layer are randomly arranged in a direction perpendicular to the thickness extension direction.

[0083] In some embodiments, in a plurality of substructure layers, a portion of the twin structure extends from one substructure layer to another along the thickness extension direction.

[0084] In some embodiments, at least some of the twin structures in each substructure layer have different sizes.

[0085] In some embodiments, the sizes of multiple twin structures in each of the multiple substructure layers are randomly distributed. This enhances the etching resistance uniformity of the first silicon carbide layer and reduces particle generation.

[0086] In some embodiments, the method further includes forming a second silicon carbide layer on at least one side of the first silicon carbide layer along its thickness extension direction. The second silicon carbide layer is composed of a non-twinned structure.

[0087] In some possible embodiments, the second silicon carbide layer may be located only on one side of the first silicon carbide layer along the thickness extension direction, or it may be located on opposite sides of the first silicon carbide layer along the thickness extension direction. This can reduce the probability of cracking in the semiconductor material along the thickness extension direction and enhance the etching resistance of the semiconductor material in the horizontal direction (i.e., perpendicular to the thickness extension direction).

[0088] In some possible embodiments, the method may specifically include: forming a bottom second silicon carbide layer on a substrate, forming a first silicon carbide layer on the bottom second silicon carbide layer, and forming a top second silicon carbide layer on the first silicon carbide layer. Thus, a second silicon carbide layer can be formed on each of opposite sides of the first silicon carbide layer along the growth direction, further improving the quality and reliability of the semiconductor material.

[0089] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0090] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A semiconductor material, characterized in that, include: First silicon carbide layer; The first silicon carbide layer includes a twinned structure and a non-twinned structure; The twinned structure is embedded in the non-twinned structure; The projection of the growth direction of the twin structure onto the thickness extension direction of the first silicon carbide layer is greater than zero; the size of the twin structure is larger than the grain size of the non-twin structure; the non-twin structure includes polycrystalline silicon carbide.

2. The semiconductor material according to claim 1, characterized in that, The twin structure comprises multiple twin crystals; adjacent twin crystals are in contact with each other.

3. The semiconductor material according to claim 2, characterized in that, The plurality of twin crystals are symmetrically arranged along a direction perpendicular to the thickness extension direction.

4. The semiconductor material according to claim 2, characterized in that, The porosity between the multiple twinned crystals is less than the porosity between the multiple grains in the non-twinned structure.

5. The semiconductor material according to claim 1, characterized in that, The atomic density of the twinned structure is greater than that of the non-twinned structure.

6. The semiconductor material according to claim 5, characterized in that, The first silicon carbide layer includes a plurality of substructure layers stacked along the thickness extension direction; wherein, the plurality of twin structures in each substructure layer are uniformly arranged in a direction perpendicular to the thickness extension direction.

7. The semiconductor material according to claim 5, characterized in that, The first silicon carbide layer includes a plurality of substructure layers stacked along the thickness extension direction; wherein, the plurality of twin structures in each substructure layer are randomly arranged in a direction perpendicular to the thickness extension direction.

8. The semiconductor material according to claim 6 or 7, characterized in that, In the plurality of said substructure layers, a portion of said twin structure extends from one substructure layer to another along the thickness extension direction.

9. The semiconductor material according to claim 6 or 7, characterized in that, In each of the multiple twin structures in the substructure layer, at least some of the twin structures have different sizes.

10. The semiconductor material according to claim 6 or 7, characterized in that, In the plurality of said substructure layers, the sizes of the plurality of said twin structures in each said substructure layer are randomly distributed.

11. The semiconductor material according to any one of claims 1 to 3, characterized in that, The semiconductor material further includes: a second silicon carbide layer; the second silicon carbide layer is composed of a non-twinned structure; the second silicon carbide layer and the first silicon carbide layer are alternately stacked along the thickness extension direction.

12. A method for preparing a semiconductor material, characterized in that, The method includes: The semiconductor material is formed by forming a first silicon carbide layer through a chemical vapor deposition process; wherein the first silicon carbide layer includes a twinned structure and a non-twinned structure; the twinned structure is embedded in the non-twinned structure; the projection of the growth direction of the twinned structure onto the thickness extension direction of the first silicon carbide layer is greater than zero; the size of the twinned structure is larger than the grain size of the non-twinned structure; the non-twinned structure includes polycrystalline silicon carbide.

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