A backside illuminated image sensor and method of fabrication

Abstract

The present application relates to the technical field of semiconductor manufacturing, in particular to a back-illuminated image sensor and a preparation method thereof, the preparation method comprising the following steps: providing a device wafer and a carrier wafer, wherein a bonding edge surface of the device wafer is an outward convex curved surface; forming a support part on a position corresponding to the bonding edge of the device wafer; grinding an inner side surface of the support part to form an inward concave curved surface which is adapted to the outward convex curved surface; bonding the device wafer and the carrier wafer, and then sequentially performing heat treatment, wafer back thinning treatment and edge cutting treatment to obtain the back-illuminated image sensor. The present application solves the problem of edge collapse caused by the suspended bonding interface of the edge of the wafer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and more specifically, to a back-illuminated image sensor and its fabrication method. Background Technology

[0002] In the manufacturing process of BSI (backside illumination) image sensors, it is usually necessary to perform wafer bonding between the front side of the device wafer, which has already formed patterns inside, and the carrier wafer. To improve the bonding quality of the wafer edges, the conventional operation is to perform a first edge trimming process on the device wafer edges before wafer bonding, followed by chemical mechanical planarization (CMP).

[0003] However, when performing CMP planarization on device wafers that have already undergone initial edge trimming, the faster grinding rate at the wafer edges during CMP results in a significantly lower film thickness at the wafer edges compared to the center. For example, on a 12-inch wafer, CMP grinding causes a significantly lower film thickness in the 145mm-150mm radius region compared to the center. This difference in film thickness across different wafer regions directly leads to ineffective bonding between the device wafer and the carrier wafer at the edges after wafer bonding, leaving them in a suspended state.

[0004] In the subsequent back-side thinning process, the grinding wheel generates downward pressure and stress on the wafer. When the bonding interface is in a suspended state, edge chipping is very likely to occur. Edge chipping not only exposes the metal layer inside the device wafer, contaminating subsequent processes, but also damages the effective functional area of ​​the wafer, ultimately leading to a decrease in product yield. Summary of the Invention

[0005] The purpose of this invention is to provide a back-illuminated image sensor and its fabrication method to solve the problem of edge chipping caused by the suspended bonding interface at the edge of the existing wafer.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] In a first aspect, the present invention provides a method for fabricating a back-illuminated image sensor, comprising the following steps:

[0008] A device wafer and a carrier wafer are provided, wherein the bonding edge surface of the device wafer is a convex curved surface;

[0009] A support portion is formed at the position corresponding to the bonding edge of the carrier wafer and the device wafer, and the inner surface of the support portion is ground to form an inner concave surface that matches the convex curved surface.

[0010] The device wafer is bonded to the carrier wafer, and then subjected to heat treatment, back-side thinning and edge trimming in sequence to obtain a back-illuminated image sensor.

[0011] According to the above-mentioned technical means, by forming a support portion at the bonding edge of the carrier wafer, and forming an inwardly concave surface on the support portion that matches the outwardly convex surface of the bonding edge surface of the device wafer, the outwardly convex surface and the inwardly concave surface precisely match to form a wedge-like structure when the device wafer and the carrier wafer are bonded. This not only effectively avoids the bonding interface between the device wafer and the carrier wafer being in a suspended state, but also increases the contact area of ​​the bonding surface, thereby forming a stable wafer bonding structure and improving the stability of the wafer bonding structure. This solves the problem of edge chipping caused by the suspended bonding interface of existing wafers, and further avoids the problem of metal layer leakage from the device wafer and contamination of subsequent processes, ensuring the quality of the effective area of ​​the wafer and improving the yield. At the same time, the support portion also plays a supporting role, thereby compensating to a certain extent for the minor deformations that may occur during wafer manufacturing and processing, ensuring the consistency and stability of wafer bonding. Furthermore, the preparation method is compatible with existing wafer manufacturing processes, allowing production to be carried out without changing existing production lines, reducing manufacturing costs and time.

[0012] Preferably, the convex surface is an convex arc-shaped surface, and the concave surface is a concave arc-shaped surface.

[0013] The bonding edge surface of the device wafer is a convex curved surface, which is formed during CMP planarization of the device wafer after the first edge trimming process, due to the relatively fast grinding rate of the wafer edge during CMP grinding. By forming a support portion with a concave arc-shaped curved surface at the bonding edge of the carrier wafer, the design of the concave arc-shaped curved surface can better match the convex arc-shaped curved surface on the device wafer, forming a tighter bonding connection. This not only enhances the mechanical strength of the wafer bonding but also increases the contact area of ​​the bonding surface. This, in turn, helps to reduce the voids at the bonding interface, improves the suspension between the device wafer and the carrier wafer, and thus achieves the purpose of improving edge chipping.

[0014] Preferably, the formation of the support portion specifically includes: forming an oxide layer on the bonding surface of the carrier wafer, grinding away the area of ​​the oxide layer corresponding to the bonding surface of the device wafer, and using the remaining oxide layer as a support portion corresponding to the bonding edge position of the device wafer.

[0015] The oxide layer is used to form a recessed structure during the CMP process, while the edge regions are retained to form a support, thereby reducing the dangling of the bonding interface and improving the stress distribution at the wafer edge.

[0016] Preferably, the formation of the oxide layer specifically includes: sequentially forming a hard mask layer and a patterned photoresist layer on the carrier wafer; using the patterned photoresist layer as a mask, etching the hard mask layer to form a patterned window, the patterned window corresponding to the bonding surface region of the device wafer; removing the patterned photoresist layer and filling the patterned window to form an oxide layer.

[0017] By growing a hard mask layer on the carrier wafer, which serves as both an etch stop layer and a CMP stop layer, the formation and stability of the edge structure are ensured. A patterned photoresist layer is then formed over the hard mask layer to protect the hard mask layer in the edge regions, ensuring that the hard mask layer for subsequent patterned windows is precisely etched away. The patterned windows are then filled, thereby forming an oxide layer.

[0018] The hard mask layer serves as an etch barrier layer, protecting the edge regions of the carrier wafer during subsequent etching steps. Because the material of the hard mask layer and the oxide layer have different etch rates, selective etching is achieved, ensuring that the oxide layer in the central region is removed while the edge regions are preserved to form the support portion. Simultaneously, during CMP polishing, the hard mask layer acts as a stop layer, ensuring that the polishing process stops at the hard mask layer. Furthermore, the hard mask layer also provides support for the subsequently formed support portion, ensuring the stability of the support portion formed at the edge of the carrier wafer.

[0019] Preferably, the thickness of the hard mask layer is between 1000 Å and 10000 Å; and the thickness of the formed oxide layer is between 1000 Å and 15000 Å.

[0020] During CMP polishing, the hard mask layer acts as a stop layer, causing the middle region corresponding to the bonding surface of the oxide layer and the device wafer to be recessed, while the edge region forms a residue to serve as a support.

[0021] Preferably, the width of the patterned photoresist layer is between 1 mm and 1.6 mm.

[0022] The patterned photoresist layer defines the area to be etched subsequently. During the etching process, the photoresist protects the hard mask layer in the edge area from being etched, ensuring that only the hard mask layer in the middle area is removed. Furthermore, by controlling the width of the patterned photoresist layer to be the same as the width of the device wafer, the size of the support portion is controlled to ensure that it matches the convex surface of the device wafer.

[0023] Preferably, CMP polishing is used to remove the region corresponding to the bonding surface of the oxide layer and the device wafer. The CMP polishing slurry has a selectivity ratio of more than 30 for the oxide layer and the hard mask layer. The CMP polishing time is between 30s and 180s, removing the middle region corresponding to the bonding surface of the oxide layer and the device wafer, so that the remaining part of the oxide layer edge forms the support portion.

[0024] By selecting a slurry with a high selectivity ratio between the oxide layer and the hard mask layer, CMP grinding stops when it reaches the hard mask layer. The oxide layer is then ground for a set time. As time goes on, a depression is formed in the middle region of the oxide layer, and a support is formed at the edge.

[0025] Preferably, the temperature of the heat treatment is set to 300~400℃ and the time is set to 5~120min.

[0026] Heat treatment of the wafer bonding structure after bonding the carrier wafer and the device wafer further enhances the bonding strength, which not only improves the mechanical stability of the wafer bonding structure, but also helps to improve the performance and reliability of the device.

[0027] Preferably, the back-side thinning and edge trimming processes specifically include: using CMP or wet etching to thin the back side of the device wafer until a preset thickness is reached; and after the back-side thinning process is completed, edge trimming is performed to remove the hard mask layer remaining at the edges.

[0028] By thinning the back of the wafer, the integration and performance of the wafer bonding structure are further improved, which helps to reduce the size and weight of the device, while improving heat dissipation and electrical performance.

[0029] The present invention also provides a back-illuminated image sensor, which is prepared by the above-described method for preparing a back-illuminated image sensor.

[0030] The present invention has the following unexpected beneficial effects.

[0031] The back-illuminated image sensor fabrication method of this invention forms a support portion at the bonding edge of a carrier wafer, and on the support portion, forms an inwardly concave surface that matches the convex surface of the bonding edge surface of the device wafer. This ensures that during bonding of the device wafer and the carrier wafer, the convex and concave surfaces precisely match to form a wedge-like structure. This design not only effectively prevents the bonding interface between the device wafer and the carrier wafer from being suspended, improving stress distribution and preventing edge chipping defects, but also increases the contact area of ​​the bonding surfaces, thereby achieving precise bonding between the device wafer and the carrier wafer. Simultaneously, it avoids metal layer leakage from the device wafer, preventing contamination of subsequent processes, ensuring the quality of the effective wafer area, and improving yield. Attached Figure Description

[0032] Figure 1 This is a schematic flowchart illustrating one embodiment of the fabrication method of the back-illuminated image sensor described in this invention.

[0033] Figure 2 This is a schematic diagram of the back-illuminated image sensor described in this invention.

[0034] Figure 3 This is a schematic diagram illustrating the structure of an existing back-illuminated image sensor exhibiting edge chipping.

[0035] Figure 4 This is a schematic diagram of the substrate structure.

[0036] Figure 5 This is a schematic diagram of the structure on which the first bonding layer is grown on the substrate.

[0037] Figure 6 This is a schematic flowchart illustrating another embodiment of the fabrication method of the back-illuminated image sensor described in this invention.

[0038] Figure 7 This is a schematic diagram of the structure after the first bonding layer and the hard mask layer are grown sequentially on the substrate.

[0039] Figure 8 This is a schematic diagram of the structure after a patterned photoresist layer is formed on a hard mask layer.

[0040] Figure 9 This is a top view after a patterned photoresist layer has been formed on the hard mask layer.

[0041] Figure 10 This is a schematic diagram of the structure after etching the hard mask layer.

[0042] Figure 11 This is a schematic diagram of the structure after the patterned photoresist layer has been removed.

[0043] Figure 12 A schematic diagram of the structure after an oxide layer is formed to fill the patterned window.

[0044] Figure 13 This is a schematic diagram of the structure after the CMP grinding oxide layer forms a support.

[0045] Figure 14 This is a schematic diagram of the bonding structure between the carrier wafer and the device wafer.

[0046] Figure 15 This is a schematic diagram of the structure after the back of the crystal has been thinned.

[0047] Wherein, 1—device wafer, 11—convex surface, 12—substrate, 13—second bonding layer, 14—functional device, 2—carrier wafer, 21—substrate, 22—first bonding layer, 3—support, 31—concave surface, 4—oxide layer, 5—hard mask layer, 6—patterned photoresist layer. Detailed Implementation

[0048] The embodiments of the present invention will be described below with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention and not for limiting the scope of protection of the present invention.

[0049] This invention aims to disclose a back-illuminated image sensor and its fabrication method to solve the problem of edge chipping caused by the excessively fast grinding rate of the wafer edges during the CMP polishing process in existing back-illuminated image sensor wafer fabrication. This edge chipping not only leads to the leakage of metal layers in the device wafer, contaminating subsequent processes, but also damages the effective area of ​​the wafer, reducing yield.

[0050] In one embodiment, such as Figure 1 As shown, the present invention provides a method for fabricating a back-illuminated image sensor, comprising the following steps:

[0051] A device wafer 1 and a carrier wafer 2 are provided, wherein the bonding edge surface of the device wafer 1 is a convex curved surface 11;

[0052] A support portion 3 is formed at the position corresponding to the bonding edge of the carrier wafer 2 and the device wafer 1. The inner surface of the support portion 3 is ground to form an inner concave curved surface 31 that is adapted to the convex curved surface 11.

[0053] The device wafer 1 is bonded to the carrier wafer 2, and then subjected to heat treatment, back-side thinning and edge trimming in sequence to obtain a back-illuminated image sensor.

[0054] The back-illuminated image sensor fabrication method of the present invention forms a support portion 3 at the bonding edge of the carrier wafer 2, and forms an inwardly concave curved surface 31 on the support portion 3 that matches the outwardly convex curved surface 11 of the bonding edge surface of the device wafer 1. This ensures that when the device wafer 1 and the carrier wafer 2 are bonded, the outwardly convex curved surface 11 and the inwardly concave curved surface 31 precisely match to form a wedge-like structure. This design not only effectively avoids the bonding interface between the device wafer 1 and the carrier wafer 2 being in a suspended state, but also increases the contact area of ​​the bonding surfaces, thereby achieving precise bonding between the device wafer 1 and the carrier wafer 2. This effectively avoids the suspended phenomenon at the bonding interface between the device wafer 1 and the carrier wafer 2, improves stress distribution, and prevents edge chipping defects. Simultaneously, it avoids the problem of metal layer leakage from the device wafer 1 contaminating subsequent processes, ensuring the quality of the effective area of ​​the wafer and improving the yield.

[0055] As a preferred embodiment of the present invention, see Figure 2 As shown, the convex surface 11 is an outwardly convex arc-shaped surface, and the concave surface 31 is an inwardly concave arc-shaped surface.

[0056] In this preferred embodiment, the bonding edge surface of the device wafer 1 is a convex curved surface 11, which is formed during CMP polishing planarization of the device wafer 1, which has already undergone the first edge trimming process, due to the relatively fast polishing rate of the wafer edge during the CMP polishing process. By forming a support portion 3 with a concave arc-shaped curved surface at the bonding edge of the carrier wafer 2, the design of the concave arc-shaped curved surface can better match the convex arc-shaped curved surface on the device wafer 1, forming a tighter bonding connection. This helps to reduce the gap at the bonding interface, improve the suspension between the device wafer 1 and the carrier wafer 2, and thus achieve the purpose of improving edge chipping.

[0057] Taking a 12-inch device wafer 1 as an example, during the first edge trimming and CMP planarization process, the film thickness in the region between 145mm and 150mm in radius (the area of ​​the first edge trimming) is significantly lower than that at the wafer center. Consequently, after wafer bonding, the interface between device wafer 1 and carrier wafer 2 in the region between 145mm and 150mm in radius is not bonded together, i.e., it is in a suspended state. During subsequent CMP back-side thinning, the grinding of the wafer with a grinding wheel creates downward pressure and stress. If the bonding interface is in a suspended state, it will cause edge chipping of device wafer 1, forming a convex curved surface 11. Figure 3 As shown, this can also cause the metal layer in device wafer 1 to leak out, contaminating subsequent processes and damaging the effective area of ​​the wafer, thus reducing the yield.

[0058] For example, the bonding method between the device wafer 1 and the carrier wafer 2 is direct bonding, anodic bonding, or adhesive bonding.

[0059] Direct bonding involves bonding the carrier wafer 2 to the device wafer 1 through chemical and physical processes, typically performed under high temperature and pressure conditions without the use of adhesives. Anodic bonding uses an electrochemical method to bond the carrier wafer 2 to the device wafer 1. Adhesive bonding achieves bonding by applying an adhesive between the carrier wafer 2 and the device wafer 1, suitable for applications requiring rapid bonding and low cost.

[0060] In a preferred embodiment of the present invention, the formation of the support portion 3 specifically includes: forming an oxide layer 4 on the bonding surface of the carrier wafer 2, grinding away the area of ​​the oxide layer 4 corresponding to the bonding surface of the device wafer 1, and using the remaining oxide layer 4 as the support portion 3 corresponding to the bonding edge position of the device wafer 1.

[0061] In this preferred embodiment, the oxide layer 4 is used to form a recessed structure in the subsequent CMP process, while the edge region is retained to form the support portion 3, and the inner surface of the support portion 3 is formed into a concave curved surface 31 so as to adapt to the convex curved surface 11 of the edge of the device wafer 1, reduce the suspension of the bonding interface, and improve the stress distribution at the edge of the wafer.

[0062] For example, the oxide layer 4 is made of silicon dioxide (SiO2), and the formation method is selected from any one of thermal oxidation, physical vapor deposition, and chemical vapor deposition.

[0063] In a preferred embodiment of the present invention, the formation of the oxide layer 4 specifically includes: forming a hard mask layer 5 and a patterned photoresist layer 6 sequentially on the carrier wafer 2; using the patterned photoresist layer 6 as a mask, etching the hard mask layer 5 to form a patterned window, the patterned window corresponding to the bonding surface region of the device wafer 1; removing the patterned photoresist layer 6 and filling the patterned window to form the oxide layer 4.

[0064] In this preferred embodiment, a hard mask layer 5 is formed on the carrier wafer 2, serving as an etch stop layer and a CMP stop layer to ensure the formation and stability of the edge structure. A patterned photoresist layer 6 is formed over the hard mask layer 5 to protect the hard mask layer 5 in the edge regions, ensuring that the hard mask layer 5 for subsequent patterned windows is precisely etched away. The patterned windows are then filled, thereby forming an oxide layer 4.

[0065] The hard mask layer 5 serves as an etch barrier layer, protecting the edge regions of the carrier wafer 2 during subsequent etching steps. Because the material of the hard mask layer 5 has a different etching rate than the oxide layer 4, selective etching is achieved, ensuring that the oxide layer 4 in the central region is removed, while the oxide layer 4 in the edge regions is retained as the support portion 3. Simultaneously, during CMP polishing of the oxide layer 4, the hard mask layer 5 acts as a stop layer, ensuring that the polishing process stops at the hard mask layer 5. Furthermore, the hard mask layer 5 also provides support for the subsequently formed support portion 3, ensuring the stability of the support portion formed at the edge of the carrier wafer 2.

[0066] For example, the hard mask layer 5 is selected from silicon nitride (SiN), titanium nitride (TiN), tantalum nitride (TaN), aluminum nitride (AlN), silicon carbide (SiC), aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), polycrystalline silicon (Poly-Si) or amorphous carbon (aC).

[0067] In a preferred embodiment of the present invention, the thickness of the oxide layer 4 is between 1000 Å and 15000 Å. The thickness of the hard mask layer 5 is between 1000 Å and 10000 Å, and the actual thickness of the hard mask layer 5 is determined according to the wafer edge quality control range.

[0068] During the CMP polishing process, since the hard mask layer 5 serves as a stop layer, the middle region of the oxide layer 4 corresponding to the bonding surface of the device wafer 1 is recessed, and the edge region remains to form the support portion 3. Therefore, the thickness of the oxide layer 4 is controlled to be greater than or equal to the thickness of the hard mask layer 5.

[0069] In a preferred embodiment of the present invention, the width of the patterned photoresist layer 6 is between 1 mm and 1.6 mm. By coating photoresist onto the hard mask layer 5, negative photoresist can be used, and edge exposure of the photolithography machine is employed, thereby retaining only the photoresist around the edge of the hard mask layer 5, while the photoresist in the central area is removed. The width of the retained photoresist is the width of the device wafer 1 at the first dicing edge, approximately 1.0 mm to 1.6 mm.

[0070] The patterned photoresist layer 6 serves several purposes: 1) Utilizing edge exposure technology, a ring of photoresist is retained only at the edge of the hard mask layer 5, while the photoresist in the middle area is removed, thus defining the area to be etched later, i.e., the patterned window. 2) During etching, the patterned photoresist layer 6 protects the hard mask layer 5 in the edge area from being etched, ensuring that only the hard mask layer 5 in the middle area is removed. 3) By controlling the width of the patterned photoresist layer 6, the dimensions of the support portion 3 are precisely controlled, ensuring that the support portion 3 matches the convex curved surface 11 of the device wafer 1.

[0071] In a preferred embodiment of the present invention, CMP polishing is used to remove the region corresponding to the bonding surface of the oxide layer and the device wafer. The CMP polishing slurry has a selectivity ratio of more than 30 for the oxide layer and the hard mask layer. The CMP polishing time is between 30s and 180s, removing the middle region corresponding to the bonding surface of the oxide layer and the device wafer, so that the remaining edge of the oxide layer forms the support portion. The polishing pad selected for CMP polishing is CES333.

[0072] In this preferred embodiment, by selecting a softer polishing pad and a slurry with a high selectivity ratio between the oxide layer 4 and the hard mask layer 5, the CMP polishing stops when it reaches the hard mask layer 5, ensuring that the CMP polishing only acts on the oxide layer 4. Subsequently, polishing of the oxide layer 4 continues. Over time, the central region corresponding to the bonding surface of the oxide layer 4 and the device wafer 1 becomes recessed, and a support portion 3 is formed at the edge of the oxide layer 4.

[0073] Specifically, the planarization of the wafer's central region can be ensured by adjusting the CMP zone pressure, while a slide-like residual (i.e., support portion 3) is formed at the interface of the hard mask layer 5. The bottom width of the support portion 3 can be adjusted by the zone pressure. The zone pressure refers to the pressure applied to the wafer by the CMP equipment's polishing head in different zones. For example, if the polishing head is divided into 5 zones, different pressures can be applied to the wafer individually in 5 different areas. By adjusting the pressure of different zones, the polishing rate of different areas on the wafer surface can be controlled to achieve better uniformity of the wafer surface film after polishing. For example, if the thickness in the middle of the wafer is found to be thicker after polishing, it indicates that the polishing amount in the middle area is insufficient. The pressure of the middle zone of the polishing head can be increased individually to polish the thicker middle area more, ultimately achieving uniformity of the wafer surface film thickness.

[0074] For example, when the material of the oxide layer 4 is silicon dioxide and the material of the hard mask layer 5 is silicon nitride, the selection ratio of the polishing slurry selected by CMP grinding for the oxide layer 4 and the hard mask layer 5 is 42:1, so that the CMP in the support area stops grinding when it reaches the hard mask layer 5.

[0075] In a preferred embodiment of the present invention, the temperature of the heat treatment is set to 300~400℃ and the time is set to 5~120min.

[0076] Heat treatment is performed on the wafer bonding structure after bonding the carrier wafer 2 and the device wafer 1 to further enhance the bonding strength. This not only improves the mechanical stability of the wafer bonding structure, but also helps to improve the performance and reliability of the device.

[0077] In a preferred embodiment of the present invention, the back-side thinning process and edge trimming process specifically include: using CMP or wet etching to thin the back side of the device wafer until a preset thickness is reached; after the back-side thinning process is completed, edge trimming is performed to remove the hard mask layer remaining at the edge.

[0078] Back-side thinning further improves the integration and performance of the wafer bonding structure. Back-side thinning helps reduce the size and weight of devices while improving heat dissipation and electrical performance.

[0079] Furthermore, in order to achieve precise bonding between device wafer 1 and carrier wafer 2, such as Figure 4 and Figure 5 As shown, the carrier wafer 2 is configured to include a substrate 21 and a first bonding layer 22 disposed on the substrate 21, and a support portion 3 is provided on the first bonding layer 22.

[0080] In one embodiment, such as Figure 6 As shown, the present invention also provides a method for fabricating a back-illuminated image sensor, comprising the following steps:

[0081] S1, such as Figure 4 , Figure 5 , Figures 7 to 9 As shown, a first bonding layer 22 and a hard mask layer 5 are sequentially grown on the substrate 21, and a patterned photoresist layer 6 is formed on the hard mask layer 5.

[0082] S2, such as Figure 10 and Figure 11 As shown, using the patterned photoresist layer 6 as a mask, the hard mask layer 5 is etched to form a patterned window, and then the patterned photoresist layer 6 is removed.

[0083] S3, such as Figure 12 As shown, an oxide layer 4 is formed by filling the patterned window;

[0084] S4, such as Figure 13 As shown, the oxide layer 4 is polished using CMP process to remove the area corresponding to the bonding surface of the oxide layer 4 and the device wafer 1, leaving the edge of the oxide layer 4 as a support portion 3;

[0085] S5, such as Figure 14 , Figure 15 As shown, device wafer 1 undergoes a first edge trimming and CMP polishing, followed by bonding with carrier wafer 2. Then, it undergoes heat treatment, backside thinning, and a second edge trimming process to obtain the desired result. Figure 1 The back-illuminated image sensor shown.

[0086] Through a carefully designed process flow, a first bonding layer 22 and a hard mask layer 5 serving as an etch stop layer and a CMP stop layer are sequentially grown on the substrate 21, ensuring the precise formation and stability of the support portion 3. A patterned photoresist layer 6 is then applied to the hard mask layer 5 to create a patterned window, protecting the hard mask layer 5 at the edges and ensuring precise etching removal of the hard mask layer 5 in the subsequent middle areas. Next, the patterned window is filled to form an oxide layer 4, which is then polished using a CMP process to remove the area corresponding to the bonding surface of the oxide layer 4 on the device wafer 1. Due to the different polishing rates of the hard mask layer 5 and the oxide layer 4, the oxide layer 4 in the middle areas is removed more quickly, while the oxide layer 4 near the edges of the hard mask layer 5 is removed more slowly, ultimately leaving the edge portion of the oxide layer 4 to form the support portion 3. Subsequently, it is bonded to the device wafer 1, so that the concave curved surface 31 on the support portion 3 matches the convex curved surface 11 of the device wafer 1. This effectively avoids the suspension phenomenon at the bonding interface between the device wafer 1 and the carrier wafer 2, improves stress distribution, prevents edge chipping defects, and thus improves yield. In summary, through the synergistic effect of the hard mask layer 5, the photoresist layer 6, and the oxide layer 4, the precise matching of the concave curved surface 31 of the support portion 3 and the convex curved surface 11 of the device wafer 1 is achieved, effectively solving the edge chipping problem caused by the suspension of the wafer edge bonding interface.

[0087] The fabrication of device wafer 1 follows conventional methods, including edge trimming, oxide deposition, and CMP polishing.

[0088] See Figure 14 As shown, the device wafer 1 includes a substrate 12, a second bonding layer 13 formed on the substrate 12, and a plurality of functional devices 14 formed within the second bonding layer 13. A convex curved surface 11 is formed at the edge of the second bonding layer 13.

[0089] For example, the material of the first bonding layer 22 is selected from materials such as silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), gallium oxide (Ga2O3), zinc oxide (ZnO), titanium oxide (TiO2), hafnium oxide (HfO2) and zirconium oxide (ZrO2), depending on the actual needs.

[0090] In some embodiments, the growth method of the first bonding layer 22 is selected from any one of thermal oxidation, physical vapor deposition, and chemical vapor deposition.

[0091] Thermal oxidation is a method that uses high-temperature heating to react silicon with oxygen to form a silicon dioxide (SiO2) film. Depending on the oxidant, thermal oxidation can be divided into dry oxidation and wet oxidation. Dry oxidation: At high temperatures (typically around 1000℃), dry, pure oxygen is used to react with silicon to form silicon dioxide. Its advantages are a dense and uniform oxide layer, but the growth rate is slower. Wet oxidation: At high temperatures, water vapor or moist oxygen is used to react with silicon to form silicon dioxide. Wet oxidation has a faster growth rate than dry oxidation, but the quality of the resulting oxide layer is slightly lower.

[0092] Physical vapor deposition (PVD) is a method that uses physical means to transfer materials from a target to a substrate surface to form a thin film. Specifically, it includes: 1) Sputtering, which uses argon plasma to bombard the target, causing target atoms to sputter out and deposit on the substrate surface to form a thin film; and 2) Evaporation, which involves heating the target to evaporate it, and then condensing it on the substrate surface to form a thin film.

[0093] Chemical vapor deposition (CVD) is a method for forming thin films on a substrate surface through chemical reactions. Specifically, it includes: 1) Conventional CVD: At high temperatures, precursor gases undergo a chemical reaction within a reaction chamber, and the resulting solid products are deposited on the substrate surface. 2) Plasma-enhanced CVD: Utilizing plasma to lower the reaction temperature, it is suitable for temperature-sensitive structures. 3) Atomic layer deposition (ALD): Forming a thin film by repeatedly depositing only a few atomic layers at a time through a series of independent steps.

[0094] In some embodiments, the thickness of the first bonding layer 22 is between 200 Å and 1000 Å. The specific thickness of the first bonding layer 22 is defined according to actual needs.

[0095] In one embodiment, the present invention provides a back-illuminated image sensor, which is prepared by the back-illuminated image sensor preparation method described in any of the above embodiments.

[0096] In summary, the fabrication method of the back-illuminated image sensor of the present invention forms a support portion 3 at the bonding edge of the carrier wafer 2, and forms an inwardly concave surface 31 on the support portion 3 that matches the outwardly convex curved surface 11 of the bonding edge surface of the device wafer 1. This ensures that when the device wafer 1 and the carrier wafer 2 are bonded, the outwardly convex curved surface 11 and the inwardly concave surface 31 precisely match to form a wedge-like structure. This design not only effectively avoids the bonding interface between the device wafer 1 and the carrier wafer 2 being in a suspended state, improving stress distribution and preventing edge chipping defects, but also increases the contact area of ​​the bonding surfaces, thereby achieving precise bonding between the device wafer 1 and the carrier wafer 2. Simultaneously, it avoids the problem of metal layer leakage from the device wafer 1 contaminating subsequent processes, ensuring the quality of the effective area of ​​the wafer and improving the yield.

[0097] The above embodiments are merely preferred embodiments of the present invention, and the scope of protection is not limited thereto. Equivalent substitutions or modifications made by those skilled in the art based on the present invention are all within the scope of protection of the present invention.

Claims

1. A method for fabricating a back-illuminated image sensor, characterized in that, Includes the following steps: A device wafer and a carrier wafer are provided, wherein the bonding edge surface of the device wafer is a convex curved surface; A support portion is formed at the position corresponding to the bonding edge of the carrier wafer and the device wafer. The formation of the support portion specifically includes: sequentially forming a hard mask layer and a patterned photoresist layer on the carrier wafer; using the patterned photoresist layer as a mask, etching the hard mask layer to form a patterned window, which corresponds to the bonding surface region of the device wafer; removing the patterned photoresist layer and filling the patterned window to form an oxide layer; grinding away the oxide layer to remove the region corresponding to the bonding surface of the device wafer, using the remaining oxide layer as the support portion corresponding to the bonding edge position of the device wafer. The inner surface of the support is ground to form a concave surface that matches the convex curved surface. The device wafer is bonded to the carrier wafer, and then subjected to heat treatment, back-side thinning and edge trimming in sequence to obtain a back-illuminated image sensor.

2. The method for fabricating a back-illuminated image sensor according to claim 1, characterized in that, The convex surface is an outwardly convex arc-shaped surface, and the concave surface is an inwardly concave arc-shaped surface.

3. The method for fabricating a back-illuminated image sensor according to claim 2, characterized in that: The device wafer undergoes edge trimming and CMP polishing to make the bonding edge surface of the device wafer a convex curved surface.

4. The method for fabricating a back-illuminated image sensor according to claim 1, characterized in that: The thickness of the hard mask layer is between 1000 Å and 10000 Å; The thickness of the oxide layer formed is between 1000 Å and 15000 Å.

5. The method for fabricating a back-illuminated image sensor according to claim 1, characterized in that, CMP polishing is used to remove the region corresponding to the bonding surface of the device wafer from the oxide layer. The CMP polishing slurry has a selectivity ratio of more than 30 for the oxide layer and the hard mask layer. The CMP polishing time is between 30s and 180s, removing the middle region corresponding to the bonding surface of the oxide layer and the device wafer, so that the remaining part of the oxide layer edge forms the support portion.

6. The method for fabricating a back-illuminated image sensor according to claim 1, characterized in that: The heat treatment temperature is set to 300~400℃ and the time is set to 5~120min.

7. The method for fabricating a back-illuminated image sensor according to claim 1, characterized in that: The back-side thinning and edge trimming processes specifically include: using CMP or wet etching to thin the back side of the device wafer until a preset thickness is reached; After the back-side thinning process is completed, edge trimming is performed to remove any remaining hard mask layer at the edges.

8. A back-illuminated image sensor, characterized in that: It is prepared by the method of fabrication of the back-illuminated image sensor as described in any one of claims 1 to 7.

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