A method and system for measuring the dynamic threshold voltage of a field-effect transistor.

Abstract

This invention relates to the field of electronic circuit technology, and more particularly to a method and system for measuring the dynamic threshold voltage of a field-effect transistor (FET). The method includes the following steps: generating a high-speed pulse signal with a preset rise time using a pulse signal generator; applying the high-speed pulse signal to the gate of the FET under test, while simultaneously acquiring the voltage waveform of the FET gate using an oscilloscope, denoted as the gate voltage waveform; and monitoring the current response of the FET drain in real time using a current probe, denoted as the drain current response, with the sampling rate of the drain current response synchronized with the sampling rate of the gate voltage waveform. This invention quantizes the channel setup delay in situ in terms of electrical characteristics, thereby redefining the threshold voltage based on the potential at the instant the channel formation is completed, eliminating the masking of transient characteristics by slow DC scanning.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a method and system for measuring the dynamic threshold voltage of a field-effect transistor. Background Technology

[0002] Oscilloscope bandwidth has increased from hundreds of megahertz to tens of gigahertz, and the operating pulse edge of its trigger channel switching transistors has shortened to nanoseconds or even sub-nanoseconds. However, device characterization methods still rely on the slow DC scan approach established in the 1970s, with test cycles in the millisecond range and gate voltage slew rates less than 1 Vμs⁻¹. This paradigm was acceptable in early low-speed scenarios, but when the gate drive pulse slew rate increased to >1 Vns⁻¹, the transient mobility of channel carriers deviated from the quasi-static model, and the channel formation delay became non-negligible, resulting in a measured threshold voltage drift of tens of millivolts relative to the nominal value. When MOSFETs are used as high-speed switches, their gates must withstand high-speed pulse signals with nanosecond-level rising edges. Under such transient conditions, the channel carrier migration rate differs significantly from that under static test conditions, leading to a delay effect in the channel formation process. The threshold voltage data obtained by traditional DC parameter testers through slow gate voltage scanning cannot reflect the transient shift in the device's conduction characteristics under real high-speed pulse drive, causing systematic errors in trigger level calibration circuits designed based on static parameters. This error manifests directly as trigger jitter in high-speed signal acquisition systems. Summary of the Invention

[0003] Therefore, it is necessary for the present invention to provide a method and system for measuring the dynamic threshold voltage of a field-effect transistor, so as to solve at least one of the above-mentioned technical problems.

[0004] To achieve the above objective, a method for measuring the dynamic threshold voltage of a field-effect transistor includes the following steps:

[0005] Step S1: Generate a high-speed pulse signal with a preset rise time using a pulse signal generator;

[0006] Step S2: Apply a high-speed pulse signal to the gate of the field-effect transistor under test, and simultaneously acquire the voltage waveform of the gate of the field-effect transistor using an oscilloscope, which is recorded as the gate voltage waveform;

[0007] Step S3: Monitor the drain current response of the field-effect transistor in real time using a current probe, and record it as the drain current response. The sampling rate of the drain current response is synchronized with the sampling rate of the gate voltage waveform.

[0008] Step S4: Determine the time delay value between the rising edge of the gate voltage waveform and the starting point of the drain current response. The time delay value is the dynamic response time required for the formation of the field-effect transistor channel.

[0009] Step S5: Based on the time delay value and the rising slope of the gate voltage waveform, calculate the dynamic threshold voltage of the field-effect transistor under dynamic conditions.

[0010] Preferably, the present invention also provides a field-effect transistor (FET) dynamic threshold voltage measurement system for performing the FET dynamic threshold voltage measurement method described above, the FET dynamic threshold voltage measurement system comprising:

[0011] The pulse generation module is used to generate high-speed pulse signals with preset rise times through a pulse signal generator;

[0012] The gate sampling module is used to apply a high-speed pulse signal to the gate of the field-effect transistor under test, and at the same time, the voltage waveform of the gate of the field-effect transistor is acquired by an oscilloscope and recorded as the gate voltage waveform.

[0013] The drain monitoring module is used to monitor the drain current response of the field-effect transistor in real time through a current probe, which is denoted as drain current response. The sampling rate of drain current response is synchronized with the sampling rate of gate voltage waveform.

[0014] The delay extraction module is used to determine the time delay value between the rising edge of the gate voltage waveform and the starting point of the drain current response. The time delay value is the dynamic response time required for the formation of the field-effect transistor channel.

[0015] The threshold calculation module is used to calculate the dynamic threshold voltage of the field-effect transistor under dynamic operating conditions based on the time delay value and the rising slope of the gate voltage waveform.

[0016] The beneficial effects of this invention are as follows:

[0017] On the one hand, by directly applying nanosecond-level high-speed pulses to the gate and simultaneously acquiring the gate voltage and drain current, the device is placed in a transient electric field equivalent to the actual trigger channel, so that the channel setup delay is quantized in situ in terms of electrical characteristics. Thus, the threshold voltage is redefined with the potential at the instant the channel formation is completed, eliminating the masking of transient characteristics by DC slow scan, ensuring that the calibration level is accurately aligned with the actual moment the device is turned on, and the systematic millivolt-level offset is directly eliminated.

[0018] On the other hand, by using an extrapolation algorithm of the gate voltage rise slope and time delay value, the transient mobility of charge carriers is transformed into measurable electrical parameters, realizing the absolute extraction of dynamic threshold voltage. This avoids the high-temperature aging or process iteration required by traditional static testing, and provides a reproducible and traceable dynamic parameter closed loop for high-speed signal paths without changing the device structure or increasing hardware overhead.

[0019] On the other hand, by extracting the threshold voltage based on a single pulse injection, the test cycle is shortened from milliseconds to microseconds, supporting online implementation synchronized with batch mass production. With automatic compensation of temperature coefficient and historical dataset, the repeatability of threshold voltage measurement can be maintained within ±1mV across the entire temperature range and process fluctuation range, significantly reducing oscilloscope trigger jitter and cumulative errors in subsequent comparator links, directly improving the timing stability and waveform reconstruction accuracy of the high-speed sampling system. Attached Figure Description

[0020] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings:

[0021] Figure 1 A flowchart illustrating the steps of a field-effect transistor dynamic threshold voltage measurement method according to an embodiment is shown.

[0022] Figure 2 A schematic diagram of a field-effect transistor structure according to an embodiment is shown.

[0023] Figure 3 A schematic diagram of a field-effect transistor dynamic threshold voltage measurement system architecture is shown. Detailed Implementation

[0024] The technical method of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0025] Furthermore, the accompanying drawings are merely illustrative of the invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor methods and / or microcontroller methods.

[0026] It should be understood that although the terms "first," "second," etc., may be used herein to describe various units, these units should not be limited by these terms. These terms are used merely to distinguish one unit from another. For example, without departing from the scope of the exemplary embodiments, a first unit may be referred to as a second unit, and similarly, a second unit may be referred to as a first unit. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0027] To achieve the above objectives, please refer to Figures 1 to 3 This invention provides a method for measuring the dynamic threshold voltage of a field-effect transistor, comprising the following steps:

[0028] Step S1: Generate a high-speed pulse signal with a preset rise time using a pulse signal generator;

[0029] Step S2: Apply a high-speed pulse signal to the gate of the field-effect transistor under test, and simultaneously acquire the voltage waveform of the gate of the field-effect transistor using an oscilloscope, which is recorded as the gate voltage waveform;

[0030] Step S3: Monitor the drain current response of the field-effect transistor in real time using a current probe, and record it as the drain current response. The sampling rate of the drain current response is synchronized with the sampling rate of the gate voltage waveform.

[0031] Step S4: Determine the time delay value between the rising edge of the gate voltage waveform and the starting point of the drain current response. The time delay value is the dynamic response time required for the formation of the field-effect transistor channel.

[0032] Step S5: Based on the time delay value and the rising slope of the gate voltage waveform, calculate the dynamic threshold voltage of the field-effect transistor under dynamic conditions.

[0033] Preferably, step S1 includes:

[0034] Step S11: Adjust the rise time of the high-speed pulse signal through the output impedance matching circuit of the pulse signal generator; wherein, the output impedance matching circuit includes an RC network composed of an adjustable resistor and an adjustable capacitor connected in series.

[0035] Step S12: Calculate the theoretical cutoff frequency of the RC network based on the input capacitance value of the gate of the field-effect transistor; wherein, the theoretical cutoff frequency is inversely proportional to the rise time of the high-speed pulse signal;

[0036] Step S13: Adjust the impedance values ​​of the adjustable resistor and / or adjustable capacitor to match the actual cutoff frequency of the RC network with the theoretical cutoff frequency.

[0037] Step S14: Monitor the rising edge waveform of the high-speed pulse signal using an oscilloscope to verify whether its rise time meets the preset high-speed slew rate requirement; if not, return to step S12 to readjust the impedance parameters of the RC network; if it meets the requirement, the generation of the high-speed pulse signal is completed.

[0038] In one implementation of this invention, the output of the pulse signal generator is first connected to an RC network consisting of a precision adjustable resistor and a high-precision NPO capacitor connected in series, with the resistance adjustment range being 0. Up to 200 The capacitor adjustment range is 1pF to 50pF, with increments of 1. With a gate input capacitance of 0.5pF; the host computer reads the typical gate input capacitance value given in the datasheet of the device under test, such as 20pF, and sets the target rise time to 2ns according to the empirical formula. From this, the required cutoff frequency is calculated to be approximately 175MHz. Then, the stepper motor is instructed to first coarsely adjust the resistance to 95. Then fine-tune the capacitor to 18pF so that the measured -3dB point of the network falls at 172MHz with an error of less than 2%. After the adjustment is completed, the oscilloscope captures the output pulse at a sampling rate of 20GHz. The cursor measures the rise time as 1.98ns, which is less than 0.1ns off from the preset 2ns. It is deemed qualified and the pulse signal is confirmed as the high-speed slew rate excitation source and enters the subsequent test process. The pulse signal is input to the field-effect transistor. Otherwise, the host computer will automatically return to step S12 to continue fine-tuning the resistance and capacitance values ​​until the requirements are met.

[0039] Please refer to the specific structure of the field-effect transistor in this case. Figure 2 The transistor is rectangular in shape with a circular hole at the top, a square area in the middle, and three equally spaced pins at the bottom. The horizontal and vertical dimension reference lines are marked with dashed lines in the diagram. The pins have pointed ends, and the transistor's external outline and pin layout are shown using a combination of solid and dashed black lines.

[0040] Preferably, the method for determining the time delay value in step S4 includes:

[0041] Calculate the ratio of the voltage difference between adjacent sampling points in the gate voltage waveform to the time interval to obtain a discrete voltage change rate sequence;

[0042] In this embodiment of the invention, after the host computer reads the gate voltage waveform at a raw sampling rate of 50GSa / s, it first calculates the difference between two adjacent points and then divides it by a fixed sampling interval of 20ps to obtain a series of discrete voltage change rate values. These values ​​are arranged in chronological order to form a preliminary change rate sequence.

[0043] In one implementation of this invention, assuming the voltage at the 100th sampling point is 1.000V and the voltage at the 101st point is 1.015V, with a time interval of 20ps, the rate of change in this interval is estimated to be approximately 0.75V / ns. The same operation is repeated for 10k sampling points to generate discrete sequences of equal length and temporarily store them in memory.

[0044] The discrete voltage change rate sequence is smoothed by a preset sliding window to obtain a denoised gate voltage change rate curve;

[0045] In this embodiment of the invention, a rectangular window with a length of 7 points is selected to perform a moving average on the discrete voltage change rate sequence. The window advances by 1 point at each step, and the arithmetic mean of the values ​​within the window is used as the new change rate at the center point of that step.

[0046] In one implementation of this invention, the window length can be dynamically switched to 5 points or 9 points. When the noise floor is low, 5 points are used to ensure resolution. When abnormal jitter is detected, the window length is automatically extended to 9 points to enhance suppression.

[0047] The noise-reduced gate voltage change rate curve is compared with a preset baseline threshold, and the region where the voltage change rate exceeds the baseline threshold is selected as the rising edge feature region of the gate voltage waveform.

[0048] In this embodiment of the invention, the threshold is set to 0.30V / ns by default. The smooth curve is compared with it point by point. The time period when the threshold is continuously higher than 8ns is marked as the effective rising region, and the rest are regarded as noise or flat region and discarded.

[0049] In one implementation of this invention, if the ambient temperature rises and causes the noise floor to rise, the system adaptively raises the threshold to 0.35V / ns and extends the minimum duration to 10ns, and finally outputs one or more intervals with start and end coordinates that meet the conditions.

[0050] Within the rising edge characteristic region, the local maximum point of the voltage change rate curve is identified as the starting moment of the rising edge of the gate voltage waveform.

[0051] In this embodiment of the invention, the coordinates of the maximum rate of change within each feature region are found. This point corresponds to the moment when the gate voltage slope is steepest, which is defined as t1, and its precise timestamp is recorded.

[0052] In one implementation of this invention, if two peaks appear in the same region and the amplitude difference is less than 5%, the earliest peak is taken as the effective starting point to avoid interference from secondary peaks caused by subsequent reflections; this strategy makes the standard deviation of repeated measurements of t1 less than 0.5 ps.

[0053] Determine the start time of the drain current based on the drain current response;

[0054] The time delay value is calculated based on the rise time and the drain current start time.

[0055] In this embodiment of the invention, the rising edge start time t1 is directly subtracted from the drain current start time t2, and the difference is the dynamic delay required for channel formation, typically about 1.8 ns.

[0056] In one implementation of this invention, the same pin under test is measured 100 times consecutively and the average is taken. If any single value differs from the average value by more than 0.2ns, it is marked as abnormal and discarded for retesting, ensuring that the repeatability of the final delay value is better than ±0.1ns.

[0057] Preferably, determining the drain current start time based on the drain current response includes:

[0058] Dynamic threshold detection is performed on the drain current response. The initial current threshold is set as a preset percentage of the maximum value of the drain current. If the deviation between the time corresponding to the initial current threshold and the starting point of the rising edge of the drain current waveform exceeds a preset time window, the initial current threshold is dynamically adjusted based on the rising edge slope of the drain current waveform until the deviation between the time corresponding to the initial current threshold and the starting point of the rising edge is less than the preset time window.

[0059] Record the time corresponding to the dynamically adjusted initial current threshold as the starting time of the drain current.

[0060] In this embodiment of the invention, the drain current waveform is first scanned within a whole pulse cycle, the maximum current value is recorded, 10% of this value is set as the initial threshold, and the sampling point that first crosses the threshold is marked as the candidate start time. If the time difference between this time and the rising edge start point estimated by the slope method exceeds a 20 picosecond window, the threshold adaptive adjustment process is entered, the threshold is reduced in steps of 2% and re-detected until the deviation falls within the window, ensuring that the taken time truly corresponds to the channel conduction start point.

[0061] In one implementation of this invention, assuming the measured maximum drain current is 80 mA, the initial threshold is set to 8 mA. If the time corresponding to 8 mA lags behind the starting point of the slope method by 25 picoseconds, exceeding the allowable window, the threshold is successively lowered to 7.8 mA and 7.6 mA by step size. Finally, at 7.4 mA, the time difference is reduced to 10 picoseconds, which meets the requirement of less than 20 picoseconds. Therefore, this point is locked as the starting time of the drain current and written into the register.

[0062] Preferably, the calculation of the dynamic threshold voltage in step S5 further includes:

[0063] Determine a preset time interval for the gate voltage waveform; wherein, the preset time interval is based on the time delay value and includes the start time of the rising edge of the gate voltage waveform and the completion time of the dynamic response;

[0064] In this embodiment of the invention, the host computer first reads the time delay value obtained in step S4. t, then taking the starting time t1 of the gate voltage rise as the left boundary, and extending to the right. The length t is used to obtain the right boundary t2, thus defining an observation window that covers the entire process of trench formation.

[0065] In one implementation of this invention, if measured If t is 1.8 ns and t1 is marked at 10.0 ns, then the window start point is set to 10.0 ns and the end point is set to 11.8 ns; the window width is fixed. t, if temperature drift causes As t changes, the window will automatically expand or contract accordingly, ensuring that the complete dynamic response segment is always captured.

[0066] Within a preset time interval, discrete sampling points of the gate voltage waveform are linearly interpolated to generate a gate voltage time function, wherein the step size of the linear interpolation is dynamically adjusted according to the rising slope of the gate voltage waveform.

[0067] In this embodiment of the invention, the average slope of the steepest slope segment within the window is first calculated. If the slope is higher than 0.5V / ns, a step size of 1ps is used for interpolation; otherwise, a step size of 2ps is used to balance accuracy and computational load. After interpolation, the voltage-time curve (gate voltage-time function) is obtained.

[0068] In one implementation of this invention, when the voltage within the window rises from 0.4V to 1.0V, the steepest slope is approximately 0.6V / ns. The system then selects a step size of 1ps and generates a total of 1800 equally spaced points. The voltage at each point is obtained by linear fitting of adjacent original sampling points.

[0069] In the gate voltage-time function, the dynamic response completion time corresponding to the dynamic threshold voltage is located based on the time delay value;

[0070] In this embodiment of the invention, the interpolation curve is shifted to the right starting from t1. The length t is used to obtain time t2, which is defined as the dynamic response time when the channel formation is completed. The gate voltage corresponding to this time is the conduction threshold of the device under this transient condition.

[0071] In one implementation of this invention, if t1 is 10.0 ns, If t is 1.8 ns, then t2 is located at 11.8 ns; the interpolation curve has a voltage reading of 0.78 V at this point, and this value is temporarily stored as the initial dynamic threshold voltage.

[0072] The gate voltage value corresponding to the completion time of the dynamic response is calculated by the gate voltage-time function, and this voltage value is used as the initial dynamic threshold voltage.

[0073] In this embodiment of the invention, the interpolation curve voltage corresponding to the positioning time t2 is read. If the curve is monotonically increasing in this interval and has no inflection point, then the voltage is directly taken as the initial threshold to ensure that the definition is consistent with the actual moment when the device is turned on.

[0074] In one implementation of this invention, the interpolated voltage at time t2 is 0.78V, which is written into the initial threshold register. If a slight backlash occurs due to noise, the average value is first taken within the ±5ps neighborhood, and then the average value of 0.781V is output as the initial value to ensure numerical stability.

[0075] Error correction is performed on the initial dynamic threshold voltage to obtain the dynamic threshold voltage.

[0076] Preferably, error correction of the initial dynamic threshold voltage includes:

[0077] The average rising edge voltage value of the gate voltage waveform is calculated based on the voltage data between the rising edge start time and the dynamic response completion time.

[0078] In this embodiment of the invention, within a locked preset time interval, the voltage value of the gate voltage time function after linear interpolation is taken point by point, and the sum is divided by the total number of points to obtain the average voltage within the interval, which serves as a benchmark for measuring the overall rise level.

[0079] In one implementation of this invention, the time interval is determined to be from 10.0ns to 11.8ns, with a total of 1800 interpolation points. The voltage value of each point is accumulated sequentially and divided by 1800 to obtain an average rising edge voltage value of 0.775V.

[0080] Calculate the voltage deviation between the initial dynamic threshold voltage and the average rising edge voltage value;

[0081] In this embodiment of the invention, the initial dynamic threshold voltage is subtracted from the average voltage, and the absolute value is taken as the voltage deviation value, which is used to quantify the degree of deviation of the current threshold from the average level of the interval.

[0082] In one implementation of this invention, the initial dynamic threshold voltage is 0.781V, the average voltage is 0.775V, and the difference between the two is 0.006V, or 6mV.

[0083] If the voltage deviation exceeds the preset error threshold, the step size of the linear interpolation is adjusted and the dynamic threshold voltage is recalculated.

[0084] In this embodiment of the invention, the preset error threshold is ±2mV. When the absolute value of the deviation is greater than this threshold, it is determined that the interpolation accuracy is too low. Therefore, the interpolation step size is halved, high-density linear interpolation is performed again on the time interval, and threshold positioning and deviation calculation are performed again until the deviation falls into the allowable range.

[0085] In one implementation of this invention, if the deviation of 6mV exceeds the 2mV threshold, the interpolation step size is shortened from 1ps to 0.5ps, 3600 interpolation points are regenerated, and the voltage at time t2 is repositioned to obtain a new initial threshold of 0.779V. If the new deviation drops to 4mV but still exceeds the limit, the step size is reduced to 0.25ps again. After one iteration, the deviation drops to 1.8mV, which meets the requirements, and the result is locked.

[0086] If the voltage deviation does not exceed the preset error threshold, the initial dynamic threshold voltage will be used as the dynamic threshold voltage.

[0087] In this embodiment of the invention, when the absolute value of the deviation falls within ±2mV for the first time, the system stops iterating, writes the current initial threshold directly into the dynamic threshold voltage output register, and reports it to the host computer, ensuring that the final parameters meet the accuracy requirements while avoiding over-calculation.

[0088] In one implementation of this invention, after two rounds of step size reduction, the deviation value is 1.8mV, which is less than the 2mV threshold. The corresponding 0.778V is locked as the final dynamic threshold voltage, and the interpolation step size and the number of iterations are recorded.

[0089] Preferably, step S2, when acquiring the gate voltage waveform using an oscilloscope, further includes:

[0090] Provided that the sampling rate of the oscilloscope is not less than 5 times the frequency of the high-speed pulse signal, the time offset is calculated based on the rise time of the high-speed pulse signal, and the trigger delay time of the oscilloscope is dynamically adjusted based on the time offset.

[0091] In this embodiment of the invention, the nominal rise time of the pulse generator output signal is first read. Furthermore, based on experience, the trigger delay is set to half of the rise time to ensure that the center of the sampling window is aligned with the steepest region of the rising edge, thus avoiding waveform truncation due to delay error.

[0092] In one implementation of this invention, the pulse signal frequency is 500MHz, the rise time is nominally 200ps, the oscilloscope sampling rate is set to 2.5GSa / s, which meets the 5-fold condition; the offset is calculated to be 100ps, and the trigger delay is set to -100ps through the programmable interface, so that the leading edge of the sampling window is advanced by 100ps, thereby ensuring that the entire rising edge falls completely into the capture record.

[0093] In this embodiment of the invention, "based on experience" refers to the use of an empirical lookup table and guard-band rules obtained from a large number of pre-experimental statistics. During the experimental phase, repeated tests were conducted on 500 DUTs from different batches, and the proportion of rise edges that were completely captured and had the smallest slope measurement error was recorded when the trigger delay was set to "0× rise time", "0.25× rise time", "0.5× rise time", "0.75× rise time", and "1× rise time", respectively. The statistical results showed that when the delay was set to "0.5× rise time", the complete capture rate reached 99.2%, and the average slope error was <0.3%. Therefore, this 0.5 relationship was written into the firmware as the default empirical coefficient, eliminating the need for users to manually scan one by one, thus achieving plug-and-play trigger delay setting.

[0094] In one implementation of this invention, the host computer first reads the nominal rise time of the pulse generator output as 200ps, then consults the aforementioned experience table to obtain a recommended delay of 100ps; the oscilloscope trigger delay is set to -100ps (the negative sign indicates early triggering) via VISA instructions, so that the center of the sampling window falls exactly at the midpoint of the rising edge; if the ambient temperature or input capacitance changes significantly, the system allows micro-self-tuning of the coefficients within the range of 0.4×~0.6×, but the default value of 0.5 times the experience value is still used to ensure that the complete waveform can be captured at any production line station without secondary manual adjustment.

[0095] The sampling triggering mechanism of the oscilloscope is started according to the trigger delay time, and the gate voltage waveform is oversampled within the preset sampling window to obtain the oversampled gate voltage waveform.

[0096] In this embodiment of the invention, based on the adjusted delay, the high-resolution mode is turned on, the sampling density is increased to 5000 points per grid, and 50000 sampling points are continuously captured within a 10ns window to form an oversampled gate voltage waveform.

[0097] In one implementation of this invention, after the trigger delay is set, the oscilloscope is started in a single-trigger mode, the sampling window width is set to 10ns, the oversampling factor is 25 times, the recorded waveform data is uploaded to the host computer in real time via the PCIe bus, the data is timestamped and saved as an original file.

[0098] The local rate of change of the rising edge slope is calculated based on the oversampled gate voltage waveform. If the deviation between the local rate of change and the preset slope threshold exceeds the set range, the vertical resolution of the oscilloscope is adjusted.

[0099] In this embodiment of the invention, a 100ps sliding window is taken on the oversampled gate voltage waveform, and the ratio of the voltage difference to the time difference within the window is calculated as the local rate of change. This is then compared with a preset slope threshold of 0.5V / ns. If the deviation is greater than 10%, it is considered that the vertical resolution is insufficient, resulting in quantization steps affecting the slope accuracy.

[0100] In one implementation of this invention, the local rate of change is calculated to be 0.44V / ns, which deviates from the threshold of 0.5V / ns by 12%, exceeding the allowable range of 10%. The system automatically increases the vertical resolution of the oscilloscope from 8 bits to 10 bits, recaptures the waveform, and recalculates the rate of change to 0.49V / ns. The deviation is reduced to 2%, which meets the accuracy requirements. The parameter is then locked and the subsequent delay value extraction process begins.

[0101] Preferably, step S3, when monitoring the drain current response using a current probe, further includes:

[0102] Calculate the cutoff frequency of the high-pass filter based on the baseline drift frequency range of the drain current response, and configure the filter parameters.

[0103] In this embodiment of the invention, the original waveform output by the current probe is first subjected to fast spectrum estimation to identify low-frequency components caused by temperature drift or mechanical vibration. If the baseline drift is concentrated below 10kHz, the cutoff frequency of the high-pass filter is set to 15kHz to ensure effective suppression of drift while retaining fast rising edge information. The order is set to 3rd and written to the filter configuration register.

[0104] In one implementation of this invention, if spectrum analysis shows that the drift energy is concentrated within 8kHz, the cutoff frequency is set to 12kHz, the filter sampling rate remains unchanged at 2.5MSa / s, and 32-bit fixed-point quantization is used; after configuration, the filter is processed in real time in a pipeline manner.

[0105] Based on the filter parameters, a digital high-pass filter is used to filter the drain current response in real time to obtain the filtered drain current response.

[0106] In this embodiment of the invention, the filter receives probe data in FIFO mode. Each time a new sample point is entered, a difference equation operation is performed, and the output result immediately replaces the original sample point. This eliminates low-frequency drift and maintains the shape of the rising edge of the waveform, ensuring that the time domain characteristics are not destroyed.

[0107] In one implementation of this invention, the filter adopts an IIR structure and runs on an 80MHz clock within the FPGA with a delay of only 3 sampling cycles. After filtering, the baseline drift of the original current waveform is reduced from ±5mA to ±0.3mA, while the rising edge slope remains unchanged.

[0108] Collect real-time amplitude distribution data of drain current response and calculate the ratio of standard deviation to mean of the current amplitude;

[0109] In this embodiment of the invention, the system uses 1kHz as a unit time slice to perform segmented statistics on the filtered waveform, first calculating the mean of each segment, then the standard deviation, and finally calculating the ratio between the two, which reflects the local noise level.

[0110] In one implementation of this invention, the mean value within the current time slice is 50 mA, the standard deviation is 1.2 mA, and the ratio is 0.024. The ratio is compared with a preset upper limit of 0.03. If the limit is not exceeded, the sensitivity coefficient is maintained at 1.0. If the ratio rises to 0.04, the sensitivity coefficient is automatically lowered to 0.8 to prevent noise-triggered false detections.

[0111] The sensitivity coefficient of threshold detection is adjusted based on the ratio of standard deviation to mean to generate an adaptive threshold detection window;

[0112] In this embodiment of the invention, the sensitivity coefficient is mapped to the window width. The lower the coefficient, the wider the window, ensuring that the true rising edge can still be locked when the noise increases. The window parameters are refreshed in real time with each statistical result to achieve tracking-type adaptive behavior.

[0113] In one implementation of this invention, a sensitivity coefficient of 0.8 corresponds to a window width of ±2mA, and upper and lower boundaries are established with this as the center. The subsequent comparator only searches for the first limit-crossing point within the window, which avoids external interference and retains the ability to identify small current steps.

[0114] The filter drain current response is processed by sliding window differentiation to obtain the current rate of change sequence. The high-frequency jitter in the current rate of change sequence is eliminated by sliding window smoothing to generate a denoised current rate of change curve.

[0115] In this embodiment of the invention, the differential is calculated using a 5-point central difference method, and then smoothed using a 7-point moving average method, taking into account both slope accuracy and noise suppression, and outputting a denoised rate of change curve for feature point recognition.

[0116] In one implementation of this invention, the rate of change curve before smoothing exhibits spikes of ±0.3 mA / ns, which are reduced to ±0.05 mA / ns after 7-point averaging, resulting in an improvement of approximately 16 dB in peak signal-to-noise ratio; the smoothing process introduces only a 1.5 ns group delay.

[0117] Identify local maxima in the denoised current rate of change curve as rising edge characteristic points of the drain current response;

[0118] In this embodiment of the invention, three consecutive points on the smoothed rate of change curve are found that satisfy the condition that the middle point is higher than the left and right neighbors. The coordinates of these points are recorded and regarded as a sign that the current begins to rise rapidly, and are marked as feature points.

[0119] In one implementation of this invention, the curve shows a peak value of 0.92 mA / ns at 11.8 ns, with adjacent points of 0.85 mA / ns and 0.88 mA / ns respectively, satisfying the local maximum condition. Therefore, the coordinates of this point are latched as a feature point, and the corresponding current value of 52 mA is output.

[0120] The current value at the rising edge feature point is compared with the preset current threshold, and the moment when the threshold is first exceeded is recorded. The sensitivity coefficient of the adaptive threshold detection window is then used to correct the moment when the preset current threshold is first exceeded.

[0121] In this embodiment of the invention, the current at the feature point is compared with the current threshold. If it is higher than the threshold and is within the adaptive window, then the time at that point is taken as the starting time of the drain current and multiplied by the sensitivity coefficient for fine-tuning.

[0122] In one implementation of this invention, the preset current threshold is 50mA, the feature point current is 52mA which is higher than the threshold and within the ±2mA window, the sensitivity coefficient is 0.8, and the corrected time is 11.8ns × 0.8 = 9.44ns (example scaling logic, actual is linear correction) and written to the current start time register for calculating the final delay value with the gate voltage start time.

[0123] Preferably, step S4, before determining the time delay value, further includes:

[0124] Extract the sampling point timestamp corresponding to the start time of the rising edge of the gate voltage waveform, and record it as the first timestamp sequence;

[0125] In this embodiment of the invention, after determining that a local maximum value appears in the gate voltage change rate curve, the internal sampling counter of the oscilloscope is immediately read, the absolute sampling number of the point is multiplied by the sampling period to obtain a timestamp based on the trigger zero point, and then stored sequentially in the first timestamp buffer.

[0126] In one implementation of this invention, the sampling rate is 50 GSa / s, the trigger zero point is set at 0 ns, and when the local maximum value falls at the 500th sampling point, the system immediately outputs a timestamp of 10.0 ns and marks it as tGV, and continues to scan subsequent waveforms. If a second rise occurs, the extraction is repeated to form a first timestamp sequence arranged in chronological order.

[0127] Extract the timestamp of the sampling point corresponding to the start time of the drain current response, and record it as the second timestamp sequence;

[0128] In this embodiment of the invention, the current probe channel and the voltage channel share the same sampling clock. After the characteristic point of the drain current change rate is confirmed, the system reads the same sampling counter, obtains the absolute number of the point and multiplies it by the period to obtain a second timestamp that is of the same origin as the voltage channel.

[0129] In one implementation of this invention, the feature point is located at the 536th sampling point, and a timestamp of 10.72 ns is generated, denoted as tDI, and written into the second timestamp buffer. If the current response has multiple steps, each step is repeatedly extracted to finally form a second timestamp sequence of the same length as the first timestamp sequence, providing a one-to-one corresponding data pair for drift correction.

[0130] Based on the sampling rate synchronization relationship between the gate voltage waveform and the drain current response, the clock drift coefficients of the first timestamp sequence and the second timestamp sequence are calculated.

[0131] In this embodiment of the invention, the two sets of timestamps are linearly fitted using the least squares method to obtain the slope k. Ideally, k should be 1. If k deviates from 1, it indicates that there is a fixed sampling interval ratio error between the two channels. k is then saved as a clock drift coefficient.

[0132] In one implementation of this invention, the fitting result k=1.0024 indicates that the current channel time axis is 2.4ps faster than the voltage channel every 1ns. This coefficient is written into the drift coefficient register, and the fitting residual is recorded synchronously. If the standard deviation of the residual is less than 0.5ps, the fitting is deemed effective and the next step of correction is performed; otherwise, it is marked as abnormal and the waveform is reacquired.

[0133] The second timestamp sequence is corrected to the time axis coordinate system of the first timestamp sequence according to the clock drift coefficient, generating a mapping relationship between the gate voltage start time and the drain current start time under a unified time axis coordinate system.

[0134] In this embodiment of the invention, the second timestamp is scaled point by point using a drift coefficient to make the time axis of the current channel and the voltage channel completely aligned. The corrected tDI is paired with the original tGV, and the final mapping table for delay value calculation is output.

[0135] In one implementation of this invention, the original value of tDI is 10.72ns, which is corrected to 10.746ns after being multiplied by a coefficient of 1.0024. This value is on the same reference axis as tGV10.0ns. This pair is written into the unified mapping cache and a correction flag is attached.

[0136] Of particular importance is that after generating the mapping relationship between the gate voltage start time and the drain current start time in a unified time axis coordinate system, the following is also included:

[0137] Construct corresponding data point pairs for the start time of gate voltage and the start time of drain current to form a timing-related dataset;

[0138] In this embodiment of the invention, 10 rising edges are continuously extracted within a single pulse test to obtain 10 tGVs and 10 corrected tDIs. These are then paired sequentially to generate data point pairs with tGV as the independent variable and tDI as the dependent variable.

[0139] In one implementation of this invention, the first pair of points is (10.0ns, 10.746ns), the second pair is (20.1ns, 20.847ns), and so on; each pair of data is accompanied by a sequence number and a valid flag. If a point's tDI is missing, the pair is automatically removed to ensure that the dataset is complete and of equal length, and to avoid missing values ​​in the fitting.

[0140] Based on the time-series correlation dataset, the linear fitting parameters between the gate voltage waveform and the drain current response are calculated, including the slope coefficient and the intercept offset.

[0141] In this embodiment of the invention, a linear regression is performed on the data point pairs in the time-series correlation dataset to obtain the slope k and intercept b, so that tDI=k×tGV+b holds true. k reflects the fixed proportional error between the two channels, and b reflects the absolute offset. The two together constitute the core parameters of the time-series deviation model.

[0142] In one implementation of this invention, the fitting results are k=1.0024, b=0.746ns, and the residual standard deviation is 0.3ps. k and b are written into the fitting parameter register, and the coefficient of determination R²=0.9998 is calculated to confirm that the linear relationship is significant and the fitting is effective. The model generation step can then be initiated.

[0143] A timing compensation model is generated based on the slope coefficient and intercept offset. The timing compensation model is then used to dynamically correct the timing deviation between the gate voltage waveform and the drain current response.

[0144] In this embodiment of the invention, the timing compensation model takes k and b as inputs, and applies the formula to any newly measured tGV. Perform reverse correction to align the current initiation time with the voltage initiation time on the same reference axis, ensuring the delay value... It only reflects the physical processes of the device and does not include channel system errors.

[0145] In one implementation of this invention, when the next test yields tGV = 30.2ns and tDI = 30.950ns, the timing compensation model is substituted into the time series compensation model for calculation. =(30.950–0.746) / 1.0024=30.138ns, then subtracting from tGV gives... t=0.938ns.

[0146] Of particular importance, step S5, which calculates the dynamic threshold voltage based on the time delay value, also includes:

[0147] Obtain the current ambient temperature value and the temperature coefficient of the threshold voltage of the field-effect transistor;

[0148] In this embodiment of the invention, before each dynamic threshold measurement, the real-time temperature is read by an NTC thermistor attached to the back of the device package with a resolution of 0.1℃, and the threshold voltage temperature coefficient of the batch of devices is retrieved from the process document library with the unit mV / ℃.

[0149] Multiply the current ambient temperature value by the temperature coefficient of the threshold voltage to obtain the temperature compensation offset;

[0150] In this embodiment of the invention, the reference temperature of 25°C from the previous calibration is used as a benchmark. The difference between the current temperature and the benchmark is calculated and then multiplied by a temperature coefficient to obtain the voltage offset relative to 25°C.

[0151] In one implementation of this invention, the temperature difference of 17.3℃ multiplied by -1.8mV / ℃ yields an offset of -31.14mV.

[0152] The initial value of the dynamic threshold voltage is added to the temperature compensation offset to generate the first dynamic threshold voltage;

[0153] In this embodiment of the invention, the temperature compensation offset is algebraically added to the initial dynamic threshold voltage to output the first dynamic threshold voltage after eliminating temperature drift, ensuring that the results at different temperatures are comparable.

[0154] In one implementation of this invention, the initial dynamic threshold voltage is 0.778V, the temperature compensation offset is -31.14mV, and the sum of these values ​​results in a first dynamic threshold voltage of 0.74686V; rounded to three decimal places, this is 0.747V.

[0155] Extract test datasets that match the current batch of field-effect transistors from the preset historical test database, and calculate the mean of the test datasets;

[0156] In this embodiment of the invention, based on the wafer batch number and packaging date, at least 500 historical dynamic threshold voltage records of the same batch are retrieved from the database. After removing outliers other than 3σ, the arithmetic mean is calculated to obtain the mean value representing the central trend of the batch.

[0157] In one implementation of this invention, the query returns 520 records, and after anomaly removal, 512 records remain, with a mean of 0.745V and a standard deviation of 6mV.

[0158] The dynamic threshold voltage is compared with the mean of the test dataset to obtain the dynamic threshold deviation.

[0159] In this embodiment of the invention, the deviation is obtained by subtracting the mean of the test dataset from the first dynamic threshold voltage and taking the absolute value, which is used to measure the degree to which the current device deviates from the center of the batch.

[0160] In one implementation of this invention, the first threshold of 0.747V deviates by 2mV from the mean of 0.745V; this value is then compared with a preset process threshold of ±5mV, and the process proceeds to the grade determination process.

[0161] If the dynamic threshold deviation exceeds the preset process threshold, the stringency level of batch screening is determined based on the ratio of the absolute value of the dynamic threshold deviation to the preset process threshold.

[0162] In this embodiment of the invention, the stringency level of batch screening is determined based on the ratio between the absolute value of the dynamic threshold deviation and the preset process threshold; the ratio range is set as follows: ≤1.2 times is level two, >1.2 times and ≤1.5 times is level one, and >1.5 times is level zero. The higher the level, the larger the sampling ratio.

[0163] In one implementation of this invention, if the deviation of 2mV does not exceed the 5mV threshold and the ratio is 0.4 times, then the default level three (normal) is maintained and no tightening is required; if the subsequent deviation reaches 8mV and the ratio is 1.6 times, then the level is reduced to zero, triggering 100% full inspection and locking the batch for traceability.

[0164] The batch screening results are determined based on the stringency level. Process optimization suggestions are generated based on the batch screening results and then fed back to the production end.

[0165] In this embodiment of the invention, a report containing threshold offset trends, possible process root causes, or suggested adjustment parameters is automatically generated according to the level, and sent to the wafer fab through the MES interface to achieve closed-loop improvement.

[0166] In one implementation of this invention, a batch report indicating a level zero threshold shift of 8mV suggests that the channel injection dose is too high, and it is recommended to reduce the injection energy by 2keV. After the process engineer confirms this on the MES terminal, the process conditions for the next batch are adjusted. The system simultaneously records the feedback time and the executor, completing the entire temperature-process linkage optimization cycle.

[0167] Preferably, the present invention also provides a field-effect transistor (FET) dynamic threshold voltage measurement system for performing the FET dynamic threshold voltage measurement method described above, the FET dynamic threshold voltage measurement system comprising:

[0168] The pulse generation module 101 is used to generate a high-speed pulse signal with a preset rise time through a pulse signal generator;

[0169] The gate sampling module 102 is used to apply a high-speed pulse signal to the gate of the field-effect transistor under test, and at the same time acquire the voltage waveform of the gate of the field-effect transistor through an oscilloscope, which is recorded as the gate voltage waveform.

[0170] The drain monitoring module 103 is used to monitor the current response of the drain of the field-effect transistor in real time through a current probe, which is denoted as the drain current response. The sampling rate of the drain current response is synchronized with the sampling rate of the gate voltage waveform.

[0171] The delay extraction module 104 is used to determine a time delay value between the rising edge of the gate voltage waveform and the starting point of the drain current response, wherein the time delay value is the dynamic response time required for the formation of the field-effect transistor channel.

[0172] The threshold calculation module 105 is used to calculate the dynamic threshold voltage of the field-effect transistor under dynamic operating conditions based on the time delay value and the rising slope of the gate voltage waveform.

[0173] Therefore, the embodiments should be considered as exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of the equivalents of the application are intended to be included within the invention.

[0174] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features of the invention herein.

Claims

1. A method for measuring the dynamic threshold voltage of a field-effect transistor, characterized in that, Includes the following steps: Step S1: Generate a high-speed pulse signal with a preset rise time using a pulse signal generator; Step S2: Apply a high-speed pulse signal to the gate of the field-effect transistor under test, and simultaneously acquire the voltage waveform of the gate of the field-effect transistor using an oscilloscope, which is recorded as the gate voltage waveform; Step S3: Monitor the drain current response of the field-effect transistor in real time using a current probe, and record it as the drain current response. The sampling rate of the drain current response is synchronized with the sampling rate of the gate voltage waveform. Step S4: Determine the time delay value between the rising edge of the gate voltage waveform and the starting point of the drain current response. The time delay value is the dynamic response time required for the formation of the field-effect transistor channel. Step S5: Based on the time delay value and the rising slope of the gate voltage waveform, calculate the dynamic threshold voltage of the field-effect transistor under dynamic operating conditions. The calculation of the dynamic threshold voltage in step S5 further includes: Determine a preset time interval for the gate voltage waveform; wherein, the preset time interval is based on the time delay value and includes the start time of the rising edge of the gate voltage waveform and the completion time of the dynamic response; Within a preset time interval, discrete sampling points of the gate voltage waveform are linearly interpolated to generate a gate voltage time function, wherein the step size of the linear interpolation is dynamically adjusted according to the rising slope of the gate voltage waveform. In the gate voltage-time function, the dynamic response completion time corresponding to the dynamic threshold voltage is located based on the time delay value; The gate voltage value corresponding to the completion time of the dynamic response is calculated by the gate voltage-time function, and this voltage value is used as the initial dynamic threshold voltage. Error correction is performed on the initial dynamic threshold voltage to obtain the dynamic threshold voltage. This error correction includes: The average rising edge voltage value of the gate voltage waveform is calculated based on the voltage data between the rising edge start time and the dynamic response completion time. Calculate the voltage deviation between the initial dynamic threshold voltage and the average rising edge voltage value; If the voltage deviation exceeds the preset error threshold, the step size of the linear interpolation is adjusted and the dynamic threshold voltage is recalculated. If the voltage deviation does not exceed the preset error threshold, the initial dynamic threshold voltage will be used as the dynamic threshold voltage.

2. The method for measuring the dynamic threshold voltage of a field-effect transistor according to claim 1, characterized in that, Step S1 includes: Step S11: Adjust the rise time of the high-speed pulse signal through the output impedance matching circuit of the pulse signal generator; wherein, the output impedance matching circuit includes an RC network composed of an adjustable resistor and an adjustable capacitor connected in series. Step S12: Calculate the theoretical cutoff frequency of the RC network based on the input capacitance value of the gate of the field-effect transistor; wherein, the theoretical cutoff frequency is inversely proportional to the rise time of the high-speed pulse signal; Step S13: Adjust the impedance values ​​of the adjustable resistor and / or adjustable capacitor to match the actual cutoff frequency of the RC network with the theoretical cutoff frequency. Step S14: Monitor the rising edge waveform of the high-speed pulse signal using an oscilloscope to verify whether its rise time meets the preset high-speed slew rate requirement; if not, return to step S12 to readjust the impedance parameters of the RC network; if it meets the requirement, the generation of the high-speed pulse signal is completed.

3. The method for measuring the dynamic threshold voltage of a field-effect transistor according to claim 1, characterized in that, The method for determining the time delay value in step S4 includes: Calculate the ratio of the voltage difference between adjacent sampling points in the gate voltage waveform to the time interval to obtain a discrete voltage change rate sequence; The discrete voltage change rate sequence is smoothed by a preset sliding window to obtain a denoised gate voltage change rate curve; The noise-reduced gate voltage change rate curve is compared with a preset baseline threshold, and the region where the voltage change rate exceeds the baseline threshold is selected as the rising edge feature region of the gate voltage waveform. Within the rising edge characteristic region, the local maximum point of the voltage change rate curve is identified as the starting moment of the rising edge of the gate voltage waveform. Determine the start time of the drain current based on the drain current response; The time delay value is calculated based on the rise time and the drain current start time.

4. The method for measuring the dynamic threshold voltage of a field-effect transistor according to claim 3, characterized in that, Determining the drain current initiation time based on the drain current response includes: Dynamic threshold detection is performed on the drain current response. The initial current threshold is set as a preset percentage of the maximum value of the drain current. If the deviation between the time corresponding to the initial current threshold and the starting point of the rising edge of the drain current waveform exceeds a preset time window, the initial current threshold is dynamically adjusted based on the rising edge slope of the drain current waveform until the deviation between the time corresponding to the initial current threshold and the starting point of the rising edge is less than the preset time window. Record the time corresponding to the dynamically adjusted initial current threshold as the starting time of the drain current.

5. The method for measuring the dynamic threshold voltage of a field-effect transistor according to claim 1, characterized in that, Step S2, which involves acquiring the gate voltage waveform using an oscilloscope, also includes: Provided that the sampling rate of the oscilloscope is not less than 5 times the frequency of the high-speed pulse signal, the time offset is calculated based on the rise time of the high-speed pulse signal, and the trigger delay time of the oscilloscope is dynamically adjusted based on the time offset. The sampling triggering mechanism of the oscilloscope is started according to the trigger delay time, and the gate voltage waveform is oversampled within the preset sampling window to obtain the oversampled gate voltage waveform. The local rate of change of the rising edge slope is calculated based on the oversampled gate voltage waveform. If the deviation between the local rate of change and the preset slope threshold exceeds the set range, the vertical resolution of the oscilloscope is adjusted.

6. The method for measuring the dynamic threshold voltage of a field-effect transistor according to claim 1, characterized in that, Step S3, which involves monitoring the drain current response using a current probe, also includes: Calculate the cutoff frequency of the high-pass filter based on the baseline drift frequency range of the drain current response, and configure the filter parameters. Based on the filter parameters, a digital high-pass filter is used to filter the drain current response in real time to obtain the filtered drain current response. Collect real-time amplitude distribution data of drain current response and calculate the ratio of standard deviation to mean of the current amplitude; The sensitivity coefficient of threshold detection is adjusted based on the ratio of standard deviation to mean to generate an adaptive threshold detection window; The filter drain current response is processed by sliding window differentiation to obtain the current rate of change sequence. The high-frequency jitter in the current rate of change sequence is eliminated by sliding window smoothing to generate a denoised current rate of change curve. Identify local maxima in the denoised current rate of change curve as rising edge characteristic points of the drain current response; The current value at the rising edge feature point is compared with the preset current threshold, and the moment when the threshold is first exceeded is recorded. The sensitivity coefficient of the adaptive threshold detection window is then used to correct the moment when the preset current threshold is first exceeded.

7. The method for measuring the dynamic threshold voltage of a field-effect transistor according to claim 1, characterized in that, Before determining the time delay value in step S4, the following steps are also included: Extract the sampling point timestamp corresponding to the start time of the rising edge of the gate voltage waveform, and record it as the first timestamp sequence; Extract the timestamp of the sampling point corresponding to the start time of the drain current response, and record it as the second timestamp sequence; Based on the sampling rate synchronization relationship between the gate voltage waveform and the drain current response, the clock drift coefficients of the first timestamp sequence and the second timestamp sequence are calculated. The second timestamp sequence is corrected to the time axis coordinate system of the first timestamp sequence according to the clock drift coefficient, generating a mapping relationship between the gate voltage start time and the drain current start time under a unified time axis coordinate system.

8. A field-effect transistor dynamic threshold voltage measurement system, characterized in that, For performing the field-effect transistor dynamic threshold voltage measurement method as described in claim 1, the field-effect transistor dynamic threshold voltage measurement system includes: The pulse generation module is used to generate high-speed pulse signals with preset rise times through a pulse signal generator; The gate sampling module is used to apply a high-speed pulse signal to the gate of the field-effect transistor under test, and at the same time, the voltage waveform of the gate of the field-effect transistor is acquired by an oscilloscope and recorded as the gate voltage waveform. The drain monitoring module is used to monitor the drain current response of the field-effect transistor in real time through a current probe, which is denoted as drain current response. The sampling rate of drain current response is synchronized with the sampling rate of gate voltage waveform. The delay extraction module is used to determine the time delay value between the rising edge of the gate voltage waveform and the starting point of the drain current response. The time delay value is the dynamic response time required for the formation of the field-effect transistor channel. The threshold calculation module is used to calculate the dynamic threshold voltage of the field-effect transistor under dynamic operating conditions based on the time delay value and the rising slope of the gate voltage waveform.

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