Low power dynamic voltage control method and circuit thereof

Abstract

The application discloses a low-power-consumption dynamic voltage control method and a circuit thereof, which comprises an analog circuit module analog_top and a digital circuit module dig_top arranged in a top module unit of a chip, the analog circuit module analog_top comprises an OSC clock generation circuit for generating a clock required by the digital circuit module dig_top to work, and the digital circuit module dig_top comprises a low-power-consumption dynamic voltage control circuit. The application realizes the function of high dynamic real-time adjustment of voltage control code with extremely low power consumption through clock pre-opening and pre-closing.

Description

Technical Field

[0001] This invention relates to a dynamic voltage control method and circuit, particularly a low-power dynamic voltage control method and circuit, belonging to the field of integrated circuit control technology. Background Technology

[0002] Dynamic voltage adjustment and control technology is a crucial aspect of low-power integrated circuit design. With the increasing energy efficiency demands of mobile devices, the Internet of Things (IoT), and high-performance computing, there is a need for a technology that can dynamically and in real-time adjust the chip's operating voltage (and frequency) according to its actual workload. This is the reason for the emergence of dynamic voltage regulation technology. Currently, this technology is experiencing deep integration and development of digital and analog solutions, where digital circuits are responsible for calculating control codewords using corresponding algorithms to control the analog circuits to output different voltage values.

[0003] As chip manufacturing processes continue to iterate, the operating voltage range of chips is further expanded, placing higher demands on voltage regulation accuracy, response speed, and stability. Therefore, high real-time performance and lower power consumption are the bottlenecks in the digital circuit design of this solution. Existing digital dynamic voltage regulation control methods are limited by factors such as chip architecture, timing, and area. Furthermore, because it is necessary to reduce the dynamic output time of the control code, the clock must be constantly toggling to detect any possible control code change commands in real time. This can lead to problems such as excessive power consumption or excessive dynamic response delay. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a low-power dynamic voltage control method and circuit, which realizes the function of high dynamic real-time adjustment of voltage control code with extremely low power consumption.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0006] A low-power dynamic voltage control method includes the following steps:

[0007] State 0, Idle State: The digital circuit module waits for a control signal from an external upper-level chip or controller. If a control signal is detected, an enable signal is generated to enable the subsequent interface protocol frame parsing module. After receiving the enable signal, the interface protocol frame parsing module parses the address and data according to the corresponding communication protocol. If the parsed address and data match the voltage dynamic adjustment code enable key, the dynamic voltage adjustment function is started and the module enters State 1.

[0008] State1: The digital circuit module generates the master clock enable pulse clk_start_en;

[0009] State2: After the analog circuit module detects the rising edge of the enable pulse clk_start_en, it turns on the clock crystal circuit and outputs a stable system clock clk to the low-power dynamic voltage control circuit of the digital circuit module within the time period Δt1.

[0010] State 3, Low-power dynamic voltage control circuit according to

[0011] Δv=(Vmax-Vmin)*(code2-code1) / 2^N

[0012] Calculate the dynamic voltage adjustment code output at each rising edge of the system clock clk;

[0013] Where Δv is the voltage adjustment amount, Vmax is the maximum value of the chip's operating voltage, Vmin is the minimum value of the chip's operating voltage, code2 is the latest dynamic control code received by the interface protocol frame parsing module, code1 is the dynamic control code previously received by the interface protocol frame parsing module or the default dynamic control code after power-on, and N is a constant.

[0014] State4: The digital circuit module generates a clock shutdown pulse. After the dynamic voltage regulation circuit completes the last voltage adjustment, it generates an end pulse enable signal clk_end_en to the analog circuit module to shut down the system clock clk.

[0015] State 5: The low-power dynamic voltage control circuit enters low-power mode. This dynamic voltage adjustment is over, and it waits for a new control signal to be sent by an external upper-level chip or controller.

[0016] State 6: After the dynamic voltage adjustment is completed, the chip's operating voltage stabilizes, and other functions gradually begin to work.

[0017] Furthermore, the control signals in State0 support SPI, UART, or I2C interface protocols.

[0018] Furthermore, the pulse width of the enable pulse clk_start_en in State1 is one clock cycle.

[0019] Furthermore, in State3, the constant N is equal to the dynamic control code bit width.

[0020] Furthermore, the pulse width of the end pulse enable signal clk_end_en in State4 is one clock cycle.

[0021] A low-power dynamic voltage adjustment circuit for implementing a low-power dynamic voltage control method includes an analog circuit module analog_top and a digital circuit module dig_top disposed in the top-level module unit of a chip. The analog circuit module analog_top includes an OSC clock generation circuit for generating the clock required for the operation of the digital circuit module dig_top. The digital circuit module dig_top includes a low-power dynamic voltage control circuit.

[0022] Furthermore, the interaction signals between the analog circuit module analog_top and the digital circuit module dig_top include the system clock clk, the enable pulse clk_start_en, the end pulse enable signal clk_end_en, and the dynamic voltage adjustment code v_code.

[0023] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides a low-power dynamic voltage control method and circuit, which realizes the function of high dynamic real-time voltage control code adjustment with extremely low power consumption through clock pre-on and pre-off. The present invention innovatively uses the interface protocol frame parsing module to generate a pre-on enable signal to turn on the master clock, and at the same time generates a clock pre-off enable signal in real time when the dynamic adjustment is about to end. It achieves high dynamic real-time response to voltage adjustment under the premise of low power consumption, solves the defects of traditional solutions, and fills the gap in low-power implementation technology solutions in working scenarios with high real-time requirements. Attached Figure Description

[0024] Figure 1 This is a flowchart of a low-power dynamic voltage control method according to the present invention.

[0025] Figure 2 This is a circuit diagram of the low-power dynamic voltage adjustment circuit of the present invention.

[0026] Figure 3 This is a schematic diagram of the interface protocol frame format according to an embodiment of the present invention.

[0027] Figure 4 This is a signal waveform diagram of an embodiment of the present invention. Detailed Implementation

[0028] To illustrate in detail the technical solutions adopted by the present invention to achieve the intended technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Furthermore, the technical means or technical features in the embodiments of the present invention can be replaced without creative effort. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0029] like Figure 1 As shown, a low-power dynamic voltage control method of the present invention includes the following steps:

[0030] State 0, Idle State: The digital circuit module waits for a control signal from an external upper-level chip or controller. The control signal supports interface protocols such as SPI, UART, or I2C. If a control signal is detected, an enable signal is generated to activate the subsequent interface protocol frame parsing module.

[0031] The specific process of detecting the control signal is as follows: if the cumulative count of the register driven by the signal at chip input port 1 is greater than 1, then the low level time of the signal at input port 2 is detected. If it exceeds 8 times the clock cycle, the specific communication protocol can be determined, and the corresponding enable signal is generated to enable the subsequent interface protocol frame parsing module.

[0032] like Figure 3 As shown, the frame format agreed upon by the interface protocol frame parsing module is as follows:

[0033] During the OFF phase, no enable signal from the upper level is detected, the system is in a closed state, and no communication occurs.

[0034] During the START_UP phase, upon detecting the enable signal from the upstream controller, the interface protocol frame parsing module begins parsing the communication protocol signals sent by the upstream main controller.

[0035] WR phase: Indicates whether this transfer is a write (W) or read (R) operation by the master controller;

[0036] ADDR and DATA represent the register address that the main controller needs to access and the data to be written, respectively.

[0037] The check bit and STOP are the checksum and stop bit calculated by the algorithm, respectively, indicating the end of this transmission.

[0038] After receiving the enable signal, the interface protocol frame parsing module parses the address ADDR and data DATA according to the corresponding communication protocol. If the parsed address ADDR and data DATA match the voltage dynamic adjustment code enable key, the dynamic voltage adjustment function is started and the system enters State 1.

[0039] For example, if the main controller detects that a write operation W is initiated at this time, the address ADDR matches the set voltage dynamic adjustment code address, and the data DATA(n) received in the nth time (i.e. this time) is not equal to the data DATA(n-1) received in the (n-1)th time, then the system enters the State1 state.

[0040] State1: The digital circuit module generates a master clock enable pulse clk_start_en, the pulse width of which is one clock cycle.

[0041] State2, such as Figure 4 As shown, after the analog circuit module detects the rising edge of the enable pulse clk_start_en, it turns on the clock crystal circuit and outputs a stable system clock clk to the low-power dynamic voltage control circuit of the digital circuit module within the time period Δt1 (the specific time depends on the specific chip process and analog circuit design).

[0042] State 3, Low-power dynamic voltage control circuit according to

[0043] Δv=(Vmax-Vmin)*(code2-code1) / 2^N

[0044] Calculate the dynamic voltage adjustment code output at each rising edge of the system clock clk.

[0045] Where Δv is the voltage adjustment amount (in mV), Vmax is the maximum value of the chip's operating voltage (in mV), Vmin is the minimum value of the chip's operating voltage (in mV), code2 is the latest dynamic control code received by the interface protocol frame parsing module, code1 is the dynamic control code previously received by the interface protocol frame parsing module or the default dynamic control code after power-on, and N is a constant. The constant N is equal to the dynamic control code bit width; since the dynamic control code bit width is 10 bits, N is set to 10.

[0046] For example, code2 also hits the data DATA(n) received after the voltage dynamic adjustment code is enabled, and code1 is the data DATA(n-1) received in the (n-1)th time. At the beginning of each voltage dynamic adjustment, the voltage adjustment digital value for each cycle is calculated (i.e., (code2-code1) / 2). N Then, on each rising edge of the system clock, a dynamic voltage adjustment code v_code is output. After the last dynamic voltage adjustment code is output, the system enters state4.

[0047] State 4: The digital circuit module generates a clock shutdown pulse. After the dynamic voltage regulation circuit completes its last voltage adjustment, it generates an end pulse enable signal clk_end_en to the analog circuit module, shutting down the system clock clk. The pulse width of the end pulse enable signal clk_end_en is one clock cycle.

[0048] State 5: After the analog circuit module detects the end pulse enable signal clk_end_en, it shuts off the main clock clk output to the digital circuit module within a time interval Δt2. The low-power dynamic voltage control circuit enters low-power mode, related signals stop toggling, this dynamic voltage adjustment ends, and it waits for a new control signal from an external upper-level chip or controller.

[0049] State 6: After the dynamic voltage adjustment is completed, the chip's operating voltage stabilizes, and other functions gradually begin to work.

[0050] like Figure 2 As shown, a low-power dynamic voltage adjustment circuit for performing a low-power dynamic voltage control method includes an analog circuit module analog_top and a digital circuit module dig_top disposed in the top-level module unit of the chip. The analog circuit module analog_top includes an OSC clock generation circuit for generating the clock required for the operation of the digital circuit module dig_top. The digital circuit module dig_top includes a low-power dynamic voltage control circuit.

[0051] The interaction signals between the analog circuit module analog_top and the digital circuit module dig_top include the system clock clk, the enable pulse clk_start_en, the end pulse enable signal clk_end_en, and the dynamic voltage adjustment code v_code.

[0052] Compared to traditional voltage control circuits and solutions that require a continuously active master clock to achieve high dynamic response, which causes signals in the circuit to continue to flip even when not in use, resulting in a significant increase in the chip's average power consumption; in addition, some solutions may decide whether to turn on the clock based on the control code after receiving a new control command, based on power consumption requirements. The disadvantage of this solution is that the adjustment response time is too long, it cannot achieve high dynamic control code output, and it is not suitable for scenarios with high real-time requirements.

[0053] This invention provides a low-power dynamic voltage control method and circuit, which achieves high dynamic real-time voltage control code adjustment with extremely low power consumption through clock pre-on and pre-off. This invention innovatively utilizes an interface protocol frame parsing module to generate a pre-on enable signal to turn on the master clock, and at the same time generates a clock pre-off enable signal in real time when the dynamic adjustment is about to end. It achieves high dynamic real-time response to voltage adjustment under the premise of low power consumption, solves the defects of traditional solutions, and fills the gap in low-power implementation technology for working scenarios with high real-time requirements.

[0054] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A low-power dynamic voltage control method, characterized in that... Includes the following steps: State 0, Idle State: The digital circuit module waits for a control signal from an external upper-level chip or controller. If a control signal is detected, an enable signal is generated to enable the subsequent interface protocol frame parsing module. After receiving the enable signal, the interface protocol frame parsing module parses the address and data according to the corresponding communication protocol. If the parsed address and data match the voltage dynamic adjustment code enable key, the dynamic voltage adjustment function is started and the module enters State 1. State1: The digital circuit module generates the master clock enable pulse clk_start_en; State2: After the analog circuit module detects the rising edge of the enable pulse clk_start_en, it turns on the clock crystal circuit and outputs a stable system clock clk to the low-power dynamic voltage control circuit of the digital circuit module within the time period Δt1. State 3, Low-power dynamic voltage control circuit according to Δv=(Vmax-Vmin)*(code2-code1) / 2 N Calculate the dynamic voltage adjustment code output at each rising edge of the system clock clk; Where Δv is the voltage adjustment amount, Vmax is the maximum value of the chip's operating voltage, Vmin is the minimum value of the chip's operating voltage, code2 is the latest dynamic control code received by the interface protocol frame parsing module, code1 is the dynamic control code previously received by the interface protocol frame parsing module or the default dynamic control code after power-on, and N is a constant. State4: The digital circuit module generates a clock shutdown pulse. After the dynamic voltage regulation circuit completes the last voltage adjustment, it generates an end pulse enable signal clk_end_en to the analog circuit module to shut down the system clock clk. State 5: The low-power dynamic voltage control circuit enters low-power mode. This dynamic voltage adjustment is over, and it waits for a new control signal to be sent by an external upper-level chip or controller. State 6: After the dynamic voltage adjustment is completed, the chip's operating voltage stabilizes, and other functions gradually begin to work.

2. The low-power dynamic voltage control method according to claim 1, characterized in that: The control signals in State0 support SPI, UART, or I2C interface protocols.

3. The low-power dynamic voltage control method according to claim 1, characterized in that: The pulse width of the enable pulse clk_start_en in State1 is one clock cycle.

4. The low-power dynamic voltage control method according to claim 1, characterized in that: In State3, the constant N is equal to the dynamic control code bit width.

5. The low-power dynamic voltage control method according to claim 1, characterized in that: The pulse width of the end pulse enable signal clk_end_en in State4 is one clock cycle.

6. A low-power dynamic voltage adjustment circuit for performing the low-power dynamic voltage control method according to any one of claims 1-5, characterized in that: It includes an analog circuit module analog_top and a digital circuit module dig_top located in the top-level module unit of the chip. The analog circuit module analog_top contains an OSC clock generation circuit to generate the clock required for the operation of the digital circuit module dig_top. The digital circuit module dig_top contains a low-power dynamic voltage control circuit.

7. The low-power dynamic voltage adjustment circuit according to claim 6, characterized in that: The interaction signals between the analog circuit module analog_top and the digital circuit module dig_top include the system clock clk, the enable pulse clk_start_en, the end pulse enable signal clk_end_en, and the dynamic voltage adjustment code v_code.

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