Chaotic system based on double-charge-control memristor model

Abstract

The invention belongs to the field of chaotic circuits, and particularly discloses a chaotic system based on a double-charge-control memristor model, which comprises a driving force module, an integral summation reverse module and a multiplication module, the integral summation reverse module comprises a first summation circuit, a first integral circuit, a second summation circuit, a second integral circuit, a first reverse circuit and a third integral circuit, the multiplication module comprises multipliers A1-A4 and a third integral circuit, and the multiplier A3 and the multiplier A4 form a charge-controlled memristor model and are used for enhancing the nonlinearity and noise immunity of the chaotic system. According to the invention, the charge-controlled memristor model is introduced into a Van der Pol-Duffing chaotic system structure, a chaotic system circuit with complex dynamic characteristics is successfully constructed, and the circuit can be suitable for a weak signal detection scene with a low signal-to-noise ratio and high precision.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of chaotic circuits, and more particularly, relates to a chaotic system based on a double charge-controlled memristor model. BACKGROUND

[0002] The memristor is a new type of passive two-terminal element, and is known as the fourth basic electronic element in addition to resistance, capacitance and inductance. As a new type of nonlinear element, the memristor is easy to realize chaotic oscillation, which has attracted great interest in the signal processing field.

[0003] Research has found that the system can exhibit stronger noise immunity and sensitivity by adding a memristor to the chaotic system, greatly improving the detection efficiency. Some research works have used memristors to replace traditional nonlinear circuit elements or introduced memristor equations to construct chaotic circuit models based on memristors, but most of the designs only realize simple chaotic behavior, with low chaotic dimension, which is difficult to be used in low signal-to-noise ratio and high precision weak signal detection scenarios.

[0004] Therefore, it is necessary to provide a chaotic system that can be applied to low signal-to-noise ratio and high precision weak signal detection scenarios. SUMMARY

[0005] In view of the defects of the prior art, the purpose of the application is to provide a chaotic system based on a double charge-controlled memristor model, which can be applied to low signal-to-noise ratio and high precision weak signal detection scenarios.

[0006] To achieve the above-mentioned purpose, in a first aspect, the application provides a chaotic system based on a double charge-controlled memristor model, which is suitable for weak signal detection scenarios, and includes: A driving force module for generating a sinusoidal signal; An integral summation reverse module including a first summation circuit, a first integral circuit, a second summation circuit, a second integral circuit, a first reverse circuit and a third integral circuit each using an operational amplifier, for sequentially performing first summation, first integral, second summation, second integral, reverse and third integral processing on the sinusoidal signal to obtain corresponding output signals; A multiplication module including multipliers A1-A4, for sequentially multiplying the output signal after third integral processing by multiplier A3, multiplying the output signal after reverse processing by multiplier A4, multiplying the output signal after second integral processing by multiplier A1, and multiplying the output signal after first integral processing by multiplier A2; the output signals after first integral, second summation, second integral, reverse and third integral processing are respectively added reversely to the sinusoidal signal by the first summation circuit; the output signal after second integral processing and the output signal obtained by multiplying the output signal after reverse processing by multiplier A4 are added reversely to the output signal after first integral processing by the second summation circuit; The third integration circuit, the multiplier A3 and the multiplier A4 constitute a charge-controlled memristor model, and are used for enhancing the nonlinearity and noise resistance of the chaotic system.

[0007] The chaotic system based on the double charge-controlled memristor model provided in the application introduces the memristor model to significantly enhance the nonlinearity and noise resistance of the system, so that the system has the potential to realize high-precision weak signal detection in a low signal-to-noise ratio environment. The introduced memristor model acts on different feedback paths of the system. On the one hand, the charge-dependent nonlinear impedance is introduced, so that the system is more sensitive to weak disturbances. On the other hand, the time correlation is introduced through the memory effect, so that the weak signal can produce an accumulation amplification effect in the system, thereby effectively distinguishing the signal from the random noise, so that the system can realize high-precision signal recognition in strong noise interference.

[0008] As a further preferred, the mathematical model of the chaotic system is:

[0009] In the formula, x 1 represents the voltage output by the output end of the operational amplifier in the third integration circuit; x 2 represents the voltage output by the output end of the operational amplifier in the second integration circuit; x 3 represents the voltage output by the output end of the operational amplifier in the first integration circuit; x 4 represents the frequency of the sinusoidal signal; represents the nonlinear damping coefficient; represents the amplitude of the sinusoidal signal; represents the memristor value, a and b are the coefficients of the first-order term and the third-order term, respectively.

[0010] As a further preferred, the method for introducing the charge-controlled memristor model into the chaotic system is: The damping term in the Van der Pol oscillator is used to replace the damping term in the Duffing system, the two systems are coupled, and the mathematical model of the Van der Pol-Duffing system is constructed; The expression of the charge-controlled memristor is used to replace the nonlinear cubic term in the mathematical model of the Van der Pol-Duffing system, and is rewritten as a differential equation group; A charge-controlled memristor is introduced, and the variable in the system is used as the input current signal of the memristor, and then the output voltage of the memristor is added to the system equation.

[0011] As a further preferred, the output of the multiplier A3 is connected to an input of the multiplier A4; the other input of the multiplier A4 is connected to the output of the operational amplifier in the first inverting circuit; one input of the multiplier A1 is connected to the output of the operational amplifier in the first inverting circuit, the other input of the multiplier A1 is connected to the output of the operational amplifier in the second integrating circuit, the output of the multiplier A1 is connected to one input of the multiplier A2; the other input of the multiplier A2 is connected to the output of the operational amplifier in the first integrating circuit.

[0012] As a further preferred, the first summing circuit comprises the resistor R1, the resistor R2, the resistor R3, the resistor R4, the resistor R5, the resistor R6 and the operational amplifier U1; Wherein, one end of the resistor R1 is connected to the inverting input of the operational amplifier U1, the other end of the resistor R1 is connected to the output of the operational amplifier U2; one end of the resistor R2 is connected to the inverting input of the operational amplifier U1, the other end of the resistor R2 is connected to the multiplier A2; one end of the resistor R3 is connected to the inverting input of the operational amplifier U1, the other end of the resistor R3 is connected to the output of the operational amplifier U4; one end of the resistor R4 is connected to the inverting input of the operational amplifier U1, the other end of the resistor R4 is connected to the multiplier A4; one end of the resistor R5 is connected to the inverting input of the operational amplifier U1, the other end of the resistor R5 is used to receive the sine signal; one end of the resistor R6 is connected to the inverting input of the operational amplifier U1, the other end of the resistor R6 is connected to the output of the operational amplifier U1; the non-inverting input of the operational amplifier U1 is grounded.

[0013] As a further preferred, the first integrating circuit comprises the resistor R7, the resistor R8, the resistor R9, the capacitor C1 and the operational amplifier U2; Wherein, the inverting input of the operational amplifier U2 is connected to the output of the operational amplifier in the first summing circuit through the resistor R7, the resistor R8 and the capacitor C1 form a first parallel network, one end of the first parallel network is connected to the inverting input of the operational amplifier U2, the other end of the first parallel network is connected to the output of the operational amplifier U2; the non-inverting input of the operational amplifier U2 is grounded through the resistor R9.

[0014] As a further preferred, the second summing circuit comprises the resistor R10, the resistor R11, the resistor R12, the resistor R13 and the operational amplifier U3; The non-inverting input terminal of the operational amplifier U3 is connected with the output terminal of the operational amplifier in the first integral circuit through the resistance R12; one end of the resistance R10 is connected with the non-inverting input terminal of the operational amplifier U3, and the other end of the resistance R10 is connected with the output terminal of the operational amplifier U4; one end of the resistance R11 is connected with the non-inverting input terminal of the operational amplifier U3, and the other end of the resistance R11 is connected with the output terminal of the multiplier A4; one end of the resistance R13 is connected with the non-inverting input terminal of the operational amplifier U3, and the other end of the resistance R13 is connected with the output terminal of the operational amplifier U3; and the non-inverting input terminal of the operational amplifier U3 is grounded.

[0015] As a further optimization, the second integral circuit comprises a resistance R14, a resistance R15, a resistance R16, a capacitor C2 and an operational amplifier U4. The non-inverting input terminal of the operational amplifier U4 is connected with the output terminal of the operational amplifier in the second summing circuit through the resistance R14; the resistance R15 and the capacitor C2 form a second parallel network, one end of the second parallel network is connected with the non-inverting input terminal of the operational amplifier U4, and the other end of the second parallel network is connected with the output terminal of the operational amplifier U4; and the non-inverting input terminal of the operational amplifier U4 is grounded through the resistance R16.

[0016] As a further optimization, the first reverse circuit comprises a resistance R17, a resistance R18, an operational amplifier U5, and the third integral circuit comprises a resistance R19, a resistance R20, a resistance R21, a capacitor C3 and an operational amplifier U6. The non-inverting input terminal of the operational amplifier U5 is connected with the output terminal of the operational amplifier in the second integral circuit through the resistance R17; one end of the resistance R18 is connected with the non-inverting input terminal of the operational amplifier U5, and the other end of the resistance R18 is connected with the output terminal of the operational amplifier U5; and the non-inverting input terminal of the operational amplifier U5 is grounded; The output terminal of the operational amplifier U5 is connected with the non-inverting input terminal of the operational amplifier U6 through the resistance R19; the resistance R20 and the capacitor C3 form a third parallel network, one end of the third parallel network is connected with the non-inverting input terminal of the operational amplifier U6, and the other end of the third parallel network is connected with the output terminal of the operational amplifier U6; the non-inverting input terminal of the operational amplifier U6 is grounded through the resistance R21, and the output terminal of the operational amplifier U6 is connected with the two input terminals of the multiplier A3.

[0017] In a second aspect, the application provides a method for determining the signal-to-noise ratio threshold of a chaotic system based on a double charge control memristor model, which comprises the following steps: (1) Adjusting the amplitude of the system driving force, i.e. the amplitude of the sine signal, so that the system is in a critical state from a chaotic state to a large-scale periodic state; (2) input a sine signal containing Gaussian white noise with a signal-to-noise ratio of SNR1 into the system, if the system enters a large-scale periodic motion state from a critical state, it indicates that the system can detect a weak sine signal under the current signal-to-noise ratio; (3) reduce the signal-to-noise ratio to SNR2, repeat the judgment process in step (2) until the system presents a chaotic running track and cannot enter a periodic state, so that it cannot be determined whether a weak signal is detected, and the signal-to-noise ratio threshold of the chaotic system for detecting a signal is obtained through the above steps.

[0018] It can be understood that the beneficial effects of the above second aspect can be referred to the related description in the above first aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a circuit schematic diagram of a chaotic system based on a double charge-controlled memristor model provided by the present application; Figure 2 is a chaotic state (a) and a periodic state (b) of a chaotic system based on a double charge-controlled memristor model provided by the present application ; Figure 3 is a chaotic state (a) and a periodic state (b) of a chaotic system based on a double charge-controlled memristor model provided by the present application ; Figure 4 is a chaotic state (a) and a periodic state (b) of a chaotic system based on a double charge-controlled memristor model provided by the present application ; Figure 5 is a signal-to-noise ratio threshold analysis flowchart of a chaotic system based on a double charge-controlled memristor model provided by the present application; Figure 6 is a process diagram of a chaotic system based on a double charge-controlled memristor model for detecting a weak signal provided by the present application; wherein (a) is a phase trajectory diagram when the chaotic system is in a critical state, (b) is a to-be-detected signal waveform diagram, (c) is a phase trajectory diagram of the chaotic system after adding a to-be-detected signal with a signal-to-noise ratio of -166dB, and (d) is a phase trajectory diagram of the chaotic system after adding a to-be-detected signal with a signal-to-noise ratio of -167dB. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0021] It needs to be understood that in the description of the present application, the terms "first" and "second" and the like are used to distinguish different objects, rather than to describe a specific order of the objects. As Figure 1 The present application provides a chaotic system based on a double charge-controlled memristor model, which is suitable for weak signal detection scenarios, including a strategy power module, an integral summation reverse module and a multiplication module.

[0022] The strategy power module includes a sine signal source XFG1 for generating a sine signal.

[0023] The integral summation reverse module includes a first summation circuit, a first integral circuit, a second summation circuit, a second integral circuit, a first reverse circuit and a third integral circuit, all of which use operational amplifiers, for sequentially performing first summation, first integral, second summation, second integral, reverse and third integral processing on the sine signal to obtain the corresponding output signal.

[0024] The multiplication module includes multipliers A1-A4 for sequentially multiplying the output signal after third integral processing through multiplier A3, multiplying the output signal after reverse processing through multiplier A4, multiplying the output signal after second integral processing through multiplier A1, and multiplying the output signal after first integral processing through multiplier A2.

[0025] The output signals after first integral, second summation, second integral, reverse and third integral processing are respectively added reversely with the sine signal through the first summation circuit; the output signal after second integral processing and the output signal obtained by multiplying the output signal after reverse processing through multiplier A4 are added reversely with the output signal after first integral processing through the second summation circuit.

[0026] In the present application, the third integral circuit, the multiplier A3 and the multiplier A4 constitute a charge-controlled memristor model for enhancing the nonlinearity and noise immunity of the chaotic system, making the memristor chaotic system more sensitive to weak disturbances, which is conducive to the identification of weak signals in noise.

[0027] The chaotic system based on a double charge-controlled memristor model provided by the present application significantly enhances the nonlinearity and noise immunity of the system by introducing a memristor model, making it have the potential to achieve high-precision weak signal detection in a low signal-to-noise ratio environment. The introduced memristor model acts on different feedback paths of the system, on the one hand, introducing a charge-dependent nonlinear impedance, making the system more sensitive to weak disturbances; on the other hand, through its memory effect, introducing time correlation, so that weak signals can produce accumulation and amplification effect in the system, thereby effectively distinguishing signals from random noise, making the system can realize high-precision signal identification in strong noise interference.

[0028] The chaotic system provided by the present application will be described in detail below in combination with specific embodiments.

[0029] The present embodiment provides a chaotic system based on a double charge control memristor model, as shown in the figure, which comprises an operational amplifier U1, an operational amplifier U2, an operational amplifier U3, an operational amplifier U4, an operational amplifier U5, an operational amplifier U6, a capacitor C1, a capacitor C2, a capacitor C3, a multiplier A1, a multiplier A2, a multiplier A3, a multiplier A4, resistors R1-R21, and a sinusoidal signal source XFG1. Figure 1

[0030] The one end of the resistor R1 is connected to the inverting input terminal of the operational amplifier U1, and the other end of the resistor R1 is connected to the output terminal of the operational amplifier U2; the one end of the resistor R2 is connected to the inverting input terminal of the operational amplifier U1, and the other end of the resistor R2 is connected to the multiplier A2; the one end of the resistor R3 is connected to the inverting input terminal of the operational amplifier U1, and the other end of the resistor R3 is connected to the output terminal of the operational amplifier U4; the one end of the resistor R4 is connected to the inverting input terminal of the operational amplifier U1, and the other end of the resistor R4 is connected to the multiplier A4; the one end of the resistor R5 is connected to the inverting input terminal of the operational amplifier U1, and the other end of the resistor R5 is connected to the positive electrode of the sinusoidal signal source XFG1; the one end of the resistor R6 is connected to the inverting input terminal of the operational amplifier U1, and the other end of the resistor R6 is connected to the output terminal of the operational amplifier U1; the non-inverting input terminal of the operational amplifier U1 is grounded, and the output terminal of the operational amplifier U1 is connected to the inverting input terminal of the operational amplifier U2 through the resistor R7.

[0031] The resistor R8 and the capacitor C1 form a first parallel network, one end of the first parallel network is connected to the inverting input terminal of the operational amplifier U2, and the other end of the first parallel network is connected to the output terminal of the operational amplifier U2; the non-inverting input terminal of the operational amplifier U2 is grounded through the resistor R9, and the output terminal of the operational amplifier U2 is connected to the inverting input terminal of the operational amplifier U3 through the resistor R12; the one end of the resistor R10 is connected to the inverting input terminal of the operational amplifier U3, and the other end of the resistor R10 is connected to the output terminal of the operational amplifier U4; the one end of the resistor R11 is connected to the inverting input terminal of the operational amplifier U3, and the other end of the resistor R11 is connected to the output terminal of the multiplier A4; the one end of the resistor R13 is connected to the inverting input terminal of the operational amplifier U3, and the other end of the resistor R13 is connected to the output terminal of the operational amplifier U3; the non-inverting input terminal of the operational amplifier U3 is grounded, and the output terminal of the operational amplifier U3 is connected to the inverting input terminal of the operational amplifier U4 through the resistor R14.

[0032] ​The resistor R15 and the capacitor C2 form a second parallel network, one end of the second parallel network is connected with the inverting input terminal of the operational amplifier U4, and the other end of the second parallel network is connected with the output terminal of the operational amplifier U4; the non-inverting input terminal of the operational amplifier U4 is grounded through the resistor R16, and the output terminal of the operational amplifier U4 is connected with the inverting input terminal of the operational amplifier U5 through the resistor R17.

[0033] One end of the resistor R18 is connected with the inverting input terminal of the operational amplifier U5, and the other end of the resistor R18 is connected with the output terminal of the operational amplifier U5; the non-inverting input terminal of the operational amplifier U5 is grounded, and the output terminal of the operational amplifier U5 is connected with the inverting input terminal of the operational amplifier U6 through the resistor R19; the resistor R20 and the capacitor C3 form a third parallel network, one end of the third parallel network is connected with the inverting input terminal of the operational amplifier U6, and the other end of the third parallel network is connected with the output terminal of the operational amplifier U6; the non-inverting input terminal of the operational amplifier U6 is grounded through the resistor R21, and the output terminal of the operational amplifier U6 is connected with the X and Y ports of the multiplier A3.

[0034] The output port of the multiplier A3 is connected with the X port of the multiplier A4; the Y port of the multiplier A4 is connected with the output terminal of the operational amplifier U5; the Y port of the multiplier A1 is connected with the output terminal of the operational amplifier U4, the X port of the multiplier A1 is connected with the output terminal of the operational amplifier U5, and the output port of the multiplier A1 is connected with the X port of the multiplier A2; the Y port of the multiplier A2 is connected with the output terminal of the operational amplifier U2.

[0035] The working principle of the chaotic system provided by the embodiment is as follows: The input sinusoidal signal XFG1 is input into the first summing circuit to obtain a first output signal; the first output signal is input into the first integration circuit to obtain a second output signal; the second output signal is input into the second summing circuit to obtain a third output signal; the third output signal is input into the second integration circuit to obtain a fourth output signal; the fourth output signal is input into the first inversion circuit to obtain a fifth output signal; and the fifth output signal is input into the third integration circuit to obtain a sixth output signal.

[0036] The first summing circuit includes resistors R1, R2, R3, R4, R5, R6, and an operational amplifier U1; the first integrating circuit includes resistors R7, R8, R9, a capacitor C1, and an operational amplifier U2; the second summing circuit includes resistors R10, R11, R12, R13, and an operational amplifier U3; the second integrating circuit includes resistors R14, R15, R16, a capacitor C2, and an operational amplifier U4; the first inverting circuit includes resistors R17, R18, and an operational amplifier U5; and the third integrating circuit includes resistors R19, R20, R21, a capacitor C3, and an operational amplifier U6.

[0037] The sixth output signal is multiplied by the multiplier A3 to obtain a seventh output signal; the seventh output signal is multiplied by the fifth output signal by the multiplier A4 to obtain an eighth output signal; the fifth output signal is multiplied by the fourth output signal by the multiplier A1 to obtain a ninth output signal; the ninth output signal is multiplied by the second output signal by the multiplier A2 to obtain a tenth output signal; the second output signal, the fourth output signal, the eighth output signal, and the tenth output signal are inversely added to the sinusoidal signal XFG1 by the first summing circuit; and the fourth output signal and the eighth output signal are inversely added to the second output signal by the second summing circuit.

[0038] In the embodiment, the third integrating circuit, the multiplier A3, and the multiplier A4 constitute a charge-controlled memristor model.

[0039] The V-I relationship of the charge-controlled memristor can be defined as formula (1): (1) The constitutive relationship thereof can be represented by a cubic nonlinear function: (2) a and b are coefficients of the first-order term and the third-order term, respectively, and are dimensionless constants, and the memristor value can be represented as (3) The mathematical models of the traditional Duffing oscillator and the Van der Pol oscillator are respectively formula (4) and (5): (4) (5) The damping term in the Van der Pol oscillator is used to replace the damping term in the Duffing system, the two systems are coupled, and a Van der Pol-Duffing system is constituted. The mathematical model thereof can be represented as: (6) wherein,x Indicates voltage. Represents the nonlinear damping coefficient. Let ω represent the amplitude of the sinusoidal signal XFG1, and ω represent the angular frequency of the sinusoidal signal XFG1. Use the expression for a charge-controlled memristor. Replacing the nonlinear cubic term in equation (6), the cosine term on the right side of the equation is called the periodic driving force. The above equation can be rewritten as a system of differential equations as shown in equation (7): (7) In equation (7), another load-controlled memristor is introduced to change the system variable. The memristor's output voltage is added to the system equations as the input current signal, thus constructing a dual-memristor Van der Pol-Duffing chaotic system. The system model expression is as follows: (8) In the formula, x 1 represents the voltage output from the operational amplifier in the third integrator circuit; x 2 represents the voltage output from the operational amplifier in the second integrator circuit; x 3 represents the voltage output from the operational amplifier in the first integrating circuit; x 4 represents the frequency of the sinusoidal signal XFG1; .

[0040] Figure 2 , Figure 3 , Figure 4 These are the chaotic state and periodic state of the chaotic system provided in this embodiment. The schematic diagram of the phase diagram, in this embodiment, operational amplifier U1, operational amplifier U2, operational amplifier U3, operational amplifier U4, operational amplifier U5 and operational amplifier U6 are all selected from operational amplifier TL082, multiplier A1, multiplier A2, multiplier A3 and multiplier A4 are all selected from four quadrant multiplier AD633, capacitor C1=100uF, capacitor C2=100uF, capacitor C3=100uF, resistance R1=20 KΩ, resistance R2=20 KΩ, resistance R3=10 KΩ, resistance R4=10 KΩ, resistance R5=10 KΩ, resistance R6=10 KΩ, resistance R7=10 KΩ, resistance R8=220 KΩ, resistance R9=10 KΩ, resistance R10=10 KΩ, resistance R11=10 KΩ, resistance R12=10 KΩ, resistance R13=10 KΩ, resistance R14=10 KΩ, resistance R15=220 KΩ, resistance R16=10 KΩ, resistance R17=10 KΩ, resistance R18=10 KΩ, resistance R19=10 KΩ, resistance R20=220 KΩ, resistance R21=10 KΩ, each parameter value is: ω=1rad / s, , a=1, When , the system is in a chaotic state; when , the system is in a periodic state; from Figure 2 , Figure 3 , Figure 4 It can be seen that the chaotic system provided in this embodiment has a unique chaotic dynamic behavior and can generate a unique chaotic signal.

[0041] The principle of the chaotic system provided in this embodiment for weak signal detection is: Taking advantage of the sensitivity of the chaotic system to parameter perturbation, and the characteristics that the system period changes essentially, the weak signal detection is performed, that is, the signal to be detected is taken as the perturbation of the periodic driving force of the chaotic system, the noise is strong, but has no influence on the change of the system state, and once there is a specific signal, due to the sensitivity of the chaotic system to the small periodic signal, even if the amplitude is small, the system will also change phase.

[0042] First, the system is placed in a critical state, that is, the amplitude γ of the driving force is set to the critical threshold γ d At this time, the system is very sensitive to the change of the parameter γ, as long as γ increases a little, the output motion state of the detection system will change very obviously, from chaotic state to periodic state. Therefore, if only noise exists in the signal to be detected, the detection system remains in a chaotic state, and when the signal to be detected contains a weak periodic signal with the same frequency as the system driving force, the periodic signal and the system driving force signal amplitude are superposed, which can be regarded as the increase of the parameter γ in the system, at this time, γ exceeds the critical threshold γ dThe system's motion state changes to a periodic state, which is significantly different from the previous chaotic motion state.

[0043] like Figure 5 As shown, the signal-to-noise ratio (SNR) threshold determination for a chaotic system provided in this embodiment includes the following steps: First, adjust the system's driving force amplitude to bring the system to a critical state transitioning from a chaotic state to a large-scale periodic state; input a sinusoidal signal containing Gaussian white noise with an SNR value of SNR1 into the chaotic detection system. If the system transitions from the critical state to a large-scale periodic motion state, it indicates that the system can detect a weak sinusoidal signal under the current SNR condition; reduce the SNR value to SNR2 and repeat the above judgment process until the system exhibits a chaotic and disordered running trajectory and cannot enter a periodic state, thus making it impossible to determine whether a weak signal has been detected. Through the above steps, the SNR threshold of the chaotic system detection signal can be obtained.

[0044] Please refer to Figure 6 , Figure 6 This is a process diagram of weak signal detection performed by the chaotic system provided in this embodiment. The phase trajectory of the dual memristor chaotic system in the critical state is as follows: Figure 6 As shown in section (a), the signal to be measured is a weak cosine signal with the same frequency and phase as the driving force, and its amplitude is 1×10⁻⁶. -10 V, at this point the signal-to-noise ratio of the signal under test is -166dB, and its waveform is as follows. Figure 6 As shown in section (b), when a signal to be measured with a signal-to-noise ratio of -166 dB is input into a dual-memristor chaotic system, the amplitude of the weak signal and the amplitude of the driving force of the critical state are superimposed, exceeding the critical threshold γ. d This causes the system to enter a periodic state, and the system's phase trajectory is as follows: Figure 6 As shown in section (c); when the signal-to-noise ratio drops to -167dB, the system becomes chaotic, exhibiting a disordered and erratic trajectory, making it impossible to determine whether a weak signal has been detected. The system's phase trajectory is as follows. Figure 6 As shown in section (d). Therefore, the minimum signal-to-noise ratio of the dual memristor chaotic system designed in this paper is -166dB, and the detection accuracy is 1×10⁻⁶. -10 V.

[0045] The beneficial effect of this embodiment is that by introducing two charge-controlled memristor models into the Van der Pol-Duffing chaotic system circuit structure, a chaotic system circuit with complex dynamic characteristics was successfully constructed. This design not only enriches the dynamic behavior of chaotic systems but also provides a new approach for weak signal detection.

[0046] Those skilled in the art can understand that the above description is only the preferred embodiment of the present application, and is not used to limit the present application, and any modification, equivalent replacement and improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A chaotic system based on a double charge-controlled memristor model, suitable for weak signal detection scenarios, characterized in that, The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system.

2. The chaos system based on the double charge-controlled memristor model according to claim 1, wherein, The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. wherein x 1 represents the voltage outputted from the output terminal of the operational amplifier in the third integration circuit; x 2 represents the voltage outputted from the output terminal of the operational amplifier in the second integration circuit; x 3 represents the voltage outputted from the output terminal of the operational amplifier in the first integration circuit; x 4 represents the frequency of the sinusoidal signal; represents the nonlinear damping coefficient; represents the amplitude of the sinusoidal signal; represents the memristor value, a and b are the coefficients of the first order term and the third order term, respectively.

3. The chaotic system based on the double charge-controlled memristor model according to claim 1 or 2, characterized in that, The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. Using the expression of the charge-controlled memristor Instead of the nonlinear cubic term in the mathematical model of the Van der Pol-Duffing system, and rewriting it as a system of differential equations; A current-controlled memristor is introduced to the system to The input current signal of the memristor is added to the system equation as the output voltage of the memristor.

4. The chaos system based on the dual charge controlled memristor model of claim 1, wherein, The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system.

5. The chaos system based on the double charge-controlled memristor model according to claim 1, wherein, The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and a method for constructing a mathematical model of the chaotic system. The application relates to a chaotic system and One end of the resistor R1 is connected with the inverting input terminal of the operational amplifier U1, the other end of the resistor R1 is connected with the output terminal of the operational amplifier U2; one end of the resistor R2 is connected with the inverting input terminal of the operational amplifier U1, the other end of the resistor R2 is connected with the multiplier A2; one end of the resistor R3 is connected with the inverting input terminal of the operational amplifier U1, the other end of the resistor R3 is connected with the output terminal of the operational amplifier U4; one end of the resistor R4 is connected with the inverting input terminal of the operational amplifier U1, the other end of the resistor R4 is connected with the multiplier A4; one end of the resistor R5 is connected with the inverting input terminal of the operational amplifier U1, the other end of the resistor R5 is used for receiving the sinusoidal signal; one end of the resistor R6 is connected with the inverting input terminal of the operational amplifier U1, the other end of the resistor R6 is connected with the output terminal of the operational amplifier U1; the non-inverting input terminal of the operational amplifier U1 is grounded.

6. The chaos system based on the dual charge-controlled memristor model according to claim 1, wherein, The first integral circuit comprises the resistor R7, the resistor R8, the resistor R9, the capacitor C1 and the operational amplifier U2; Wherein, the inverting input terminal of the operational amplifier U2 is connected with the output terminal of the operational amplifier in the first summing circuit through the resistor R7, the resistor R8 and the capacitor C1 form a first parallel network in parallel, one end of the first parallel network is connected with the inverting input terminal of the operational amplifier U2, the other end of the first parallel network is connected with the output terminal of the operational amplifier U2; the non-inverting input terminal of the operational amplifier U2 is grounded through the resistor R9.

7. The chaos system based on the dual charge-controlled memristor model according to claim 1, wherein, The second summing circuit comprises the resistor R10, the resistor R11, the resistor R12, the resistor R13 and the operational amplifier U3; Wherein, the inverting input terminal of the operational amplifier U3 is connected with the output terminal of the operational amplifier in the first integral circuit through the resistor R12; one end of the resistor R10 is connected with the inverting input terminal of the operational amplifier U3, the other end of the resistor R10 is connected with the output terminal of the operational amplifier U4; one end of the resistor R11 is connected with the inverting input terminal of the operational amplifier U3, the other end of the resistor R11 is connected with the output terminal of the multiplier A4; one end of the resistor R13 is connected with the inverting input terminal of the operational amplifier U3, the other end of the resistor R13 is connected with the output terminal of the operational amplifier U3; the non-inverting input terminal of the operational amplifier U3 is grounded.

8. The chaos system based on the dual charge-controlled memristor model according to claim 1, wherein, The second integral circuit comprises the resistor R14, the resistor R15, the resistor R16, the capacitor C2 and the operational amplifier U4; Wherein, the inverting input terminal of the operational amplifier U4 is connected with the output terminal of the operational amplifier in the second summing circuit through the resistor R14; the resistor R15 and the capacitor C2 form a second parallel network in parallel, one end of the second parallel network is connected with the inverting input terminal of the operational amplifier U4, the other end of the second parallel network is connected with the output terminal of the operational amplifier U4; the non-inverting input terminal of the operational amplifier U4 is grounded through the resistor R16.

9. The chaos system based on the dual charge-controlled memristor model according to claim 1, wherein, The first reverse circuit comprises the resistor R17, the resistor R18 and the operational amplifier U5, the third integral circuit comprises the resistor R19, the resistor R20, the resistor R21, the capacitor C3 and the operational amplifier U6; The inverting input terminal of the operational amplifier U5 is connected with the output terminal of the operational amplifier in the second integrating circuit through the resistor R17; one end of the resistor R18 is connected with the inverting input terminal of the operational amplifier U5, and the other end of the resistor R18 is connected with the output terminal of the operational amplifier U5; the non-inverting input terminal of the operational amplifier U5 is grounded; The output terminal of the operational amplifier U5 is connected with the inverting input terminal of the operational amplifier U6 through the resistor R19; the resistor R20 and the capacitor C3 constitute a third parallel network, one end of the third parallel network is connected with the inverting input terminal of the operational amplifier U6, and the other end of the third parallel network is connected with the output terminal of the operational amplifier U6; the non-inverting input terminal of the operational amplifier U6 is grounded through the resistor R21, and the output terminal of the operational amplifier U6 is connected with two input terminals of the multiplier A3.

10. The method of determining the SNR threshold of a chaotic system based on a double charge controlled memristor model according to any one of claims 1-9, wherein, The method comprises the following steps: (1) adjusting the amplitude of the system driving force, i.e. the amplitude of the sinusoidal signal, so that the system is in a critical state from a chaotic state to a large-scale periodic state; (2) inputting a sinusoidal signal containing Gaussian white noise with a signal-to-noise ratio of SNR1 into the system, and if the system enters a large-scale periodic motion state from the critical state, it is indicated that the system can detect a weak sinusoidal signal under the current signal-to-noise ratio; (3) reducing the signal-to-noise ratio to SNR2, repeating the judgment process in step (2), until the system presents a chaotic running track and cannot enter a periodic state, so that it cannot be judged whether a weak signal is detected, and the signal-to-noise ratio threshold of the chaotic system for detecting a signal is obtained through the above steps.

Images