An over-etching identification method and system

Abstract

The application provides an over-etching identification method and system, wherein the method comprises the following steps: obtaining an initial length of an initial overlay mark of a chip to be etched at a preset position; after a passivation layer etching of the chip to be etched is performed by an etching machine, obtaining a target length of a to-be-measured overlay mark at the preset position, wherein the to-be-measured overlay mark is obtained by removing the passivation layer above the initial overlay mark through the passivation layer etching; and identifying an etching state according to the initial length and the target length, wherein the etching state is used to indicate whether the passivation layer etching is over-etching. By monitoring the difference between the initial length and the target length, it can be determined in real time whether the passivation layer etching is over-etching or whether there is under-etching, so as to make up for the short board that the passivation layer etching process step cannot monitor the etching degree in real time, and provide a reference for timely discovering process abnormalities and adjusting the process direction.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor etching, and particularly relates to an over-etching identification method and system. BACKGROUND

[0002] The passivation layer on a semiconductor device is a protective layer of a chip. It is mainly composed of oxide and silicon nitride, and is used to prevent other moisture and particles in the air from entering the chip, thereby protecting the chip. The passivation layer etching process needs to etch away the oxide layer and the nitride layer above the PAD (pin pad) position. In order to ensure that the metal (generally aluminum) at the PAD position is completely exposed, the passivation layer etching will cause a certain degree of metal loss. Whether the passivation layer etching causes over-etching is determined by whether the amount of metal loss is acceptable.

[0003] However, since the remaining thickness of the metal layer after etching cannot be measured in the prior art, it is difficult to determine whether over-etching occurs. Only by monitoring the change of etching rate and speculating the amount of metal loss according to past experience can it be determined. When there is no experience value or in the case of a new product, time needs to be spent to do PRS (Process Release Standard), and the amount of metal loss is detected by slicing to determine whether over-etching occurs. The identification efficiency is low and the cost is high. SUMMARY

[0004] Therefore, the purpose of the present application is to provide at least an over-etching identification method and system. The passivation layer above the overlay mark of a chip is etched to obtain a target length of the overlay mark at a preset position. Whether the passivation layer is over-etched is determined according to the target length and the initial length of the preset position before etching. The technical problem of low identification efficiency and high cost of over-etching in the prior art is solved, and the technical effect of improving the identification efficiency of over-etching and reducing the cost is achieved.

[0005] The present application mainly includes the following aspects:

[0006] In a first aspect, an over-etching identification method is provided. The method includes: obtaining an initial length of an initial overlay mark at a preset position of a chip to be etched; after the passivation layer etching of the chip to be etched is performed by a etching machine, obtaining a target length of a to-be-measured overlay mark at the preset position, the to-be-measured overlay mark being an overlay mark obtained by removing the passivation layer above the initial overlay mark through passivation layer etching; and identifying an etching state according to the initial length and the target length, the etching state being used to indicate whether the passivation layer etching is over-etching.

[0007] Optionally, the etching state includes a first etching state corresponding to over-etching of the passivation layer or a second etching state corresponding to non-over-etching of the passivation layer, and the etching state is identified by: calculating a length difference between the initial length and the target length; identifying that the etching state is in the first etching state when the length difference is greater than a preset difference; and identifying that the etching state is in the second etching state when the length difference is less than or equal to the preset difference.

[0008] Optionally, the passivation layer of the chip to be etched is etched by: controlling an etching machine to etch the passivation layer of the chip to be etched through a first mask to etch the passivation layer above the top metal layer of the chip to be etched to form a pin pad and etch the passivation layer above the initial overlay mark to obtain the overlay mark to be measured.

[0009] Optionally, the passivation layer of the chip to be etched is etched by: controlling an etching machine to etch the passivation layer of the chip to be etched through a second mask and a third mask respectively to etch the passivation layer above the top metal layer of the chip to be etched and the passivation layer above the initial overlay mark respectively to gradually form the pin pad and the overlay mark to be measured.

[0010] Optionally, the preset difference is obtained by: obtaining a plurality of test length differences respectively corresponding to a plurality of test chips, the test length difference being a difference between an initial length and a target length of the test chip at the preset position, the plurality of test chips respectively performing different degrees of passivation layer etching; determining at least one defect test chip having an over-etching defect in the plurality of test chips through slicing, and taking a minimum value of the test length difference corresponding to the at least one defect test chip or a maximum value of the test length difference of other test chips as the preset difference, the other test chips being test chips other than the defect test chips in the plurality of test chips.

[0011] Optionally, the preset position is a bottom edge and / or a top edge of a side of the overlay mark.

[0012] Optionally, the passivation layer includes an oxidation layer and a nitridation layer, and the nitridation layer is above the oxidation layer.

[0013] In a second aspect, the embodiments of the present application further provide an over-etching identification system, which includes: a processor configured to perform the steps of the method described in the first aspect or any possible implementation manner of the first aspect; a feature size measurement device configured to measure the initial length and the target length; and an etching machine configured to etch the passivation layer of the chip to be etched.

[0014] In a third aspect, the embodiments of the present application further provide a mask plate, which is applied to the method in the first aspect or any possible implementation manner of the first aspect, or applied to the system in the second aspect. The mask plate comprises one mask plate provided with a first pattern and a second pattern. The first pattern is used for etching a passivation layer above a top metal layer of the chip to be etched. The second pattern is used for etching the passivation layer above the initial overlay mark.

[0015] In a fourth aspect, the embodiments of the present application further provide a mask plate, which is applied to the method in the first aspect or any possible implementation manner of the first aspect, or applied to the system in the second aspect. The mask plate comprises one mask plate provided with a first pattern and another mask plate provided with a second pattern. The first pattern is used for etching a passivation layer above a top metal layer of the chip to be etched. The second pattern is used for etching the passivation layer above the initial overlay mark.

[0016] The embodiments of the present application provide an over-etching identification method and system. The method comprises the following steps: obtaining an initial length of an initial overlay mark of a chip to be etched at a preset position; after a passivation layer etching of the chip to be etched is performed by an etching machine, obtaining a target length of a to-be-measured overlay mark at the preset position. The to-be-measured overlay mark refers to an overlay mark obtained by removing the passivation layer above the initial overlay mark through the passivation layer etching. According to the initial length and the target length, an etching state is identified. The etching state is used to indicate whether the passivation layer etching is over-etching. The target length of the overlay mark at the preset position is obtained by etching the passivation layer above the overlay mark of the chip. Whether the passivation layer is over-etched is determined according to the target length and the initial length of the preset position before etching. The technical problem that the efficiency of identifying over-etching is low and the cost is high in the prior art is solved. The technical effects that the efficiency of identifying over-etching is improved and the cost is reduced are achieved.

[0017] In order to make the above objectives, characteristics and advantages of the present application more apparent, clear and easy to understand, the following will specifically describe the preferred embodiments of the present application with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be considered as limiting the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0019] Figure 1 A flow chart of an over-etching identification method provided by the embodiments of the present application is shown.

[0020] Figure 2 A schematic diagram of a chip to be etched is shown.

[0021] Figure 3 A schematic diagram of the influence of the etching degree of the passivation layer on the amount of metal loss is shown.

[0022] Figure 4 A schematic diagram of a chip obtained after etching the passivation layer of the chip to be etched is shown.

[0023] Figure 5 A schematic diagram of a second pattern is shown.

[0024] Figure 6 A side view of a measurement overlay mark to be measured is shown.

[0025] Figure 7 A top view of a measurement overlay mark to be measured is shown. DETAILED DESCRIPTION

[0026] To make the objectives, technical solutions, and superiorities of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in connection with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of description and illustration, and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn according to the actual proportions. The flowcharts show the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowcharts can not be implemented in sequence, and the steps without logical context relationship can be reversed in sequence or implemented simultaneously. In addition, one or more other operations can be added to the flowcharts or one or more operations can be removed from the flowcharts under the guidance of the content of the present application.

[0027] In addition, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. The components of the embodiments of the present application described and shown in the drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0028] In the prior art, the amount of metal loss (aluminum loss) caused by passivation layer etching is generally controlled by controlling the length of etching time. However, since the etching rate is not fixed, different etching recipes and different etching machines will produce etching rate differences at different times, thereby causing the amount of metal loss to be uncertain. The amount of metal loss caused by passivation layer etching (dry etching) and the plasma-induced damage (PID) caused during etching are positively correlated in theory. The greater the amount of metal loss, the greater the surface plasma bombardment of the metal, and the greater the charge introduced through the metal during etching, which affects the quality of the chip. Therefore, determining whether the passivation layer etching is over-etching is very important for ensuring the yield of semiconductor devices.

[0029] Currently, the thickness of the metal layer of the wafer cannot be measured after the passivation layer etching, so the change in the thickness of the metal layer cannot be known, that is, the amount of metal loss caused by the passivation layer etching cannot be known. In the prior art, the amount of metal loss can only be estimated according to past experience values after the etching rate of the entire passivation layer etching process is monitored. If there are no experience values or in the case of preparing new products, the amount of metal loss can only be measured by slicing, which will damage the wafer and the analysis process is relatively complex, resulting in a relatively complex and high-cost process of determining whether over-etching occurs.

[0030] Based on this, the embodiments of the present application provide an over-etching identification method and system. The passivation layer above the overlay mark of the chip is etched to obtain the target length of the overlay mark at the preset position. Whether the passivation layer is over-etched is determined according to the target length and the initial length of the preset position before etching. The technical problem of low efficiency and high cost of identifying over-etching in the prior art is solved, and the technical effect of improving the efficiency of identifying over-etching and reducing the cost is achieved. Specifically as follows:

[0031] Please refer to Figure 1 , Figure 1 The flowchart of an over-etching identification method provided by the embodiments of the present application. As shown in Figure 1 , the over-etching identification method provided by the embodiments of the present application includes the following steps:

[0032] S101: Obtain the initial length of the initial overlay mark of the to-be-etched chip at the preset position.

[0033] The chip to be etched can be any type of chip that requires passivation layer etching; there are no restrictions on the type of chip. The initial overlay mark is generated during the fabrication process of the chip to be etched. The initial overlay mark (TopMetal CD bar) refers to the mark used to detect the feature size (CD). The initial overlay mark is located inside the passivation layer of the chip to be etched, and the initial overlay mark and the top metal layer are on the same layer.

[0034] Specifically, the preset position is the bottom edge and / or top edge of the side of the overprinted mark. The side of the initial overprinted mark can be approximated as a trapezoid, and the preset position of the initial overprinted mark refers to the bottom edge and / or top edge of the trapezoid approximated by the side of the initial overprinted mark.

[0035] Please see Figure 2 , Figure 2 This is a schematic diagram of the chip to be etched provided in an embodiment of this application. Figure 2 As shown, in the chip to be etched, the passivation layer 101 is located on the base substrate 102. The passivation layer 101 includes an oxide layer 1011 and a nitride layer 1012, with the nitride layer located on top of the oxide layer. The top metal layer 103 and the initial overlay mark 104 are located inside the oxide layer 1011. The side of the initial overlay mark 104 can be approximately trapezoidal, and the length of the predetermined position of the initial overlay mark refers to the length of the base side Ld1 and the length of the top side Lt1 of the trapezoid.

[0036] For example, the chip to be etched is prepared by: depositing a metal layer on a base substrate, and then etching the metal layer to prepare a top metal layer 103 and an initial overlay mark 104. The top metal layer is used to prepare the lead pads (PADs) in the future, and the initial overlay mark is used to detect the size of the feature size; an oxide layer 1011 and a nitride layer 1012 are deposited in sequence, with the oxide layer 1011 covering the top metal layer 103 and the initial overlay mark 104, and the nitride layer 1012 covering the oxide layer 1011, thereby preparing the chip to be etched.

[0037] In other words, the top metal layer and the initial overlay mark are obtained by etching the same metal layer. Therefore, the thickness of the top metal layer should be approximately the same as the thickness of the initial overlay mark. Furthermore, when the thickness of the top metal layer is approximately the same as the thickness of the initial overlay mark, the degree of passivation layer etching can be reflected by the change in the length of the bottom and / or top edge of the initial overlay mark.

[0038] S102: After the etching machine is controlled to perform passivation layer etching on the chip to be etched, the target length of the overlay mark to be measured at the preset position is obtained.

[0039] The to-be-measured overlay mark refers to an overlay mark obtained by removing the passivation layer above the initial overlay mark through passivation layer etching.

[0040] That is, the passivation layer above the initial overlay mark should be removed through passivation layer etching of the to-be-etched chip by the etching machine, and the initial overlay mark after passivation layer etching is taken as the to-be-measured overlay mark. In this way, etching the passivation layer above the initial overlay mark will etch away part of the initial overlay mark to some extent, so that the size of the to-be-measured overlay mark obtained by etching is different from that of the initial overlay mark. Therefore, whether the etching is excessive is reflected by measuring the length change of the same preset position of the initial overlay mark and the to-be-measured overlay mark.

[0041] Please refer to Figure 3 , Figure 3 The schematic diagram of the influence of the passivation layer etching degree on the metal loss amount provided by the embodiment of the present application. As shown in Figure 3 , the abscissa is used to indicate the passivation layer etching degree, the arrow direction of the abscissa is used to indicate that the passivation layer etching degree is enhanced, that is, the etching rate and / or etching time is larger, the ordinate is used to indicate the metal loss amount of the overlay mark caused by the passivation layer etching, and the arrow direction of the ordinate is used to indicate that the metal loss amount is enhanced. That is, the passivation layer etching will gradually etch the metal from the side, and the larger the metal loss amount, the smaller the bottom edge and the top edge of the overlay mark, and the side of the overlay mark will gradually change from a trapezoidal shape to a triangular shape.

[0042] Please refer to Figure 4 , Figure 4 The schematic diagram of the chip obtained after the passivation layer etching of the to-be-etched chip provided by the embodiment of the present application. As shown in Figure 4 , the top metal layer is taken as a pin pad 201 after passivation layer etching, the initial overlay mark is taken as a to-be-measured overlay mark 202 after passivation layer etching, and the length of the preset position of the to-be-measured overlay mark 202 refers to the bottom edge length Ld2 and the top edge length Lt2 of the to-be-measured overlay mark 202.

[0043] And, since the size of the overlay mark is obviously smaller than the size of the top metal layer, when etching the passivation layer according to the same etching parameters, the thickness change of the passivation layer caused by etching the passivation layer above the top metal layer and the passivation layer above the overlay mark should tend to be consistent, but when etching to the top metal layer, the rate of metal thickness reduction will be smaller than the rate of passivation layer thickness reduction. Thus, the rate of passivation layer thickness reduction on both sides of the overlay mark is greater than the rate of thickness reduction of the overlay mark metal, so that when the passivation layer on both sides of the overlay mark is removed, the top metal layer and the overlay mark metal are not removed, and further etching is performed not only on the top surface of the overlay mark metal but also from the side surface of the overlay mark metal, further affecting the length change of the preset position.

[0044] In which, the passivation layer etching of the chip to be etched is performed by controlling the etching machine to etch the chip to be etched through the first mask to etch the passivation layer above the top metal layer of the chip to be etched to form the pin pad, and etch the passivation layer above the initial overlay mark to obtain the overlay mark to be measured.

[0045] That is, when performing the passivation layer etching, one mask is used to etch the passivation layer above the top metal layer and the passivation layer above the initial overlay mark synchronously, so as to synchronously obtain the pin pad and the overlay mark to be measured. Since the pin pad and the overlay mark to be measured are prepared synchronously and the various etching parameters (such as etching rate, etching time) involved in the etching process are the same, the specification change of the overlay mark to be measured can better reflect whether the passivation layer etching is over-etched, and using one mask can only perform the passivation layer etching once, without additional etching time.

[0046] Or, the passivation layer etching of the chip to be etched is performed by controlling the etching machine to etch the chip to be etched through the second mask and the third mask respectively to etch the passivation layer above the top metal layer of the chip to be etched and the passivation layer above the initial overlay mark respectively, to gradually form the pin pad and the overlay mark to be measured.

[0047] That is, the passivation layer etching can be performed twice on the chip to be etched, once to etch the passivation layer above the top metal layer of the chip to be etched to form the pin pad, and the other to etch the passivation layer above the initial overlay mark to form the measurement overlay mark. The pin pad should be etched first, and then the measurement overlay mark. The parameters for etching the passivation layer above the initial overlay mark are consistent with those for etching the passivation layer above the top metal layer of the chip to be etched. Further, the pin pad and the measurement overlay mark are prepared by the same etching parameters, so that the etching degree of the passivation layer etching for the pin pad can be reflected by the specification change of the measurement overlay mark, and whether the over-etching problem occurs can be reflected.

[0048] Further, two passivation layer etchings require an additional mask for etching the measurement overlay mark, and the existing mask for etching the pin pad can still be used, preventing waste of the existing mask.

[0049] S103: Identify the etching state according to the initial length and the target length.

[0050] The etching state is used to indicate whether the passivation layer etching is over-etched. Specifically, the etching state includes a first etching state corresponding to over-etching of the passivation layer etching or a second etching state corresponding to non-over-etching of the passivation layer etching.

[0051] In other words, the etching state is used to identify whether the etching degree of the passivation layer etching is acceptable. When the etching degree is not acceptable, the etching state is the first etching state; when the etching degree is acceptable, the etching state is the second etching state.

[0052] Further, when it is determined that the etching state is used to indicate over-etching, over-etching can be avoided by reducing the etching rate or reducing the etching time, and when it is determined that the etching state is used to indicate non-over-etching, the passivation layer etching step in the subsequent generation process can be performed according to the conditions of the current passivation layer etching, without the need for slice analysis of the chip, avoiding waste of the chip without over-etching, providing identification rate and reducing cost.

[0053] The etching state is identified by calculating the length difference between the initial length and the target length, identifying the etching state in the first etching state when the length difference is greater than a preset difference, and identifying the etching state in the second etching state when the length difference is less than or equal to the preset difference.

[0054] That is, the length difference between the initial length and the target length refers to the length change of the same preset position before and after the passivation layer etching, and the length difference between the initial length and the target length is used to measure the amount of metal loss caused by the passivation layer etching.

[0055] Further, when the length variation is greater than the preset difference, it is considered that the metal loss caused by the passivation layer etching is too large, and the passivation layer etching causes over-etching problem; when the length variation is less than or equal to the preset difference, it is considered that the metal loss caused by the passivation layer etching is acceptable, and the passivation layer etching does not cause over-etching problem.

[0056] For example, when the preset position is the bottom edge, the length difference refers to the difference between the bottom edge length of the initial overlay mark before the passivation layer etching and the bottom edge length of the overlay mark to be measured after the passivation layer etching; when the preset position is the top edge, the length difference refers to the difference between the top edge length of the initial overlay mark before the passivation layer etching and the top edge length of the overlay mark to be measured after the passivation layer etching; when the preset position is the top edge and the bottom edge, the length difference refers to the statistical value (for example, the average value) of the bottom edge length difference and the top edge length difference, the bottom edge length difference refers to the difference between the bottom edge length of the initial overlay mark before the passivation layer etching and the bottom edge length of the overlay mark to be measured after the passivation layer etching, and the top edge length difference refers to the difference between the top edge length of the initial overlay mark before the passivation layer etching and the top edge length of the overlay mark to be measured after the passivation layer etching. Further, the size of the metal loss is reflected by the change before and after the etching of the same preset position.

[0057] In addition, the preset position with a target length of 0 after etching should be selected. For example, if the side of the overlay mark to be measured after the passivation layer etching is a triangle, the top edge length is approximately 0 at this time. Since the side of the overlay mark may have become a triangle during the etching process, it is difficult to accurately reflect the metal loss by using the top edge as the preset position. Therefore, when the top edge length is 0 after the passivation layer etching, the bottom edge should be selected as the preset position to increase the accuracy.

[0058] For example, the preset difference can be a manually set value or determined through multiple experiments.

[0059] Specifically, the preset difference is obtained by: obtaining a plurality of test chips respectively corresponding to a test length difference, the test length difference refers to the difference between the initial length and the target length of the preset position of the test chip, and the plurality of test chips respectively perform different degrees of passivation layer etching; determining at least one defect test chip with over-etching defect in the plurality of test chips through slicing, and taking the minimum value of the test length difference corresponding to the at least one defect test chip or the maximum value of the test length difference of other test chips as the preset difference, the other test chips refer to the test chips in the plurality of test chips except the defect test chips.

[0060] The multiple test chips have the same chip specifications when the passivation layer is not etched, that is, the thickness of the passivation layer, the thickness and size of the overlay mark, the thickness and size of the top metal layer, and other chip specification related parameters are consistent.

[0061] Further, the initial length of the initial overlay mark of each test chip at the preset position is collected. In theory, the initial length of each test chip is consistent because the chip specifications of each test chip are the same. The passivation layer etching is performed according to different etching parameters, that is, each test chip performs passivation layer etching through different etching parameters to produce different degrees of etching results. The target length of the measured overlay mark of the multiple test chips after passivation layer etching at the preset position is collected. Because the degrees of passivation layer etching of each test chip are different, the target lengths of each test chip should be different. Thus, the difference between the initial length and the target length of each test chip is calculated, and the difference is taken as the test length difference of each test chip. The test length differences of each test chip should be different.

[0062] That is, different degrees of passivation layer etching are performed to produce different length changes at the preset position. Further, each test chip is processed by slicing and whether each test chip produces an over-etching defect is identified manually. The test chip that produces an over-etching defect is taken as a defective test chip. In this way, the test length differences of each defective test chip are sorted, and the minimum value of the test length differences of the defective test chips is taken as a preset difference value, or the test length differences of the test chips other than the defective test chips are sorted, and the maximum value of the test length differences of the other test chips is taken as the preset difference value. In this way, whether a chip produces an over-etching defect is distinguished by the preset difference value.

[0063] Based on the same application concept, the present embodiment also provides an over-etching identification system corresponding to the over-etching identification method provided in the above-mentioned embodiment. Since the system in the present embodiment has a similar principle to the over-etching identification method of the above-mentioned embodiment, the implementation of the system can be referred to the implementation of the method, and the repeated parts will not be described here.

[0064] The present embodiment also provides an over-etching identification system, which comprises: a processor configured to execute the steps of the method provided in the above-mentioned embodiment; a feature size measurement device configured to measure the initial length and the target length; and an etching machine configured to perform passivation layer etching on the chip to be etched.

[0065] That is, the processor is configured to perform the above-mentioned processing steps, and the processor is connected with a feature size measuring device (CD-SEM) and an etching machine, respectively, so that the feature size measuring device collects an initial length of a preset position of the chip before etching of the passivation layer and sends the initial length to the processor, the processor sends an etching start signal to the etching machine to make the etching machine etch the passivation layer of the chip to be etched, and the feature size measuring device collects a target length of the preset position of the chip after etching of the passivation layer and sends the target length to the processor, so that the processor can determine whether over-etching occurs according to the initial length and the target length.

[0066] Based on the same application concept, the embodiment of the present application also provides a mask corresponding to the over-etching identification method provided in the above-mentioned embodiment. Since the principle of solving the problem of the mask in the embodiment of the present application is similar to that of the over-etching identification method in the above-mentioned embodiment of the present application, the implementation of the mask can be referred to the implementation of the method, and the repeated parts will not be described herein.

[0067] The embodiment of the present application also provides a mask applied to the method provided in the above-mentioned embodiment or applied to the system provided in the above-mentioned embodiment, and the mask comprises one, one mask is provided with a first pattern and a second pattern, the first pattern is used for etching the passivation layer above the top metal layer of the chip to be etched, and the second pattern is used for etching the passivation layer above the initial overlay mark.

[0068] That is, one passivation layer etching is performed by using one mask provided with the first pattern and the second pattern, so that the pin pad and the overlay mark to be measured are etched. Further, the first pattern is used for preparing the pin pad, and the second pattern is used for etching the overlay mark to be measured.

[0069] In the existing mask for etching the passivation layer, only the first pattern is provided, and then a mask containing the first pattern and the second pattern needs to be prepared. The preparation of the mask belongs to the prior art, and will not be described herein.

[0070] Based on the same application concept, the embodiment of the present application also provides another mask corresponding to the over-etching identification method provided in the above-mentioned embodiment. Since the principle of solving the problem of the mask in the embodiment of the present application is similar to that of the over-etching identification method in the above-mentioned embodiment of the present application, the implementation of the mask can be referred to the implementation of the method, and the repeated parts will not be described herein.

[0071] The embodiment of the present application further provides a mask plate, which is applied to the method provided by the above embodiment or the system provided by the above embodiment, and comprises a mask plate provided with a first pattern and another mask plate provided with a second pattern, the first pattern is used for etching a passivation layer above a top metal layer of the chip to be etched, and the second pattern is used for etching the passivation layer above the initial overlay mark.

[0072] That is, the passivation layer etching is performed by two mask plates, one mask plate is used for etching the passivation layer above the top metal layer of the chip to be etched to obtain a pin pad, and the other mask plate is used for etching the passivation layer above the initial overlay mark to obtain the overlay mark to be measured. Further, the mask plate provided with the first pattern can be directly used in the existing mask plate, and the mask plate provided with the second pattern needs to be prepared again. The preparation of the mask plate belongs to the prior art, and the present application will not be described here.

[0073] For example, refer to Figure 5 , Figure 5 the schematic view of the second pattern provided by the embodiment of the present application. As shown in Figure 5 , the metal etching mask plate 301 is provided with a pattern for etching the initial overlay mark, and the initial overlay mark 104 is generated on the chip after etching according to the metal etching mask plate 301, and then the passivation layer etching is performed by the mask plate containing at least the second pattern 401 to remove the passivation layer above the initial overlay mark.

[0074] For example, refer to Figure 6 and Figure 7 , Figure 6 the side view of the overlay mark to be measured provided by the embodiment of the present application, Figure 7 the top view of the overlay mark to be measured provided by the embodiment of the present application. As shown in Figure 6 , the side surface 501 of the overlay mark to be measured generated after the passivation layer etching by the mask plate containing at least the second pattern is approximately triangular, at this time, the length of the top edge is approximately 0, and then the bottom edge is selected as the preset position, and the length Ld2 of the bottom edge is the target length. As shown in Figure 7 , the etching window 601 corresponding to the second pattern is generated on the chip after the passivation layer etching, and from the enlarged part etching window 602, it can be known that the length of the preset position is shortened after etching the initial overlay mark, that is, the target length Ld2 of the bottom edge is shortened, so that whether over-etching is generated can be measured by the change of the length of the bottom edge.

[0075] Based on the same application concept, the embodiment of the present application further provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is run by a processor to execute the steps of the over-etching identification method provided in the above embodiment.

[0076] Specifically, the storage medium can be a general storage medium, such as a mobile disk, a hard disk, etc., and the computer program stored on the storage medium can be run to execute the above over-etching identification method, to obtain the target length of the overlay mark in the preset position by etching the passivation layer above the overlay mark of the chip, and to determine whether the passivation layer is over-etched according to the target length and the initial length of the preset position before etching, so as to solve the technical problems of low efficiency and high cost in identifying over-etching in the prior art, and to achieve the technical effects of improving the efficiency of identifying over-etching and reducing the cost.

[0077] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described system and device can refer to the corresponding process in the foregoing method embodiment, and will not be described here. In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. The above-described device embodiments are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some communication interface, device or unit, and can be electrical, mechanical or other forms.

[0078] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0079] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit.

[0080] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a nonvolatile computer readable storage medium executable by a processor. Based on this understanding, the technical solutions of the present application or the parts of the present application that essentially contribute to the prior art or the parts of the technical solutions can be embodied in the form of software products. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0081] The above merely describes the specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. An over-etching recognition method, characterized by, The method comprises: acquiring an initial length of an initial overlay mark at a preset position of a chip to be etched, the initial overlay mark being a mark for detecting feature size; after a passivation layer etching of the chip to be etched by a etching machine, acquiring a target length of a to-be-measured overlay mark at the preset position, the to-be-measured overlay mark being an overlay mark obtained by removing the passivation layer above the initial overlay mark through the passivation layer etching; according to the initial length and the target length, identifying an etching state, the etching state being used to indicate whether the passivation layer etching is over-etching; the etching state comprises a first etching state corresponding to over-etching of the passivation layer etching or a second etching state corresponding to non-over-etching of the passivation layer etching, wherein the etching state is identified by: calculating a length difference value of the initial length and the target length; when the length difference value is greater than a preset difference value, identifying that the etching state is in the first etching state; when the length difference value is less than or equal to the preset difference value, identifying that the etching state is in the second etching state.

2. The method of claim 1, wherein, the passivation layer etching of the chip to be etched is performed by: controlling the etching machine to perform the passivation layer etching of the chip to be etched through a first mask, so as to etch the passivation layer above a top metal layer of the chip to be etched to form a pin pad, and etch the passivation layer above the initial overlay mark to obtain the to-be-measured overlay mark.

3. The method of claim 1, wherein, the passivation layer etching of the chip to be etched is performed by: controlling the etching machine to perform the passivation layer etching of the chip to be etched through a second mask and a third mask respectively, so as to etch the passivation layer above the top metal layer of the chip to be etched and the passivation layer above the initial overlay mark respectively, to gradually form the pin pad and the to-be-measured overlay mark.

4. The method of claim 1, wherein, the preset difference value is obtained by: acquiring a plurality of test length difference values respectively corresponding to a plurality of test chips, the test length difference value being a difference value of an initial length and a target length of the test chip at the preset position, the plurality of test chips respectively performing different degrees of passivation layer etching; determining at least one defect test chip existing over-etching defect in the plurality of test chips through slicing, taking a minimum value of the test length difference value corresponding to the at least one defect test chip or a maximum value of the test length difference value of other test chips as the preset difference value, the other test chips being test chips other than the defect test chips in the plurality of test chips.

5. The method according to any one of claims 1 to 4, characterized in that, the preset position is a bottom edge and / or a top edge of a side of the overlay mark.

6. The method according to any one of claims 1 to 4, characterized in that, the passivation layer comprises an oxidation layer and a nitridation layer, the nitridation layer being above the oxidation layer.

7. An over-etching identification system, comprising: The system comprises: a processor configured to perform the steps of the method according to any one of claims 1 to 6; a feature size measurement device configured to measure the initial length and the target length; an etching machine configured to perform the passivation layer etching of the chip to be etched.

8. A mask, characterized in that, application to the method according to any one of claims 1 to 6, or application to the system according to claim 7, The mask plate comprises one, one mask plate is provided with a first pattern and a second pattern, The first pattern is used for etching the passivation layer above the top metal layer of the chip to be etched, and the second pattern is used for etching the passivation layer above the initial overlay mark.

9. A mask, characterized in that The method is applied to the method as claimed in any one of claims 1 to 6, or the system as claimed in claim 7, The mask plate comprises one, one mask plate is provided with a first pattern and a second pattern, The first pattern is used for etching the passivation layer above the top metal layer of the chip to be etched, and the second pattern is used for etching the passivation layer above the initial overlay mark.

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