Wafer carrying table

Abstract

The invention provides a wafer mounting table, which is characterized in that a first conductive layer and a second conductive layer which are different in height are conducted through a conduction part, and the heat uniformity of a wafer is improved. The wafer placement table (10) is configured in such a manner that a sub RF electrode (21) (first conductive layer) and a jumper layer (22) (second conductive layer) are implanted at different heights inside a ceramic base body (12) having a wafer placement surface (12a), and that the wafer placement table (10) is provided with a conduction part (30) for electrically conducting the sub RF electrode (21) and the jumper layer (22). The conduction part (30) is a transversely placed coil or a cylindrical body with a hole. The material of the ceramic base body (12) enters the internal space of the conduction part (30).

Description

[0001] This application is a divisional application of the invention patent application with application number 2022114031762, application date November 10, 2022, and invention title "Chip Placement Stage". Technical Field

[0002] This invention relates to a wafer mounting stage. Background Technology

[0003] Previously, wafer mounting stages for processing wafers were known. Examples of wafer mounting stages include ceramic heaters, electrostatic chucks, and bases (bases containing electrodes for plasma generation). For example, Patent Document 1 discloses a wafer mounting stage in which a circular first electrode and an annular second electrode with an outer diameter larger than that of the first electrode are implanted parallel to the wafer mounting surface, inside a ceramic substrate having a wafer mounting surface, from the side closest to the wafer mounting surface. The first and second electrodes are electrically connected via a conductive section. Patent Document 1 discloses examples of using a zigzag-bent metal mesh and examples of placing a coil longitudinally, among others, as the conductive section.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2003-163259 Summary of the Invention

[0007] However, when a zigzag-shaped metal mesh and a longitudinally placed coil are used as the conductive part, the conductive path of the conductive part is quite long compared to the distance between the first and second electrodes. This can easily lead to heat generation in the conductive part, sometimes negatively impacting the heat dissipation of the wafer.

[0008] The present invention was implemented to solve the above-mentioned problems. Its main objective is to improve the heat uniformity of the wafer on a wafer stage in which the first conductive layer and the second conductive layer of different heights are connected through a conductive section.

[0009] The wafer placement stage of the present invention is configured as follows:

[0010] Inside a ceramic substrate having a wafer mounting surface, a first conductive layer and a second conductive layer are implanted at different heights, and a conductive portion is provided to electrically connect the first conductive layer and the second conductive layer.

[0011] The wafer stage is characterized in that...

[0012] The conductive part is a horizontally placed coil or a perforated cylindrical body.

[0013] In this wafer mounting stage, the conductive portion is either a horizontally placed coil or a perforated cylindrical body. Therefore, compared to cases where a zigzag-bent metal mesh or a vertically placed coil is used as the conductive portion, the conductive path of the conductive portion is closer to the distance between the first and second conductive layers. Thus, heat generation in the conductive portion can be suppressed, thereby improving the wafer's heat dissipation. It should be noted that examples of perforated cylindrical bodies include, for instance, perforated metal cylindrical bodies and metal mesh cylindrical bodies.

[0014] In the wafer stage of the present invention, the material of the ceramic substrate can enter the internal space of the conductive portion. Accordingly, the density deviation of the ceramic substrate is reduced, and the strength is increased.

[0015] In the wafer stage of the present invention, the cross-sectional shape of the conductive portion can be circular or elliptical. Accordingly, even if a force in the compression direction is applied from above and below the conductive portion during the manufacturing process, the conductive portion can absorb the force.

[0016] In the wafer stage of the present invention, the conductive portion can be a coil, and at least one of the first conductive layer and the second conductive layer can have a hole extending along the thickness direction. The coil enters the hole, allowing the inner surface of the hole to contact the side surface of the coil. Therefore, compared to the case where the coil and each conductive layer are in point contact, the contact area is increased, thus making it easier to ensure conductivity.

[0017] In the wafer stage of the present invention, the second conductive layer can be a linear or rectangular conductive layer that intersects the first conductive layer when viewed from above, and the axis of the conductive portion can be a straight line along the extension direction of the second conductive layer. Accordingly, the length of the conductive portion can be relatively long, making it easier to ensure the conductivity between the first and second conductive layers.

[0018] In the wafer stage of the present invention, the second conductive layer can be a ring-shaped or fan-shaped conductive layer that repeats the shape of the first conductive layer when viewed from above, and the axis of the conductive portion can be an arc concentric with the second conductive layer. Accordingly, the length of the conductive portion can be relatively long, easily ensuring conductivity between the first and second conductive layers. Attached Figure Description

[0019] Figure 1 This is a plan view of the chip placement stage 10.

[0020] Figure 2 yes Figure 1 AA section diagram.

[0021] Figure 3 This is a side view of the conductive part 30 and its surrounding area.

[0022] Figure 4 yes Figure 3View B.

[0023] Figure 5 This is an explanatory diagram showing the manufacturing process of the chip carrier stage 10.

[0024] Figure 6 This is an explanatory diagram illustrating an example of using the chip carrier stage 10.

[0025] Figure 7 This is a plan view of the chip placement stage 110.

[0026] Figure 8 yes Figure 7 CC section view.

[0027] Figure 9 This is a plan view of the conductive section 130 and its surrounding area.

[0028] Figure 10 yes Figure 9 The D view.

[0029] Figure 11 This is an explanatory diagram showing a variation of the first embodiment.

[0030] Figure 12 This is an explanatory diagram showing a variation of the first embodiment.

[0031] Figure 13 This is an explanatory diagram showing a variation of the first embodiment.

[0032] Figure 14 This is an explanatory diagram of the chip placement stage 310.

[0033] Figure 15 This is an explanatory diagram of the chip placement stage 410.

[0034] Figure 16 This is an explanatory diagram of the 510 chip carrier stage.

[0035] Figure 17 This is an explanatory diagram of the 610 chip carrier stage.

[0036] Figure 18 It is a three-dimensional view of a perforated metal cylindrical body.

[0037] Symbol Explanation

[0038] 10. Wafer stage, 12. Ceramic substrate, 12a. Wafer placement surface, 12b. Back side, 20. Main RF electrode, 20a. Power supply bar, 21. Secondary RF electrode, 21b. Hole, 22. Jumper layer, 22a. Power supply bar, 22b. Hole, 30. Conductor section, 30a. End section, 30b. Wire harness section, 31. Coil, 41. First ceramic molded body, 42. Second ceramic molded body, 42a. Hole, 43. Third ceramic molded body, 44. Stack, 46. Ceramic substrate, 50. Cooling plate, 80. Chamber, 90. Nozzle, 110. Wafer stage, 112. Ceramic substrate, 112a. Wafer placement surface, 112b. Back side, 121. First RF electrode, 121a. Power supply bar, 122. Second RF electrode, 130, 230. Conductor sections. Detailed Implementation

[0039] [First Implementation Method]

[0040] Hereinafter, the first embodiment of the present invention will be described with reference to the accompanying drawings. Figure 1 This is a plan view of the chip stage 10. Figure 2 yes Figure 1 AA section diagram, Figure 3 This is a side view of the conductive part 30 and its surrounding area. Figure 4 yes Figure 3 View B. It should be noted that in this specification, "up" and "down" refer to relative positional relationships rather than absolute positional relationships. Therefore, depending on the orientation of the wafer stage 10, "up" and "down" may become "down" and "up," or "left" and "right," or "front" and "back."

[0041] The wafer stage 10 is a component used for performing CVD, etching, and other processes on wafers using plasma, and it is disposed in a chamber (not shown) used in semiconductor processes. The wafer stage 10 has a main RF electrode 20, a secondary RF electrode 21, a jumper layer 22, and a conductive section 30 inside a ceramic substrate 12.

[0042] The ceramic substrate 12 is a circular plate formed from ceramic materials such as aluminum nitride, silicon carbide, silicon nitride, and aluminum oxide. The ceramic substrate 12 includes a circular wafer mounting surface 12a and a back surface 12b opposite to the wafer mounting surface 12a. Inside the ceramic substrate 12, a circular main RF electrode 20 and an annular secondary RF electrode 21 are arranged concentrically on the same plane. A rectangular jumper layer 22 is provided on a surface inside the ceramic substrate 12 that is different from the plane where the main RF electrode 20 and secondary RF electrode 21 are located. Multiple irregularities (not shown) are formed on the wafer mounting surface 12a by embossing. A heat-conducting gas (e.g., He gas) is supplied from the back surface 12b through a gas supply path (not shown) between the recesses on the wafer mounting surface 12a and the wafer mounted on the wafer mounting surface 12a.

[0043] The main RF electrode 20 is a circular plate electrode concentric with the ceramic substrate 12, and is configured to be opposite to and parallel to the wafer mounting surface 12a. Parallelism includes not only complete parallelism but also parallelism within an acceptable range (e.g., tolerance). The main RF electrode 20 is an electrode whose main component is a high-melting-point composite metal containing two or more of Mo, Nb, W, Ta, their carbides, or a metal mesh, perforated metal, or metal plate. The main component refers to the component with the highest content among the components. When plasma is generated in the space above the central region of the wafer mounted on the wafer mounting surface 12a, an RF voltage is applied between the main RF electrode 20 and the upper electrode (the nozzle 90 described later). The main RF electrode 20 is connected to a power supply rod 20a inserted into the back surface 12b of the ceramic substrate 12. The power supply rod 20a is configured not to contact the jumper layer 22.

[0044] The secondary RF electrode 21 is an annular electrode with an outer diameter larger than that of the primary RF electrode 20 and concentric with the ceramic substrate 12. A gap is provided between the inner periphery of the secondary RF electrode 21 and the outer periphery of the primary RF electrode 20. The secondary RF electrode 21 is formed of a metal mesh, perforated metal, or metal plate made of the same material as the primary RF electrode 20. When plasma is generated in the space above the outer periphery region of the wafer placed on the wafer mounting surface 12a, an RF voltage is applied between the secondary RF electrode 21 and the upper electrode (the nozzle 90 described later).

[0045] The jumper layer 22 is a rectangular and planar conductive layer extending along the diameter of the ceramic substrate 12. The jumper layer 22 is formed of a metal mesh, perforated metal, or metal plate made of the same material as the main RF electrode 20. The jumper layer 22 is connected to a power supply rod 22a inserted into the back surface 12b of the ceramic substrate 12.

[0046] The conductive section 30 is a component that electrically connects the secondary RF electrode 21 and the jumper layer 22, and is provided at two locations on both the secondary RF electrode 21 and the jumper layer 22 when viewed from above. The conductive section 30 is a horizontally placed coil. A horizontally placed coil means that the axis of the coil faces the horizontal direction (the same below). Horizontal means not only completely horizontal, but also horizontal within an acceptable range (e.g., tolerance) (the same below). The conductive section 30 is configured such that the axis of the coil is straight along the extension direction of the jumper layer 22 (here, the diameter direction of the ceramic substrate 12). The coil is formed of a material whose main components are Mo, Nb, W, Ta, their carbides, or high-melting-point composite metals containing two or more of them. The coil can be formed of the same material as the main RF electrode 20, or it can be formed of a different material. The wire diameter of the coil is preferably 0.6 mm or less. Figure 4As shown, the coil is elliptical in shape, with its minor axis coinciding with the distance between the secondary RF electrode 21 and the jumper layer 22. The end portion 30a of the coil constituting the conductive section 30 is located inside the outer diameter of the coil (see reference). Figure 4 ).

[0047] Next, adopt Figure 5 A manufacturing example of the chip carrier stage 10 will be described. Figure 5 This is an explanatory diagram showing the manufacturing process of the chip carrier stage 10.

[0048] First, using ceramic powder with an average particle size of several μm to tens of μm, a first ceramic molded body 41 in the shape of a disc is made, and a jumper layer 22 is formed on one side of it (see reference). Figure 5 (A)). For example, the first ceramic molded body 41 can be obtained by casting. When forming the jumper layer 22, a metal mesh or the like can be placed on the upper surface of the first ceramic molded body 41, or the conductive paste that will become the jumper layer 22 can be printed on the upper surface of the first ceramic molded body 41.

[0049] Next, a second ceramic molded body 42, fabricated in the same manner as the first ceramic molded body 41, is placed on the surface of the first ceramic molded body 41 where the jumper layer 22 is formed, making them integral. Then, using a drill bit, a hole 42a is formed in the second ceramic molded body 42 at the location where the conductive portion 30 is to be provided, reaching the jumper layer 22 (see reference). Figure 5 (B)).

[0050] Next, place the circular or elliptical coil 31 horizontally into the hole 42a (refer to...). Figure 5 (C)). Then, ceramic powder is filled into the gaps of coil 31 to form the main RF electrode 20 and the secondary RF electrode 21 on the upper surface of the second ceramic molded body 42 (see reference). Figure 5 (D)).

[0051] Next, a third ceramic molded body 43, manufactured in the same manner as the first ceramic molded body 41, is placed on the upper surface of the second ceramic molded body 42, integrating them to obtain a laminate 44 (see reference). Figure 5 (E)).

[0052] Next, the laminate 44 is hot-pressed and sintered, thereby sintering the ceramic powder contained in the laminate 44 into a circular ceramic substrate 46 (see reference). Figure 5(F) The horizontally placed coil 31 is compressed along the vertical direction during hot pressing and firing, thus deforming into an ellipse to become the conductive part 30. Because the conductive part 30 is a coil compressed into an ellipse, it comes into strong contact with the secondary RF electrode 21 and the jumper layer 22. Next, the shape of the circular ceramic substrate 46 is processed, and holes are provided for inserting the power supply rods 20a and 22a. The power supply rod 20a is connected to the main RF electrode 20, and the power supply rod 22a is connected to the jumper layer 22. Accordingly, a wafer stage 10 having a ceramic substrate 12 is obtained.

[0053] Next, adopt Figure 6 The following describes an example of the use of the chip carrier stage 10. Figure 6 This is an explanatory diagram illustrating an example of using the chip carrier stage 10.

[0054] After mounting a metal cooling plate 50 on the back side 12b of the ceramic substrate 12, the wafer stage 10 is placed inside the chamber 80. Power supply rods 20a and 22a are electrically insulated from the cooling plate 50. A nozzle 90 is positioned in the chamber 80 opposite the wafer stage 10. A disc-shaped wafer W is placed on the wafer placement surface 12a of the wafer stage 10. In this state, the interior of the chamber 80 is set to a predetermined vacuum atmosphere (or reduced pressure atmosphere), and process gas is supplied from the nozzle 90 while plasma is generated above the wafer W. Specifically, high-frequency power is supplied to the main RF electrode 20 via the power supply rod 20a, and high-frequency power is supplied to the secondary RF electrode 21 independently of the main RF electrode 20 via the power supply rod 22a, jumper layer 22, and conductive portion 30, thereby generating plasma. Because different high-frequency powers (e.g., powers of the same frequency but different wattages, powers of different frequencies but the same wattage, powers of different frequencies and different wattages, etc.) can be supplied to the main RF electrode 20 and the secondary RF electrode 21 respectively, the plasma density on the wafer W placed on the wafer mounting surface 12a can be made uniform. Then, CVD film deposition or etching is performed on the wafer W using this plasma. The temperature of the wafer W can be controlled by adjusting the temperature of the coolant supplied to the coolant passage (not shown) of the cooling plate 50 mounted on the back of the wafer mounting stage 10.

[0055] Here, the correspondence between the constituent elements of this embodiment and the constituent elements of the present invention is clarified. The ceramic substrate 12 of this embodiment corresponds to the ceramic substrate of the present invention, the secondary RF electrode 21 corresponds to the first conductive layer, the jumper layer 22 corresponds to the second conductive layer, and the conductive part 30 corresponds to the conductive part.

[0056] In the wafer stage 10 described above, the conductive section 30 is a horizontally placed coil. Therefore, compared to cases where a zigzag-shaped metal mesh or a vertically placed coil is used as the conductive section, the conductive path of the conductive section 30 is close to the distance between the sub-RF electrode 21 and the jumper layer 22. Specifically, the conductive path of the conductive section 30 is a roughly semi-elliptical path (see reference). Figure 4 (The double-dotted line). Therefore, it is possible to suppress heat generation in the conductive part 30, thereby improving the heat uniformity of the chip.

[0057] Furthermore, the same ceramic material as the ceramic substrate 12 enters the internal space of the coil constituting the conductive part 30, thus reducing the density deviation of the ceramic substrate 12 and increasing its strength.

[0058] Furthermore, the coil constituting the conductive section 30 is an elliptical coil. During the manufacturing process, a force in the compression direction is applied from above and below the horizontally placed circular or elliptical coil, at which time the coil absorbs the force and becomes elliptical.

[0059] Furthermore, the jumper layer 22 is a rectangular conductive layer that intersects with the secondary RF electrode 21 when viewed from above, and the axis of the coil constituting the conductive part 30 is a straight line along the extending direction of the jumper layer 22. Therefore, the length of the horizontally placed coil can be relatively long, making it easier to ensure the conduction between the secondary RF electrode 21 and the jumper layer 22.

[0060] [Second Implementation]

[0061] Hereinafter, the second embodiment of the present invention will be described with reference to the accompanying drawings. Figure 7 This is a plan view of the chip stage 110. Figure 8 yes Figure 7 CC section diagram, Figure 9 This is a plan view of the conductive section 130 and its surrounding area. Figure 10 yes Figure 9 The D view.

[0062] The wafer stage 110 is a component used for performing CVD, etching, and other processes on wafers using plasma, and it is disposed in a chamber (not shown) used in semiconductor processes. The wafer stage 110 has a first RF electrode 121, a second RF electrode 122, and a conductive section 130 inside a ceramic substrate 112.

[0063] The ceramic substrate 112 is a circular plate formed of ceramic materials such as aluminum nitride, silicon carbide, silicon nitride, and aluminum oxide. The ceramic substrate 112 includes a circular wafer mounting surface 112a and a back surface 112b opposite to the wafer mounting surface 112a. Inside the ceramic substrate 112, a first RF electrode 121 and a second RF electrode 122 are sequentially implanted parallel to the wafer mounting surface 112a from the side closest to it. Multiple irregularities (not shown) are formed on the wafer mounting surface 112a by embossing. A heat-conducting gas (e.g., He gas) is supplied from the back surface 112b through a gas supply path (not shown) between the recesses on the wafer mounting surface 112a and the wafer mounted on the wafer mounting surface 112a.

[0064] The first RF electrode 121 is a circular plate electrode concentric with the ceramic substrate 112 and is positioned opposite the wafer mounting surface 112a. The first RF electrode 121 is an electrode primarily composed of Mo, Nb, W, Ta, their carbides, or high-melting-point composite metals containing two or more of these elements, and is formed from a metal mesh, perforated metal, or metal plate. When plasma is generated in the space above the central region of the wafer mounted on the wafer mounting surface 112a, an RF voltage is applied between the first RF electrode 121 and an upper electrode (not shown). The first RF electrode 121 is connected to a power supply rod 121a inserted into the back surface 112b of the ceramic substrate 112.

[0065] The second RF electrode 122 is an annular electrode with an outer diameter larger than that of the first RF electrode 121 and concentric with the ceramic substrate 112. The second RF electrode 122 is formed of a metal mesh, perforated metal, or metal plate made of the same material as the first RF electrode 121. The second RF electrode 122 is positioned to overlap with the first RF electrode 121 when viewed from above. When plasma is generated in the space above the outer peripheral region of the wafer placed on the wafer mounting surface 112a, an RF voltage is applied between the second RF electrode 122 and an upper electrode (not shown).

[0066] The conductive portion 130 is a component that electrically connects the first RF electrode 121 and the second RF electrode 122, and is provided at multiple locations in the overlapping portions of the first RF electrode 121 and the second RF electrode 122 when viewed from above. Here, as... Figure 7 As shown, multiple conductive portions 130 (here, eight) are arranged at equal intervals along the circumference of the wafer stage 10. Each conductive portion 130 is a horizontally placed coil. The conductive portion 130 is configured such that the axis of the coil is arc-shaped (here, an arc-shaped circle concentric with the second RF electrode 122). The coil is formed of the same material as the first RF electrode 121. The wire diameter of the coil is preferably 0.6 mm or less. Figure 8As shown, the coil is elliptical in shape, and its minor axis is the same as the distance between the first RF electrode 121 and the second RF electrode 122.

[0067] The manufacturing and usage examples of the wafer stage 110 are described in the same way as the manufacturing and usage examples of the wafer stage 10, therefore, their descriptions are omitted here.

[0068] Here, the correspondence between the constituent elements of this embodiment and the constituent elements of the present invention is clarified. The ceramic substrate 112 of this embodiment corresponds to the ceramic substrate of the present invention, the first RF electrode 121 corresponds to the first conductive layer, the second RF electrode 122 corresponds to the second conductive layer, and the conductive part 130 corresponds to the conductive part.

[0069] In the wafer stage 110 described above, the conductive section 130 is a horizontally placed coil. Therefore, compared to cases where a zigzag-shaped metal mesh or a vertically placed coil is used as the conductive section, the conductive path of the conductive section 130 is close to the distance between the first RF electrode 121 and the second RF electrode 122. Specifically, the conductive path of the conductive section 130 is a roughly semi-elliptical path (see reference). Figure 10 (The double-dotted line). Therefore, it is possible to suppress heat generation in the conductive part 130, thereby improving the heat uniformity of the chip.

[0070] In addition, the same ceramic material as the ceramic substrate 112 enters the internal space of the coil constituting the conductive part 130, so the density deviation of the ceramic substrate 112 becomes smaller and the strength is improved.

[0071] Furthermore, the coil constituting the conductive section 130 is an elliptical coil. In the manufacturing process, a force in the compression direction is applied from above and below the horizontally placed circular or elliptical coil, at which time the coil absorbs the force and becomes elliptical.

[0072] Furthermore, the second RF electrode 122 is a ring-shaped conductive layer that repeats the shape of the first RF electrode 121 when viewed from above, and the axis of the coil constituting the conductive portion 130 is an arc concentric with the ring-shaped second RF electrode 122. Therefore, the length of the horizontally placed coil can be relatively long, making it easier to ensure the conduction between the first RF electrode 121 and the second RF electrode 122.

[0073] It should be noted that the present invention is not limited to any of the above embodiments. Of course, as long as it falls within the technical scope of the present invention, it can be implemented in various ways.

[0074] In the first embodiment described above, as Figure 11As shown, a hole 21b extending along the thickness direction can be provided in the sub-RF electrode 21, which serves as the first conductive layer, and a hole 22b extending along the thickness direction can be provided in the jumper layer 22, which serves as the second conductive layer. The coil constituting the conductive portion 30 enters the holes 21b and 22b, so that the inner surfaces of the holes 21b and 22b contact the side surface of the coil. Accordingly, compared with the case where the coil constituting the conductive portion 30 makes point contact with the sub-RF electrode 21 and the jumper layer 22, the contact area is increased, and thus, it is easier to ensure conduction. It should be noted that the hole can be provided in either the sub-RF electrode 21 or the jumper layer 22. In addition, the above-mentioned hole can also be provided in the second embodiment.

[0075] In the first and second embodiments described above, an elliptical coil was used; however, a circular coil or a polygonal coil may also be used. When using a polygonal coil, it is preferable to have at least one corner of the polygon disposed between the first conductive layer and the second conductive layer, and more preferably, two or more corners. Figure 12 This is an example in the first embodiment where a hexagonal coil is used as the conducting part 230. Figure 12 In the middle, two corners are arranged between the secondary RF electrode 21 (first conductive layer) and the jumper layer 22 (second conductive layer).

[0076] In the first embodiment described above, a jumper layer 22 is used; however, it can be as follows: Figure 13 The jumper layer 22 is replaced by a wire bundle portion 30b, which is obtained by stretching the end portion of the coil constituting the conducting portion 30 in a manner parallel to the surface of the secondary RF electrode 21.

[0077] In the first embodiment described above, the annular secondary RF electrode 21, which serves as the first conductive layer, and the rectangular jumper layer 22, which serves as the second conductive layer, are connected by a conductive section 30. In the second embodiment, the circular first RF electrode 121, which serves as the first conductive layer, and the annular second RF electrode 122, which serves as the second conductive layer, are connected by a conductive section 130. However, the shapes of the first conductive layer and the second conductive layer are not particularly limited to the shapes described above, and various shapes can be used.

[0078] In the first embodiment described above, an example is illustrated where the first conductive layer is an RF electrode and the second conductive layer is a jumper layer, but this is not particularly limiting. For example, the first conductive layer may be an electrostatic electrode and the second conductive layer may be a jumper layer, or the first conductive layer may be a heater electrode (resistive heating element) and the second conductive layer may be a jumper layer. Furthermore, in the second embodiment described above, an example is illustrated where both the first and second conductive layers are RF electrodes, but this is not particularly limiting. For example, both the first and second conductive layers may be electrostatic electrodes, or both may be heater electrodes.

[0079] In the first embodiment described above, a ceramic molded body was produced using a casting method, but this is not a particular limitation. For example, a ceramic molded body obtained by pressing ceramic powder can be used, a ceramic molded body produced by a casting method can be used, and combinations of these methods can also be employed.

[0080] In the first and second embodiments described above, a step for mounting the focusing ring can be provided on the outer periphery of the upper surface of the ceramic substrates 12 and 112. The focusing ring has the functions of stabilizing plasma generation up to the outer periphery of the wafer and protecting the surface of the wafer mounting stage.

[0081] In addition to the first and second embodiments described above, as preferred embodiments in which the present invention is applied, examples are shown. Figures 14-17 The chip carrier stages are 310, 410, 510, and 610.

[0082] Figure 14 This is an explanatory diagram of the chip placement stage 310. Figure 14 (A) is a floor plan. Figure 14 (B) is the EE cross-sectional view. Figure 14 (C)~ Figure 14 (E) is a cross-sectional view of the wafer stage 310 when it is horizontally cut along the first conductive layer 321, the conductive portion 330, and the second conductive layer 322. The wafer stage 310 is a unipolar electrostatic chuck and has a ceramic substrate 312 with a wafer placement surface 312a. The ceramic substrate 312 is in the shape of a circular plate, and a stepped surface 312b is provided on the outer periphery of its upper surface. The first conductive layer 321 is a circular electrostatic electrode implanted in the ceramic substrate 312. A power supply rod 321a is connected to the lower surface of the center of the first conductive layer 321. The second conductive layer 322 is an annular electrostatic electrode implanted at a different height from the first conductive layer 321. The conductive portion 330 is a horizontally placed coil with a circular (or elliptical) cross-section, which electrically connects the first conductive layer 321 and the second conductive layer 322. The conductive portion 330 is an annular component formed by connecting the coils in an endless manner, and is arranged concentrically with the second conductive layer 322. When DC power is supplied to the power supply bar 321a of the wafer stage 310, DC voltage is simultaneously applied to the first conductive layer 321 and the second conductive layer 322.

[0083] Figure 15 This is an explanatory diagram of the chip placement stage 410. Figure 15 (A) is a floor plan. Figure 15 (B) is the FF cross-sectional view. Figure 15 (C)~ Figure 15(E) is a cross-sectional view of the wafer stage 410 when it is horizontally cut along the first conductive layers 421, 423, the conductive portions 430, 432, and the second conductive layers 422, 424. The wafer stage 410 is a bipolar electrostatic chuck and includes a ceramic substrate 412 with a wafer placement surface 412a. The ceramic substrate 412 is in the shape of a circular plate, and a stepped surface 412b is provided on the outer periphery of its upper surface. The first conductive layers 421 and 423 are semi-circular (fan-shaped) electrostatic electrodes separately embedded in the ceramic substrate 412. A power supply rod 421a is connected to the lower surface of the first conductive layer 421, and a power supply rod 423a is connected to the lower surface of the first conductive layer 423. The second conductive layers 422 and 424 are semi-circular (fan-shaped) electrostatic electrodes separately embedded at different heights from the first conductive layers 421 and 423. The conductive portion 430 is a horizontally placed coil that electrically connects the first conductive layer 421 and the second conductive layer 422. The conductive portion 432 is a horizontally placed coil that electrically connects the first conductive layer 423 and the second conductive layer 424. The conductive portions 430 and 432 are coils with a circular (or elliptical) cross-section and an arc-shaped axis, arranged concentrically with the second conductive layers 422 and 424. If the power supply rod 421a of the wafer stage 410 is connected to the positive terminal and the power supply rod 423a is connected to the negative terminal, then the first conductive layer 421 and the second conductive layer 422 become the positive terminals, and the first conductive layer 423 and the second conductive layer 424 become the negative terminals.

[0084] Figure 16 This is an explanatory diagram of the 510 chip carrier stage. Figure 16 (A) is a floor plan. Figure 16 (B) is the cross-sectional view of GG. Figure 16 (C)~ Figure 16(E) is a cross-sectional view of the wafer stage 510 when horizontally cut along the comb electrodes 521, 523, the conductive portion 530, and the conductive layer 522. The wafer stage 510 is a bipolar electrostatic chuck and includes a ceramic substrate 512 with a wafer placement surface 512a. The ceramic substrate 512 is in the shape of a circular plate, with a stepped surface 512b on the outer periphery of its upper surface. The bipolar comb electrodes 521 and 523 are a pair of electrostatic electrodes separately embedded in the ceramic substrate 512. A power supply rod 521a is connected to the lower surface of the comb electrode 521, and a power supply rod 523a is connected to the lower surface of the comb electrode 523. The conductive layer 522 is an annular electrostatic electrode embedded at a different height from the comb electrodes 521 and 523. The conductive portion 530 is a horizontally placed coil that electrically connects the comb electrode 521 (first conductive layer) and the conductive layer 522 (second conductive layer). The conductive part 530 is a coil with a circular (or elliptical) cross-section and an arc-shaped axis, and is arranged concentrically with the conductive layer 522. If the power supply rod 521a of the wafer stage 510 is connected to the positive terminal and the power supply rod 523a is connected to the negative terminal, then the comb electrode 521 and the conductive layer 522 become the positive terminal, and the comb electrode 523 becomes the negative terminal.

[0085] Figure 17 This is an explanatory diagram of the 610 chip carrier stage. Figure 17 (A) is a floor plan. Figure 17 (B) is the HH cross-sectional view. Figure 17 (C)~ Figure 17 (E) is a cross-sectional view of the wafer stage 610 when horizontally cut across the upper conductive layers 621, 623, conductive portions 630, 632, and lower conductive layer 622. The wafer stage 610 is a bipolar electrostatic chuck and includes a ceramic substrate 612 with a wafer placement surface 612a. The ceramic substrate 612 is circular, with a stepped surface 612b on the outer periphery of its upper surface. The upper conductive layers 621 and 623 are electrostatic electrodes separately embedded in the ceramic substrate 612; the upper conductive layer 621 is annular, and the upper conductive layer 623 is circular. A power supply rod 623a is connected to the lower surface of the circular upper conductive layer 623. The lower conductive layer 622 is an annular electrostatic electrode embedded at a different height from the upper conductive layers 621 and 623, and a power supply rod 622a is connected to its lower surface. Two conductive sections 630 and 632 are horizontally placed coils that electrically connect the annular upper conductive layer 621 (first conductive layer) and the circular lower conductive layer 622 (second conductive layer). The conductive section 630 is a coil with an arc-shaped axis and a circular (or elliptical) cross-section, arranged concentrically with the lower conductive layer 622. If the power supply rod 622a on the wafer stage 610 is connected to the positive terminal and the power supply rod 623a is connected to the negative terminal, then the upper conductive layer 621 and the lower conductive layer 622 become the positive terminals, and the upper conductive layer 623 becomes the negative terminal.

[0086] The first and second embodiments described above, Figures 14-17 In the illustrated embodiment, a horizontally placed coil is used as the conductive part; however, a horizontally placed perforated cylindrical body can also be used as the conductive part. The perforated cylindrical body is configured such that a hole is provided on the side of the conductive cylindrical body. Examples of perforated cylindrical bodies include, for instance, a perforated metal cylindrical body (see reference). Figure 18 Examples of materials used include metal mesh cylinders, etc. For perforated cylinders, the ceramic matrix material can enter the interior through the side holes. Similar to coils, materials primarily composed of Mo, Nb, W, Ta, their carbides, or high-melting-point composite metals containing two or more of these can be used as materials for the perforated cylinder. Even when a horizontally placed perforated cylinder is used instead of a horizontally placed coil, the same effect as when using a coil is achieved.

Claims

1. A wafer mounting stage, wherein, Inside a ceramic substrate having a wafer mounting surface, a first conductive layer and a second conductive layer are implanted at different heights, and a conductive portion is provided to electrically connect the first conductive layer and the second conductive layer. The wafer stage is characterized in that... The conductive part is a horizontally placed coil or a perforated cylindrical body. The material of the ceramic matrix enters the internal space of the conductive part.

2. The wafer stage according to claim 1, characterized in that, The cross-sectional shape of the conductive part is circular or elliptical.

3. The wafer stage according to claim 1 or 2, characterized in that, The conductive part is a coil. At least one of the first conductive layer and the second conductive layer has a hole extending along the thickness direction, through which the coil enters, such that the inner surface of the hole contacts the side surface of the coil.

4. The wafer stage according to any one of claims 1 to 3, characterized in that, The second conductive layer is a linear or rectangular conductive layer that intersects with the first conductive layer when viewed from above. The axis of the conductive part is a straight line along the extension direction of the second conductive layer.

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