Chip packaging structure in multi-project wafer, packaging method and chip finished product

Abstract

The invention discloses a chip packaging structure in a multi-project wafer, a packaging method and a chip finished product, which are applied to the field of semiconductor packaging and are characterized in that the front surface of the multi-project wafer is in bonding connection with a bonding carrier; a cofferdam structure is arranged on the surface of the bonding carrier and comprises a first cofferdam part and a second cofferdam part; the back surface of the multi-project wafer is provided with a cutting channel; a plurality of first cofferdam parts are arranged on the surface of the bonding carrier, each chip is arranged in an area defined by the corresponding first cofferdam part, and all the first cofferdam parts are the same in shape and size; a second cofferdam part corresponding to at least part of the chip is formed on the surface of the bonding carrier; the second cofferdam part is located in the first cofferdam part, so that the shape and the size of each area defined by the combination of the first cofferdam part and the second cofferdam part are matched with those of the corresponding chips. The first cofferdam part forms the same cofferdam boundary at different chips, and the second cofferdam part fills the gap between the small-size chip and the first cofferdam part, so that the convenience of the subsequent process is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging, and in particular to a chip packaging structure, packaging method, and finished chip product in a multi-project wafer. Background Technology

[0002] Traditional MPW (Multi-Project Wafer) technology solves the cost problem of front-end wafer manufacturing by integrating multiple chip designs on a single wafer. However, after tape-out, these different chip designs typically need to be diced into individual dies for separate packaging. For MPWs containing dozens or even hundreds of different designs, traditional single-die packaging is cumbersome, requiring different packaging solutions, tools, and materials for each chip, resulting in extremely long lead times and low overall packaging efficiency. It fails to capitalize on the cost advantages of fabricating multiple chip types on the same wafer. Furthermore, the independent packaging and testing processes cause the costs of R&D, testing, and reliability verification to increase linearly with the number of chip types, partially offsetting the cost advantages of MPW in front-end manufacturing and complicating subsequent chip testing processes.

[0003] Therefore, how to provide a structure that can simultaneously package chips in multiple project wafers is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a chip packaging structure, packaging method and chip product in multi-project wafers, which solves the problem that the complex testing process of multi-project wafers in the prior art offsets the cost advantage brought by MPW in the front-end manufacturing.

[0005] To address the aforementioned technical problems, this invention provides a chip packaging structure in a multi-project wafer, comprising:

[0006] A bonding carrier and a multi-project wafer; the front surface of the multi-project wafer is bonded to the bonding carrier; the bonding carrier has a dam structure on the surface of the multi-project wafer, the dam structure including a first dam portion and a second dam portion; the back surface of the multi-project wafer has a dicing channel.

[0007] The bonding carrier surface is provided with a plurality of first dam portions, and each chip is placed in the area enclosed by the corresponding first dam portion, and all the first dam portions have the same shape and size;

[0008] The bonding carrier surface has a second dam formed on at least a portion of the chips in the multi-project wafer; the second dam is located inside the first dam, so that the shape and size of each region enclosed by the combination of the first dam and the second dam match the corresponding chip.

[0009] Optionally, the shape and size of the area enclosed by the first dike portion match the largest chip size in the multi-project wafer;

[0010] The shape and size of the area jointly enclosed by the first and second cofferdams correspond to and match the non-maximum size chip in the multi-project wafer.

[0011] Optionally, the dicing channels are arranged along the contour of the largest chip in the multi-project wafer, and the spacing between adjacent dicing channels is the same;

[0012] If there are multiple chips within the same cutting area defined by the cutting channel, an additional cutting channel is provided between adjacent chips.

[0013] Optionally, the multi-project wafer is provided with TSV vias, and the wafer electrodes are connected to the back surface of the multi-project wafer through the TSV vias using a fan-in rewiring connection structure.

[0014] Optionally, when multiple chips are placed within the area enclosed by the first dike portion, at least a portion of the second dike portion is disposed between adjacent chips to separate them.

[0015] The present invention also provides a chip packaging method in a multi-project wafer for fabricating a chip packaging structure as described above, comprising:

[0016] Provide the multi-project wafer and the bonding carrier;

[0017] The front surface of the multi-project wafer is bonded to the bonding carrier so that the chip is placed within the corresponding dike structure.

[0018] Optionally, after bonding the front surface of the multi-project wafer to the bonding carrier to place the chip within the corresponding dike structure, the method further includes:

[0019] TSV vias are etched on the back surface of the multi-project wafer after bonding, and conductive structures are formed within the TSV vias to connect the wafer electrodes to the back surface of the multi-project wafer.

[0020] Optional, including:

[0021] TSV vias are fabricated by etching on the back surface of the multi-project wafer after bonding is completed until the wafer electrodes are exposed, thus obtaining the first structure to be processed.

[0022] A first insulating layer is prepared on the back surface of the first structure to be processed, and the first insulating layer covering the wafer electrode is removed to expose at least part of the wafer electrode, thereby obtaining the second structure to be processed.

[0023] A redistribution layer is prepared on the back surface of the second structure to be processed to connect the wafer electrode to the back surface of the multi-project wafer.

[0024] Optional, including:

[0025] TSV vias are etched on the back surface of the multi-project wafer after bonding, and dicing channels are formed on the back surface of the multi-project wafer. Conductive structures are formed within the TSV vias to connect the wafer electrodes to the back surface of the multi-project wafer. The dicing channels are arranged along the contour of the largest chip in the multi-project wafer, and the spacing between adjacent dicing channels is the same. If there are multiple chips in the same dicing area defined by the dicing channels, an additional dicing channel is provided between adjacent chips.

[0026] The present invention also provides a finished chip product, which is a finished chip product cut along the dicing track in the chip packaging structure of the above-mentioned multi-project wafer.

[0027] As can be seen, the chip packaging structure in a multi-project wafer provided by the present invention includes a bonding carrier and a multi-project wafer; the front surface of the multi-project wafer is bonded to the bonding carrier; a dam structure is provided on the surface of the bonding carrier facing the multi-project wafer, the dam structure including a first dam portion and a second dam portion; a dicing channel is provided on the back surface of the multi-project wafer; a plurality of first dam portions are provided on the surface of the bonding carrier, each chip is placed in the area enclosed by the corresponding first dam portion, and all first dam portions have the same shape and size; a second dam portion is formed on the surface of the bonding carrier corresponding to at least some chips in the multi-project wafer; the second dam portion is located inside the first dam portion, so that the shape and size of each area enclosed by the combination of the first dam portion and the second dam portion match the corresponding chip. This invention utilizes a combination of a first cofferdam and a second cofferdam to correspond to the chip arrangement. The first cofferdam forms the same cofferdam boundary at different chips, and the second cofferdam fills the gap between the small-sized chip and the first cofferdam, thereby strengthening the support for the wafer at the small-sized chip, improving the regularity of the packaging structure, enabling simultaneous packaging of chips in multiple project wafers, improving the regularity of the chips after dicing, and enhancing the convenience of subsequent processes.

[0028] In addition, the present invention also provides a chip packaging method and a finished chip product in a multi-project wafer, which also have the above-mentioned beneficial effects. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of a chip packaging structure in a multi-project wafer provided by an embodiment of the present invention;

[0031] Figure 2 This is a schematic diagram of a cofferdam structure provided in an embodiment of the present invention;

[0032] Figure 3 This is a schematic diagram of a multi-project wafer structure provided in an embodiment of the present invention;

[0033] Figure 4 This is a schematic diagram of the structure of a bonding carrier provided in an embodiment of the present invention;

[0034] Figure 5 This is a cross-sectional view of a chip packaging structure in a multi-project wafer, provided as an embodiment of the present invention.

[0035] Figure 6 A schematic diagram of a chip packaging structure with TSV vias fabricated on the back surface of a multi-project wafer, provided in an embodiment of the present invention;

[0036] Figure 7 A cross-sectional view of a chip packaging structure with TSV vias fabricated on the back surface of a multi-project wafer, provided in an embodiment of the present invention.

[0037] Figure 8 This is a schematic diagram of a chip packaging structure in which a first insulating layer is fabricated on the back surface of a multi-project wafer, according to an embodiment of the present invention.

[0038] Figure 9 A cross-sectional view of a chip packaging structure with a first insulating layer fabricated on the back surface of a multi-project wafer, provided in an embodiment of the present invention.

[0039] Figure 10 This is a schematic diagram of a chip packaging structure with a rewiring connection structure fabricated on the back surface of a multi-project wafer, provided in an embodiment of the present invention.

[0040] Figure 11A cross-sectional view of a chip packaging structure with a rewiring connection structure fabricated on the back surface of a multi-project wafer, provided in an embodiment of the present invention.

[0041] Figure 12 A cross-sectional view of a chip packaging structure with solder balls fabricated on the back surface of a multi-project wafer, provided in an embodiment of the present invention.

[0042] Figure 13 A flowchart of a chip packaging method in a multi-project wafer is provided as an embodiment of the present invention;

[0043] Figure 14 This is a schematic diagram of the structure of a finished chip product provided in an embodiment of the present invention;

[0044] The annotations in the attached figures are explained as follows:

[0045] 1- Bonding surface, 2- A-chip bonding cavity, 3- B-chip bonding cavity, 4- Multi-project wafer, 401- Wafer thinning removal line, 402- Back surface of multi-project wafer, 5- A-chip, 501- A-chip TSV via, 502- A-chip redistribution, 503- Finished A-chip, 6- B-chip, 601- B-chip TSV via, 602- B-chip redistribution, 603- Finished B-chip, 7- Bond and carrier, 8- Area enclosed by the dam structure corresponding to the A-chip, 9- Area enclosed by the dam structure corresponding to the B-chip, 10- Dam structure, 11- First dam section 11, 12- Second dam section 12, 20- Protective film, 30- Bond and material, 40- Chip, 50- Wafer electrode, 51- Redistribution layer, 52- Solder ball, 60- Redistribution dicing, 70- TSV via, 71- TSV slot, 72- TSV opening, 80 - first insulating layer, 90 - second insulating layer. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0047] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a chip packaging structure in a multi-project wafer according to an embodiment of the present invention. The chip packaging structure in the multi-project wafer 4 may include:

[0048] A bonding carrier and a multi-project wafer 4; the front surface of the multi-project wafer 4 is bonded to the bonding carrier; a dam structure 10 is provided on the surface of the bonding carrier facing the multi-project wafer 4, the dam structure 10 including a first dam portion 11 and a second dam portion 12; a dicing channel is provided on the back surface 402 of the multi-project wafer.

[0049] The bonding carrier surface is provided with a plurality of first dam portions 11, and each chip 40 is placed in the area enclosed by the corresponding first dam portion 11, and all the first dam portions 11 have the same shape and size.

[0050] The bonding carrier surface corresponds to at least a portion of the chips 40 in the multi-project wafer 4 having a second dam portion 12; the second dam portion 12 is located within the first dam portion 11, so that the shape and size of each region enclosed by the combination of the first dam portion 11 and the second dam portion 12 match the corresponding chip 40.

[0051] In this embodiment, the multi-project wafer 4 designs multiple chips 40 on a single wafer, meaning that one wafer can produce multiple designed chip 40s, reducing manufacturing costs and improving manufacturing efficiency. Furthermore, the packaging structure in this embodiment matches the front-end processes, enabling the packaging of multiple chips 40 at once. This reduces R&D, testing, and reliability costs, and the production of multiple finished chip products in a single step saves packaging time and improves manufacturing efficiency. In this embodiment, as... Figure 1 The bonding surface 1 is the contact surface formed when the bond and carrier 7 is bonded to the multi-project wafer 4. Since the surface of the bond and carrier 7 is provided with a dam structure 10, a cavity is formed within the area enclosed by the dam structure 10 to accommodate the chip 40. Figure 1 Taking a multi-project wafer 4 containing two types of chips 40 as an example, a dam structure 10 is formed at the rebonding surface 1, and the resulting cavity includes a bonding cavity 2 for chip A and a bonding cavity 3 for chip B.

[0052] In this embodiment, the function of the dam structure 10 is to form a sealed cavity between the front side of the wafer and the bond and carrier 7 when the bond and carrier 7 are bonded to the multi-project wafer 4. This protects the chip functional areas from mechanical and chemical damage during subsequent back-side processes, such as substrate thinning and etching. The substrate thinning process can remove the substrate portion to be removed along the wafer thinning removal line 401. The material can be photoresist, which can be fabricated through patterning processes such as coating, exposure, and development. The first dam portion 11 and the second dam portion 12 in this embodiment can be referenced... Figure 2 , Figure 2 This is a schematic diagram of a cofferdam structure provided in an embodiment of the present invention. The first cofferdam portion 11 forms the overall framework of the cofferdam structure 10, while the second cofferdam portion 12 is disposed within the first cofferdam portion 11, realizing the graphical representation of the cofferdam structure 10. The multi-project wafer in this embodiment can be referenced... Figure 3 ,Figure 3 This is a schematic diagram of a multi-project wafer structure provided in an embodiment of the present invention. Figure 3 The explanation will also use an example with two types of chips 40, namely chip A 5 and chip B 6. The keys and carriers mentioned above can be found in [reference needed]. Figure 4 , Figure 4 This is a schematic diagram of a bonding carrier structure provided in an embodiment of the present invention. The dam structure corresponds to region 8 enclosed by chip A and region 9 enclosed by chip B, respectively, and is used to accommodate chip A 5 and chip B 6. The structure of the multi-project wafer 4 bonded to the bonding carrier 7 in this embodiment can be referred to... Figure 5 , Figure 5 This is a cross-sectional view of a chip packaging structure in a multi-project wafer according to an embodiment of the present invention. In this embodiment, a protective film 20 can be prepared on the side of the bond and carrier 7 facing away from the multi-project wafer 4 to prevent damage to the bond and carrier 7 in subsequent processes. Specifically, the protective film 20 can be a polishing-type BG film. Furthermore, at the bond and carrier 7 and the multi-project wafer 4, a bond material 30 needs to be provided to ensure a complete bonding connection.

[0053] In this embodiment, the first cofferdam 11 mainly implements standardized packaging units, while the second cofferdam 12 mainly provides protection for differentiated chips 40. The first cofferdam 11 defines the external boundary of the final package. All first cofferdams 11 have the same shape and size, meaning that the external specifications of all packaging units are unified, with the aim of standardizing subsequent testing and mounting. The second cofferdam 12 is an adaptive structure that fills the internal space of the unified first cofferdam 11, forming a sealed cavity of just the right size for the smaller chip 40. This ensures that even small chips are adequately protected, preventing the large suspended silicon wafer above them from cracking due to insufficient strength after thinning. In other words, the first cofferdam 11 provides system-level support and shape definition, while the second cofferdam 12 provides chip-level adaptive protection. The combination of the two solves the problem of high packaging difficulty caused by the different sizes of chips 40 on multiple wafers 4.

[0054] Furthermore, in this embodiment, the bonding carrier is preferably a glass or silicon substrate, and the dam structure 10 can be formed by processes such as photoresist coating, exposure, and development. The area enclosed by the first dam portion 11 constitutes a standard packaging unit area, the size of which is at least larger than the largest chip 40 on the wafer. A standard packaging area can be preset. For chips 40 whose size is smaller than this standard packaging area, a second dam portion 12 is added within the corresponding standard packaging area to form a sealed cavity that matches the size of the current chip 40 and is smaller than the standard packaging area.

[0055] Furthermore, in order to improve the regularity of the outer contour of the packaging unit while ensuring the mechanical strength of the package, the shape and size of the area enclosed by the first dam 11 can be set to match the largest chip 40 in the multi-project wafer 4.

[0056] The shape and size of the area enclosed by the first cofferdam 11 and the second cofferdam 12 correspond to and match the non-maximum size chip 40 in the multi-project wafer 4.

[0057] In this embodiment, the cofferdam structure 10 is set with the largest chip 40 as the reference to determine the standard size of the package, maximize the use of the wafer area, and ensure the mechanical strength of the package. The external dimensions of all package units are unified to match the largest chip 40, avoiding the problem that subsequent testing and other processes need to be adapted to different chip 40 package structures due to different package sizes, thereby increasing the packaging complexity. At the same time, the second cofferdam 12 adapts to chips 40 of various sizes, ensuring the safety of small chips in the process and achieving a balance between strength and compatibility.

[0058] Furthermore, in order to balance the regularity of the outer contour of the packaging unit and ensure that each chip 40 is individually cut into single items, the cutting path can be set along the contour of the largest chip 40 in the multi-project wafer 4, and the spacing between adjacent cutting paths is the same.

[0059] If there are multiple chips 40 within the same cutting area defined by the cutting channel, an additional cutting channel is set between adjacent chips 40.

[0060] In this embodiment, the outline of the largest chip 40 is used as a reference to determine the standard size of the final package. The actual path of the dicing track is replanned and photolithographically defined on the wafer based on this standard size, rather than simply tracing the edge of the original chip 40. Each chip package structure only needs to be individually cut to form the finished product. In this embodiment, both the dicing track and the addition of dicing tracks can be referenced. Figure 6 , Figure 6 This is a schematic diagram of a chip packaging structure with TSV vias fabricated on the back surface of a multi-project wafer, provided as an embodiment of the present invention. The redistribution dicing track 60 includes dicing tracks and additional dicing tracks, to... Figure 6 For example, the redistributed cutting channel 60 set around chip A 5 is called the cutting channel, and the additional redistributed cutting channel 60 added between adjacent chip B 6 is called the additional cutting channel.

[0061] Furthermore, to achieve interconnection between chip 40 in multi-project wafer 4 and external leads, reference can be made to... Figure 6 , Figure 6This is a schematic diagram of a chip packaging structure with TSV vias fabricated on the back surface of a multi-project wafer, as provided in an embodiment of the present invention. The multi-project wafer 4 may be provided with TSV vias 70, and wafer electrodes 50 are connected to the back surface 402 of the multi-project wafer via the TSV vias 70 using a fan-in rewiring connection structure.

[0062] In this embodiment, the TSV via 70 can be a via or deep trench formed by dry etching after thinning the back side of the wafer to expose the wafer electrode 50 on the front side. The fan-in redistribution connection structure includes an insulating layer for isolation and protection, and a redistribution layer 51, which can be formed by sputtering, electroplating, or other processes to reconnect the electrodes exposed by the TSV via 70 to the planned pad positions on the back side of the wafer. In this embodiment, the pad metal layer at the end of the redistribution layer 51 is used to connect solder balls 52 for external connection. The TSV via 501 of chip A and the TSV via 601 of chip B are as follows... Figure 6 As shown. Figure 7 As shown, Figure 7 This is a cross-sectional view of a chip packaging structure with TSV vias fabricated on the back surface of a multi-project wafer, provided as an embodiment of the present invention. The TSV vias 70 are fabricated by first creating a slot and then an opening, wherein the TSV slots 71 and TSV openings 72 are as follows... Figure 7 As shown.

[0063] In this embodiment, the TSV via 70 can be formed using a deep reactive ion etching process. The fan-in redistribution structure can be referenced. Figure 8 , Figure 9 , Figure 10 and Figure 11 , Figure 8 This is a schematic diagram of a chip packaging structure in which a first insulating layer is fabricated on the back surface of a multi-project wafer, according to an embodiment of the present invention. Figure 9 A cross-sectional view of a chip packaging structure with a first insulating layer fabricated on the back surface of a multi-project wafer, provided in an embodiment of the present invention. Figure 10 This is a schematic diagram of a chip packaging structure with a rewiring connection structure fabricated on the back surface of a multi-project wafer, provided in an embodiment of the present invention. Figure 11This is a cross-sectional view of a chip package structure with a redistribution connection structure fabricated on the back surface of a multi-project wafer, as provided in an embodiment of the present invention. It may include: a first insulating layer 80 covering the back surface of the wafer, the first insulating layer 80 having openings at TSV vias 70 to expose wafer electrodes 50. In this embodiment, taking a multi-project wafer 4 with two types of chips 40 as an example, the aforementioned TSV vias 70 may include A-chip TSV via 501 and B-chip TSV via 601; a redistribution layer 51 formed on the first insulating layer 80, which can also be described using two types of chips 40 as an example, i.e., including A-chip redistribution 502 and B-chip redistribution 602. The redistribution layer 51 electrically connects the TSV vias 70 to preset pad positions; a second insulating layer 90 covering the redistribution layer 51, the second insulating layer 90 having openings corresponding to the pad positions; and solder balls 52 formed at the openings, the solder balls being referenced... Figure 12 , Figure 12 This is a cross-sectional view of a chip packaging structure with solder balls fabricated on the back surface of a multi-project wafer, provided as an embodiment of the present invention. Specifically, the solder balls 52 can be configured as solder balls.

[0064] Furthermore, in order to prevent the functional areas of adjacent chips 40 from interfering with or contaminating each other during bonding, and to enhance the mechanical strength of the area, when multiple chips 40 are placed in the area enclosed by the first dam portion 11, at least part of the second dam portion 12 can be disposed between adjacent chips 40 to separate adjacent chips 40.

[0065] When multiple chips 40 are planned within the same standard package unit, the second dike portion 12 also acts as a physical isolation wall between adjacent chips 40. This structure prevents the functional areas of adjacent chips 40 from interfering with or contaminating each other during bonding, and can serve as an alignment reference for adding dicing channels during subsequent dicing, facilitating the separation of multiple chips 40 within the standard package area into independent packages. Furthermore, it enhances the local mechanical strength of this area to support the silicon regions between the multiple chips 40.

[0066] By applying the above embodiments, the present invention, through the combined application of a standardized first cofferdam 11 and an adaptable second cofferdam 12, and the coordinated redistribution of the cutting path, successfully solves the connection problem from manufacturing to packaging of MPW, realizing true wafer-level heterogeneous chip integrated packaging. It merges multiple separate packaging processes into one, greatly reduces R&D and packaging costs, shortens the packaging preparation cycle, and improves the regularity of the external dimensions of the final package, facilitating subsequent testing and mounting, and improving the overall process yield and packaging reliability.

[0067] The chip packaging structure in the multi-project wafer 4 provided by the present invention includes a bonding carrier and a multi-project wafer 4; the front surface of the multi-project wafer 4 is bonded to the bonding carrier; a dam structure 10 is provided on the surface of the bonding carrier facing the multi-project wafer 4, the dam structure 10 including a first dam portion 11 and a second dam portion 12; a dicing channel is provided on the back surface 402 of the multi-project wafer; a plurality of first dam portions 11 are provided on the surface of the bonding carrier, each chip 40 is placed in the area enclosed by the corresponding first dam portion 11, and all first dam portions 11 have the same shape and size; a second dam portion 12 is formed on the surface of the bonding carrier corresponding to at least some of the chips 40 in the multi-project wafer 4; the second dam portion 12 is located inside the first dam portion 11, so that the shape and size of each area enclosed by the combination of the first dam portion 11 and the second dam portion 12 matches the corresponding chip 40. This invention utilizes a combination of a first cofferdam 11 and a second cofferdam 12 to correspond to the chip 40. The first cofferdam 11 forms the same cofferdam boundary at different chips 40, and the second cofferdam 12 fills the gap between the small-sized chip and the first cofferdam 11, thereby strengthening the support of the wafer at the small-sized chip, improving the regularity of the packaging structure, enabling simultaneous packaging of chips 40 in multiple project wafers 4, improving the regularity of the chip 40 after dicing, and enhancing the convenience of subsequent processes.

[0068] Furthermore, in this embodiment of the invention, the shape and size of the area enclosed by the first cofferdam 11 are matched with the largest chip in the multi-project wafer 4, and the shape and size of the area jointly enclosed by the first cofferdam 11 and the second cofferdam 12 are matched with the non-largest chip in the multi-project wafer 4. This ensures the mechanical strength of the package while improving the regularity of the outer contour of the package unit. By setting the dicing channels along the contour of the largest chip in the multi-project wafer 4, and ensuring that the spacing between adjacent dicing channels is the same and located within the same cutting area defined by the dicing channels, if there are multiple chips 40, an additional dicing channel is set between adjacent chips 40, which can balance the regularity of the outer contour of the package unit. The system ensures that each chip 40 is individually diced into a single product. By setting TSV vias 70 in the multi-project wafer 4, the wafer electrode 50 is connected to the back surface 402 of the multi-project wafer through the TSV vias 70 using a fan-in rewiring connection structure, thereby achieving external connection between the chip 40 in the multi-project wafer 4. By setting at least a portion of the second cofferdam 12 between adjacent chips 40 when multiple chips 40 are placed in the area enclosed by the first cofferdam 11, the adjacent chips 40 are separated, which can prevent the functional areas of adjacent chips 40 from interfering with or contaminating each other during bonding, and can enhance the mechanical strength of the area to support the silicon area between multiple chips 40.

[0069] The following describes the chip packaging method in a multi-project wafer provided by the embodiments of the present invention. The chip packaging method in a multi-project wafer described below is used to prepare the chip packaging structure in a multi-project wafer as described above, and can be referred to in correspondence with the chip packaging structure in a multi-project wafer described above.

[0070] Please refer to the details. Figure 13 , Figure 13 A flowchart of a chip packaging method in a multi-project wafer provided by an embodiment of the present invention may include:

[0071] S101: Provides multi-project wafers and bonding carriers.

[0072] The execution subject of this embodiment is a chip packaging system in a multi-project wafer. In this embodiment, the multi-project wafer contains various types of chips. The bonds and carriers are used to fabricate dam patterns according to different chips. The dam material can be photoresist, and the corresponding dam patterns are prepared through coating, exposure, and development.

[0073] S102: Bond the front surface of the multi-project wafer to the bonding carrier so that the chip is placed in the corresponding dike structure.

[0074] In this embodiment, the first cofferdam 11 defines the outer boundary of the final package. All first cofferdams have the same shape and size. The second cofferdam, as an adaptable structure, fills the internal space of the uniform first cofferdams, forming a sealed cavity of just the right size for a smaller chip. In this embodiment, the front side of the multi-project wafer can be bonded to the bonding carrier using bonding materials such as adhesives. The cofferdam structure set on the surface of the bond and the carrier forms a cavity to accommodate and protect the functional areas of the chip.

[0075] Furthermore, to achieve interconnection between the multi-project wafer and external components, after bonding the front surface of the multi-project wafer to the bonding carrier so that the chip is placed within the corresponding containment structure, the method may further include:

[0076] TSV vias are etched on the back surface of the multi-project wafer after bonding, and conductive structures are fabricated within the TSV vias to conduct wafer electrodes to the back surface of the multi-project wafer.

[0077] In this embodiment, an abrasive BG film can also be attached to the side of the bonding carrier facing away from the bonding surface to protect the bond and carrier during subsequent process fabrication. In this case, the substrate of the multi-project wafer can be thinned to the target silicon thickness for TSV packaging, in preparation for TSV slotting and opening.

[0078] Furthermore, to improve the flexible placement of pads on the back surface of multi-project wafers, the aforementioned method of etching TSV vias on the back surface of the multi-project wafer after bonding and fabricating conductive structures within the TSV vias to connect wafer electrodes to the back surface of the multi-project wafer may include the following steps:

[0079] Step S11: Etch TSV vias on the back surface of the multi-project wafer after bonding until the wafer electrodes are exposed to obtain the first structure to be processed.

[0080] Step S12: Prepare a first insulating layer on the back surface of the first structure to be processed, and remove the first insulating layer covering the wafer electrode to expose at least part of the wafer electrode, thereby obtaining the second structure to be processed;

[0081] Step S13: Prepare a redistribution layer on the back surface of the second structure to be processed to connect the wafer electrode to the back surface of the multi-project wafer.

[0082] In this embodiment, a TSV (Transient Vias) slotting and opening process can be performed on the back surface of the multi-project wafer using a dry etching process to expose the wafer electrodes and prepare for subsequent electrical connections. A first insulating layer is prepared on the back surface of the multi-project wafer, and the first insulating layer is opened at the corresponding wafer electrodes to prevent short circuits caused by direct connection between subsequent conductive structures and the multi-project wafer. Then, the circuits of different chips are redistributed through redistribution to bring out the internal electrodes of the chips. At this time, a second insulating layer can be prepared on the back surface of the wafer, and the second insulating layer is opened at the locations where the various chips are brought out to external connections, forming pads for chip connection to external connections. Solder balls can be soldered to these pads to further achieve external connections.

[0083] Furthermore, to facilitate dicing into finished chip products after packaging, the aforementioned process of etching TSV vias on the back surface of the multi-project wafer after bonding and fabricating conductive structures within the TSV vias to connect wafer electrodes to the back surface of the multi-project wafer may include:

[0084] TSV vias are etched on the back surface of the multi-project wafer after bonding, and dicing channels are formed on the back surface of the multi-project wafer. Conductive structures are formed within the TSV vias to connect wafer electrodes to the back surface of the multi-project wafer. The dicing channels are set along the contour of the largest chip in the multi-project wafer, and the spacing between adjacent dicing channels is the same. If there are multiple chips in the same dicing area divided by the dicing channels, an additional dicing channel is set between adjacent chips.

[0085] In this embodiment, during the TSV (Transfer-Side Vessel) slotting and opening process on the back surface of the wafer, the dicing channels can be redistributed and etched simultaneously to facilitate subsequent dicing into finished chip products. After the interconnect structure on the back side of the multi-project wafer is fabricated, the packaging structure can be diced based on the aforementioned dicing channels and any additional dicing channels to form multiple finished chip products.

[0086] The multi-project wafer chip packaging method provided in this invention is used to prepare the multi-project wafer chip packaging structure as described above, including S101: providing a multi-project wafer and the bonding carrier; S102: bonding the front surface of the multi-project wafer to the bonding carrier so that the chip is placed in the corresponding dam structure. This invention utilizes a first dam portion 11 and a second dam portion 12 in combination with corresponding chip settings. The first dam portion 11 forms the same dam boundary at different chip locations, and the second dam portion 12 fills the gap between the small-sized chip and the first dam portion 11, thereby strengthening the support for the wafer at the small-sized chip location, improving the regularity of the packaging structure, enabling simultaneous packaging of chips in a multi-project wafer, improving the regularity of the diced chips, and enhancing the convenience of subsequent processes.

[0087] Furthermore, in this embodiment of the invention, TSV vias are etched on the back surface of the multi-project wafer after bonding, and conductive structures are fabricated within the TSV vias to connect wafer electrodes to the back surface of the multi-project wafer, thereby enabling the multi-project wafer to connect to the outside. A redistribution structure is used to connect the wafer electrodes of the multi-project wafer to designated locations on the back surface of the multi-project wafer, improving the flexibility of pad placement on the back surface of the multi-project wafer. By fabricating and adding dicing channels on the back surface of the multi-project wafer, it is easier to cut the packaged wafer into finished chip products.

[0088] The following describes a finished chip product provided by an embodiment of the present invention. The finished chip product described below can be referred to in correspondence with the chip packaging structure in the multi-project wafer described above.

[0089] Please refer to the details. Figure 14 , Figure 14 This is a schematic diagram of a finished chip product provided in an embodiment of the present invention. The finished chip product can be set as a chip product cut along the dicing track in the chip packaging structure of the multi-project wafer described above.

[0090] In this embodiment, as shown... Figure 14As shown, taking a multi-project wafer 4 with two types of chips 40 as an example, the finished chips include the aforementioned chip A finished product 503 and chip B finished product 603. In this embodiment, the redistribution dicing track 60 includes both the dicing track arranged on the back surface 402 of the multi-project wafer and the additional dicing track. In this embodiment, the chip packaging structure in the multi-project wafer includes at least a bonding carrier 7 and a multi-project wafer 4; the front surface of the multi-project wafer 4 is bonded to the bonding carrier 7; a dam structure 10 is provided on the surface of the bonding carrier 7 facing the multi-project wafer 4, the dam structure 10 including a first dam portion 11 and a second dam portion 12; a dicing channel is provided on the back surface 402 of the multi-project wafer; a plurality of first dam portions 11 are provided on the surface of the bonding carrier 7, each chip 40 is placed in the area enclosed by the corresponding first dam portion 11, and all first dam portions 11 have the same shape and size; a second dam portion 12 is formed on the surface of the bonding carrier 7 corresponding to at least some of the chips 40 in the multi-project wafer 4; the second dam portion 12 is located inside the first dam portion 11, so that the shape and size of each area enclosed by the combination of the first dam portion 11 and the second dam portion 12 match the corresponding chip 40. This invention utilizes a combination of a first cofferdam 11 and a second cofferdam 12 to correspond to the chip 40. The first cofferdam 11 forms the same cofferdam boundary at different chips 40, and the second cofferdam 12 fills the gap between the small-sized chip and the first cofferdam 11, thereby strengthening the support of the wafer at the small-sized chip, improving the regularity of the packaging structure, enabling the simultaneous packaging of chips 40 in multiple project wafers 4, and improving the regularity of the finished chip after dicing, thus improving the convenience of subsequent processes.

[0091] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0092] Finally, it should be noted that in this document, relationships such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion.

[0093] The foregoing has provided a detailed description of a chip packaging structure, packaging method, and finished chip product in a multi-project wafer provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A chip packaging structure in a multi-project wafer, characterized in that, include: A bonding carrier and a multi-project wafer; the front surface of the multi-project wafer is bonded to the bonding carrier; the bonding carrier has a dam structure on the surface of the multi-project wafer, the dam structure including a first dam portion and a second dam portion; the back surface of the multi-project wafer has a dicing channel. The bonding carrier surface is provided with a plurality of first dam portions, and each chip is placed in the area enclosed by the corresponding first dam portion, and all the first dam portions have the same shape and size; The bonding carrier surface has a second dam formed on at least a portion of the chips in the multi-project wafer; the second dam is located inside the first dam, so that the shape and size of each region enclosed by the combination of the first dam and the second dam match the corresponding chip.

2. The chip packaging structure in a multi-project wafer according to claim 1, characterized in that, The shape and size of the area enclosed by the first dike part match the largest chip size in the multi-project wafer; The shape and size of the area jointly enclosed by the first and second cofferdams correspond to and match the non-maximum size chip in the multi-project wafer.

3. The chip packaging structure in a multi-project wafer according to claim 2, characterized in that, The dicing channels are arranged along the contour of the largest chip in the multi-project wafer, and the spacing between adjacent dicing channels is the same. If there are multiple chips within the same cutting area defined by the cutting channel, an additional cutting channel is provided between adjacent chips.

4. The chip packaging structure in a multi-project wafer according to claim 1, characterized in that, The multi-project wafer is provided with TSV vias, and the wafer electrodes are connected to the back surface of the multi-project wafer through the TSV vias using a fan-in rewiring connection structure.

5. The chip packaging structure in a multi-project wafer according to claim 1, characterized in that, When multiple chips are placed within the area enclosed by the first cofferdam, at least a portion of the second cofferdam is disposed between adjacent chips to separate them.

6. A chip packaging method in a multi-project wafer, characterized in that, For fabricating the chip packaging structure in a multi-project wafer as described in claim 1, comprising: Provide the multi-project wafer and the bonding carrier; The front surface of the multi-project wafer is bonded to the bonding carrier so that the chip is placed within the corresponding dike structure.

7. The chip packaging method in a multi-project wafer according to claim 6, characterized in that, After bonding the front surface of the multi-project wafer to the bonding carrier to place the chip within the corresponding dike structure, the method further includes: TSV vias are etched on the back surface of the multi-project wafer after bonding is completed, and conductive structures are formed within the TSV vias to connect the wafer electrodes to the back surface of the multi-project wafer.

8. The chip packaging method in a multi-project wafer according to claim 7, characterized in that, include: TSV vias are fabricated by etching on the back surface of the multi-project wafer after bonding is completed until the wafer electrodes are exposed, thus obtaining the first structure to be processed. A first insulating layer is prepared on the back surface of the first structure to be processed, and the first insulating layer covering the wafer electrode is removed to expose at least part of the wafer electrode, thereby obtaining the second structure to be processed. A redistribution layer is prepared on the back surface of the second structure to be processed to connect the wafer electrode to the back surface of the multi-project wafer.

9. The chip packaging method in a multi-project wafer according to claim 7, characterized in that, include: TSV vias are etched on the back surface of the multi-project wafer after bonding, and dicing channels are formed on the back surface of the multi-project wafer. Conductive structures are formed within the TSV vias to connect the wafer electrodes to the back surface of the multi-project wafer. The dicing channels are arranged along the contour of the largest chip in the multi-project wafer, and the spacing between adjacent dicing channels is the same. If there are multiple chips in the same dicing area defined by the dicing channels, an additional dicing channel is provided between adjacent chips.

10. A finished chip, characterized in that, The finished chip is a chip product cut along the dicing path in the chip packaging structure of the multi-project wafer as described in any one of claims 1 to 5.

Images