Power module packaging structure with high overload capacity and packaging method

Abstract

The invention relates to a power module packaging structure with high overload capacity and a packaging method. The invention provides a power module packaging structure with high overload capacity, which comprises an upper electrode assembly, a first low thermal resistance bonding layer, a chip, a second low thermal resistance bonding layer and a lower electrode plate, and is characterized in that the upper electrode assembly comprises an upper electrode plate and a boss electrode which are fixedly connected; the first low-thermal-resistance bonding layer is located on the lower surface of the boss electrode; the chip is located on the lower surface of the first low-thermal-resistance bonding layer; the second low-thermal-resistance bonding layer is located on the lower surface of the chip; the lower electrode plate is positioned on the lower surface of the second low-thermal-resistance bonding layer; wherein the main body structures of the upper electrode assembly and the lower electrode plate are made of high-performance materials which have high heat capacity characteristics and are matched with the thermal expansion coefficient of a chip material. Through the high-heat-capacity material and the low-heat-resistance design, the heat storage and heat dissipation capability of the packaging assembly in the overcurrent process is improved, and the overload tolerance time of the device is prolonged.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of chip packaging, and particularly relates to a power module packaging structure with high overload capacity and a packaging method. BACKGROUND

[0002] In recent years, high proportion of new energy access and high proportion of power electronic equipment application have become the significant features of new power systems. However, the safe operation of the existing direct current transmission system is subject to the limited overload tolerance capacity of its core power devices. During system failure, power electronic equipment is prone to trigger off-grid protection due to exceeding its tolerance limit, which not only seriously threatens the safe and stable operation of the system, hinders the rapid recovery process after failure, but also weakens its key grid support capacity. For example, in the flexible direct current transmission scene, the instantaneous current surge caused by direct current short-circuit fault requires the converter device to withstand 2 to 3 times the rated current impact within the time scale of hundreds of milliseconds to seconds; in the new energy station grid connection scene, the transient overcurrent caused by grid voltage sag requires the converter device to maintain ultra-high current density within the time scale of seconds; in the network-constructed energy storage scene, when the conventional direct current receiving end is locked, the sending and receiving ends will both have large fluctuations in reactive power, requiring the network-constructed static var generator (SVG) device to have a rapid overload output capacity and withstand 3 times the rated current for a short time (about 600 milliseconds) to maintain system voltage stability.

[0003] At present, the mainstream commercial high-voltage and high-power devices are insufficient in packaging design under fault state conditions, and only promise the ability to shut off 2 times the rated current within 1 millisecond, which is difficult to fully meet the needs of the above-mentioned severe working conditions for the continuous overload capacity of power electronic equipment. In actual application, a large number of parallel pressure contact type power modules are usually needed to provide redundant capacity to share the overload current stress of single-chip devices. However, this method significantly increases the complexity, volume, cost and subsequent operation and maintenance burden of the system.

[0004] Therefore, it is urgent to develop a new packaging method to solve the problem of rapid rise of junction temperature and short overload tolerance time of existing pressure contact type power modules under overload conditions, so as to break through the technical bottleneck and ensure the reliable operation and effective support of power electronic equipment during fault ride-through. SUMMARY

[0005] In order to overcome the defects of the prior art and the current situation that the low heat capacity of the existing crimping packaging structure causes sharp transient temperature rise and the heat dissipation capacity of the module is limited to cause thermal failure, the application provides a power module packaging structure, in order to solve the problem of insufficient heat capacity and long heat conduction path of the chip direct contact structure in the existing crimping packaging structure, a high-performance electrode material with high heat capacity characteristics and a thermal expansion coefficient matched with the material of the chip is adopted, the high-thermal-resistance buffer layer is cancelled, the heat conduction path is reduced, and the electrode structure material has the characteristics of high thermal conductivity and high specific heat capacity, the transient thermal response performance is greatly improved, the thermal failure problem caused by the rapid temperature rise of the chip under overload working conditions is improved, and the heat storage and heat dissipation capacity of the chip on the heat flow path can be significantly improved compared with the existing crimping packaging.

[0006] The application adopts the following technical scheme: A power module packaging structure with high overload capacity, comprising: An upper electrode assembly comprising a fixedly connected upper electrode plate and a boss electrode; A first low-thermal-resistance bonding layer located at the lower surface of the boss electrode; A chip located at the lower surface of the first low-thermal-resistance bonding layer; A second low-thermal-resistance bonding layer located at the lower surface of the chip; A lower electrode plate located at the lower surface of the second low-thermal-resistance bonding layer; Wherein, the main structure of the upper electrode assembly and the lower electrode plate adopts a high-performance material with high heat capacity characteristics and a thermal expansion coefficient matched with the material of the chip.

[0007] A new electrode material with a thermal expansion coefficient matched with the chip and high heat capacity characteristics is adopted. On the one hand, the traditional molybdenum sheet buffer layer is omitted, the packaging layer number is reduced, and the heat dissipation efficiency is improved. On the other hand, the high heat capacity characteristics of the electrode material are utilized to significantly enhance the transient heat dissipation capacity of the module, thereby effectively inhibiting the rising rate of the chip junction temperature under overload working conditions and prolonging the overload tolerance time of the device.

[0008] Preferably, the thermal conductivity of the high-performance material is greater than or equal to 400 W / (m K). The high heat capacity material can effectively absorb the instantaneous heat generated during overload while providing an excellent heat dissipation path, and reduce the chip temperature rise rate.

[0009] Preferably, the absolute value of the difference between the thermal expansion coefficient of the high-performance material and the thermal expansion coefficient of the chip is less than or equal to 5ppm / K. By using a material close to the thermal expansion coefficient of the chip, on the one hand, mechanical stress generated by the device under high-temperature cycling can be avoided, which can cause solder layer cracking or interface peeling; on the other hand, the thermal expansion rate of the transition metal sheet in the traditional compression packaging structure can be removed, which can avoid the early failure problem caused by the difference in thermal expansion rate between the transition metal sheet and the chip. At the same time, the removal of the transition metal sheet simplifies the packaging structure and reduces the overall thermal resistance from the chip to the electrode assembly.

[0010] These materials can effectively absorb the instantaneous heat generated during overload while providing excellent heat conduction paths, thereby reducing the chip temperature rise rate.

[0011] Preferably, the boss electrode is a resilient structure. The resilient electrode of the upper electrode assembly can be elastically deformed in the vertical direction of the chip, so that when the upper electrode assembly is in contact with the chip, the chip will not bear excessive pressure, thereby improving the reliability of the chip and reducing the difficulty of compression packaging. At the same time, when the chip expands due to temperature rise, the resilient electrode can also transfer excess stress while ensuring sufficient electrical conductivity, thereby further ensuring the reliability of the chip.

[0012] Preferably, the resilient structure is one of a spring structure, an S-shaped structure, and a porous structure.

[0013] Preferably, the upper electrode assembly is integrally formed. This design eliminates the assembly interface between components, reduces the heat dissipation path during heat transfer, and avoids the contact thermal resistance caused by the interface, thereby significantly improving the overall heat dissipation performance of the module.

[0014] Preferably, a metallization layer is deposited on the corresponding contact surface of the lower surface and / or the upper surface of the chip and the lower electrode plate and / or the upper electrode assembly, and the metallization layer is one or more of silver, gold, nickel, and rhodium.

[0015] Preferably, the thermal conductivity of the first low-thermal-resistance bonding layer and the second low-thermal-resistance bonding layer is ≥ 100 W / (m•K). The low-thermal-resistance bonding layer eliminates the contact thermal resistance between the contact surfaces of adjacent components, thereby significantly reducing the thermal resistance of the packaging structure from the chip to the heat dissipation surface of the power module and improving the heat dissipation effect of the chip.

[0016] Preferably, the chip is classified by type, including IGBT chips, IGCT chips, diode chips, and MOSFET chips, and by material, including silicon-based chips or silicon carbide chips.

[0017] Based on the same inventive concept, the application also provides a power module packaging method with high overload capacity, including the following steps: The upper electrode plate, boss electrode, and lower electrode plate are fabricated using high-performance materials that have both high heat capacity and a coefficient of thermal expansion that matches the chip material. The lower surface of the chip is connected to the lower electrode plate to prepare a second low thermal resistance bonding layer; The upper surface of the chip is connected to the upper electrode assembly to prepare the first low thermal resistance bonding layer.

[0018] Preferably, the first low thermal resistance bonding layer and the second low thermal resistance bonding layer are formed by welding or sintering processes. The formation of the first low thermal resistance bonding layer and the second low thermal resistance bonding layer significantly reduces the contact thermal resistance at the chip-electrode interface, thereby improving the overall heat dissipation capability of the module.

[0019] Preferably, the sintering process includes: nano-silver sintering, nano-copper sintering, and nano-silver-copper mixed sintering.

[0020] Preferably, the welding process uses a high thermal conductivity solder.

[0021] The entire structure is fully welded. This reduces the contact thermal resistance between material interfaces, lowers the steady-state chip junction temperature during normal operation, and provides a larger margin for the rise in chip junction temperature under overload conditions.

[0022] Compared with the prior art, the beneficial effects of the present invention are as follows: The present invention provides a power module packaging structure with high overload capacity, comprising: an upper electrode assembly including a fixedly connected upper electrode plate and a boss electrode; a first low thermal resistance bonding layer located on the lower surface of the boss electrode; a chip located on the lower surface of the first low thermal resistance bonding layer; a second low thermal resistance bonding layer located on the lower surface of the chip; and a lower electrode plate located on the lower surface of the second low thermal resistance bonding layer. The main structures of the upper electrode assembly and the lower electrode plate are made of high-performance materials that possess both high thermal capacity and a coefficient of thermal expansion matching the chip material. Traditional packaging structures typically introduce buffer layers such as molybdenum sheets to alleviate the mismatch in thermal expansion coefficients between the chip and electrode materials, but this inevitably increases the thermal resistance of the packaging structure. This invention optimizes the packaging design by selecting high-performance electrode materials with both high thermal capacity and a thermal expansion coefficient that matches the chip material. This eliminates the need for an additional high-resistance buffer layer, thereby not only eliminating the additional thermal resistance caused by traditional buffer layers and simplifying the traditional packaging structure, but also reducing the overall thermal resistance from the chip to the electrode assembly. Furthermore, it optimizes the heat conduction path through the high thermal conductivity material itself.

[0023] The power module packaging method with high overload capacity provided by the present invention uses interconnect technology to form a low thermal resistance bonding layer at the interface between the chip and key components, which significantly reduces the contact thermal resistance inside the device, reduces the chip junction temperature under normal operating conditions, and reserves space for the chip junction temperature to rise under overload conditions. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the packaging structure of a power module with high overload capacity according to Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the packaging structure of a power module with high overload capacity according to Embodiment 2 of the present invention; Figure 3 This is a schematic diagram of the elastic electrode structure in Embodiment 2 of the present invention; Figure 4 This is a diagram showing the junction temperature of the IGBT in the heat dissipation mode of the packaged chip according to the present invention. Among them, 100 is the upper electrode assembly; 101 is the upper electrode plate; 102 is the boss electrode; 103 is the elastic electrode; 200 is the chip; 300 is the lower electrode plate; 400 is the first low thermal resistance bonding layer; and 500 is the second low thermal resistance bonding layer. Detailed Implementation

[0025] The present invention will be further described below with reference to the accompanying drawings and embodiments. The following embodiments are provided to better understand the present invention and are not intended to limit the preferred embodiments described. They do not constitute a limitation on the content and scope of protection of the present invention. Any product that is the same as or similar to the present invention, derived by any person under the guidance of the present invention or by combining the features of the present invention with other prior art, falls within the protection scope of the present invention.

[0026] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0027] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0028] This packaging structure is categorized by chip type and is applicable to chip types including IGBT chips, IGCT chips, diode chips, and MOSFET chips; and by chip material and is applicable to silicon-based chips or silicon carbide chips.

[0029] Example 1 like Figure 1 As shown, this embodiment provides a power module packaging structure with high overload capacity, including: Upper electrode assembly 100, the upper electrode assembly 100 includes an upper electrode plate 101 and a boss electrode 102; A first low thermal resistance bonding layer 400 is located on the lower surface of the upper electrode assembly 100, specifically on the lower surface of the boss electrode 102. Chip 200, the chip 200 being located on the lower surface of the first low thermal resistance bonding layer 400; A second low thermal resistance bonding layer 500 is located on the lower surface of the chip 200. The lower electrode plate 300 is located on the lower surface of the second low thermal resistance bonding layer 500; The upper electrode assembly 100 and the lower electrode plate 300 are made of high-performance materials that have both high heat capacity and a coefficient of thermal expansion that matches the chip material.

[0030] In this embodiment, the upper surface of the chip 200 is connected to the boss electrode 102, and the lower surface of the chip 200 is connected to the lower electrode plate 300. The upper and lower sides of the chip 200 dissipate heat through the upper electrode assembly 100 and the lower electrode plate 300, achieving a double-sided heat dissipation effect, which can significantly reduce the thermal resistance of the device and improve the heat dissipation capacity of the device.

[0031] In this embodiment, the upper electrode plate 101 and the boss electrode 102 are integrally processed. Since the upper electrode assembly 100 is an integrally processed electrode structure, it has better electrical and thermal conductivity, which can improve the thermal conductivity of the chip 200.

[0032] The upper electrode plate 101, the boss electrode 102, and the lower electrode plate 300 are made of high-performance materials that have both high heat capacity and a coefficient of thermal expansion that matches the chip material. Specifically, the thermal conductivity of the material is ≥ 400 W / (m•K), the material has good electrical conductivity and a coefficient of thermal expansion that matches the power semiconductor chip material, and the absolute value of the difference between its coefficient of thermal expansion and the coefficient of thermal expansion of the chip material is less than or equal to 5ppm / K.

[0033] In this embodiment, the upper electrode plate 101 is made of copper, while the lower electrode plate 300 and the boss electrode 102 are made of aluminum diamond. These materials provide excellent thermal conductivity, and their high specific heat capacity can effectively absorb the instantaneous heat generated during overload, reducing the chip temperature rise rate.

[0034] In this embodiment, the thermal expansion coefficients of the materials of the chip 200, the upper electrode assembly 100, and the lower electrode plate 300 are close. On the one hand, this can avoid mechanical stress generated in the device under high-temperature cycling, which could lead to solder layer cracking or interface peeling. On the other hand, it can remove the thermal expansion coefficient transition metal sheet in the traditional press-fit packaging structure, avoiding early failure caused by the difference in thermal expansion coefficient between the transition metal sheet and the chip. At the same time, the removal of the transition metal sheet simplifies the packaging structure and reduces the overall thermal resistance from the chip to the electrode assembly.

[0035] Chip 200 is connected to the boss electrode 102 via a low thermal resistance bonding layer formed by welding or sintering interconnection processes. Similarly, chip 200 is connected to the lower electrode plate 300 via a low thermal resistance bonding layer formed by welding or sintering interconnection processes. In this embodiment, a first low thermal resistance bonding layer 400 and a second low thermal resistance bonding layer 500 are prepared using a nano-copper sintering process. Correspondingly, copper plating is applied to the chip surface to meet the sintering process requirements. The low thermal resistance bonding layer eliminates the contact thermal resistance between adjacent component contact surfaces, thereby significantly reducing the thermal resistance from chip 200 to the heat dissipation surface of the power module's packaging structure, and improving the heat dissipation effect of chip 200.

[0036] Example 2 refer to Figure 2 This embodiment provides a power module packaging structure with high overload capacity, including: The upper electrode assembly 100 includes an upper electrode plate 101 and a boss electrode 102.

[0037] Chip 200 is disposed below the upper electrode assembly, and the upper surface of chip 200 is electrically connected to the boss electrode 102.

[0038] A lower electrode plate 300 is disposed opposite to the upper electrode assembly. The lower surface of the chip 200 is electrically connected to the lower electrode plate 300. In this embodiment, the lower electrode plate 300 is a lower electrode plate.

[0039] The upper electrode assembly 100 is an electrode integrally processed, thus the upper electrode assembly 100 has excellent electrical and thermal conductivity, thereby enabling the power module packaging structure of the present invention to have excellent electrical conductivity and heat dissipation capabilities for the chip 200.

[0040] In this embodiment, the boss electrode 102 is an elastic structure. This elastic structure is formed by processing a rigid boss structure and creating a specific shape within the boss structure, thereby forming an elastic structure, including but not limited to spring structures, S-shaped structures, porous structures, etc. Figure 3 As shown. Specifically, the electrode itself does not possess good elastic properties. When subjected to pressure along the vertical direction of the chip 200, the elastic electrode 103 deforms, achieving a vertical compression effect, rather than utilizing the inherent elasticity of the electrode itself. The protruding electrode 102 of the upper electrode assembly 100 can elastically deform along the vertical direction of the chip 200. Therefore, when the elastic electrode 103 contacts the chip 200, the chip 200 will not bear excessive pressure, improving the reliability of the chip 200 and reducing the difficulty of press-fit packaging. Simultaneously, when the chip 200 expands due to temperature increase, the protruding electrode 102, while ensuring sufficient conductivity, can also transfer excess stress, further ensuring the reliability of the chip 200.

[0041] In this embodiment, the upper electrode plate 101, the elastic electrode assembly 103 and the lower electrode plate 300 are made of high-performance materials that have both high heat capacity and a coefficient of thermal expansion that matches the chip material. Specifically, the material has a thermal conductivity ≥ 400 W / (m•K), good electrical conductivity, and a coefficient of thermal expansion that matches that of power semiconductor chip materials. The absolute value of the difference between its coefficient of thermal expansion and that of the chip material is less than or equal to 5ppm / K. The upper electrode plate 101 is made of beryllium copper, and the lower electrode plate 300 and the boss electrode 102 are made of aluminum diamond. While providing an excellent heat conduction path, the material's high specific heat capacity can effectively absorb the instantaneous heat generated during overload, reducing the chip temperature rise rate.

[0042] In this embodiment, the thermal expansion coefficients of the materials of the chip 200, the upper electrode assembly 100, and the lower electrode plate 300 are close. On the one hand, this can avoid mechanical stress generated in the device under high-temperature cycling, which could lead to solder layer cracking or interface peeling. On the other hand, it can remove the thermal expansion coefficient transition metal sheet in the traditional press-fit packaging structure, avoiding early failure caused by the difference in thermal expansion coefficient between the transition metal sheet and the chip. At the same time, the removal of the transition metal sheet simplifies the packaging structure and reduces the overall thermal resistance from the chip to the electrode assembly.

[0043] In this embodiment, the chip 200 and the boss electrode 102 are connected by a first low thermal resistance bonding layer 400 formed by welding or sintering interconnection processes, and the chip 200 and the lower electrode plate 300 are connected by a second low thermal resistance bonding layer 500 formed by welding or sintering interconnection processes. The low thermal resistance bonding layer eliminates the contact thermal resistance between the contact surfaces of adjacent components, thereby significantly reducing the thermal resistance of the chip 200 to the heat dissipation surface of the power module's packaging structure and improving the heat dissipation effect of the chip 200.

[0044] In this embodiment, the first low thermal resistance bonding layer 400 and the second low thermal resistance bonding layer 500 are prepared by welding with high thermal conductivity solder.

[0045] Example 3 This embodiment provides a power module packaging method with high overload capacity, comprising the following steps: Step 1: Fabricate the lower electrode plate using a high-performance material that combines high heat capacity with a coefficient of thermal expansion that matches the chip material; connect the lower surface of the chip to the lower electrode plate; The connection between the lower surface of the chip and the lower electrode plate can be achieved by sintering with nano-silver or nano-copper or by other high thermal conductivity solders. When using nano-silver or nano-copper sintering, the chip surface needs to be plated with silver or copper to meet the sintering process requirements.

[0046] The lower electrode plate material can be a high-performance material such as copper, beryllium copper, or aluminum diamond, which has both high heat capacity and a coefficient of thermal expansion that matches the chip material.

[0047] Step 2: Fabricate the upper electrode assembly using a high-performance material that combines high thermal capacity with a coefficient of thermal expansion that matches the chip material; connect the upper surface of the chip to the upper electrode assembly; The elastic electrode is formed by precision machining, and the elastic electrode and the upper electrode plate are integrally machined. The surface finish of the electrode is controlled at about 3.2 micrometers, and the spring part of the electrode is cut out by wire cutting technology.

[0048] The rigid electrode is precision machined, and the rigid electrode and the upper electrode plate are integrally machined, with a surface finish of 3.2 micrometers.

[0049] The connection between the upper surface of the chip and the contact surface of the boss can be achieved by sintering with nano-silver or nano-copper or by other high thermal conductivity solders. When using nano-silver or nano-copper sintering, the chip surface needs to be plated with silver or copper to meet the sintering process requirements.

[0050] The upper electrode plate material can be a high-performance material such as copper, beryllium copper, or aluminum diamond, which has both high heat capacity and a coefficient of thermal expansion that matches the chip material.

[0051] Step 3: Connect the tube shell to the four sides of the upper electrode plate and the four sides of the lower electrode plate. The tube shell can be made of sheet molding compound (SMC) and bonded to the upper and lower bottom plates around the sides using a high-temperature resistant and insulating adhesive. The tube shell can also be precision injection molded using epoxy resin and bonded to the upper and lower bottom plates around the sides using a high-temperature resistant and insulating adhesive. The outer circumference of the tube shell is provided with insulating skirts. The insulation design of the tube shell is in accordance with the standard, and the insulation gap and creepage distance meet the required insulation requirements.

[0052] Step 4: Encapsulation, where insulating material is encapsulated onto the chip surface, so that the chip is encapsulated by the insulating material; The potting insulation material can be an organic insulating material, such as at least one of silicone rubber, silicone gel and polyimide.

[0053] The potting process is vacuum potting to ensure that air bubbles are completely eliminated.

[0054] Test case To verify the optimization effect of the present invention, finite element analysis software was used to perform electrical, thermal, and thermo-mechanical coupling simulations on a power module with high overload capacity. The input conditions for the simulation are as follows: (1) The traditional packaging structure uses copper as the material for the upper and lower electrodes. There is a molybdenum sheet between the chip and the electrode to balance the thermal expansion coefficient between the electrode and the chip. The optimized high overload packaging structure uses copper as the upper electrode plate and aluminum diamond as the material for the lower electrode and the boss. Since the thermal expansion coefficient between the chip and the electrode is matched, there is no need for a molybdenum sheet as a buffer layer.

[0055] (2) Set the simulation ambient temperature to 45℃, set the initial water inlet temperature on both sides of the water-cooled radiator to 45℃, and set the water-cooling convection coefficient to 5000 W / (m²). 2 ·K), the initial temperature of the IGBT is 45℃, and the heat source in the active area uses a rated power (3.5941×10 K). 9 W / m 3 Steady-state thermal simulation was performed, and the maximum junction temperature corresponding to the simulation results was used as the initial temperature of the IGBT under the double overcurrent condition for transient simulation. The double overcurrent power was 1.08851 × 10⁻⁶. 10 W / m 3 .

[0056] like Figure 4As shown, under the same double overcurrent power surge, the junction temperature rise rate of the optimized high overload capacity power module of this invention is significantly lower than that of the power module with a conventional packaging structure. The time for the power module with a conventional packaging structure to reach the 125°C safety threshold is approximately 49 ms, while the time for the high overload capacity power module to reach the safety threshold is approximately 600 ms, an improvement of approximately 12.2 times from tens of milliseconds to hundreds of milliseconds. Transient simulation results demonstrate that the high heat capacity electrode material can not only quickly conduct heat away but also absorb a large amount of heat in a short time, resulting in a slower temperature rise. Therefore, the optimized packaging structure design proposed in this invention can improve the high overload capacity of the packaged module. The packaging structure of this application significantly improves the heat storage capacity and heat dissipation efficiency of the packaged component during overload, effectively suppresses the junction temperature rise rate, and extends the overload withstand time of the device, thereby greatly improving the operational reliability of the press-fit power module under harsh operating conditions (such as fault ride-through).

[0057] The above are merely embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of the claims of the present invention pending approval.

Claims

1. A power module packaging structure with high overload capacity, characterized in that, include: An upper electrode assembly, the upper electrode assembly comprising a fixedly connected upper electrode plate and a boss electrode; A first low thermal resistance bonding layer is located on the lower surface of the boss electrode. The chip is located on the lower surface of the first low thermal resistance bonding layer; A second low thermal resistance bonding layer is located on the lower surface of the chip. The lower electrode plate is located on the lower surface of the second low thermal resistance bonding layer; The main structure of the upper electrode assembly and the lower electrode plate uses high-performance materials that combine high heat capacity with a coefficient of thermal expansion that matches the chip material.

2. The power module packaging structure with high overload capacity according to claim 1, characterized in that, The thermal conductivity of the high-performance material is ≥400 W / (m•K).

3. The power module packaging structure with high overload capacity according to claim 2, characterized in that, The absolute value of the difference between the coefficient of thermal expansion of the high-performance material and the coefficient of thermal expansion of the chip is less than or equal to 5 ppm / K.

4. The power module packaging structure with high overload capacity according to claim 1, characterized in that, The boss electrode has an elastic structure.

5. The power module packaging structure with high overload capacity according to claim 4, characterized in that, The elastic structure is one of the following: spring structure, S-shaped structure, or porous structure.

6. The power module packaging structure with high overload capacity according to claim 5, characterized in that, The upper electrode assembly is integrally molded.

7. The power module packaging structure with high overload capacity according to claim 1, characterized in that, A metallization layer is deposited on the lower and / or upper surface of the chip, and on the corresponding contact surfaces of the lower electrode plate and / or upper electrode assembly. The metallization layer is one or more of silver, gold, nickel, and rhodium.

8. The power module packaging structure with high overload capacity according to claim 1, characterized in that, The thermal conductivity of the first low thermal resistance bonding layer and the second low thermal resistance bonding layer is ≥100W / (m•K).

9. The power module packaging structure with high overload capacity according to claim 1, characterized in that, The chips are classified by type as IGBT chips, IGCT chips, diode chips, and MOSFET chips; and by material as silicon-based chips or silicon carbide chips.

10. A method for packaging a power module with high overload capacity, characterized in that, Includes the following steps: The upper electrode plate, boss electrode, and lower electrode plate are fabricated using high-performance materials that have both high heat capacity and a coefficient of thermal expansion that matches the chip material. The lower surface of the chip is connected to the lower electrode plate to prepare a second low thermal resistance bonding layer; The upper surface of the chip is connected to the boss electrode to prepare the first low thermal resistance bonding layer.

11. The power module packaging method with high overload capacity according to claim 10, characterized in that, The first low thermal resistance bonding layer and the second low thermal resistance bonding layer are formed by welding or sintering processes.

12. The power module packaging method with high overload capacity according to claim 11, characterized in that, The sintering process includes: nano-silver sintering, nano-copper sintering, and nano-silver-copper mixed sintering. The welding process uses high thermal conductivity solder.

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