Motor drive circuit with dynamic matching of hysteresis window to rotational speed

Abstract

The present application relates to the field of motor drive control, and particularly relates to a motor drive circuit with dynamic matching of hysteresis window and rotating speed, comprising a Hall voltage output module, an adjustable hysteresis comparator module, a logic control module, a three-phase non-overlapping clock module, a voltage stabilizing and reference voltage output module, a frequency multiplication module, a frequency-voltage conversion module, an H-bridge drive signal output module, a comparison module, a ROM module and a DAC module; the flip threshold voltage output by the logic control module corresponds to the rotating speed of the motor, and the hysteresis window can be dynamically adjusted according to the size of the rotating speed; at low rotating speed, the hysteresis window is relatively large, which reduces the occurrence of motor jitter caused by frequent coil magnetic field commutation due to noise and other factors at low speed; at high rotating speed, the hysteresis window is automatically switched to a smaller one, which helps to reduce the phase delay during coil commutation, synchronize the coil commutation signal with the rotor position, and improve the stability of the motor during high-speed operation.

Description

Technical Field

[0001] This invention relates to the field of motor drive control, and more specifically to a motor drive circuit that dynamically matches the rotational speed using a hysteresis window. Background Technology

[0002] The core function of a motor drive circuit is to convert the low-power electrical signal output from the microcontroller into high-power electrical energy capable of driving the motor, while simultaneously achieving precise control over parameters such as motor speed, direction, and torque. For example, a typical DC motor drive circuit usually includes power switching devices (such as MOSFETs or IGBTs), freewheeling diodes, a driver chip, and protection circuitry. The power switching devices, as the core actuators, control the direction and magnitude of the current in the motor windings through high-speed switching. For instance, an H-bridge circuit, through the coordinated operation of four switching transistors, can achieve both forward and reverse rotation of the motor and adjust the average voltage using pulse width modulation (PWM) technology, thereby controlling the speed. The freewheeling diodes provide a release path for the energy in the motor inductance when the switch is open, preventing back electromotive force from damaging the devices. The driver chip is responsible for converting the microcontroller's logic level signals into high-voltage / high-current signals sufficient to drive the power switches, while also integrating overcurrent, overtemperature, and undervoltage protection functions to improve system reliability.

[0003] Hall effect motor drive chips accurately detect the rotor position and intelligently control the current, ensuring efficient and stable motor operation. Utilizing the Hall effect principle, they can sense changes in the magnetic field generated when the motor rotor rotates and convert them into electrical signals. After processing these signals internally, the rotor position and speed can be accurately calculated, providing crucial data for motor control.

[0004] Hall effect motor driver chips employ a specific hysteresis window during N / S pole commutation of the coil magnetic field based on the rotor position. This prevents the coil magnetic field from repeatedly switching near the critical point due to noise or other factors. Traditional Hall effect motor driver chips typically have a fixed hysteresis window size, requiring a suitable fixed value to be found between low and high speed operation. However, at high speeds, the rotor angle changes rapidly, making it highly sensitive to signal phase delays. A fixed hysteresis window can lead to increased Hall signal transition delays, causing lag in rotor position determination and resulting in commutation errors. Summary of the Invention

[0005] The purpose of this invention is to provide a motor drive circuit with dynamic matching speed using a hysteresis window, which aims to improve the problem that setting a fixed hysteresis window in conventional Hall motor drive chips may lead to increased delay in Hall signal transitions, resulting in delayed determination of the motor rotor position and causing commutation errors.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] A motor drive circuit with hysteresis window dynamic speed matching includes a Hall voltage output module, an adjustable hysteresis comparator module, a logic control module, a three-phase non-overlapping clock module, a voltage regulator and reference voltage output module, a frequency multiplier module, a frequency-to-voltage conversion module, an H-bridge drive signal output module, a comparator module, a ROM module, and a DAC module.

[0008] The output terminals of the Hall voltage output module and the DAC module are both electrically connected to the adjustable hysteresis comparator module. The Hall voltage output module and the DAC module output Hall voltage and hysteresis control voltage DACout to the adjustable hysteresis comparator module, respectively.

[0009] The output terminals of the adjustable hysteresis comparator module and the three-phase non-overlapping clock module are both electrically connected to the logic control module. The adjustable hysteresis comparator module and the three-phase non-overlapping clock module respectively output hysteresis voltage V. hys The clock signals S1, S2, and S3 are sent to the logic control module;

[0010] The first and second output terminals of the logic control module are electrically connected to the H-bridge drive signal output module and the frequency multiplier module, respectively. The first and second output terminals output a flip threshold voltage and a commutation signal to the H-bridge drive signal output module and the frequency multiplier module, respectively. The H-bridge drive signal outputs a motor drive signal to the outside.

[0011] The output terminal of the frequency multiplier module is electrically connected to the frequency-to-voltage conversion module. The frequency multiplier module amplifies the commutation signal and outputs it to the frequency-to-voltage conversion module.

[0012] The output of the frequency-to-voltage conversion module is electrically connected to the comparator module. The frequency-to-voltage conversion module converts the amplified commutation signal into a voltage signal Vout and outputs it to the comparator module. The output of the comparator module is electrically connected to the ROM module, and the output of the ROM module is electrically connected to the DAC module. The voltage regulator and reference voltage output module outputs a reference voltage to the comparator module and the DAC module, and outputs a digital voltage Vout. DD1 The comparison module outputs a voltage signal Vout to the ROM module and a frequency-to-voltage conversion module; the comparison result between the voltage signal Vout and the reference voltage is sent to the ROM module for index conversion; the DAC module converts the index conversion signal into a hysteresis control voltage DACout.

[0013] Furthermore, the DAC module includes inverters INV1, INV2, INV3, INV4, and INV5; NOR gates NOR1, NOR gate NOR2, NOR gate NOR3, NOR gate NOR4, NOR gate NOR5, NOR gate NOR6, NOR gate NOR7, NOR gate NOR8, NOR gate NOR9, NOR gate NOR10, NOR gate NOR11, and NOR gate NOR12; MOSFETs N1 and N2; and MOSFETs N2 and N2. Transistor N3, MOSFET N4, MOSFET N5, MOSFET N6, MOSFET N7, MOSFET N8, MOSFET N9, MOSFET N10, MOSFET N11, MOSFET N12, MOSFET N13, MOSFET N14, MOSFET N15, MOSFET N16 and resistors R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13;

[0014] The ROM module outputs the first index result E0o to the input of inverter INV1, the first input of NOR5, NOR7, NOR9, and NOR11; the ROM module outputs the second index result E1o to the input of inverter INV2, the second input of NOR5, NOR6, NOR9, and NOR10; the ROM module outputs the third index result... The ROM module outputs the fourth index result E3o to the input of inverter INV3, the third input of NOR5, NOR6, NOR7, and NOR8; and the ROM module outputs the fifth index result E4o to the input of inverter INV5, the first input of NOR3, and the first input of NOR4.

[0015] The output of inverter INV1 is electrically connected to the first input of NOR6, NOR8, NOR10, and NOR12; the output of inverter INV2 is electrically connected to the second input of NOR7, NOR8, NOR11, and NOR12; the output of inverter INV3 is electrically connected to the third input of NOR9, NOR10, NOR11, and NOR12; the output of inverter INV4 is electrically connected to the second input of NOR1 and NOR3; and the output of inverter INV5 is electrically connected to the first input of NOR1 and NOR2.

[0016] The output of NOR1 is electrically connected to the gates of MOSFETs N1 and N3; the output of NOR2 is electrically connected to the gates of MOSFETs N2 and N4; the output of NOR3 is electrically connected to the gates of MOSFETs N5 and N7; the output of NOR4 is electrically connected to the gates of MOSFETs N6 and N8; the output of NOR5 is electrically connected to the gate of MOSFET N9; and the output of NOR6... The output of NOR7 is electrically connected to the gate of MOSFET N10; the output of NOR8 is electrically connected to the gate of MOSFET N12; the output of NOR9 is electrically connected to the gate of MOSFET N13; the output of NOR10 is electrically connected to the gate of MOSFET N14; the output of NOR11 is electrically connected to the gate of MOSFET N15; and the output of NOR12 is electrically connected to the gate of MOSFET N16.

[0017] The voltage regulator and reference voltage output module outputs a reference voltage V. H One end of resistor R1 is connected to the resistor; the other end of resistor R1 is electrically connected to one end of resistor R2 and the drain of MOSFET N1; the other end of resistor R2 is electrically connected to one end of resistor R3 and the drains of MOSFET N2 and MOSFET N3; the other end of resistor R3 is electrically connected to one end of resistor R4 and the drains of MOSFET N4 and MOSFET N5; the other end of resistor R4 is electrically connected to one end of resistor R5 and the drains of MOSFET N6 and MOSFET N7; the other end of resistor R5 is electrically connected to one end of resistor R6 and the drain of MOSFET N8.

[0018] The sources of MOSFETs N1, N2, N5, and N6 are all electrically connected to the other end of resistor R13 and the drain of MOSFET N16; the sources of MOSFETs N3, N4, N7, and N8 are all electrically connected to one end of resistor R7 and the drain of MOSFET N9; the other end of resistor R7 is electrically connected to one end of resistor R8 and the drain of MOSFET N10; the resistor R... The other end of resistor 8 is electrically connected to one end of resistor R9 and the drain of MOSFET N11; the other end of resistor R9 is electrically connected to one end of resistor R10 and the drain of MOSFET N12; the other end of resistor R10 is electrically connected to one end of resistor R11 and the drain of MOSFET N13; the other end of resistor R11 is electrically connected to one end of resistor R12 and the drain of MOSFET N14; the other end of resistor R12 is electrically connected to one end of resistor R13 and the drain of MOSFET N15.

[0019] The source of MOSFET N9 is electrically connected to the sources of MOSFETs N10, N11, N12, N13, N14, N15, and N16, and serves as the output terminal to output the hysteresis control voltage DACout to the adjustable hysteresis comparator module; the other end of resistor R6 is grounded.

[0020] Furthermore, the resistors R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, and R13 satisfy the following conditional expression:

[0021] R1=5Rsh; R2=R3=R4=R5=R6=Rsh; R7=R8=R9=R10=R11=R12=R13=2Rsh;

[0022] Where Rsh is the unit resistance value.

[0023] Furthermore, the Hall voltage output module includes a Hall disk and an instrumentation amplifier U6; the adjustable hysteresis comparator module includes a hysteresis comparator U7, switches 1S3_HY0, 1S3_HY1, 2S3_HY0, 2S3_HY1, 1S1, 1S2, 1S3, 2S1, 2S2, 2S3, 3S1, 3S2, 3S3, 4S1, 4S2, 4S3, capacitors C1a, C1b, C2a, C2b, C3a, C3b, trigger U8, NOT gates A1, A2, A3, A4, A5, A6, A7, A8, and NAND gates B1 and B2;

[0024] The DAC module outputs a hysteresis control voltage DACout to one end of switch 1S3_HY1 and one end of switch 2S3_HY0; the other end of switch 1S3_HY1 is electrically connected to one end of switch 1S3_HY0, one end of capacitor C1a, and the non-inverting input of hysteresis comparator U7; the other end of switch 2S3_HY0 is electrically connected to one end of switch 2S3_HY1, one end of capacitor C1b, and the inverting input of hysteresis comparator U7.

[0025] The Hall effect sensor outputs an induced voltage VIN1 to one end of switch 1S3 and one end of switch 2S2. The Hall effect sensor outputs an induced voltage VIN2 to one end of switch 1S2 and one end of switch 2S3. The other ends of switch 1S3 and switch 1S2 are electrically connected to the first input terminal of instrumentation amplifier U6. The other ends of switch 2S2 and switch 2S3 are electrically connected to the second input terminal of instrumentation amplifier U6. The first output terminal of instrumentation amplifier U6 outputs a Hall voltage Vo1 to one end of switch 3S2 and one end of switch 3S3. The other end of switch 3S2 is electrically connected to one end of switch 1S1 and one end of capacitor C2a. The other end of switch 3S3 is electrically connected to one end of switch 2S1 and one end of capacitor C3a.

[0026] The second output terminal of the instrumentation amplifier U6 outputs Hall voltage Vo2 to one end of switch 4S2 and one end of switch 4S3. The other end of switch 4S2 is electrically connected to one end of switch 4S1, the other end of switch 2S1, and one end of capacitor C2b. The other end of switch 4S3 is electrically connected to one end of capacitor C3b, one end of switch 3S1, and the other end of switch 1S1. The other end of switch 3S1 is electrically connected to the non-inverting input terminal of hysteresis comparator U7, and the other end of switch 4S1 is electrically connected to the inverting input terminal of hysteresis comparator U7.

[0027] The output of the hysteresis comparator U7 is electrically connected to the input of NOT gate A1. The output of NOT gate A1 is electrically connected to the first input of flip-flop U8. The three-phase non-overlapping clock module outputs clock signal S1 to the input of NOT gate A2. The output of NOT gate A2 is electrically connected to the second input of flip-flop U8. The first output of flip-flop U8 is electrically connected to the first input of NAND gate B1. The second output of flip-flop U8 is electrically connected to the second input of NAND gate B2. The three-phase non-overlapping clock module outputs clock signal S3 to the second input of NAND gate B1 and the first input of NAND gate B2. The output of NAND gate B1 and the input of NOT gate A3 are connected to the input of NAND gate A2. The input terminals of NOT gate A4 and NOT gate B2 are electrically connected, and the output terminal of NOT gate A4 is electrically connected to the input terminal of NOT gate A5. The output terminal of NOT gate B2 and the input terminals of NOT gate A6 and NOT gate A8 are electrically connected, and the output terminal of NOT gate A6 is electrically connected to the input terminal of NOT gate A7. The output terminals of NOT gate A3, NOT gate A5, NOT gate A7, and NOT gate A8 respectively output control signals S3_HY0, S3b_HY0, S3b_HY1, and S3_HY1, which respectively control the on / off state of switches 1S3_HY0, 1S3_HY1, 2S3_HY1, and 2S3_HY0.

[0028] The other ends of switch 1S3_HY0, switch 2S3_HY1, capacitor C1a, capacitor C1b, capacitor C2a, capacitor C2b, capacitor C3a, and capacitor C3b are all grounded.

[0029] Furthermore, the capacitors C1a, C1b, C2a, C2b, C3a, and C3b satisfy the following conditions:

[0030] C1a=C1b=C1;

[0031] C2a=C2b=C2;

[0032] C3a=C3b=C3;

[0033] Where C1 is the capacitance value of capacitors C1a and C1b, C2 is the capacitance value of capacitors C2a and C2b, and C3 is the capacitance value of capacitors C3a and C3b.

[0034] Furthermore, the frequency-to-voltage conversion module includes a monostable multivibrator unit and an active low-pass filter unit;

[0035] The output of the frequency multiplier module is electrically connected to the input of the monostable multivibrator unit, the output of the monostable multivibrator unit is electrically connected to the input of the active low-pass filter unit, and the output of the active low-pass filter unit outputs a voltage signal Vout to the comparator module.

[0036] The monostable multivibrator unit performs pulse shaping on the commutation signal and outputs a pulse wave of the same frequency to the active low-pass filter unit. The active low-pass filter unit converts the pulse wave into a DC voltage signal Vout and outputs it to the comparison module.

[0037] Furthermore, the monostable multivibrator unit includes MOSFET P1, MOSFET P2, MOSFET N17, resistor R14, capacitor C1, NOT gate A9, NOT gate A10, NOT gate A11 and NAND gate B3;

[0038] The output terminal of the frequency multiplier module is electrically connected to the input terminal of NAND gate A9 and the second input terminal of NAND gate B3; the voltage regulator and reference voltage output module outputs a digital voltage V. DD1 To the source of MOSFET P1 and the source of MOSFET P2;

[0039] The output of NOT gate A9 is electrically connected to the gate of MOSFET P1 and the gate of MOSFET N17. The drain of MOSFET P1 is electrically connected to one end of resistor R14. The other end of resistor R14 is electrically connected to one end of capacitor C1, the drain of MOSFET P2, the drain of MOSFET N17, and the input of NOT gate A10. The output of NOT gate A10 and the gate of MOSFET P2 are both electrically connected to the first input of NAND gate B3. The output of NAND gate B3 is electrically connected to the input of NOT gate A11. The output of NOT gate A11 is electrically connected to the input of the active low-pass filter unit.

[0040] The source of the MOS transistor N2 and the other end of the capacitor C2 are both grounded.

[0041] Furthermore, the active low-pass filter unit includes an operational amplifier U9, capacitors C2 and C3, and resistors R15 and R16.

[0042] The output terminal of NOT gate A11 is electrically connected to one end of resistor R15. The other end of resistor R15 is electrically connected to one end of resistor R16 and one end of capacitor C2. The other end of resistor R16 is electrically connected to one end of capacitor C3 and the non-inverting input terminal of operational amplifier U9. The output terminal and the inverting input terminal of operational amplifier U9 are both electrically connected to the other end of capacitor C2, and output voltage signal Vout to the comparator module as the output terminal.

[0043] The other end of capacitor C3 is grounded.

[0044] Furthermore, the comparison module includes comparator U1, comparator U2, comparator U3, comparator U4 and comparator U5;

[0045] The frequency-to-voltage conversion module outputs a voltage signal Vout to the non-inverting inputs of comparators U1, U2, U3, U4, and U5; the voltage regulation and reference voltage output module outputs a reference voltage Vout respectively. REF1 V REF2 V REF3 V REF4 and V REF5 The inverting inputs of comparators U1, U2, U3, U4, and U5 are connected to the inverting input terminals of each comparator. The outputs of comparators U1, U2, U3, U4, and U5 output the comparison result signal DAC. in0 Comparison result signal DAC in1 Comparison result signal DAC in2 Comparison result signal DAC in3 Comparison result signal DAC in4 To the ROM module.

[0046] Furthermore, comparators U1, U2, U3, U4, and U5 are all dynamic latch comparators with hysteresis.

[0047] By adopting the above technical solution, the present invention has the following advantages compared with the prior art:

[0048] The logic control module uses the hysteresis voltage V output by the adjustable hysteresis comparator module. hys The system generates a flip threshold voltage and a commutation signal. The frequency multiplier module amplifies the commutation signal, while the frequency-to-voltage conversion module converts the rotational speed frequency signal into a voltage signal for the comparator module. The comparator module outputs digital codes corresponding to different rotational speed ranges. The ROM module performs index conversion on the digital codes, and the DAC module converts the index-converted signal into a hysteresis control voltage DACout, which is output to the adjustable hysteresis comparator module to adjust the hysteresis voltage V according to the actual rotational speed. hys This causes the hysteresis voltage V to be... hysMatching the rotational speed, the switching threshold voltage output by the logic control module corresponds to the motor speed. The hysteresis window can be dynamically adjusted according to the speed. At low speeds, it has a relatively large hysteresis window, which reduces motor vibration caused by frequent commutation of the coil magnetic field due to noise and other factors. At high speeds, it adaptively switches to a smaller hysteresis window, which helps to reduce the phase delay during coil commutation, synchronizes the coil commutation signal with the rotor position, and improves the stability of the motor when running at high speeds. Attached Figure Description

[0049] Figure 1 This is a block diagram of the motor drive circuit with hysteresis window dynamic speed matching according to the present invention.

[0050] Figure 2 This is a circuit diagram of the adjustable hysteresis comparator module of the motor drive circuit with hysteresis window dynamic speed matching described in this invention.

[0051] Figure 3 This is a ROM module circuit diagram of the motor drive circuit with hysteresis window dynamic speed matching described in this invention.

[0052] Figure 4 This is a circuit diagram of the DAC module of the motor drive circuit with hysteresis window dynamic speed matching described in this invention;

[0053] Figure 5 This is a circuit diagram of the three-phase non-overlapping clock module of the motor drive circuit with hysteresis window dynamic speed matching described in this invention.

[0054] Figure 6 This is a circuit diagram of the frequency-voltage conversion module of the motor drive circuit with hysteresis window dynamic speed matching described in this invention;

[0055] Figure 7 This is a simulation diagram of the DAC module of the motor drive circuit with hysteresis window dynamic speed matching described in this invention;

[0056] Figure 8 This is a simulation diagram of the hysteresis control voltage DACout value corresponding to the six cases of '00000', '00001', etc. in the motor drive circuit with hysteresis window dynamic speed matching described in this invention.

[0057] Figure 9 The simulation waveform of the three-phase non-overlapping clock of the motor drive circuit with hysteresis window dynamic speed matching described in this invention is shown.

[0058] Figure 10 This is a circuit diagram of a 100µs periodic frequency square wave to voltage conversion for a motor drive circuit with hysteresis window dynamic speed matching as described in this invention.

[0059] Figure 11V, which is the motor drive circuit with hysteresis window dynamically matching speed described in this invention. DACout Simulation diagram of hysteresis voltage at 0.5V;

[0060] Figure 12 V, which is the motor drive circuit with hysteresis window dynamically matching speed described in this invention. DACout Simulation diagram of hysteresis voltage at 0.9V;

[0061] Figure 13 V, which is the motor drive circuit with hysteresis window dynamically matching speed described in this invention. DACout Simulation diagram of hysteresis voltage at 1.3V;

[0062] Figure 14 V, which is the motor drive circuit with hysteresis window dynamically matching speed described in this invention. DACout Simulation diagram of hysteresis voltage at 1.7V;

[0063] Figure 15 V, which is the motor drive circuit with hysteresis window dynamically matching speed described in this invention. DACout Simulation diagram of hysteresis voltage at 2.1V;

[0064] Figure 16 V, which is the motor drive circuit with hysteresis window dynamically matching speed described in this invention. DACout Simulation diagram of hysteresis voltage at 2.5V;

[0065] Figure 17 This is a circuit diagram of the voltage regulation and reference voltage output module of the motor drive circuit with hysteresis window dynamic speed matching described in this invention;

[0066] Figure 18 This is a circuit diagram of the H-bridge drive signal output module of the motor drive circuit with hysteresis window dynamic speed matching described in this invention;

[0067] Figure 19 This is a simplified schematic diagram of the H-bridge drive circuit control logic of the H-bridge signal drive module described in this invention.

[0068] Figure 20 This is an oscillator circuit diagram of the motor drive circuit with hysteresis window dynamic speed matching described in this invention. Detailed Implementation

[0069] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0070] Additionally, it should be noted that the terms "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" are all based on the orientation or positional relationship shown in the accompanying drawings. They are merely for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element of the present invention must have a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0071] When an element is referred to as being "fixed to," "set on," or "contained on" another element, it can be directly on or indirectly on that other element. When an element is referred to as being "connected to," it can be directly connected to or indirectly connected to that other element.

[0072] Unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances. Example

[0073] Please refer to Figure 1-20 As shown, this embodiment provides a motor drive circuit for dynamically matching the rotational speed using a hysteresis window, including a Hall voltage output module, an adjustable hysteresis comparator module, a logic control module, a three-phase non-overlapping clock module, a voltage regulator and reference voltage output module, a frequency multiplier module, a frequency-to-voltage conversion module, an H-bridge drive signal output module, a comparator module, a ROM module, and a DAC module.

[0074] The output terminals of the Hall voltage output module and the DAC module are both electrically connected to the adjustable hysteresis comparator module. The Hall voltage output module and the DAC module output the Hall voltage and the hysteresis control voltage DACout to the adjustable hysteresis comparator module, respectively.

[0075] The outputs of the adjustable hysteresis comparator module and the three-phase non-overlapping clock module are both electrically connected to the logic control module. The adjustable hysteresis comparator module and the three-phase non-overlapping clock module respectively output hysteresis voltage V. hys The clock signals S1, S2, and S3 are sent to the logic control module.

[0076] The first and second output terminals of the logic control module are electrically connected to the H-bridge drive signal output terminal module and the frequency multiplier module, respectively. The first and second output terminals output the flip threshold voltage and the commutation signal to the H-bridge drive signal output terminal module and the frequency multiplier module, respectively. The H-bridge drive signal output motor drive signal is sent to the outside.

[0077] The output of the frequency multiplier module is electrically connected to the frequency-to-voltage conversion module. The frequency multiplier module amplifies the commutation signal and outputs it to the frequency-to-voltage conversion module.

[0078] The output of the frequency-to-voltage conversion module is electrically connected to the comparator module. The frequency-to-voltage conversion module converts the amplified commutation signal into a voltage signal Vout and outputs it to the comparator module. The output of the comparator module is electrically connected to the ROM module, and the output of the ROM module is electrically connected to the DAC module. The voltage regulation and reference voltage output module outputs a reference voltage to the comparator module and the DAC module, and outputs a digital voltage Vout. DD1 The voltage signal Vout from the comparison module is compared with the reference voltage and sent to the ROM module for index conversion. The DAC module then converts the index conversion signal into a hysteresis control voltage DACout.

[0079] The two induced voltage signals generated by the Hall effect sensor are amplified by the instrumentation amplifier U6 and then compared by the adjustable hysteresis comparator module. The comparison result is sent to the logic control module, which then outputs the coil magnetic field commutation signal fin, which is related to the motor position and can reflect the state and speed of the motor rotor at this time.

[0080] The commutation signal fin is a square wave signal. After being multiplied by the frequency multiplier module, it is sent to the frequency-to-voltage conversion module to be converted into a DC voltage V. out Then V out By comparing the values ​​with comparators U1 to U5 in the comparison module, the five-bit digital codes DACin0 to DACin4 corresponding to different speed ranges can be obtained. The voltage regulation and reference voltage module generates the reference voltage V. REF V is obtained through resistor voltage division. REF1 To V REF5 The value is shown as the VREF(i) threshold in Table 3. In this embodiment, the comparison module has 6 output combinations, such as '00000' and '00001'. The output result of these 6 combinations after passing through the five-bit DAC is not linear. Therefore, the five-bit digital code DACin0 to DACin4 is first sent to the ROM module and indexed to obtain the corresponding five-bit output codes E0o to E4o. The DAC output voltage corresponding to the new digital code exhibits an arithmetic progression characteristic. Finally, the corresponding hysteresis control voltage DACout is generated by the DAC module, which in turn generates the hysteresis voltage V output by the adjustable hysteresis comparator module. hys Adjust it according to the rotation speed.

[0081] The logic control module uses the hysteresis voltage V output by the adjustable hysteresis comparator module. hysThe system generates a flip threshold voltage and a commutation signal. The frequency multiplier module amplifies the commutation signal, while the frequency-to-voltage conversion module converts the rotational speed frequency signal into a voltage signal for the comparator module. The comparator module outputs digital codes corresponding to different rotational speed ranges. The ROM module performs index conversion on the digital codes, and the DAC module converts the index-converted signal into a hysteresis control voltage DACout, which is output to the adjustable hysteresis comparator module to adjust the hysteresis voltage V according to the actual rotational speed. hys This causes the hysteresis voltage V to be... hys Matching the rotational speed, the switching threshold voltage output by the logic control module corresponds to the motor speed. The hysteresis window can be dynamically adjusted according to the speed. At low speeds, it has a relatively large hysteresis window, which reduces motor vibration caused by frequent commutation of the coil magnetic field due to noise and other factors. At high speeds, it adaptively switches to a smaller hysteresis window, which helps to reduce the phase delay during coil commutation, synchronizes the coil commutation signal with the rotor position, and improves the stability of the motor when running at high speeds.

[0082] Please refer to Figure 3 As shown in the figure, in this embodiment, the ROM module includes three parts: an address decoder, a storage matrix, and an output buffer. E0 to E4 in the figure correspond to the output DACs of comparators U1 to U5 of the comparison module, respectively. in0 To DAC in4 .

[0083] Table 1: Output Signals of the Comparison Module

[0084]

[0085] Table 2: Output Signals After ROM Module Indexing

[0086]

[0087] Combining Table 1 and Table 2, we can obtain the six sets of input signals E0 to E4 corresponding to different speed ranges. After being indexed by the ROM module, they output new output codes E0o to E4o. The remaining input signal code combinations all output "11111" after being indexed.

[0088] Please refer to Figure 4As shown, specifically, the DAC module includes inverters INV1, INV2, INV3, INV4, and INV5; NOR gates NOR1, NOR2, NOR3, NOR4, NOR5, NOR6, NOR7, NOR8, NOR9, NOR10, NOR11, and NOR12; MOSFETs N1 and N2; and MOSFET N3. Transistor N3, MOSFET N4, MOSFET N5, MOSFET N6, MOSFET N7, MOSFET N8, MOSFET N9, MOSFET N10, MOSFET N11, MOSFET N12, MOSFET N13, MOSFET N14, MOSFET N15, MOSFET N16 and resistors R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13.

[0089] The ROM module outputs the first index result E0o to the input of inverter INV1, the first input of NOR5, NOR7, NOR9, and NOR11; the ROM module outputs the second index result E1o to the input of inverter INV2, the second input of NOR5, NOR6, NOR9, and NOR10; the ROM module outputs the third index result. E2o is connected to the input of inverter INV3, the third input of NOR5, NOR6, NOR7, and NOR8; the ROM module outputs the fourth index result E3o to the input of inverter INV4, the second input of NOR2, and the second input of NOR4; the ROM module outputs the fifth index result E4o to the input of inverter INV5, the first input of NOR3, and the first input of NOR4.

[0090] The output of inverter INV1 is electrically connected to the first input of NOR6, NOR8, NOR10, and NOR12; the output of inverter INV2 is electrically connected to the second input of NOR7, NOR8, NOR11, and NOR12; the output of inverter INV3 is electrically connected to the third input of NOR9, NOR10, NOR11, and NOR12; the output of inverter INV4 is electrically connected to the second input of NOR1 and NOR3; and the output of inverter INV5 is electrically connected to the first input of NOR1 and NOR2.

[0091] The output of NOR gate NOR1 is electrically connected to the gates of MOSFETs N1 and N3; the output of NOR gate NOR2 is electrically connected to the gates of MOSFETs N2 and N4; the output of NOR gate NOR3 is electrically connected to the gates of MOSFETs N5 and N7; the output of NOR gate NOR4 is electrically connected to the gates of MOSFETs N6 and N8; the output of NOR gate NOR5 is electrically connected to the gate of MOSFET N9; and the output of NOR gate NOR6 is electrically connected to the gate of MOSFET N9. The output of NOR7 is electrically connected to the gate of MOSFET N10; the output of NOR8 is electrically connected to the gate of MOSFET N12; the output of NOR9 is electrically connected to the gate of MOSFET N13; the output of NOR10 is electrically connected to the gate of MOSFET N14; the output of NOR11 is electrically connected to the gate of MOSFET N15; and the output of NOR12 is electrically connected to the gate of MOSFET N16.

[0092] The voltage regulator and reference voltage output module outputs a reference voltage V. H Connect one end of resistor R1; connect the other end of resistor R1 to one end of resistor R2 and the drain of MOSFET N1; connect the other end of resistor R2 to one end of resistor R3 and the drains of MOSFET N2 and MOSFET N3; connect the other end of resistor R3 to one end of resistor R4 and the drains of MOSFET N4 and MOSFET N5; connect the other end of resistor R4 to one end of resistor R5 and the drains of MOSFET N6 and MOSFET N7; connect the other end of resistor R5 to one end of resistor R6 and the drain of MOSFET N8.

[0093] The sources of MOSFETs N1, N2, N5, and N6 are electrically connected to the other end of resistor R13 and the drain of MOSFET N16; the sources of MOSFETs N3, N4, N7, and N8 are electrically connected to one end of resistor R7 and the drain of MOSFET N9; the other end of resistor R7 is electrically connected to one end of resistor R8 and the drain of MOSFET N10; resistor R... The other end of resistor 8 is electrically connected to one end of resistor R9 and the drain of MOSFET N11; the other end of resistor R9 is electrically connected to one end of resistor R10 and the drain of MOSFET N12; the other end of resistor R10 is electrically connected to one end of resistor R11 and the drain of MOSFET N13; the other end of resistor R11 is electrically connected to one end of resistor R12 and the drain of MOSFET N14; the other end of resistor R12 is electrically connected to one end of resistor R13 and the drain of MOSFET N15.

[0094] The source of MOSFET N9 is electrically connected to the sources of MOSFETs N10, N11, N12, N13, N14, N15, and N16, and serves as the output terminal to output the hysteresis control voltage DACout to the adjustable hysteresis comparator module; the other end of resistor R6 is grounded.

[0095] Furthermore, resistors R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, and R13 satisfy the following condition:

[0096] R1=5Rsh; R2=R3=R4=R5=R6=Rsh; R7=R8=R9=R10=R11=R12=R13=2Rsh;

[0097] Where Rsh is the unit resistance value.

[0098] Therefore,

[0099] ;

[0100] Among them, V DACout K represents the voltage value of the hysteresis control voltage DACout. E4E3 and K E2E1E0 These are the high two and low three scaling factors of the DAC module, and they satisfy the following relationship with the input signal:

[0101] ;

[0102] ;

[0103] When '00000' is entered in E0o to E4o, V DACout The minimum value is 0.1V H When '11111' is entered, V DACout The maximum value is 0.5V H Combined with the appendix Figure 7 Different DAC inputs are used to input V. H Under the condition of 5V, the hysteresis control voltage DACout can output 32 voltage values ​​in the range of (0.5V, 2.5V), which is consistent with the calculated value.

[0104] Please refer to the appendix. Figure 8 The six output combinations of the comparison module, such as '00000' and '00001', are passed through the ROM indexing module to obtain new combinations 'E0o E1o E2o E3o E4o'. After being decoded by the DAC module, the outputs are 0.504V, 0.905V, 1.275V, 1.711V, 2.081V, and 2.482V, respectively, which correspond to the output results in Table 2.

[0105] Please refer to the appendix. Figure 1 and Figure 2 The Hall voltage output module includes a Hall disk and an instrumentation amplifier U6; the adjustable hysteresis comparator module includes a hysteresis comparator U7, switches 1S3_HY0, 1S3_HY1, 2S3_HY0, 2S3_HY1, 1S1, 1S2, 1S3, 2S1, 2S2, 2S3, 3S1, 3S2, 3S3, 4S1, 4S2, 4S3, capacitors C1a, C1b, C2a, C2b, C3a, C3b, trigger U8, NOT gates A1, A2, A3, A4, A5, A6, A7, A8, and NAND gates B1 and B2.

[0106] The DAC module outputs a hysteresis control voltage DACout to one end of switch 1S3_HY1 and one end of switch 2S3_HY0; the other end of switch 1S3_HY1 is electrically connected to one end of switch 1S3_HY0, one end of capacitor C1a, and the non-inverting input of hysteresis comparator U7; the other end of switch 2S3_HY0 is electrically connected to one end of switch 2S3_HY1, one end of capacitor C1b, and the inverting input of hysteresis comparator U7.

[0107] The Hall effect sensor outputs an induced voltage VIN1 to one end of switch 1S3 and one end of switch 2S2. The Hall effect sensor outputs an induced voltage VIN2 to one end of switch 1S2 and one end of switch 2S3. The other ends of switches 1S3 and 1S2 are electrically connected to the first input terminal of instrumentation amplifier U6. The other ends of switches 2S2 and 2S3 are electrically connected to the second input terminal of instrumentation amplifier U6. The first output terminal of instrumentation amplifier U6 outputs a Hall voltage Vo1 to one end of switch 3S2 and one end of switch 3S3. The other end of switch 3S2 is electrically connected to one end of switch 1S1 and one end of capacitor C2a. The other end of switch 3S3 is electrically connected to one end of switch 2S1 and one end of capacitor C3a.

[0108] The second output terminal of the instrumentation amplifier U6 outputs Hall voltage Vo2 to one end of switch 4S2 and one end of switch 4S3. The other end of switch 4S2 is electrically connected to one end of switch 4S1, the other end of switch 2S1, and one end of capacitor C2b. The other end of switch 4S3 is electrically connected to one end of capacitor C3b, one end of switch 3S1, and the other end of switch 1S1. The other end of switch 3S1 is electrically connected to the non-inverting input terminal of hysteresis comparator U7, and the other end of switch 4S1 is electrically connected to the inverting input terminal of hysteresis comparator U7.

[0109] The output of hysteresis comparator U7 is electrically connected to the input of NOT gate A1. The output of NOT gate A1 is electrically connected to the first input of flip-flop U8. The three-phase non-overlapping clock module outputs clock signal S1 to the input of NOT gate A2. The output of NOT gate A2 is electrically connected to the second input of flip-flop U8. The first output of flip-flop U8 is electrically connected to the first input of NAND gate B1. The second output of flip-flop U8 is electrically connected to the second input of NAND gate B2. The three-phase non-overlapping clock module outputs clock signal S3 to the second input of NAND gate B1 and the first input of NAND gate B2. The output of NAND gate B1 is connected to the input of NOT gate A3. The input terminals of NOT gate A4 are electrically connected, and the output terminal of NOT gate A4 is electrically connected to the input terminal of NOT gate A5; the output terminal of NAND gate B2 is electrically connected to the input terminals of NOT gate A6 and NOT gate A8, and the output terminal of NOT gate A6 is electrically connected to the input terminal of NOT gate A7; the output terminals of NOT gate A3, NOT gate A5, NOT gate A7, and NOT gate A8 respectively output control signals S3_HY0, S3b_HY0, S3b_HY1, and S3_HY1, which respectively control the on / off state of switches 1S3_HY0, 1S3_HY1, 2S3_HY1, and 2S3_HY0.

[0110] The other ends of switch 1S3_HY0, switch 2S3_HY1, capacitor C1a, capacitor C1b, capacitor C2a, capacitor C2b, capacitor C3a, and capacitor C3b are all grounded.

[0111] Furthermore, capacitors C1a, C1b, C2a, C2b, C3a, and C3b satisfy the following conditions:

[0112] C1a=C1b=C1;

[0113] C2a=C2b=C2;

[0114] C3a=C3b=C3;

[0115] Where C1 is the capacitance value of capacitors C1a and C1b, C2 is the capacitance value of capacitors C2a and C2b, and C3 is the capacitance value of capacitors C3a and C3b.

[0116] Switches 1S1, 2S1, 3S1, and 4S1 are controlled by clock signal S1 and its inverted signal; switches 1S2, 2S2, 3S2, and 4S2 are controlled by clock signal S2 and its inverted signal; switches 1S3, 2S3, 3S3, and 4S3 are controlled by clock signal S3 and signal S3b. Clock signals S1, S2, and S3 are three-phase non-overlapping clock signals, with only one clock signal being 1 at any given time; signal S3b is the inverted signal generated by the inverter of clock signal S3.

[0117] Control signals S3_HY0 and S3_HY1 are hysteresis control signals, output by hysteresis comparator U7. HYCOMP_Y The clock signals S1 and S3 are generated by a logic circuit consisting of NAND gates, NOT gates, and flip-flops.

[0118] When V HYCOMP_Y When = 0, control signal S3_HY0 outputs signal S3, control signal S3b_HY0 outputs signal S3b, control signal S3_HY1 is always 0, and control signal S3b_HY1 is always 1.

[0119] When V HYCOMP_YWhen =1, control signal S3_HY0 is always 0, control signal S3b_HY0 is always 1, control signal S3_HY1 outputs signal S3, and control signal S3b_HY1 outputs signal S3b. Control signals S3_HY0, S3b_HY0, S3_HY1, and S3b_HY1 control the on / off states of switches 1S3_HY0, 1S3_HY1, 2S3_HY0, and 2S3_HY1, respectively.

[0120] The voltage V at the non-inverting input of the hysteresis comparator U7 inp_comp In the first two phases, the capacitor charge satisfies the following relationship:

[0121] Clock signal S2=1:

[0122] ;

[0123] Clock signal S3=1:

[0124] ;

[0125] ;

[0126] Among them, V CTRL The hysteresis control voltage, also known as the voltage that controls the amount of charge, is V. CTRL The DACout value is set at time S3_HY1=1, and the control signal is set to 0 at time S3_HY0=1. Q2 represents the accumulated charge on capacitor C2a at time S2=1, and Q1 and Q3 represent the accumulated charges on capacitors C1a and C3a at time S3=1, respectively. The accumulated charges on capacitors C2b and C3b are equal to the charges on capacitors C2a and C3a, respectively. The charges on capacitors C1a and C1b depend on V. CTRL V O1_S2 The output voltage Vo1 of amplifier U6 for the timekeeping device is given by clock signal S2=1. O2_S3 Vo2 is the output voltage of amplifier U6 for the timekeeping device when the clock signal S3=1 is 1.

[0127] Switches 1S2, 2S2, 3S2, 4S2 and 1S3, 2S3, 3S3, 4S3 are chopper switches to reduce input offset and low-frequency noise. Therefore, the clock signal S2=1, and the output voltage V at the VO1 terminal of the timekeeping amplifier U6 is... O1_S2 And the clock signal S3=1, the timekeeping amplifier U6 outputs voltage V at the VO2 terminal. O2_S3 Equal, i.e., V O1_S2 =V O2_S3 V will be used consistently throughout this text. O1_S2 Refers to.

[0128] Hysteresis comparator U7 performs comparisons only when the clock signal S1=1, at which time the voltage V at the non-inverting input is... inp_comp for

[0129] ;

[0130] After sorting, we can obtain

[0131] ;

[0132] make,

[0133] ;

[0134] but,

[0135] ;

[0136] Therefore, the voltage at the non-inverting input of the hysteresis comparator U7 is determined by the hysteresis control voltage V. CTRL and the output voltage V of instrumentation amplifier U6 O1_S2 Together, they decided to control the hysteresis control voltage V. CTRL The size can control the hysteresis.

[0137] The hysteresis voltage at the non-inverting and inverting inputs of the hysteresis comparator U7 is expressed as V. CTRL+ and V CTRL- At this time, the voltage V at the non-inverting input terminal inp_comp and the voltage at the inverting input terminal V inn_comp They are respectively,

[0138] ;

[0139] ;

[0140] The difference between the non-inverting and inverting inputs of the hysteresis comparator U7 is,

[0141] ;

[0142] Right now,

[0143] ;

[0144] When the clock signal S1=1, the hysteresis comparator U7 performs a comparison, and the hysteresis control voltage V... CTRL The value is determined by the DAC module and controlled by the output of the hysteresis comparator U7, that is,

[0145] When V HYCOMP_Y When =1,

[0146] = ;

[0147] = ;

[0148] but,

[0149] ;

[0150] at this time,

[0151] .

[0152] When V HYCOMP_Y When =0,

[0153] =0;

[0154] = ;

[0155] but,

[0156] ;

[0157] at this time,

[0158] And the absolute value gradually increases.

[0159] Therefore, for the hysteresis comparator U7 to flip when its output is 1, the following conditions must be met:

[0160] ,

[0161] Right now,

[0162] Let be the inversion point of the comparator output. Substituting this into the above equation, we can obtain...

[0163] ;

[0164] The voltage difference V between the non-inverting and inverting inputs of the comparator at this time O1_S2 -V O2_S2 Let it be hysteresis voltage V y=1，hys ,but,

[0165] ;

[0166] At this time, V y=1，hys <0, and the absolute value gradually increases.

[0167] Similarly, when the output of the hysteresis comparator U7 is 0, then...

[0168] ;

[0169] For the hysteresis comparator U7 to flip, the following conditions must be met:

[0170] ;

[0171] Right now,

[0172] Let U be the toggling point of the hysteresis comparator U7. Substituting this into the above equation, we can obtain...

[0173] ;

[0174] The current flip voltage difference V O1_S2 -V O2_S2 Let it be hysteresis voltage V y=0，hys ,but,

[0175] ;

[0176] At this time, V y=1，hys >0, and the absolute value gradually increases.

[0177] Therefore, the hysteresis voltage V y=1，hys and hysteresis voltage V y=0，hys The voltage V is output by the DAC module respectively. DACout The ratio of capacitance k c Jointly decided, k c and V DACout The larger the value, the greater the hysteresis voltage V. hys The larger.

[0178] In this embodiment, a fixed capacitance ratio k is used. c Adjust only the DAC module output voltage V DACout The method used to control the hysteresis voltage V output of the hysteresis comparator U7 hys Different V values ​​are set according to the rotational speed. DACout The value of can then be used to match the speed information with the comparator's hysteresis. The output signal of the adjustable hysteresis comparator module, after passing through the logic control module and the H-bridge drive signal output module, outputs OUT1 and OUT2 signals, which can be used for coil magnetic field control, thereby obtaining a motor coil magnetic field commutation hysteresis window whose magnitude matches the speed. In this embodiment, the H-bridge drive signal output module includes an H-bridge drive unit and an H-bridge unit electrically connected in sequence, with the H-bridge unit outputting OUT1 and OUT2 signals. In this embodiment,

[0179] The logic control module is a digital logic module responsible for converting the output signal of the adjustable hysteresis comparator into the commutation signal HYCOMP_S1_Y and implementing functions such as stall protection. The commutation signal is inverted compared to the output of the adjustable hysteresis comparator. The frequency multiplier module can be either a digital frequency multiplier or an external MCU for frequency multiplication.

[0180] Please refer to the appendix. Figure 17 The voltage regulation and reference voltage module includes a bandgap voltage source, an LDO module, and a resistor divider module. It is responsible for providing reference voltages VREF1-VREF5 to the comparator module, reference voltage VH to the DAC module, and power supply VDD1 to the other modules.

[0181] Please refer to the attached document. Figure 18 The H-bridge drive signal output module includes an H-bridge circuit and an H-bridge drive circuit. It is responsible for providing motor drive signals OU1 and OUT2, which are related to the commutation signal HYCOMP_S1_Y and have dead time.

[0182] Please refer to the attached document. Figure 19 The control logic of the H-bridge driver circuit is simplified. The dead-time control logic in the H-bridge driver signal output module is achieved by setting an RS flip-flop and an inverter delay chain to ensure a time difference between the high-side P-channel gate drive signal 'a' and the low-side N-channel gate drive signal 'c', and between the high-side P-channel gate drive signal 'b' and the low-side N-channel gate drive signal 'd'. Normally, in a stable state, signals a and c are in phase, b and d are in phase, and a and c are out of phase with b and d. Taking signals a and c as an example, when signals a and c switch from low to high, signal a switches to high first. After a dead time, signal c switches to high to prevent the high-side P-channel and ground-side N-channel from conducting simultaneously and generating a large current.

[0183] Please refer to the appendix. Figure 20 The oscillator module generates a square wave signal CLK to provide a clock for the three-phase non-overlapping clock module.

[0184] Please refer to the appendix. Figure 1 and Figure 5 In this embodiment, the three-phase non-overlapping clock module consists of a frequency divider circuit and a delay inverter chain, and CLK is the square wave signal generated by the oscillator module. (See attached diagram.) Figure 9 The input signal CLK is processed by a three-phase non-overlapping clock module to obtain clock signals S1, S2 and S3, and the three-phase clock signals do not overlap.

[0185] Please refer to the appendix. Figure 6The frequency-to-voltage conversion module includes a monostable multiplier unit and an active low-pass filter unit. The output of the frequency multiplier module is electrically connected to the input of the monostable multiplier unit, and the output of the monostable multiplier unit is electrically connected to the input of the active low-pass filter unit. The output of the active low-pass filter unit is a voltage signal Vout sent to the comparator module. The monostable multiplier unit performs pulse shaping on the commutation signal and outputs a pulse wave of the same frequency to the active low-pass filter unit. The active low-pass filter unit converts the pulse wave into a DC voltage signal Vout and outputs it to the comparator module.

[0186] Specifically, the monostable multivibrator unit includes MOSFETs P1, P2, and N17, resistor R14, capacitor C1, NOT gates A9, A10, and A11, and NAND gate B3. The output terminal of the frequency multiplier module is electrically connected to the input terminal of NAND gate A9 and the second input terminal of NAND gate B3; the voltage regulator and reference voltage output module outputs a digital voltage V. DD1 The source terminals of MOSFETs P1 and P2 are connected to each other. The output terminal of NOT gate A9 is electrically connected to the gate of MOSFET P1 and the gate of MOSFET N17. The drain of MOSFET P1 is electrically connected to one end of resistor R14. The other end of resistor R14 is electrically connected to one end of capacitor C1, the drain of MOSFET P2, the drain of MOSFET N17, and the input terminal of NOT gate A10. The output terminal of NOT gate A10 and the gate of MOSFET P2 are both electrically connected to the first input terminal of NOT gate B3. The output terminal of NOT gate B3 is electrically connected to the input terminal of NOT gate A11. The output terminal of NOT gate A11 is electrically connected to the input terminal of the active low-pass filter unit.

[0187] The source of MOSFET N2 and the other end of capacitor C2 are both grounded.

[0188] Pulse shaping is performed using resistor R14 and capacitor C1 to convert square waves of different frequencies into pulse waves of the same frequency. The transient time, i.e., the charging and discharging speed of the RC circuit, is related to the time constant formed by resistor R14 and C1.

[0189] The active low-pass filter unit includes operational amplifier U9, capacitors C2 and C3, and resistors R15 and R16. The output of NOT gate A11 is electrically connected to one end of resistor R15. The other end of resistor R15 is electrically connected to one end of resistor R16 and one end of capacitor C2. The other end of resistor R16 is electrically connected to one end of capacitor C3 and the non-inverting input of operational amplifier U9. Both the output and inverting input of operational amplifier U9 are electrically connected to the other end of capacitor C2, serving as the output voltage signal Vout to the comparator module. The other end of capacitor C3 is grounded.

[0190] The active low-pass filter unit converts the pulse wave generated by the preceding monostable multivibrator unit into a matching DC voltage signal. The value of this voltage signal is determined by the average value of the pulse signal.

[0191] ;

[0192] Where D is the duty cycle, V DD1 The voltage regulator and reference voltage output module outputs a digital voltage value. In this embodiment, the active low-pass filter unit is a second-order SK low-pass filter, which has higher filtering efficiency than a first-order low-pass filter.

[0193] The commutation signal fin, which is related to the motor speed, is output by the logic control module and multiplied by a frequency multiplier module to facilitate frequency-to-voltage conversion in subsequent stages. The EN signal allows selection between internal frequency multiplier and external MCU frequency multiplication modes. The multiplied commutation signal has a frequency of 100*fin and is a square wave signal. The input square wave signal is first shaped by a monostable multivibrator unit to form a pulse waveform with a fixed pulse width of 25µs and a frequency of 100*fin. The specific correspondence is shown in Table 3.

[0194] Table 3: Correspondence Table of Speed ​​Matching Thresholds

[0195]

[0196] T / 100 is the signal period after frequency doubling. This signal satisfies the condition that it is less than 50us when the speed is higher than 12000rpm and higher than 2000us when the speed is lower than 300rpm. This makes the signal frequency much higher than the cutoff frequency of the active low-pass filter unit, thereby outputting a smooth DC voltage with less ripple.

[0197] The pulse signal output from the monostable multivibrator unit is demodulated by a second-order SK low-pass filter to obtain a DC voltage signal. Based on the ratio of the pulse width to the period of the pulse signal, the corresponding output voltage can be obtained. The theoretical output voltage values ​​corresponding to speeds from 300 to 12000 rpm are 0.0625 to 2.5V, respectively. Therefore, the reference voltage VREF of comparator groups U1 to U5 can be set to values ​​from 0.1 to 2.3V.

[0198] Combined with appendix Figure 10 Taking a square wave with a rotational speed of 6000 rpm (i.e., a frequency multiplier and an input period of 100 µs) as an example, the frequency-multiplied commutation signal T / 100, after passing through a monostable multivibrator unit, converts the 50 µs pulse-width square wave into a pulse wave with a pulse width of 25 µs and a period of 100 µs. After demodulation by a second-order SK low-pass filter, the output V is... out The value is 1.235V, which is basically consistent with the theoretical value in Table 3.

[0199] Please refer to the appendix. Figure 1 The comparison module includes comparator U1, comparator U2, comparator U3, comparator U4 and comparator U5.

[0200] The frequency-to-voltage conversion module outputs a voltage signal Vout to the non-inverting inputs of comparators U1, U2, U3, U4, and U5; the voltage regulation and reference voltage output modules output a reference voltage Vout respectively. REF1 V REF2 V REF3 V REF4 and V REF5 The comparison result signal DAC is output from the inverting inputs of comparators U1, U2, U3, U4, and U5; the outputs of comparators U1, U2, U3, U4, and U5 are connected to the inverting inputs of comparators U1, U2, U3, U4, and U5. in0 Comparison result signal DAC in1 Comparison result signal DAC in2 Comparison result signal DAC in3 Comparison result signal DAC in4 To the ROM module.

[0201] Specifically, comparators U1, U2, U3, U4, and U5 are all dynamic latch comparators with hysteresis. This effectively avoids VL. out Voltage at reference voltage V REF1 To V REF5 During comparison, the output oscillates repeatedly near the critical point.

[0202] As can be seen from the above, the output voltage V of the DAC module DACout A quantity related to rotational speed, meaning that different speed ranges have different V values. DACout Output; while the DAC module output voltage V DACout The output hysteresis voltage V of the adjustable hysteresis comparator module hys To better illustrate the hysteresis voltage V of the hysteresis comparator U7, adjustments are made. hys In this embodiment, a larger V is used in relation to the rotational speed. DACout To obtain a larger value of hysteresis voltage V hys In practical use, adjust the reference voltage V of the DAC module. H V can be adjusted as needed DACout The value of .

[0203] Please refer to the appendix. Figure 11 -Appendix Figure 16Simulations were performed on input commutation signals within different frequency ranges, V out This is the output voltage of the frequency-to-voltage conversion module. V out The voltage ranges from approximately 50mV to 2.5V, with the corresponding output voltage value V varying depending on the frequency. out V in the diagram DACout This is the output voltage of the DAC module, i.e., the hysteresis control voltage. V out and V DACout The simulated values ​​are basically consistent with the theoretical values ​​in Tables 2 and 3.

[0204] V HYCOMP_Y The output voltage of the hysteresis comparator U7 is the threshold voltage, which is affected by the hysteresis voltage V of the hysteresis comparator U7. hys Control. Simulation results show that V... DACout The value is between 0.5V and 2.48V, and the corresponding hysteresis voltage V hys (HP1-HP3 in the simulation diagram) and V DACout There is a positive correlation, and the voltage fluctuates between approximately 0.15V and 0.6V. The higher the rotational speed, the higher the voltage (V). DACout The larger the value, the greater the hysteresis voltage V. hys The lower the value, and at low speeds, V DACout The smaller the value, the lower the hysteresis voltage V. hys The higher.

[0205] The results demonstrate that the motor drive circuit with dynamically matched hysteresis window speed disclosed in this embodiment can dynamically adjust the hysteresis window according to the rotational speed. This feature allows the chip to have a relatively large hysteresis window at low speeds, reducing motor jitter caused by noise-induced false triggering at low speeds. Furthermore, it can adaptively switch to a smaller hysteresis window at high speeds, which helps reduce phase delay during coil commutation and improves the stability of the motor during high-speed operation.

[0206] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A motor drive circuit for dynamically matching rotational speed using a hysteresis window, characterized in that, It includes a Hall voltage output module, an adjustable hysteresis comparator module, a logic control module, a three-phase non-overlapping clock module, a voltage regulator and reference voltage output module, a frequency multiplier module, a frequency-to-voltage conversion module, an H-bridge drive signal output module, a comparator module, a ROM module, and a DAC module; The output terminals of the Hall voltage output module and the DAC module are both electrically connected to the adjustable hysteresis comparator module. The Hall voltage output module and the DAC module output Hall voltage and hysteresis control voltage DACout to the adjustable hysteresis comparator module, respectively. The output terminals of the adjustable hysteresis comparator module and the three-phase non-overlapping clock module are both electrically connected to the logic control module. The adjustable hysteresis comparator module and the three-phase non-overlapping clock module respectively output hysteresis voltage V. hys The clock signals S1, S2, and S3 are sent to the logic control module; The first and second output terminals of the logic control module are electrically connected to the H-bridge drive signal output module and the frequency multiplier module, respectively. The first and second output terminals output a flip threshold voltage and a commutation signal to the H-bridge drive signal output module and the frequency multiplier module, respectively. The H-bridge drive signal outputs a motor drive signal to the outside. The output terminal of the frequency multiplier module is electrically connected to the frequency-to-voltage conversion module. The frequency multiplier module amplifies the commutation signal and outputs it to the frequency-to-voltage conversion module. The output of the frequency-to-voltage conversion module is electrically connected to the comparator module. The frequency-to-voltage conversion module converts the amplified commutation signal into a voltage signal Vout and outputs it to the comparator module. The output of the comparator module is electrically connected to the ROM module, and the output of the ROM module is electrically connected to the DAC module. The voltage regulator and reference voltage output module outputs a reference voltage to the comparator module and the DAC module, and outputs a digital voltage Vout. DD1 The comparison module outputs a voltage signal Vout to the ROM module and a frequency-to-voltage conversion module; the comparison result between the voltage signal Vout and the reference voltage is sent to the ROM module for index conversion; the DAC module converts the index conversion signal into a hysteresis control voltage DACout.

2. The motor drive circuit with hysteresis window dynamic speed matching according to claim 1, characterized in that: The DAC module includes inverters INV1, INV2, INV3, INV4, and INV5; NOR gates NOR1, NOR2, NOR3, NOR4, NOR5, NOR6, NOR7, NOR8, NOR9, NOR10, NOR11, and NOR12; and MOSFETs N1, N2, and N3. MOSFETs N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15, and N16, and resistors R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, and R13; The ROM module outputs the first index result E0o to the input of inverter INV1, the first input of NOR5, NOR7, NOR9, and NOR11; the ROM module outputs the second index result E1o to the input of inverter INV2, the second input of NOR5, NOR6, NOR9, and NOR10; the ROM module outputs the third index result... The ROM module outputs the fourth index result E3o to the input of inverter INV3, the third input of NOR5, NOR6, NOR7, and NOR8; and the ROM module outputs the fifth index result E4o to the input of inverter INV5, the first input of NOR3, and the first input of NOR4. The output of inverter INV1 is electrically connected to the first input of NOR6, NOR8, NOR10, and NOR12; the output of inverter INV2 is electrically connected to the second input of NOR7, NOR8, NOR11, and NOR12; the output of inverter INV3 is electrically connected to the third input of NOR9, NOR10, NOR11, and NOR12; the output of inverter INV4 is electrically connected to the second input of NOR1 and NOR3; and the output of inverter INV5 is electrically connected to the first input of NOR1 and NOR2. The output of NOR1 is electrically connected to the gates of MOSFETs N1 and N3; the output of NOR2 is electrically connected to the gates of MOSFETs N2 and N4; the output of NOR3 is electrically connected to the gates of MOSFETs N5 and N7; the output of NOR4 is electrically connected to the gates of MOSFETs N6 and N8; the output of NOR5 is electrically connected to the gate of MOSFET N9; and the output of NOR6... The output of NOR7 is electrically connected to the gate of MOSFET N10; the output of NOR8 is electrically connected to the gate of MOSFET N12; the output of NOR9 is electrically connected to the gate of MOSFET N13; the output of NOR10 is electrically connected to the gate of MOSFET N14; the output of NOR11 is electrically connected to the gate of MOSFET N15; and the output of NOR12 is electrically connected to the gate of MOSFET N16. The voltage regulator and reference voltage output module outputs a reference voltage V. H One end of resistor R1 is connected to the resistor; the other end of resistor R1 is electrically connected to one end of resistor R2 and the drain of MOSFET N1; the other end of resistor R2 is electrically connected to one end of resistor R3 and the drains of MOSFET N2 and MOSFET N3; the other end of resistor R3 is electrically connected to one end of resistor R4 and the drains of MOSFET N4 and MOSFET N5; the other end of resistor R4 is electrically connected to one end of resistor R5 and the drains of MOSFET N6 and MOSFET N7; the other end of resistor R5 is electrically connected to one end of resistor R6 and the drain of MOSFET N8. The sources of MOSFETs N1, N2, N5, and N6 are all electrically connected to the other end of resistor R13 and the drain of MOSFET N16; the sources of MOSFETs N3, N4, N7, and N8 are all electrically connected to one end of resistor R7 and the drain of MOSFET N9; the other end of resistor R7 is electrically connected to one end of resistor R8 and the drain of MOSFET N10; the resistor R... The other end of resistor 8 is electrically connected to one end of resistor R9 and the drain of MOSFET N11; the other end of resistor R9 is electrically connected to one end of resistor R10 and the drain of MOSFET N12; the other end of resistor R10 is electrically connected to one end of resistor R11 and the drain of MOSFET N13; the other end of resistor R11 is electrically connected to one end of resistor R12 and the drain of MOSFET N14; the other end of resistor R12 is electrically connected to one end of resistor R13 and the drain of MOSFET N15. The source of MOSFET N9 is electrically connected to the sources of MOSFETs N10, N11, N12, N13, N14, N15, and N16, and serves as the output terminal to output the hysteresis control voltage DACout to the adjustable hysteresis comparator module; the other end of resistor R6 is grounded.

3. The motor drive circuit with hysteresis window dynamic speed matching according to claim 2, characterized in that: The resistors R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, and R13 satisfy the following condition: R1=5Rsh; R2=R3=R4=R5=R6=Rsh; R7=R8=R9=R10=R11=R12=R13=2Rsh; Where Rsh is the unit resistance value.

4. The motor drive circuit with hysteresis window dynamic speed matching according to claim 1, characterized in that: The Hall voltage output module includes a Hall disk and an instrumentation amplifier U6; the adjustable hysteresis comparator module includes a hysteresis comparator U7, switches 1S3_HY0, 1S3_HY1, 2S3_HY0, 2S3_HY1, 1S1, 1S2, 1S3, 2S1, 2S2, 2S3, 3S1, 3S2, 3S3, 4S1, 4S2, 4S3, capacitors C1a, C1b, C2a, C2b, C3a, C3b, trigger U8, NOT gates A1, A2, A3, A4, A5, A6, A7, A8, and NAND gates B1 and B2; The DAC module outputs a hysteresis control voltage DACout to one end of switch 1S3_HY1 and one end of switch 2S3_HY0; the other end of switch 1S3_HY1 is electrically connected to one end of switch 1S3_HY0, one end of capacitor C1a, and the non-inverting input of hysteresis comparator U7; the other end of switch 2S3_HY0 is electrically connected to one end of switch 2S3_HY1, one end of capacitor C1b, and the inverting input of hysteresis comparator U7. The Hall effect sensor outputs an induced voltage VIN1 to one end of switch 1S3 and one end of switch 2S2. The Hall effect sensor outputs an induced voltage VIN2 to one end of switch 1S2 and one end of switch 2S3. The other ends of switch 1S3 and switch 1S2 are electrically connected to the first input terminal of instrumentation amplifier U6. The other ends of switch 2S2 and switch 2S3 are electrically connected to the second input terminal of instrumentation amplifier U6. The first output terminal of instrumentation amplifier U6 outputs a Hall voltage Vo1 to one end of switch 3S2 and one end of switch 3S3. The other end of switch 3S2 is electrically connected to one end of switch 1S1 and one end of capacitor C2a. The other end of switch 3S3 is electrically connected to one end of switch 2S1 and one end of capacitor C3a. The second output terminal of the instrumentation amplifier U6 outputs Hall voltage Vo2 to one end of switch 4S2 and one end of switch 4S3. The other end of switch 4S2 is electrically connected to one end of switch 4S1, the other end of switch 2S1, and one end of capacitor C2b. The other end of switch 4S3 is electrically connected to one end of capacitor C3b, one end of switch 3S1, and the other end of switch 1S1. The other end of switch 3S1 is electrically connected to the non-inverting input terminal of hysteresis comparator U7, and the other end of switch 4S1 is electrically connected to the inverting input terminal of hysteresis comparator U7. The output of the hysteresis comparator U7 is electrically connected to the input of NOT gate A1. The output of NOT gate A1 is electrically connected to the first input of flip-flop U8. The three-phase non-overlapping clock module outputs clock signal S1 to the input of NOT gate A2. The output of NOT gate A2 is electrically connected to the second input of flip-flop U8. The first output of flip-flop U8 is electrically connected to the first input of NAND gate B1. The second output of flip-flop U8 is electrically connected to the second input of NAND gate B2. The three-phase non-overlapping clock module outputs clock signal S3 to the second input of NAND gate B1 and the first input of NAND gate B2. The output of NAND gate B1 and the input of NOT gate A3 are connected to the input of NAND gate A2. The input terminals of NOT gate A4 and NOT gate B2 are electrically connected, and the output terminal of NOT gate A4 is electrically connected to the input terminal of NOT gate A5. The output terminal of NOT gate B2 and the input terminals of NOT gate A6 and NOT gate A8 are electrically connected, and the output terminal of NOT gate A6 is electrically connected to the input terminal of NOT gate A7. The output terminals of NOT gate A3, NOT gate A5, NOT gate A7, and NOT gate A8 respectively output control signals S3_HY0, S3b_HY0, S3b_HY1, and S3_HY1, which respectively control the on / off state of switches 1S3_HY0, 1S3_HY1, 2S3_HY1, and 2S3_HY0. The other ends of switch 1S3_HY0, switch 2S3_HY1, capacitor C1a, capacitor C1b, capacitor C2a, capacitor C2b, capacitor C3a, and capacitor C3b are all grounded.

5. The motor drive circuit with hysteresis window dynamic speed matching according to claim 4, characterized in that: The capacitors C1a, C1b, C2a, C2b, C3a, and C3b satisfy the following conditions. C1a=C1b=C1; C2a=C2b=C2; C3a=C3b=C3; Where C1 is the capacitance value of capacitors C1a and C1b, C2 is the capacitance value of capacitors C2a and C2b, and C3 is the capacitance value of capacitors C3a and C3b.

6. The motor drive circuit with hysteresis window dynamic speed matching according to claim 1, characterized in that: The frequency-to-voltage conversion module includes a monostable trigger unit and an active low-pass filter unit; The output of the frequency multiplier module is electrically connected to the input of the monostable multivibrator unit, the output of the monostable multivibrator unit is electrically connected to the input of the active low-pass filter unit, and the output of the active low-pass filter unit outputs a voltage signal Vout to the comparator module. The monostable multivibrator unit performs pulse shaping on the commutation signal and outputs a pulse wave of the same frequency to the active low-pass filter unit. The active low-pass filter unit converts the pulse wave into a DC voltage signal Vout and outputs it to the comparison module.

7. The motor drive circuit with hysteresis window dynamic speed matching according to claim 6, characterized in that: The monostable multivibrator unit includes MOSFET P1, MOSFET P2, MOSFET N17, resistor R14, capacitor C1, NOT gate A9, NOT gate A10, NOT gate A11 and NAND gate B3; The output terminal of the frequency multiplier module is electrically connected to the input terminal of NAND gate A9 and the second input terminal of NAND gate B3; the voltage regulator and reference voltage output module outputs a digital voltage V. DD1 To the source of MOSFET P1 and the source of MOSFET P2; The output of NOT gate A9 is electrically connected to the gate of MOSFET P1 and the gate of MOSFET N17. The drain of MOSFET P1 is electrically connected to one end of resistor R14. The other end of resistor R14 is electrically connected to one end of capacitor C1, the drain of MOSFET P2, the drain of MOSFET N17, and the input of NOT gate A10. The output of NOT gate A10 and the gate of MOSFET P2 are both electrically connected to the first input of NAND gate B3. The output of NAND gate B3 is electrically connected to the input of NOT gate A11. The output of NOT gate A11 is electrically connected to the input of the active low-pass filter unit. The source of the MOS transistor N2 and the other end of the capacitor C2 are both grounded.

8. The motor drive circuit with hysteresis window dynamic speed matching according to claim 7, characterized in that: The active low-pass filter unit includes an operational amplifier U9, capacitor C2, capacitor C3, and resistors R15 and R16. The output terminal of NOT gate A11 is electrically connected to one end of resistor R15. The other end of resistor R15 is electrically connected to one end of resistor R16 and one end of capacitor C2. The other end of resistor R16 is electrically connected to one end of capacitor C3 and the non-inverting input terminal of operational amplifier U9. The output terminal and the inverting input terminal of operational amplifier U9 are both electrically connected to the other end of capacitor C2, and output voltage signal Vout to the comparator module as the output terminal. The other end of capacitor C3 is grounded.

9. The motor drive circuit with hysteresis window dynamic speed matching according to claim 1, characterized in that: The comparison module includes comparator U1, comparator U2, comparator U3, comparator U4 and comparator U5; The frequency-to-voltage conversion module outputs a voltage signal Vout to the non-inverting inputs of comparators U1, U2, U3, U4, and U5; the voltage regulation and reference voltage output module outputs a reference voltage Vout respectively. REF1 V REF2 V REF3 V REF4 and V REF5 The inverting inputs of comparators U1, U2, U3, U4, and U5 are connected to the inverting input terminals of each comparator. The outputs of comparators U1, U2, U3, U4, and U5 output the comparison result signal DAC. in0 Comparison result signal DAC in1 Comparison result signal DAC in2 Comparison result signal DAC in3 Comparison result signal DAC in4 To the ROM module.

10. The motor drive circuit with hysteresis window dynamic speed matching according to claim 9, characterized in that: Comparators U1, U2, U3, U4, and U5 are all dynamic latch comparators with hysteresis.

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