Class AB high voltage operational amplifier based on cross-coupled push-pull output

Abstract

The application belongs to the technical field of analog integrated circuits, and particularly relates to a Class AB high-voltage operational amplifier based on cross-coupled push-pull output. The application is based on cross-coupled push-pull output, and a dynamic bias generation model is established through a composite feedback path of a low-voltage operational amplifier circuit and a high-voltage current mirror. A transconductance gain stage is composed of low-voltage common-source MOS tubes M17 and M18, which can improve the gain efficiency compared with traditional high-voltage tubes, the output current of which is cross-coupled through high-voltage common-gate LDMOS tubes HM19 and HM20 and injected into diode-connected high-voltage tubes HM21 and HM22 to generate gate drive voltages of Class AB high-voltage push-pull output stages HM23 and HM24, so as to realize rail-to-rail output swing. The application realizes the nonlinear driving capability of AB class output under the condition of no additional compensation circuit, realizes low power consumption, small area and full swing output of high-voltage driving, and does not need additional LDMOS high-voltage bias circuit, and the number of LDMOS is optimized to 6, which breaks through the efficiency and area bottleneck of traditional high-voltage operational amplifiers.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of analog integrated circuits, and particularly relates to a Class AB high-voltage operational amplifier based on cross-coupled push-pull output, which meets the requirements of motor driving and micro-electro-mechanical system (MEMS) sensor large array driving. BACKGROUND

[0002] In recent years, with the rapid development of MEMS, its application in the fields of sensors, actuators and large array systems is increasingly widespread. MEMS technology, with its miniaturization, high precision and good compatibility with standard semiconductor processes, has gradually replaced traditional electro-mechanical systems and become an important part of modern integrated circuit design. In particular, in optical phased array (OPA) electrically driven control chips, the large-scale array driving requirements of MEMS actuators have put forward higher requirements for high-voltage driving circuits.

[0003] However, the high-voltage operational amplifier design based on the conventional operational amplifier architecture has inherent defects: in order to realize the output swing above the common voltage domain (5V), a plurality of high-voltage MOS devices need to be cascaded on the signal path, resulting in an increase of several times in the core circuit area (compared with low-voltage operational amplifier); in addition, the parasitic diode leakage of high-voltage MOS, the complex isolation structure and the low transconductance efficiency will also significantly worsen the power consumption and area performance of the circuit. The above problems increase the complexity of the design and the system overhead, seriously restricting the integration density and system efficiency of large-scale MEMS array electrically driven chips, and thus becoming the main bottleneck for the overall performance improvement of optical phased array. How to use the least number of LDMOS tubes to realize the low-voltage to high-voltage (LV-to-HV) conversion stage design becomes the key to reducing the high-voltage operational amplifier (HV-AMP) area.

[0004] In view of the above area-power trade-off problem of high-voltage operational amplifier, three main solutions are proposed in the academic field, including stacked transistor structure, level shifter and multi-stage amplifier architecture:

[0005] 1. Stacked transistor structure: by vertically cascading topology (such as common-source common-gate or floating cascade), the high voltage is gradually distributed to each low-voltage transistor, which relies on dynamic gate biasing technology to distribute high voltage, is easily affected by process deviation, needs complex calibration circuit, and the cumulative parasitic capacitance causes frequency response to deteriorate, in addition, the increase of stacked level will aggravate the cumulative effect of parasitic capacitance, resulting in complex frequency response characteristics and the position of zero and pole changing with working state, especially in the large swing dynamic output scene, which is easy to cause bandwidth attenuation and efficiency decline.

[0006] 2. Level Shifter: This type of trans-voltage shifter achieves a withstand voltage interface by converting low-voltage logic to high-voltage drive. Its core mechanism relies on dynamic threshold compensation and trans-voltage domain isolation design. Typical solutions employ current feedback topologies and hybrid output architectures to improve high-voltage drive bandwidth, but require multi-layer capacitor compensation networks and have high requirements for device matching accuracy.

[0007] 3. Multi-stage amplifier architecture: High voltage output is achieved by cascading low-voltage high-gain amplification in the front stage and high-voltage drive in the rear stage. However, the stacking of high-voltage devices and compensation circuits leads to a significant increase in chip area and static power consumption. Transient voltage overshoot is easily caused when the load changes suddenly, and the dynamic bias stability is poor.

[0008] In summary, existing solutions cannot effectively address the synergistic optimization problem of low power consumption, small area, and high performance driving of high-voltage operational amplifiers that meet the requirements of motor drive and large MEMS sensor array drive. An innovative architecture is urgently needed to break through the bottlenecks of traditional design. Summary of the Invention

[0009] To address the aforementioned problems or shortcomings, this invention proposes a Class AB high-voltage operational amplifier based on cross-coupled push-pull output, which solves the problems of high power consumption, large area, and low driving efficiency of traditional high-voltage operational amplifiers.

[0010] A Class AB high-voltage operational amplifier based on cross-coupled push-pull output is a two-stage amplifier consisting of a low-voltage pre-amplification input stage gm1, a push-pull high-voltage Class AB output buffer stage, and a feedback network (see attached diagram). Figure 2 (As shown).

[0011] The low-voltage pre-amplification input stage g m1 Its positive input terminal is connected to INP, its negative input terminal is connected to one end of resistor R1, its power supply voltage is connected to the low power supply voltage AVDD, its ground potential is connected to AGND, and its output terminal is connected to the gate of M17 and the gate of M18.

[0012] The push-pull high-voltage Class AB output buffer stage, which realizes low-voltage to high-voltage level conversion, includes: a low-voltage NMOS transistor M17, a low-voltage PMOS transistor M18, high-voltage transistors HM19, HM20, HM21, HM22, HM23, and HM24, Zener diodes D1 and D2, an amplifier, a low power supply voltage AVDD, a high power supply voltage AVCC, and a negative power supply voltage AVSS. "High" and "low" refer to power supply voltage AVCC being greater than power supply voltage AVDD, and "negative" refers to power supply voltage AVSS being less than or equal to ground potential AGND.

[0013] M17 gate connection g m1The output end of the M18 is connected with the source electrode of the HM19, and the drain electrode of the M18 is connected with the source electrode of the HM20; the gate electrode of the HM19 is connected with the enable voltage ENB, the source electrode of the M17, the gate electrode and the drain electrode of the HM22, the gate electrode of the HM24, and the negative end of the D2.

[0014] The gate and the drain of the HM22 are short-circuited, and are connected with the drain electrode of the HM19, the gate electrode of the HM24, and the negative end of the D2, and the source electrode of the HM22 is connected with the negative power supply voltage AVSS; the source electrode of the HM24 is connected with the negative power supply voltage AVSS, and the drain electrode of the HM24 is connected with the drain electrode of the HM23, and the drain electrode of the HM24 is used as the output end of the whole Class AB high-voltage operational amplifier.

[0015] The positive end of the D2 is connected with the negative power supply voltage AVSS.

[0016] The gate electrode of the M18 is connected with the negative input end of the low-voltage pre-amplification input stage g m1 The output end of the M18 is connected with the source electrode of the HM19, and the drain electrode of the M18 is connected with the source electrode of the HM20; the gate electrode of the HM19 is connected with the enable voltage ENB, the source electrode of the M17, the gate electrode and the drain electrode of the HM22, the gate electrode of the HM24, and the negative end of the D2.

[0017] The gate and the drain of the HM21 are short-circuited, and are connected with the drain electrode of the HM20, the gate electrode of the HM23, and the positive end of the D1, and the source electrode of the HM21 is connected with the high power supply voltage AVCC; the source electrode of the HM23 is connected with the high power supply voltage AVCC, and the drain electrode of the HM23 is connected with the drain electrode of the HM24, and the drain electrode of the HM23 is used as the output end of the whole Class AB high-voltage operational amplifier.

[0018] The negative end of the D1 is connected with the high power supply voltage AVCC.

[0019] The feedback network comprises resistors R1 and R2; one end of the resistor R1 is connected with the common-mode voltage VCM, and the other end of the resistor R1 is connected with the negative input end of the low-voltage pre-amplification input stage g m1 and one end of the resistor R2; one end of the resistor R2 is connected with the negative input end of the low-voltage pre-amplification input stage g m1 and one end of the resistor R1, and the other end of the resistor R1 is connected with the drain electrode of the HM23 and the drain electrode of the HM24.

[0020] The working process of the above-mentioned Class AB high-voltage operational amplifier based on the cross-coupled push-pull output is as follows:

[0021] After low power voltage, high power voltage and negative power voltage are powered in turn, the input signal INP is amplified by the low-voltage pre-amplification input stage gml, and the amplified signal is transmitted to the input tubes M17 and M18 of the second stage to generate a low-voltage gate voltage control signal; since the high-voltage common-gate tube HM19 / HM20 is cross-connected with the low-voltage MOS tube M17 / M18, a cross-voltage domain driving loop is formed, the low-voltage gate voltage control signal is converted into a current signal through the low-voltage MOS tube M17 / M18, and then the conversion from low-voltage current to high-voltage voltage is realized through the high-voltage common-gate tube HM19 / HM20, the current is converted by the diode-connected HM21 and HM22 to generate the gate end control voltage of the high-voltage push-pull output stage (HM23 / HM24), so that a cross-voltage domain driving loop is formed as a whole, and high-voltage output is realized.

[0022] Further, the above-mentioned Class AB high-voltage operational amplifier based on cross-coupled push-pull output is applied to motor driving and micro-electro-mechanical system (MEMS) sensor large array driving.

[0023] In summary, based on the circuit structure of cross-coupled push-pull output, the dynamic bias generation model is established through the composite feedback path of the low-voltage operational amplifier circuit and the high-voltage current mirror; the transconductance gain stage is composed of the low-voltage common-source MOS tubes M17 and M18, which can improve the gain efficiency compared with the traditional high-voltage tube input, the output current is cross-coupled through the high-voltage common-gate LDMOS tubes HM19 and HM20, and is injected into the diode-connected high-voltage tubes HM21 and HM22 to generate the gate drive voltage of the Class AB high-voltage push-pull output stage HM23 and HM24, so as to realize the rail-to-rail output swing. The nonlinear driving capability of the AB class output is realized under the condition of no additional compensation circuit, the low power consumption, small area and full swing output of high-voltage driving are realized. In addition, the architecture of the application does not require additional LDMOS high-voltage bias circuit, and the number of LDMOS in the whole architecture is optimized to 6. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 is the circuit system architecture schematic diagram of the application.

[0025] Figure 2 is the circuit specific structure schematic diagram of the application.

[0026] Figure 3 is the circuit structure schematic diagram for realizing the high-voltage static bias technology of the application. DETAILED DESCRIPTION

[0027] The application will be further described in detail below with reference to the drawings and in combination with the preferred embodiments.

[0028] Based on the cross-voltage domain cascaded bias architecture, the application proposes a full low-voltage domain driven high-voltage static bias technology, and the implementation mechanism is as followsFigure 3 As shown, the floating gate control network is built by stacking low-voltage MOS devices (M19-M20, M21-M22) in diode connection, and the constant gate-source bias (V GS ≈XV) is generated by the floating gate charge redistribution mechanism. The bias voltage is coupled to the gate of the high-voltage output stage (HM23-HM24) through the linear transconductance loop (M9 / M10 / M11 / M12) and the transconductance of the high-voltage LDMOS current mirror (HM21-HM22), realizing the full low-voltage domain generation of the high-voltage domain static bias. The number of LDMOS in the entire architecture is optimized to 4.

[0029] Let the gate-source voltage of the nth MOS transistor be V GSn , the threshold voltage be V T , the drain-source current be I DSn , and K be a process parameter, (W / L) n be the width-length ratio thereof. Large signal analysis shows that:

[0030] V GS19 +V GS20 =V GS10 +V GS17 (1)

[0031]

[0032] Assuming that the threshold voltages of the MOS transistors are equal, it can be obtained from (1) and (2) that:

[0033]

[0034] The output current expression is:

[0035]

[0036] Theoretical derivation shows that M19 and M17 are in current mirror relationship, and M20 and M10 are in current mirror relationship. The output current is in linear proportional relationship with the width-length ratio (W / L) of the low-voltage MOS M10 / M19, and is independent of the width-length ratio of the high-voltage LDMOS. This characteristic reveals the constraint mechanism of the static current: through the dynamic balance effect of the transconductance loop (formula (1)), the system strictly limits the static current to the uA order of magnitude under the ±10V high-voltage domain, and the theoretical limit value is determined by the ratio of (W / L) 10 / (W / L) 19 . Compared with the traditional high-voltage AB class output structure, the present scheme realizes the topology reconstruction of all low-voltage domain devices (low-voltage device proportion is 100%), without the need for additional high-voltage devices for bias circuit.

[0037] In the specific circuit embodiment, the bias circuit is implemented by stacking low-voltage MOS devices (M19-M20, M21-M22) in diode connection, and the constant gate-source bias (V Figure 2In this design, a simplified high-voltage LDMOS architecture (HM19-HM24) is adopted. The traditional AB class push-pull output stage is reconstructed by utilizing the asymmetric breakdown voltage characteristics of LDMOS (drain breakdown voltage ±10V, source / gate low-voltage drive): the common gate stage HM19 / HM20 is cross-connected with the low-voltage MOS (M17 / M18) to form a cross-voltage domain drive loop. The low-voltage gate voltage control signal is modulated by the LDMOS transistor (HM21 / HM22) and then transmitted to the gate of the high-voltage push-pull output stage (HM23 / HM24). The low supply voltage AVDD is 5V, the high supply voltage AVCC is 10V, and the negative supply voltage AVSS is -10V, achieving a full swing output from -10V to 10V.

[0038] The first stage low-voltage preamplifier input stage g m1 A folded cascode operational transconductance amplifier (OTA) is constructed using standard low-voltage CMOS transistors M1-M16. The differential input pair M3 / M4 is defined with a transconductance gm1 = 60µS by optimizing the width-to-length ratio (W / L = 48μm / 4μm). The output impedance of MΩ level is achieved by utilizing the cascode structure M5-M8 and M13-M16, thereby obtaining a small-signal gain of 71dB in the pre-amplification stage. Rmp, Rmn, Cmp, and Cmn are Miller compensation resistors and capacitors.

[0039] The floating bias Class AB control circuit composed of M9-M12: When the input signal drives the drain current increment ΔI of the P-channel Class AB transistors (M9, M10), P At that time, the drain current of the N-channel AB-class transistors (M11, M12) will undergo an equal negative change ΔI. N =-ΔI P This complementary working mechanism induces a symmetrical shift in the push-pull node voltage, specifically manifested as follows:

[0040]

[0041] In the formula, ΔV G,P With ΔV G,N These represent the offset of the P / N channel pair output voltage, g. m,9-10 With g m,11-12 These are the transconductance values ​​for the P / N channel pair, respectively. This voltage offset is coupled to the gate of the output stage through a high-voltage level shifting stage (HM19-HM22), driving the LDMOS transistor to switch between two operating modes: when V G,P When V shifts upwards, the output stage draws current from the load (Sourcing Mode); when V... G,N When the output stage moves downward, it injects current into the load (Sinking Mode).

[0042] The second-stage push-pull high-voltage Class AB output buffer stage adopts a low-voltage-high-voltage hybrid structure, and the key to the design is a cross-voltage-domain signal fidelity transmission mechanism. A low-voltage common-source stage (M17 / M18) converts a voltage signal into a current signal through a transconductance gm17,18, and a high-voltage common-gate stage (HM19 / HM20) converts the low-voltage current into a high-voltage voltage under the constraint of a VDS<5V voltage resistance. Diode-connected HM21 and HM22 convert the current to generate a gate-end control voltage of the high-voltage push-pull output stage, and realize rail-to-rail output swing.

[0043] As can be seen from the above embodiments, the present application deploys a main gain stage in a 5V low-voltage domain to realize high-gain signal pre-amplification, and the high-voltage domain only undertakes the output buffer function, thereby significantly reducing the number of high-voltage devices. Moreover, the output current of the low-voltage common-source stage is taken as a controlled current source, and is injected into a high-voltage current mirror network through a cross-coupling topology, thereby providing a static working point for gate driving of the second-stage push-pull common-source amplifier through a low-voltage VGS cascade structure without using high-voltage devices and a high-voltage domain. In combination with a high-fidelity voltage conversion network, the low-voltage domain biasing signal is transmitted to a high-voltage LDMOS output stage, thereby realizing all-low-voltage-domain generation of the high-voltage output stage biasing, and further realizing high-voltage domain Class AB push-pull output, thereby breaking through the efficiency and area bottleneck of the traditional high-voltage operational amplifier.

Claims

1. A Class AB high-voltage operational amplifier based on cross-coupled push-pull output, characterized in that: It consists of a low-voltage pre-amplification input stage gm1, a push-pull high-voltage Class AB output buffer stage, and a feedback network; The low-voltage pre-amplification input stage g m1 Its positive input terminal is connected to INP, its negative input terminal is connected to one end of resistor R1, its power supply voltage is connected to the low power supply voltage AVDD, its ground potential is connected to AGND, and its output terminal is connected to the gate of M17 and the gate of M18. The push-pull high-voltage Class AB output buffer stage realizes low-voltage to high-voltage level conversion and includes: low-voltage NMOS transistor M17, low-voltage PMOS transistor M18, high-voltage transistors HM19, HM20, HM21, HM22, HM23, HM24, Zener diodes D1 and D2, an amplifier, low power supply voltage AVDD, high power supply voltage AVCC, and negative power supply voltage AVSS; where high and low refer to high power supply voltage AVCC being greater than low power supply voltage AVDD, and negative refers to negative power supply voltage AVSS being less than or equal to ground potential AGND; M17 gate connection g m1 The output terminal is connected to the low power supply voltage AVDD and the drain is connected to the source of HM19; the gate of HM19 is connected to the enable voltage ENB, the source is connected to the drain of M17, and the drain is connected to the gate and drain of HM22, the gate of HM24, and the negative terminal of D2. The gate and drain of HM22 are shorted and connected to the drain of HM19, the gate of HM24, and the negative terminal of D2. The source of HM22 is connected to the negative power supply voltage AVSS. The source of HM24 is connected to the negative power supply voltage AVSS, and its drain is connected to the drain of HM23. The drain of HM24 is used as the output terminal of the entire Class AB high-voltage op-amp. The positive terminal of D2 is connected to the negative power supply voltage AVSS; M18 gate connection g m1 The output terminal of the transistor is connected to the source of the transistor HM20, and the source is connected to ground potential AGND. The gate of the transistor HM20 is connected to the enable voltage EN, the drain is connected to the drain and gate of the transistor HM21, the gate of the transistor HM23 and the positive terminal of the transistor D1, and the source is connected to the drain of the transistor M18. The gate and drain of HM21 are shorted and connected to the drain of HM20, the gate of HM23, and the positive terminal of D1. The source of HM21 is connected to the high power supply voltage AVCC. The source of HM23 is connected to the high power supply voltage AVCC, and its drain is connected to the drain of HM24. The drain of HM23 is used as the output terminal of the entire Class AB high voltage op-amp. The negative terminal of D1 is connected to the high power supply voltage AVCC; The feedback network includes resistors R1 and R2; one end of resistor R1 is connected to the common-mode voltage VCM, and the other end is connected to the low-voltage pre-amplifier input stage g. m1 The negative input terminal is connected to one end of resistor R2; one end of resistor R2 is connected to the low-voltage preamplifier input stage g. m1 The negative input terminal is connected to one end of resistor R1, and the other end is connected to the drain of HM23 and the drain of HM24.

2. The Class AB high-voltage operational amplifier based on cross-coupled push-pull output as described in claim 1, characterized in that: The low-voltage pre-amplification input stage g m1 A folded cascode operational transconductance amplifier is constructed using standard low-voltage CMOS transistors.

3. The Class AB high-voltage operational amplifier based on cross-coupled push-pull output as described in claim 1, characterized in that: The low power supply voltage AVDD is 5V, the high power supply voltage AVCC is 10V, and the negative power supply voltage AVSS is -10V, achieving a full swing output from -10V to 10V.

4. The Class AB high-voltage operational amplifier based on cross-coupled push-pull output as described in claim 1, characterized in that, The specific work process is as follows: After the low power supply voltage AVDD, the high power supply voltage AVCC, and the negative power supply voltage AVSS are powered on in sequence, the input signal INP is amplified by the low-voltage pre-amplifier input stage gm1 and transmitted to the input transistors of the second stage, the low-voltage NMOS transistor M17 and the low-voltage PMOS transistor M18, to generate a low-voltage gate voltage control signal. High-voltage transistors HM19 and HM20 are connected to low-voltage NMOS transistors M17 and M18, respectively, forming a cross-voltage domain drive loop. The low-voltage gate voltage control signal is converted into a current signal by low-voltage NMOS transistors M17 and M18, and then converted from low-voltage current to high-voltage voltage by high-voltage transistors HM19 and HM20. High-voltage transistors HM21 and HM22, which are connected by diodes, convert the current and generate the gate control voltages of high-voltage transistors HM23 and HM24 in the high-voltage push-pull output stage, respectively. Thus, the whole system forms a cross-voltage domain drive loop to achieve high-voltage output.

5. The Class AB high-voltage operational amplifier based on cross-coupled push-pull output as described in claim 1, characterized in that, It is applied to motor drives and large array drives for MEMS sensors.

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