A three-code-in-one interpretation method and device based on a probability domain of a memory-computing integrated device

Abstract

The application relates to the field of decoding technology and discloses a three-code-in-one interpretation method and device based on a probability domain of a memory-computing integrated device, which can be based on target probability graph models corresponding to three to-be-interpreted error correction codes, configure a three-code-in-one decoding array including an LDPC decoding array, a Polar decoding array and a Turbo decoding array on the memory-computing integrated device, determine the initial probability of the state value of each variable node in each target probability graph model according to a probability domain operation mode, use the initial probability of the state value of each variable node in each target probability graph model and the three-code-in-one decoding array to uniformly interpret the three to-be-interpreted error correction codes, realize the unified interpretation of to-be-interpreted LDPC codes, Polar codes and Turbo codes, and effectively reduce the unified decoding power consumption of the to-be-interpreted LDPC codes, Polar codes and Turbo codes.

Description

Technical Field

[0001] This invention relates to the field of decoding technology, and in particular to a method and apparatus for three-code unification based on the probability domain of an in-memory computing unit. Background Technology

[0002] With the development of science and technology, decoding technology is constantly improving.

[0003] Turbo codes, LDPC codes, and Polar codes are commonly used modern channel codes, all possessing theoretical performance reaching or approaching the Shannon limit, and are applied in 3G, 4G, and 5G communication technologies. The decoding of Turbo codes, LDPC codes, and Polar codes generally relies on complex iterative algorithms.

[0004] Related technologies rely on complex iterative algorithms to decode Turbo codes, LDPC codes, or Polar codes, resulting in high power consumption. Furthermore, when Turbo codes, LDPC codes, and Polar codes are received simultaneously and need to be decoded, even higher power consumption is required. Summary of the Invention

[0005] This invention provides a three-code unification decoding method and apparatus based on the probability domain of an in-memory computing unit, which solves the problem of high power consumption in decoding Turbo codes, LDPC codes and Polar codes in related technologies. Based on the in-memory computing unit and the probability domain, the Turbo codes, LDPC codes and Polar codes to be decoded are decoded in a unified manner, which effectively reduces decoding power consumption.

[0006] In a first aspect, the present invention provides a three-code unification decoding method based on the probability domain of an in-memory computing device, applied at the decoding end, the method comprising:

[0007] The receiver sends multiple error correction codes to be decoded, including LDPC codes, Polar codes, and Turbo codes to be decoded.

[0008] For any of the error correction codes to be decoded, a target parity-check matrix and a target probabilistic graphical model are created based on the error correction code. The initial probability of the state value of each variable node in the target probabilistic graphical model is determined based on the probability domain operation method. Based on each undirected edge in the target probabilistic graphical model and the target parity-check matrix, an initial decoding submatrix corresponding to each undirected edge is created. The number of rows in the initial decoding submatrix corresponding to each undirected edge created based on each error correction code to be decoded is not exactly the same.

[0009] The initial decoding submatrix corresponding to each undirected edge created based on each of the error correction codes to be decoded is aligned at the bottom and concatenated horizontally to obtain the corresponding matrix containing null values.

[0010] Fill each null value position in the null value matrix with 0 to construct a three-in-one decoding matrix including the LDPC decoding matrix, the Polar decoding matrix, and the Turbo decoding matrix;

[0011] Based on the three-code-in-one decoding matrix, the node state is configured in the in-memory computing unit to obtain a three-code-in-one decoding array including an LDPC decoding array, a Polar decoding array, and a Turbo decoding array;

[0012] Using the initial probability of the state value of each variable node and the three-code unified decoding array, each error correction code to be decoded is uniformly decoded to obtain the original bit information corresponding to each error correction code to be decoded.

[0013] Secondly, the present invention provides a three-code unification decoding device based on the probability domain of an in-memory computing unit, applied at a decoding end, the device comprising:

[0014] The receiving unit is used to receive multiple error correction codes to be decoded sent by the encoding end, wherein the multiple error correction codes to be decoded include LDPC codes, Polar codes and Turbo codes to be decoded;

[0015] The first creation unit is used to create a target verification matrix and a target probability graph model based on any of the error correction codes to be deciphered.

[0016] The determining unit is used to determine the initial probability of the state value of each variable node in the target probabilistic graphical model based on the probability domain operation method.

[0017] The second creation unit is used to create an initial decoding sub-matrix corresponding to each undirected edge based on each undirected edge in the target probabilistic graphical model and the target parity check matrix; wherein the number of matrix rows of the initial decoding sub-matrix corresponding to each undirected edge created based on each error correction code to be decoded is not exactly the same;

[0018] The splicing unit is used to align the bottom end of the initial decoding submatrix corresponding to each undirected edge created according to each of the error correction codes to be decoded and splice them horizontally to obtain the corresponding matrix containing null values.

[0019] Filling units are used to fill each null position in the null matrix with 0 to construct a three-in-one decoding matrix including the LDPC decoding matrix, the Polar decoding matrix, and the Turbo decoding matrix.

[0020] The configuration unit is used to configure the node state in the in-memory computing unit according to the three-code-in-one decoding matrix to obtain a three-code-in-one decoding array including an LDPC decoding array, a Polar decoding array, and a Turbo decoding array.

[0021] The decoding unit is used to perform unified decoding on each of the error correction codes to be decoded using the initial probability of the state value of each variable node and the three-code unified decoding array, so as to obtain the original bit information corresponding to each error correction code to be decoded.

[0022] Thirdly, the present invention provides a computer device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the three-code unification decoding method based on the probability domain of the in-memory computing unit described in the first aspect or any corresponding embodiment.

[0023] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions, which are used to cause a computer to execute the three-code unification method based on the probability domain of the in-memory computing unit described in the first aspect or any corresponding embodiment above.

[0024] The present invention provides a method and apparatus for unified decoding of three codes based on the probability domain of an in-memory computing device. This method configures a unified decoding array, including an LDPC decoding array, a Polar decoding array, and a Turbo decoding array, on an in-memory computing device based on the target probabilistic graphical models corresponding to the three error correction codes to be decoded. According to the probability domain operation method, the initial probability of the state value of each variable node in each target probabilistic graphical model is determined. Using the initial probability of the state value of each variable node in each target probabilistic graphical model and the unified decoding array, the three error correction codes to be decoded are decoded uniformly. This achieves unified decoding of the LDPC code, Polar code, and Turbo code, and can effectively reduce the power consumption of unified decoding of the LDPC code, Polar code, and Turbo code. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in this invention or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 A flowchart of a three-code unification decoding method based on the probability domain of an in-memory computing device provided in an embodiment of the present invention;

[0027] Figure 2 This is a schematic diagram illustrating the connection relationship between verification nodes and variable nodes in a target probabilistic graphical model provided by an embodiment of the present invention;

[0028] Figure 3 A schematic diagram of an initial decoding submatrix and a submatrix containing null values ​​provided for an embodiment of the present invention;

[0029] Figure 4 A schematic diagram of another submatrix containing null values ​​provided in an embodiment of the present invention;

[0030] Figure 5 A schematic diagram of a matrix containing null values ​​provided in an embodiment of the present invention;

[0031] Figure 6 A schematic diagram of a three-code-in-one decoding matrix provided in an embodiment of the present invention;

[0032] Figure 7 This is a schematic diagram of the structure of a three-code-in-one decoding array provided in an embodiment of the present invention;

[0033] Figure 8 This is a schematic diagram illustrating the decoding process using a Turbo decoding array in a three-in-one decoding array, as provided in an embodiment of the present invention.

[0034] Figure 9 This is a schematic diagram of the structure of a three-code decoding device based on the probability domain of an in-memory computing unit, provided in an embodiment of the present invention.

[0035] Figure 10 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0037] The following is combined with Figures 1-8 The present invention describes a probability domain-based three-code unification decoding method based on an in-memory computing device.

[0038] like Figure 1 As shown, this embodiment proposes a first three-code unification decoding method based on the probability domain of an in-memory computing device. This method is applied to the decoding end and may include the following steps:

[0039] S101. Receive multiple error correction codes to be decoded sent by the encoding end; wherein, the multiple error correction codes to be decoded include LDPC code, Polar code and Turbo code to be decoded, the error correction codes to be decoded are obtained by the encoding end through digital modulation of the original error correction code, and the original error correction code is obtained by the encoding end through encoding the original bit information.

[0040] The decoding end and the encoding end can be different terminal devices, such as mobile phones, computers, tablets and servers.

[0041] It should be noted that this embodiment can be applied to the decoding end. The decoding end can decode the error-correcting code to be decoded obtained by the encoding end using error-correcting code encoding and digital modulation to obtain the original bit information.

[0042] Taking Binary Phase Shift Keying (BPSK) and Turbo codes as examples, this paper introduces the communication between the encoder and decoder, and the decoding objective of this embodiment. Specifically, the encoder can encode the original K codewords into N codewords using a Turbo encoder. x Then, based on BPSK modulation, N symbols s are generated and sent to the decoding end. Due to noise interference during transmission, the decoding end in this embodiment receives N symbols. y The decoding task at the decoding end is to... y The original K codewords, or raw bit information, are restored.

[0043] In-memory computing devices are integrated devices that combine storage and computing capabilities, such as resistive random access memory (RRAM), phase-change memory (PCM), magnetic memory (MRAM), and flash memory.

[0044] The error correction code to be decoded can be the error correction code sent by the encoder and requiring decoding, such as the Turbo code to be decoded. The error correction code to be decoded can include N codewords, where N is an integer greater than 1.

[0045] S102. For any error correction code to be decoded, create a target parity matrix and a target probability graphical model based on the error correction code to be decoded.

[0046] The target verification matrix is ​​a verification matrix created based on the error correction code to be decoded, used to decode the error correction code.

[0047] Specifically, the target probabilistic graphical model is a unified probabilistic graphical model corresponding to the target parity check matrix, used for decoding the error correction code to be decoded.

[0048] Specifically, for any error-correcting code to be decoded, this embodiment can create a corresponding target parity-check matrix and target probability graphical model based on that code. The target parity-check matrix and target probability graphical model can be different for different error-correcting codes.

[0049] Specifically, the target probabilistic graphical model can include multiple variable nodes, multiple verification nodes, and multiple undirected edges. Undirected edges are used to connect variable nodes and verification nodes that have a connection relationship. Each variable node uniquely corresponds to a column vector in the target verification matrix, and each verification node uniquely corresponds to a row vector in the target verification matrix. If the row order in the target verification matrix is ​​equal to... i Column order equals j If the element is 1, then the order of the first node is equal to... i The order of the verification node and the second node is equal to j The variable nodes have a connection relationship, if the row order in the target verification matrix is ​​equal to i Column order equals j If the element is 0, then the order of the first node is equal to... i The order of the verification node and the second node is equal to j The variable nodes have no connection relationship. The first node's order is the sequence number of the check node among all check nodes, and the second node's order is the sequence number of the variable node among all variable nodes.

[0050] To better illustrate the relationship between the target verification matrix and the target probabilistic graphical model, as well as the relationship between variable nodes, verification nodes, and undirected edges, the following Example 1 is presented and combined with... Figure 2 Let me introduce it.

[0051] Example 1: When the target verification matrix H When a matrix has I rows and J columns, and the row vector of its third row is [0, 1, 1, 1, 0, 0], the target probabilistic graphical model includes I verification nodes and J variable nodes (in this case, J is 6). The third verification node in the target probabilistic graphical model... i (at this time, i 3) The connection relationships between the variables and the nodes are as follows: Figure 2 As shown in the diagram, the 2nd, 3rd, and 4th elements of this row vector are 1, and the 1st, 5th, and 6th elements are 0. Therefore, the 3rd check node is connected to the 2nd, 3rd, and 4th variable nodes via undirected edges, while the 3rd check node is not connected to the 1st, 5th, and 6th variable nodes. It should be noted that... Figure 2 Apart from the third verification node, the connection relationships between other verification nodes and variable nodes are not shown. The connection relationships between other verification nodes and variable nodes can be understood by referring to the connection relationship between the third verification node and variable nodes mentioned above.

[0052] Optionally, step S102 includes:

[0053] An initial check matrix and a corresponding initial probability graphical model are created based on the error correction code to be decoded. The initial probability graphical model includes multiple initial variable nodes.

[0054] When the error correction code to be decoded is a Turbo code to be decoded, the short loop structure in the initial parity check matrix and the initial probabilistic graphical model is eliminated to obtain the target parity check matrix and the target probabilistic graphical model. The target probabilistic graphical model includes each initial variable node and E extended variable nodes; where E is 0 or a positive integer.

[0055] When the error-correcting code to be decoded is a Polar code, the butterfly polarization relation corresponding to the error-correcting code is tiled to generate an intermediate probabilistic graphical model and an intermediate parity check matrix. The intermediate probabilistic graphical model includes each initial variable node and F additional variable nodes. The intermediate probabilistic graphical model and the intermediate parity check matrix are pruned and optimized to obtain the target probabilistic graphical model, which includes each initial variable node and Z additional variable nodes; where F and Z are positive integers, and F is greater than Z.

[0056] When the error correction code to be decoded is the LDPC code to be decoded, the initial parity check matrix is ​​directly used as the target parity check matrix, and the initial probabilistic graphical model is used as the target probabilistic graphical model.

[0057] Specifically, for any error-correcting code to be decoded, this embodiment can create an initial parity-check matrix and an initial probabilistic graphical model based on the code. The following example uses a Turbo code to be decoded to illustrate the creation process of the initial parity-check matrix and the initial probabilistic graphical model.

[0058] This embodiment can establish algebraic constraints based on the two recursive systematic convolutional (RSC) components of the Turbo encoder. Let the input information sequence be... System bits and check bits The check bits are determined by two generator polynomials, which are the feedback polynomial and feedforward polynomial set internally by the RSC encoder.

[0059] Specifically, in this embodiment, the generator polynomial described above can be used to map the Galois field GF(2) to binary coefficient vectors [1,0,1,1] and [1,1,0,1]. Based on the number of encoded information bits K, a cyclic shift is performed (the first row is padded with 0s to length K, the second row is obtained by cyclically shifting one bit to the right of the first row padded with 0s to length K, the third row is obtained by cyclically shifting one bit to the right of the second row again, and so on) to obtain a K×K cyclic shift matrix. and For example, when K equals 8, and the generator polynomial is mapped to a binary coefficient vector [1,0,1,1], an 8×8 cyclic shift matrix can be constructed:

[0060] .

[0061] This embodiment can be used to construct a cyclic shift matrix. and By performing horizontal concatenation, the component verification matrix is ​​obtained. .

[0062] Wherein, the component parity check matrix satisfies . Indicated by system bits and check bits The concatenated vector. The dot product symbol represents the dot product of two row vectors.

[0063] Subsequently, according to the interleaving rules, the interleaving effect of the second RSC component encoder is written as a permutation matrix. The corresponding check relation is right-multiplied. ,get:

[0064] .

[0065] Similarly, satisfying Based on the above component parity-check matrices, the overall parity-check matrix of the Turbo code (code rate 1 / 3, unchanged), i.e., the initial parity-check matrix, is as follows:

[0066] .

[0067] The initial check matrix has a size of 2K×3K (K is the number of encoded information bits) and satisfies the check relationship.

[0068] Subsequently, this embodiment can create a corresponding initial probabilistic graphical model based on the initial parity-check matrix. It should be noted that the relationship between the initial probabilistic graphical model and the initial parity-check matrix, as well as the relationship between variable nodes, parity nodes, and undirected edges in the initial probabilistic graphical model, can be found in [reference needed]. Figure 2 Let's understand this through an example. In this embodiment, we can create initial parity-check matrices and initial probabilistic graphical models corresponding to the LDPC, Polar, and Turbo codes to be decoded, respectively.

[0069] Specifically, when the error correction code to be decoded is a Polar code or a Turbo code, this embodiment can identify and eliminate short loop structures in the initial parity check matrix and the initial probabilistic graphical model corresponding to the error correction code to be decoded, thereby obtaining the target parity check matrix and the target probabilistic graphical model.

[0070] It should be noted that, compared to the initial verification matrix and the initial probabilistic graphical model, the number of variable nodes increases in the target verification matrix and the target probabilistic graphical model obtained after extended optimization.

[0071] Taking Turbo codes as an example, during the encoding, modulation, and transmission processes, the encoding end can encode the original bit information K codewords into N codewords. x The signal is then modulated into N symbols s using BPSK modulation and sent to the decoder. Due to noise interference during transmission, the decoder will receive N symbols. y Each y The original K codewords are restored, which are the original bit information. At this point, the decoder receives N codewords in the error-correcting code to be decoded. .

[0072] It should be noted that when the error-correcting code to be decoded is an LDPC code, this embodiment can directly use the initial probabilistic graphical model corresponding to the error-correcting code to be decoded as the target probabilistic graphical model. In this case, during the encoding, modulation, and transmission processes, the encoder can encode the original bit information K codewords into K... x Then, based on BPSK modulation, K symbols s are generated and sent to the decoding end. Due to noise interference during transmission, the decoding end will receive K symbols. y Each y The original K codewords are restored, which are the original bit information. At this point, the decoder receives N codewords in the error-correcting code to be decoded. .

[0073] S103. Determine the initial probability of the state value of each variable node in the target probabilistic graphical model based on the probability domain operation method.

[0074] Each variable node's initial probability state value can include a first initial probability and a second initial probability, given that the original error correction codeword corresponding to the variable node is 1 and 0, respectively.

[0075] Specifically, for any target probabilistic graphical model corresponding to an error correction code to be decoded, this embodiment can use probability domain arithmetic to determine the initial probability of the state value of each variable node in the target probabilistic graphical model.

[0076] Optionally, step S103 includes:

[0077] Obtain the noise variance corresponding to the error correction code to be decoded;

[0078] For any variable node in the target probabilistic graphical model, when the variable node is an initial variable node, according to the noise variance and probability domain operation method, calculate the first initial probability and the second initial probability of the original error correction codeword corresponding to the variable node being 1 and 0 respectively, under the condition that the received codeword corresponding to the variable node is known, and take the first initial probability and the second initial probability as a whole as the initial probability of the state value of the variable node.

[0079] When a variable node is an extended variable node or an added variable node, under the condition that the extended codeword corresponding to the variable node is known, the third initial probability and the fourth initial probability of the original error correction codeword corresponding to the variable node are 1 and 0 respectively, both determined to be 0.5, and the third initial probability and the fourth initial probability as a whole are used as the initial probability of the state value of the variable node.

[0080] Specifically, for the Turbo and Polar codes to be decoded, taking the Turbo code as an example, the total number of variable nodes in the target probabilistic graphical model will increase compared to the initial probabilistic graphical model. At this point, each variable node in the target probabilistic graphical model uniquely corresponds to an extended codeword. For the variable nodes in this target probabilistic graphical model...

[0081] j ( The initial probabilities of its state values ​​include the first and second initial probabilities, given that the original Turbo codewords corresponding to the variable nodes are 1 and 0 respectively. Taking BPSK modulated signals as an example, the calculation formula is as follows: , , This represents the noise variance, and the calculation formula is the probability domain operation method. For variable nodes... , J Let be the total number of variable nodes in the target probabilistic graphical model, and be the number of variable nodes at this point. j Since this was obtained by the decoder itself in this embodiment and does not contain prior channel information, it is considered that... .

[0082] Specifically, for the LDPC code to be decoded, this embodiment can refer to the variable node. The probability domain operation method of the initial probability of the state value is used to determine the initial probability of the state value of each variable node in the target probabilistic graphical model corresponding to the LDPC code to be decoded.

[0083] S104. Based on each undirected edge in the target probabilistic graphical model and the target parity check matrix, create an initial decoding submatrix corresponding to each undirected edge; wherein, the number of rows in the initial decoding submatrix corresponding to each undirected edge created based on each error correction code to be decoded is not exactly the same.

[0084] Specifically, the initial decoding submatrix is ​​a matrix used to configure the state of nodes in the in-memory computing unit.

[0085] It should be noted that, in this embodiment, for any error-correcting code to be decoded, an initial decoding sub-matrix corresponding to each undirected edge in the target probabilistic graphical model can be created based on each undirected edge and the target parity check matrix in the target probabilistic graphical model corresponding to the error-correcting code. Specifically, in this embodiment, for any parity check node in the target probabilistic graphical model, each target variable node connected to the parity check node through an undirected edge can be determined, as well as the target undirected edges between the parity check node and each target variable node. Based on each target undirected edge and the extended parity check matrix, an initial decoding sub-matrix corresponding to each target undirected edge is constructed.

[0086] It is understood that this embodiment can construct an initial decoding sub-matrix for each target undirected edge connected to a certain verification node in the target probabilistic graphical model. Therefore, this embodiment can construct an initial decoding sub-matrix for each undirected edge in the target probabilistic graphical model. The total number of initial decoding sub-matrixes constructed based on the target probabilistic graphical model corresponds to the total number of undirected edges in the target probabilistic graphical model.

[0087] Specifically, for any verification node in the target probabilistic graphical model, this embodiment can determine each target variable node connected to the verification node through undirected edges, and determine the target undirected edges between the verification node and each target variable node, count the number t of target undirected edges, and determine the internal order of each target undirected edge among all target undirected edges.

[0088] Construct multiple candidate vectors obtained by arranging and combining t target binary characters. For any candidate vector, if the element order of the target binary characters in the candidate vector is equal to the internal order of the target undirected edge, then establish an association between the target binary characters in the candidate vector and the target variable nodes connected by the target undirected edge.

[0089] Iterate through each target undirected edge in turn;

[0090] For the a-th undirected edge of the target encountered, the multiple candidate vectors are divided into multiple first candidate vectors and multiple second candidate vectors to be processed. Based on each first candidate vector, second candidate vector, association relationship and target verification matrix, the initial decoding sub-matrix corresponding to the undirected edge of the target is constructed; where the a-th element in the first candidate vector is 1 and the a-th element in the second candidate vector is 0.

[0091] Specifically, based on each first candidate vector, second candidate vector, association relationship, and target verification matrix, the initial decoding submatrix corresponding to the target undirected edge is constructed, including:

[0092] For any candidate vector to be processed, construct a zero vector with the total number of elements equal to the total number of variable nodes. Determine the node order of the target variable nodes associated with each target binary character in the candidate vector to be processed as the unique order to be arranged for each target binary character. Replace each zero element in the zero vector whose position order is equal to the order to be arranged with the target binary character that uniquely corresponds to the order to be arranged to obtain the processed candidate vector.

[0093] Wherein, the candidate vector to be processed is either the first candidate vector or the second candidate vector. When the candidate vector to be processed is the first candidate vector, the processed candidate vector is the first processed candidate vector; when the candidate vector to be processed is the second candidate vector, the processed candidate vector is the second processed candidate vector.

[0094] In the target verification matrix, determine the unique target row vector corresponding to the verification node;

[0095] For any first-processed candidate vector, perform a modulo operation between the target row vector and the first-processed candidate vector to obtain the corresponding first value, invert the first value to obtain the first inverted value; arrange each first inverted value to obtain the first node resistive state column vector.

[0096] For any second-processed candidate vector, perform a modulo operation between the target row vector and the second-processed candidate vector to obtain the corresponding second value. Invert the second value to obtain the second inverted value. Arrange each second inverted value to obtain the second node resistive column vector.

[0097] By concatenating the first and second column vectors horizontally, we obtain the initial decoding submatrix corresponding to the target undirected edge.

[0098] To better illustrate the above execution process, this embodiment continues to combine Example 1 and... Figure 2 Let me introduce it.

[0099] Example 1: In this embodiment, for any verification node... i The verification node can be determined in the target probabilistic graphical model. iConnecting the target variable nodes and the target undirected edges. For example... Figure 2 As shown, when i When the value is 3, the target variable nodes connected to the 3rd verification node are the 2nd, 3rd, and 4th variable nodes, respectively. At this time, the number of target undirected edges t is equal to 3, and each target undirected edge is an undirected edge connecting the 3rd verification node to the 2nd, 3rd, and 4th variable nodes, respectively. The internal order of each target undirected edge among all target undirected edges is 1, 2, and 3, respectively.

[0100] The target binary characters include 0 and 1. At this point, t equals 3. Multiple candidate vectors are constructed by permuting and combining the three target binary characters. The number of candidate vectors is 2^3, or 8 candidate vectors: (0,0,0), (0,0,1), (0,1,0), (0,1,1), (1,0,0), (1,0,1), (1,1,0), and (1,1,1). It can be understood that the number of elements in the candidate vectors is the same as the number of target undirected edges. The first, second, and third target binary characters in the candidate vectors are associated with the target variable nodes connected by the target undirected edges of order 1, 2, and 3, respectively. In other words, the first, second, and third target binary characters in the candidate vectors are associated with the second, third, and fourth variable nodes, respectively.

[0101] 'a' represents the internal order of the target undirected edges. The first, second, and third target undirected edges are traversed sequentially. Upon reaching each target undirected edge, the eight candidate vectors are divided into first and second candidate vectors. For example, when traversing the third target undirected edge, 'a' equals 3. If the third element of a candidate vector is 1, it is determined as the first candidate vector; if the third element is 0, it is determined as the second candidate vector. The first candidate vectors at this point include (0,0,1), (0,1,1), (1,0,1), and (1,1,1), while the second candidate vectors include (0,0,0), (0,1,0), (1,0,0), and (1,1,0).

[0102] Each of the first and second candidate vectors mentioned above is taken as a candidate vector to be processed. For example, when the first candidate vector (0, 1, 1) is taken as a candidate vector to be processed, a zero vector (0, 0, 0, 0, 0, 0) with a total number of elements equal to the total number of variable nodes (6) is first constructed. The first, second, and third target binary characters in the first candidate vector are associated with the second, third, and fourth variable nodes, respectively. Therefore, in this embodiment, the second, third, and fourth zero elements in the zero vector can be replaced with the first, second, and third target binary characters in the first candidate vector, respectively, to obtain the corresponding first processed candidate vector (0, 0, 1, 1, 0, 0).

[0103] At this point, when this embodiment traverses to the third target undirected edge, it can obtain four first-processed candidate vectors and four second-processed candidate vectors based on this target undirected edge. Then, this embodiment can determine the unique target row vector corresponding to the third verification node in the target verification matrix, i.e., the third row vector in the target verification matrix. For any first-processed candidate vector, the target row vector is moduloed with the first-processed candidate vector to obtain the corresponding first value. This first value is then inverted to obtain the first inverted value. At this point, four corresponding first inverted values ​​are obtained, and these four first inverted values ​​are arranged vertically to obtain the first column vector. For any second-processed candidate vector, the target row vector is moduloed with the second-processed candidate vector to obtain the corresponding second value. This second value is then inverted to obtain the second inverted value. At this point, four corresponding second inverted values ​​are obtained, and these four second inverted values ​​are arranged vertically to obtain the second column vector. The first and second column vectors are concatenated horizontally to obtain the initial decoding submatrix corresponding to the third target undirected edge.

[0104] It is understandable that, as can be seen from the creation process of the initial decoding submatrix, the initial decoding submatrix corresponding to different target undirected edges connected to the same check node has the same number of rows and 2 columns. For example, the initial decoding submatrix connected to the check node... i In the initial decoding sub-matrices A and B connecting two target undirected edges, matrices A and B have the same number of rows and 2 columns. The initial decoding sub-matrices corresponding to different target undirected edges connecting different check nodes can have different numbers of rows, but both matrices have 2 columns. For example, the initial decoding sub-matrices connecting check nodes... ia The initial decoding submatrix C corresponding to a certain target undirected edge, and the check node ib The initial decoding submatrix D corresponds to a certain target undirected edge. The two matrices C and D have different numbers of rows, and both matrices have 2 columns.

[0105] S105. Align the bottom edges of the initial decoding submatrix corresponding to each undirected edge created based on each error correction code to be decoded and then concatenate them horizontally to obtain the corresponding matrix containing null values.

[0106] Specifically, in this embodiment, the initial decoding sub-matrices corresponding to each undirected edge created according to different error correction codes to be decoded can be aligned at the bottom and then horizontally concatenated to construct a matrix containing null values.

[0107] Optionally, the number of rows in the initial decoding submatrix corresponding to each undirected edge created from the error-correcting code to be decoded may not be exactly the same. In this case, step S105 includes:

[0108] For any error correction code to be decoded, the initial decoding sub-matrix corresponding to each undirected edge created based on the error correction code to be decoded is aligned at the bottom and concatenated horizontally to obtain the null sub-matrix corresponding to the error correction code to be decoded; wherein, the null sub-matrix includes multiple null values ​​and the initial decoding sub-matrix corresponding to each undirected edge created based on the error correction code to be decoded.

[0109] Each null-value submatrix is ​​bottom-aligned and horizontally concatenated to obtain a null-value matrix; wherein the null-value matrix includes multiple null values ​​and an initial decoding submatrix corresponding to each undirected edge created based on each error-correcting code to be decoded.

[0110] To better illustrate the process of concatenating the initial decoding submatrices corresponding to different undirected edges to obtain a submatrix containing null values, this embodiment presents the following Example 2 and combines it with... Figure 3 Let me introduce it.

[0111] Example 2, such as Figure 3 As shown, when initial decoding submatrices A and B corresponding to two undirected edges are obtained based on the error-correcting code M1 to be decoded, this embodiment aligns the bottom edges of the initial decoding submatrices A and B and concatenates them horizontally to obtain the null-valued submatrice C corresponding to the error-correcting code M1 to be decoded. Wherein, Figure 3 In this context, null represents an empty value.

[0112] like Figure 4 As shown, in this embodiment, submatrices C, D, and E containing null values ​​are obtained based on each code to be corrected. At this time, as... Figure 5 As shown, in this embodiment, the null submatrices C, D, and E can be aligned at the bottom and horizontally joined to obtain the corresponding null matrix T1.

[0113] S106. Fill each null position in the null matrix with 0 to construct a three-in-one decoding matrix including the LDPC decoding matrix, the Polar decoding matrix, and the Turbo decoding matrix.

[0114] Optionally, step S106 includes:

[0115] For any undirected edge in the null value matrix, determine the target column order of the initial decoding submatrix in the null value matrix, fill each null position in the target column order of the null value matrix with 0, and take each 0 filled in the target column order and each element in the initial decoding submatrix as a whole as the decoding submatrix corresponding to the undirected edge.

[0116] For any error correction code to be decoded, the decoding sub-matrix corresponding to each undirected edge in the target probabilistic graphical model created based on the error correction code to be decoded will be used as the decoding matrix corresponding to the error correction code to be decoded; wherein, the decoding matrix corresponding to the error correction code to be decoded is an LDPC decoding matrix, a Polar decoding matrix, or a Turbo decoding matrix.

[0117] The decoding matrix corresponding to each error-correcting code to be decoded is used as a whole as a three-code unified decoding matrix.

[0118] Following on from Example 2 above, such as Figure 2 , Figure 3 , Figure 4 and Figure 5 As shown, the first two columns of the null value matrix T1 include the initial decoding submatrix A corresponding to the undirected edge and two null values. In this embodiment, the null values ​​in the two columns of the initial decoding submatrix where the null value matrix T1 is located are filled with 0, and the two columns after filling with 0 are used as a whole as the decoding submatrix corresponding to the undirected edge.

[0119] Continuing from Example 2 above, such as Figure 2 , Figure 3 , Figure 4 and Figure 5 As shown, for the initial decoding submatrices A and B corresponding to the two undirected edges obtained from the error correction code M1 to be decoded, in this embodiment, zeros can be filled into the empty values ​​in the two columns at A and B respectively to obtain the decoding submatrices corresponding to the two undirected edges, and the decoding submatrices corresponding to the two undirected edges can be determined as the decoding matrix corresponding to the error correction code M1 to be decoded.

[0120] Specifically, in this embodiment, after obtaining the decoding matrix corresponding to each error-correcting code to be decoded, the decoding matrix corresponding to each error-correcting code to be decoded can be used as a whole as a three-code unified decoding matrix. This embodiment can obtain the decoding matrix corresponding to each error-correcting code to be decoded based on the null value matrix T1, that is, by filling each null value position in the null value matrix T1 with 0, resulting in the following... Figure 6 The diagram shows a three-in-one decoding matrix T2, which includes an LDPC decoding matrix, a Polar decoding matrix, or a Turbo decoding matrix. Figure 6 In the three-code-in-one decoding matrix T2, columns 1 to 4 are Turbo decoding matrices, columns 5 to 8 are Polar decoding matrices, and columns 9 to 12 are LDPC decoding matrices.

[0121] S107. Configure the node state in the in-memory computing unit according to the three-code-in-one decoding matrix to obtain a three-code-in-one decoding array including LDPC decoding array, Polar decoding array and Turbo decoding array.

[0122] Optionally, the elements in the three-code unified decoding matrix are 0 or 1; when the in-memory computing unit is a memristor, step S107 includes:

[0123] Obtain the memristor to be configured corresponding to the three-code unified decoding matrix. The number of rows and columns of nodes in the memristor to be configured is the same as the number of rows and columns of elements in the three-code unified decoding matrix.

[0124] Traverse the decoding submatrix corresponding to each undirected edge in the three-code unified decoding matrix;

[0125] For any target element in the decoding submatrix corresponding to the traversed undirected edge, determine the first row order and first column order of the target element in the three-code-in-one decoding matrix. Based on the first row order and first column order, determine the corresponding target node in the memristor to be configured. The second row order and second column order of the target node in the memristor to be configured are equal to the first row order and first column order, respectively. When the target element is 0, set the resistance state of the target node to a high resistance state. When the target element is 1, set the resistance state of the target node to a low resistance state to obtain the decoding subarray corresponding to the undirected edge. The decoding subarray corresponding to the undirected edge is the subarray obtained by configuring the node resistance state in the memristor to be configured based on each target element in the decoding submatrix.

[0126] For any error correction code to be decoded, the decoding subarray corresponding to each undirected edge in the target probabilistic graphical model created based on the error correction code to be decoded is used as the decoding array corresponding to the error correction code to be decoded; wherein, the decoding array is an LDPC decoding array, a Polar decoding array, or a Turbo decoding array.

[0127] The decoding array corresponding to each error correction code to be decoded is used as a three-code unified decoding array.

[0128] The number of node rows in the memristor to be configured is the same as the number of element rows in the three-code unified decoding matrix, and the number of node columns in the memristor to be configured is the same as the number of element columns in the three-code unified decoding matrix.

[0129] by Figure 6 Taking the three-code-in-one decoding matrix shown as an example, this embodiment can obtain the following by configuring the resistance states of the nodes in the memristor to be configured: Figure 7 The diagram shows a three-in-one decoding array that includes a Turbo decoding array, a Polar decoding array, and an LDPC decoding array.

[0130] S108. Using the initial probability of the state value of each variable node and the three-code unified decoding array, perform unified decoding on each error correction code to be decoded to obtain the original bit information corresponding to each error correction code to be decoded.

[0131] Specifically, in this embodiment, the three error correction codes can be uniformly decoded on a three-code-in-one decoding array based on the initial probability of the state value of each variable node in the target probabilistic graphical model corresponding to the three error correction codes to be decoded, so as to obtain the original bit information corresponding to the three error correction codes to be decoded.

[0132] The three-code unified decoding method based on the probability domain of an in-memory computing unit proposed in this embodiment can configure a three-code unified decoding array, including an LDPC decoding array, a Polar decoding array, and a Turbo decoding array, on an in-memory computing unit based on the target probabilistic graphical models corresponding to the three error correction codes to be decoded. According to the probability domain operation method, the initial probability of the state value of each variable node in each target probabilistic graphical model is determined. Using the initial probability of the state value of each variable node in each target probabilistic graphical model and the three-code unified decoding array, the three error correction codes to be decoded are decoded in a unified manner, realizing the unified decoding of the LDPC code, Polar code, and Turbo code to be decoded, and can effectively reduce the power consumption of the unified decoding of the LDPC code, Polar code, and Turbo code to be decoded.

[0133] based on Figure 1 This embodiment proposes a second method for three-code unification decoding based on the probability domain of an in-memory computing device. In this method, the LDPC decoding array, Polar decoding array, and Turbo decoding array in the three-code unification decoding array can be used to decode the LDPC code, Polar code, and Turbo code to be decoded, thereby obtaining the original bit information corresponding to the LDPC code, Polar code, and Turbo code to be decoded, and realizing the unified decoding of the LDPC code, Polar code, and Turbo code to be decoded.

[0134] Specifically, step S108 includes:

[0135] For any error correction code to be decoded, the initial probability of the state value of each first variable node is used as the confidence level by which the first variable node transmits its own state value to each connected verification node. Based on each confidence level and each first undirected edge, a voltage column vector corresponding to each first undirected edge is constructed. Here, the first variable node is the variable node in the target probabilistic graphical model corresponding to the error correction code to be decoded, the first undirected edge is the undirected edge in the target probabilistic graphical model corresponding to the error correction code to be decoded, and the voltage column vector corresponding to the first undirected edge includes N voltage elements.

[0136] For any first undirected edge, based on the N voltage elements in the voltage column vector corresponding to the first undirected edge, generate N voltage signals corresponding one-to-one with the N voltage elements, and input the N voltage signals into the first N input terminals of the three-code-in-one decoding array from bottom to top, and read the output current of the decoding subarray corresponding to the first undirected edge; where N is a positive integer.

[0137] Based on the output current of the decoding subarray corresponding to each first undirected edge, the voltage column vector corresponding to each first undirected edge is iteratively updated until the iteration stopping condition is met, so as to decode the original bit information corresponding to the error correction code to be decoded.

[0138] Specifically, in this embodiment, for any verification node in the target probabilistic graphical model corresponding to the error correction code to be decoded, each target variable node connected to the verification node through undirected edges can be determined, and the target undirected edges between the verification node and each target variable node can be determined respectively. The number t of the target undirected edges is counted, and the internal order of each target undirected edge in all target undirected edges is determined respectively.

[0139] Construct multiple candidate vectors obtained by arranging and combining t target binary characters. For any candidate vector, if the element order of the target binary characters in the candidate vector is equal to the internal order of the target undirected edge, then establish an association between the target binary characters in the candidate vector and the target variable nodes connected by the target undirected edge.

[0140] Each target undirected edge is traversed sequentially. For the 'a'-th target undirected edge encountered, the 'a'-th element in each candidate vector is deleted, resulting in multiple first vectors. Duplicates are removed from these first vectors, resulting in multiple second vectors. For any second vector, the target confidence level corresponding to each target binary character in the second vector is determined. The target confidence levels corresponding to each target binary character in the second vector are multiplied together to obtain the product of the second vector. The products of each second vector are arranged to obtain the voltage column vector corresponding to the target undirected edge. The target confidence level corresponding to the target binary character in the second vector is the confidence level of the target variable node associated with the target binary character, which transmits its own state value, equal to the target binary character, to the verification node.

[0141] To better illustrate the above execution process, this embodiment continues to combine Example 1 and... Figure 2 Let me introduce it.

[0142] Example 1: Let 'a' be the internal order of the undirected edges connecting the third verification node. When 'a' is 3, the eight candidate vectors created in this embodiment are (0, 0, 0), (0, 0, 1), (0, 1, 0), (0, 1, 1), (1, 0, 0), (1, 0, 1), (1, 1, 0), and (1, 1, 1). In this case, the third element of each candidate vector can be deleted to obtain eight first vectors (0, 0), (0, 0), (0, 1), (0, 1), (1, 0), (1, 0), (1, 1), and (1, 1). After deduplication, the remaining four second vectors (0, 0), (0, 1), (1, 0), and (1, 1) are obtained. For any of the second vectors, such as the second vector (0, 1), this embodiment can determine the target confidence level corresponding to each target binary character in the second vector. The confidence level corresponding to the first target binary character in the second vector is: the confidence level of the target variable node (i.e., the second variable node) associated with the target binary character transmitting the message with its own state value equal to 0 to the third verification node. The confidence level corresponding to the second target binary character in the second vector is: the confidence level of the target variable node (i.e., the third variable node) associated with the target binary character transmitting the message with its own state value equal to 1 to the third verification node. Multiplying the two determined confidence levels yields one product corresponding to the second vector. Four products are calculated for the four second vectors. Arranging these four products vertically yields the voltage column vector corresponding to the third target undirected edge.

[0143] The voltage column vector corresponding to the target undirected edge constructed in this embodiment can be represented as:

[0144] .

[0145] by Let's take an example to explain the meaning of each character. Among them, Indicates the first i The verification node and the first j An undirected edge between variable nodes, where the subscript 2 of x represents the second element in the voltage column vector. Indicates the first i The verification node and the first j The second element in the voltage column vector corresponding to the undirected edge of each variable node.

[0146] Optionally, the voltage column vector corresponding to each first undirected edge is iteratively updated based on the output current of the decoding subarray corresponding to each first undirected edge until the iteration stopping condition is met, so as to decode the original bit information corresponding to the error correction code to be decoded, including:

[0147] Based on the output current of the decoding subarray corresponding to each first undirected edge, the new confidence level of each first variable node in transmitting its own state value to each connected check node, and the probability of the new state value of each first variable node are updated.

[0148] Hard decision is made on the probability of the new state value of each first variable node to obtain the codeword vector;

[0149] Perform a modulo operation on the target parity check matrix and the codeword vector to obtain the result;

[0150] If the calculation result is not equal to 0, it is determined that the iteration stopping condition has not been met. Each first variable node passes its own state value to each connected verification node with a new confidence level as the current confidence level. Then, the process of constructing the voltage column vector corresponding to each first undirected edge based on each confidence level and each first undirected edge is returned until the latest calculation result is equal to 0.

[0151] If the latest calculation result is equal to 0, then the iteration stopping condition is met, and the original bit information corresponding to the error correction code to be decoded is determined based on the latest codeword vector.

[0152] Specifically, each decoder subarray corresponding to the first undirected edge includes a first node column and a second node column, and the output current of each decoder subarray corresponding to the first undirected edge includes a first current value of the first node column and a second current value of the second node column.

[0153] Optionally, the above updates the new confidence level of each first variable node in transmitting its own state value to each connected check node, and the probability of the new state value of each first variable node, respectively, based on the output current of the decoding subarray corresponding to each first undirected edge, including:

[0154] Based on the first current value and the second current value read from the decoding subarray corresponding to each first undirected edge, the new confidence level of each first variable node in transmitting its own state value to each verification node is updated, and the new probability of the state value of each first variable node is updated.

[0155] Optionally, the above update of the new confidence level of each first variable node transmitting its own state value to each check node, and the update of the new probability of the state value of each first variable node, based on the first current value and the second current value read from the decoding subarray corresponding to each first undirected edge, includes:

[0156] For the first element with connectivity in the objective probabilistic graphical model i The verification node and the first jFor each first variable node, based on the check node and the node order of the first variable node, determine the group of undirected edges connected to the first variable node, and determine the first undirected edge between the check node and the first variable node. Then, determine any undirected edge in the group of undirected edges other than the first undirected edge as a second undirected edge. Multiply the first current value in the decoding subarray corresponding to each second undirected edge by the first initial probability in the initial probability of the first variable node's state value to obtain a new confidence level for the first variable node to transmit its own state value equal to 1 to the check node. Finally, multiply the second current value in the decoding subarray corresponding to each second undirected edge by the second initial probability in the initial probability of the first variable node's state value to obtain a new confidence level for the first variable node to transmit its own state value equal to 0 to the check node.

[0157] Optionally, the above update yields new probabilities for the state value of each first variable node, including:

[0158] For any first variable node, determine each undirected edge connected to the first variable node, multiply the first current value in the decoding subarray corresponding to each undirected edge connected to the first variable node by the square of the first initial probability in the initial probability of the first variable node's state value, and obtain a new probability that the first variable node's own state value is equal to 1. Multiply the second current value in the decoding subarray corresponding to each undirected edge connected to the first variable node by the square of the second initial probability in the initial probability of the first variable node's state value, and obtain a new probability that the first variable node's own state value is equal to 0.

[0159] To better illustrate the above execution process, this embodiment combines Example 1 and... Figure 2 and combination Figure 8 The Turbo decoding array in the three-code-in-one decoding array shown is used as an example to illustrate the process of decoding the Turbo code to be decoded using the Turbo decoding array in the three-code-in-one decoding array, respectively using the LDPC decoding array, Polar decoding array and Turbo decoding array in the three-code-in-one decoding array.

[0160] Example 1: In this embodiment, when introducing the construction of the initial decoding sub-matrix corresponding to the undirected edge, the first column vector and the second column vector are horizontally concatenated to obtain the initial decoding sub-matrix corresponding to the undirected edge. Specifically, in Figure 2The part of the decoding subarray corresponding to the third target undirected edge in the middle, except for all the filling 0 (only the 0 filling in the original null value position), is regarded as the target array. The target array includes a first node column and a second node column. The resistance state of each node in the first node column is configured according to each element in the first column vector, and the resistance state of each node in the second node column is configured according to each element in the second column vector.

[0161] The target array in the decoding subarray corresponding to the undirected edge constructed in this embodiment can be represented as a matrix:

[0162] .

[0163] Among them, with Let's take an example to explain the meaning of each character. Indicates the first i The verification node and the first j Undirected edges between nodes, where 1 and 2 in the x index represent... It is the second element in the first row of the target array. Indicates the first i The verification node and the first j The second element in the first row of the target array corresponds to the undirected edge between the variable nodes. and Each represents a candidate vector after the first processing described above. Each of these represents a candidate vector after the second processing described above. The first column on the left of this matrix is ​​configured based on the first column vector described above, and the second column on the right of this matrix is ​​configured based on the second column vector described above.

[0164] Among them, in the target array This is obtained by configuring the resistive states based on the elements of the initial decoding submatrix corresponding to the undirected edges, and the elements of the initial decoding submatrix can be configured as follows: , The negation operator is 'NOT', and mod is the modulo operator. The first element in the target parity-check matrix corresponding to the Turbo code to be decoded i row vectors. Indicates according to the first i The verification node and the first j The above-mentioned processed candidate vector is constructed from the undirected edges between the variable nodes.

[0165] like Figure 8 As shown, in this embodiment, based on the decoding subarray corresponding to each undirected edge in the target probabilistic graphical model corresponding to the Turbo code to be decoded, each target array has... The voltage column vector corresponding to each undirected edge is: The output currents of each decoder subarray read are: . Figure 8 The DAC is an exponential-to-analog converter, and the ADC is an exponential-to-digital converter.

[0166] in, This represents the target array in the decoder subarray corresponding to the undirected edge between the first verification node and the first target variable node with a connection relationship. Indicates the first I The verifiable node and the first node with a connection relationship The target array in the decoding subarray corresponds to the undirected edges between the target variable nodes. It should be noted that... and It does not refer to the second node order of the variable node, but rather to the order of the target variable node connected to the verification node among all target variable nodes connected to that verification node.

[0167] This represents the voltage column vector corresponding to the undirected edge between the first verification node and the first target variable node with a connection relationship. Indicates the first I The verifiable node and the first node with a connection relationship The voltage column vectors corresponding to the undirected edges between the target variable nodes. This includes the first and second current values ​​in the decoder subarray corresponding to the undirected edge between the first verification node and the first target variable node with a connection relationship. Including the first I The verifiable node and the first node with a connection relationship The first and second current values ​​in the decoder subarray corresponding to the undirected edges between the target variable nodes.

[0168] First, regarding the first undirected edge... When the voltage column vector corresponding to the undirected edge When the array includes N voltage elements, this embodiment can be based on the undirected edge corresponding to... The N voltage elements in the array are used to generate N voltage signals corresponding one-to-one with the N voltage elements via a digital-to-analog converter (DAC). These N voltage signals are then input to the first N input terminals of a three-in-one decoding array from bottom to top, thereby inputting the N voltage signals into the target array of the decoding subarray corresponding to the undirected edge. In this embodiment, the first and second current values ​​output by the decoding subarray corresponding to the undirected edge can then be read using an analog-to-digital converter (ADC). It does not read the output current of other decoding subarrays in the Turbo decoding array, nor does it read the output current values ​​of the LDPC decoding array and the Polar decoding array.

[0169] Next, this embodiment focuses on the next undirected edge. and When the voltage column vector corresponding to the undirected edge When the array includes N voltage elements, this embodiment can be based on the undirected edge corresponding to... The N voltage elements in the array are used to generate N voltage signals corresponding one-to-one with the N voltage elements via a digital-to-analog converter (DAC). These N voltage signals are then input to the first N input terminals of a three-in-one decoding array from bottom to top, thereby inputting the N voltage signals into the target array of the decoding subarray corresponding to the undirected edge. In this embodiment, the first and second current values ​​output by the decoding subarray corresponding to the undirected edge can then be read using an analog-to-digital converter (ADC). It does not read the output current of other decoding subarrays in the Turbo decoding array, nor does it read the output current values ​​of the LDPC decoding array and the Polar decoding array.

[0170] The output current of all decoding subarrays in the Turbo decoding array is processed and read until the process is complete.

[0171] The operation process performed in the decoder subarray can be represented in matrix multiplication form as follows:

[0172] .

[0173] in, T This is the matrix transpose symbol. and middle, ij Indicates the first i The verification node and the first j Undirected edges between nodes with variable values. (The value in parentheses is 1.) , indicating the first column. (The text in parentheses is incomplete and cannot be translated.) , indicating the second column. Indicates the first i The verification node and the first j The first current value output by the decoding subarray corresponding to the undirected edge between each variable node. Indicates the first i The verification node and the first j The second current value output by the decoder subarray corresponding to the undirected edge between the variable nodes.

[0174] Continuing with Example 1 above and Figure 2 This section describes the process of updating the confidence level of a variable node as it passes its own state value to the verification node.

[0175] For example, in this embodiment, during the process of updating the new confidence level obtained by the second variable node transmitting its own state value to the third verification node, all undirected edges connected to the second variable node, i.e., the undirected edge group (this undirected edge group includes the undirected edges between the second variable node and each verification node with a connection relationship), can be determined first, and the second variable node can be determined first. j The undirected edge between the first variable node and the third check node is called the first undirected edge. The undirected edges in this group other than the first undirected edge are called the second undirected edges. In this embodiment, the first current value in the decoding subarray corresponding to each second undirected edge is multiplied by the first initial probability in the initial probability of the state value of the second variable node to obtain the corresponding product. That is, the second variable node transmits its own state value of 1 to the third check node with a new confidence level. Similarly, the second current value in the decoding subarray corresponding to each second undirected edge is multiplied by the second initial probability in the initial probability of the state value of the second variable node to obtain the corresponding product. That is, the second variable node transmits its own state value of 0 to the third check node with a new confidence level.

[0176] The confidence update formula can be:

[0177] .

[0178] in, For the first j The first variable node passes its own state value to the first variable node. i The new confidence level of each verification node For the first j The first or second initial probability in the initial probability of the state values ​​of each variable node, when When it is 1, Let the first initial probability be, when When it is 0, This is the second initial probability. N ( j ) indicates the relationship with the first j A set of check nodes connected to each variable node. This indicates that, except for the first node in the set of verification nodes... i Other verification nodes besides the one verification node.

[0179] The confidence update formula can be implemented by cascading multipliers.

[0180] Then, this embodiment can update the new probability of the state value of each variable node. Continuing with Example 1 above and... Figure 2 This paper introduces the process of updating the confidence of variable nodes in the target probabilistic graphical model corresponding to the Turbo code to be decoded by passing their own state values ​​to the verification nodes during Turbo decoding using a Turbo decoding array.

[0181] For example, in this embodiment, for the second variable node in the target probabilistic graphical model corresponding to the Turbo code to be decoded, all undirected edges connected to the second variable node are determined. The squares of the first current values ​​in the decoding subarray corresponding to each undirected edge connected to the second variable node are multiplied together to obtain the corresponding product, which is the new probability that the state value of the second variable node is equal to 1. The squares of the second current values ​​in the decoding subarray corresponding to each undirected edge connected to the second variable node are multiplied together to obtain the corresponding product, which is the new probability that the state value of the second variable node is equal to 0.

[0182] The formula for calculating the new probability of the variable node's own state value can be expressed as:

[0183] ;

[0184] .

[0185] in, Indicates the first j The new probability of a variable node having a state value of 1. This represents the first initial probability in the initial probability of the state value of the variable node. Indicates the first j The new probability of a variable node having a state value of 0. This represents the second initial probability in the initial probability of the state value of the variable node.

[0186] The iteration stopping condition is a set condition used to determine whether to stop iterating or continue iterating.

[0187] Subsequently, this embodiment can determine whether decoding is successful by judging the iteration stopping condition based on the new probability of the state value of each variable node.

[0188] Specifically, in this embodiment, a hard decision can be made on the new probability of the state value of each variable node. If the new probability of a variable node's own state value being equal to 1 is greater than the new probability of its own state value being equal to 0, then the codeword corresponding to that variable node is determined to be 1. If the new probability of a variable node's own state value being equal to 1 is not greater than the new probability of its own state value being equal to 0, then the codeword corresponding to that variable node is determined to be 0.

[0189] The formula for a hard decision can be expressed as:

[0190] .

[0191] in, The first one obtained by decoding j The codewords corresponding to each variable node.

[0192] At this point, after hard-determining the new probabilities of the state values ​​of each variable node in this embodiment, a codeword vector consisting of J codewords can be generated. The target parity-check matrix and the codeword vector are then compared. Perform the modulo operation , H The target parity-check matrix corresponding to the Turbo code to be decoded is obtained. The calculation result is used to determine the decoding success. If the result is 0, the iteration stopping condition is met, the decoding is successful, and the first K codewords in the codeword vector are selected as the decoding result, i.e., the original bit information. If the result is not 0, the iteration stopping condition is not met, and the decoding is not successful. In this case, the new confidence level of each variable node, which is the state value passed to each check node, is used as the current confidence level. The process of constructing the voltage column vector corresponding to each first undirected edge based on each confidence level and each first undirected edge is repeated until the latest calculation result is 0.

[0193] Optionally, the above determination of the original bit information corresponding to the error-correcting code to be decoded based on the latest codeword vector includes:

[0194] When the error correction code to be decoded is an LDPC code or a Turbo code, determine the total number of characters K of the original bit information corresponding to the error correction code to be decoded, select the first K elements from the latest codeword vector, and use them as the original bit information corresponding to the error correction code to be decoded; where K is a positive integer.

[0195] When the error correction code to be decoded is the Polar code to be decoded, determine the total number of codewords N of the error correction code to be decoded, select the first N elements in the latest codeword vector, and use them as the original error correction code corresponding to the error correction code to be decoded. Decode the original error correction code corresponding to the error correction code to be decoded to obtain the original bit information corresponding to the error correction code to be decoded; where K is a positive integer.

[0196] Specifically, the latest calculation result is the remainder of the target parity matrix and the latest codeword vector. When the latest calculation result is equal to 0, this embodiment can determine that the iteration stopping condition is met, and determine the original bit information corresponding to the error correction code to be decoded in the latest codeword vector.

[0197] It should be noted that the process of using the LDPC decoding array in the three-code-in-one decoding array to decode the LDPC code to be decoded, and the process of using the Polar decoding array in the three-code-in-one decoding array to decode the Polar code to be decoded, can be referred to the above description of using the Turbo decoding array in the three-code-in-one decoding array to decode the Turbo code to be decoded, and will not be repeated here.

[0198] The three-code unification decoding method based on the probability domain of the in-memory computing unit proposed in this embodiment can use the LDPC decoding array, Polar decoding array and Turbo decoding array in the three-code unification decoding array to decode the LDPC code, Polar code and Turbo code to be decoded, respectively, to obtain the original bit information corresponding to the LDPC code, Polar code and Turbo code to be decoded, and realize the unified decoding of the LDPC code, Polar code and Turbo code to be decoded.

[0199] like Figure 9 As shown, this embodiment proposes a three-code unification decoding device based on the probability domain of an in-memory computing unit, applied at the decoding end. The device includes:

[0200] The receiving unit 901 is used to receive multiple error correction codes to be decoded sent by the encoding end; wherein, the multiple error correction codes to be decoded include LDPC codes, Polar codes and Turbo codes to be decoded, the error correction codes to be decoded are obtained by the encoding end digitally modulating the original error correction codes, and the original error correction codes are obtained by the encoding end encoding the original bit information;

[0201] The first creation unit 902 is used to create a target verification matrix and a target probability graph model based on any error correction code to be deciphered;

[0202] Unit 903 is used to determine the initial probability of the state value of each variable node in the target probabilistic graphical model based on the probability domain operation method.

[0203] The second creation unit 904 is used to create an initial decoding sub-matrix corresponding to each undirected edge based on each undirected edge and the target parity check matrix in the target probabilistic graphical model; wherein the number of matrix rows of the initial decoding sub-matrix corresponding to each undirected edge created based on each error correction code to be decoded is not exactly the same.

[0204] The splicing unit 905 is used to align the bottom end of the initial decoding submatrix corresponding to each undirected edge created according to each error correction code to be decoded and splice it horizontally to obtain the corresponding matrix containing null values.

[0205] Filling unit 906 is used to fill each null position in the null matrix with 0 to construct a three-in-one decoding matrix including LDPC decoding matrix, Polar decoding matrix and Turbo decoding matrix;

[0206] Configuration unit 907 is used to configure the node status in the in-memory computing unit according to the three-code-in-one decoding matrix to obtain a three-code-in-one decoding array including LDPC decoding array, Polar decoding array and Turbo decoding array.

[0207] The decoding unit 908 is used to perform unified decoding of each error correction code to be decoded using the initial probability of the state value of each variable node and the three-code unified decoding array, so as to obtain the original bit information corresponding to each error correction code to be decoded.

[0208] It should be noted that the processing procedures and beneficial effects of the receiving unit 901, the first creation unit 902, the determining unit 903, the second creation unit 904, the splicing unit 905, the filling unit 906, the configuration unit 907, and the decoding unit 908 can be referred to respectively. Figure 1 Steps S101 to S108 are not described in detail here.

[0209] Optionally, the first creation unit 902 is also used for:

[0210] An initial check matrix and a corresponding initial probability graphical model are created based on the error correction code to be decoded. The initial probability graphical model includes multiple initial variable nodes.

[0211] When the error correction code to be decoded is a Polar code or a Turbo code, the short loop structure in the initial parity check matrix and the initial probabilistic graphical model is eliminated to obtain the target parity check matrix and the target probabilistic graphical model. The target probabilistic graphical model includes each initial variable node and F extended variable nodes; where F is 0 or a positive integer.

[0212] When the error correction code to be decoded is the LDPC code to be decoded, the initial parity check matrix is ​​directly used as the target parity check matrix, and the initial probabilistic graphical model is used as the target probabilistic graphical model.

[0213] Optionally, the determining unit 903 is also used for

[0214] Obtain the noise variance corresponding to the error correction code to be decoded;

[0215] For any variable node in the target probabilistic graphical model, when the variable node is an initial variable node, according to the noise variance and probability domain operation method, calculate the first initial probability and the second initial probability of the original error correction codeword corresponding to the variable node being 1 and 0 respectively, under the condition that the received codeword corresponding to the variable node is known, and take the first initial probability and the second initial probability as a whole as the initial probability of the state value of the variable node.

[0216] When the variable node is an extended variable node, under the condition that the extended codeword corresponding to the variable node is known, the third initial probability and the fourth initial probability of the original error correction codeword corresponding to the variable node are 1 and 0 respectively, both determined to be 0.5, and the third initial probability and the fourth initial probability as a whole are used as the initial probability of the state value of the variable node.

[0217] Optionally, the number of rows in the initial decoding submatrix corresponding to each undirected edge created from the error correction code to be decoded may not be exactly the same;

[0218] The 905 splicing unit is also used for:

[0219] For any error correction code to be decoded, the initial decoding sub-matrix corresponding to each undirected edge created based on the error correction code to be decoded is aligned at the bottom and concatenated horizontally to obtain the null sub-matrix corresponding to the error correction code to be decoded; wherein, the null sub-matrix includes multiple null values ​​and the initial decoding sub-matrix corresponding to each undirected edge created based on the error correction code to be decoded.

[0220] Each null-value submatrix is ​​bottom-aligned and horizontally concatenated to obtain a null-value matrix; wherein the null-value matrix includes multiple null values ​​and an initial decoding submatrix corresponding to each undirected edge created based on each error-correcting code to be decoded.

[0221] Optionally, filler unit 906 is also used for:

[0222] For any undirected edge in the null value matrix, determine the target column order of the initial decoding submatrix in the null value matrix, fill each null position in the target column order of the null value matrix with 0, and take each 0 filled in the target column order and each element in the initial decoding submatrix as a whole as the decoding submatrix corresponding to the undirected edge.

[0223] For any error correction code to be decoded, the decoding sub-matrix corresponding to each undirected edge in the target probabilistic graphical model created based on the error correction code to be decoded will be used as the decoding matrix corresponding to the error correction code to be decoded; wherein, the decoding matrix corresponding to the error correction code to be decoded is an LDPC decoding matrix, a Polar decoding matrix, or a Turbo decoding matrix.

[0224] The decoding matrix corresponding to each error-correcting code to be decoded is used as a whole as a three-code unified decoding matrix.

[0225] Optionally, the elements in the three-code-in-one decoding matrix are 0 or 1; when the in-memory processor is a memristor, the configuration unit 907 is also used for:

[0226] Obtain the memristor to be configured corresponding to the three-code unified decoding matrix. The number of rows and columns of nodes in the memristor to be configured is the same as the number of rows and columns of elements in the three-code unified decoding matrix.

[0227] Traverse the decoding submatrix corresponding to each undirected edge in the three-code unified decoding matrix;

[0228] For any target element in the decoding submatrix corresponding to the traversed undirected edge, determine the first row order and first column order of the target element in the three-code-in-one decoding matrix. Based on the first row order and first column order, determine the corresponding target node in the memristor to be configured. The second row order and second column order of the target node in the memristor to be configured are equal to the first row order and first column order, respectively. When the target element is 0, set the resistance state of the target node to a high resistance state. When the target element is 1, set the resistance state of the target node to a low resistance state to obtain the decoding subarray corresponding to the undirected edge. The decoding subarray corresponding to the undirected edge is the subarray obtained by configuring the node resistance state in the memristor to be configured based on each target element in the decoding submatrix.

[0229] For any error correction code to be decoded, the decoding subarray corresponding to each undirected edge in the target probabilistic graphical model created based on the error correction code to be decoded is used as the decoding array corresponding to the error correction code to be decoded; wherein, the decoding array is an LDPC decoding array, a Polar decoding array, or a Turbo decoding array.

[0230] The decoding array corresponding to each error correction code to be decoded is used as a three-code unified decoding array.

[0231] Optionally, the decoding unit 908 is also used for:

[0232] For any error correction code to be decoded, the initial probability of the state value of each first variable node is used as the confidence level by which the first variable node transmits its own state value to each connected verification node. Based on each confidence level and each first undirected edge, a voltage column vector corresponding to each first undirected edge is constructed. Here, the first variable node is the variable node in the target probabilistic graphical model corresponding to the error correction code to be decoded, the first undirected edge is the undirected edge in the target probabilistic graphical model corresponding to the error correction code to be decoded, and the voltage column vector corresponding to the first undirected edge includes N voltage elements.

[0233] For any first undirected edge, based on the N voltage elements in the voltage column vector corresponding to the first undirected edge, generate N voltage signals corresponding one-to-one with the N voltage elements, and input the N voltage signals into the first N input terminals of the three-code-in-one decoding array from bottom to top, and read the output current of the decoding subarray corresponding to the first undirected edge; where N is a positive integer.

[0234] Based on the output current of the decoding subarray corresponding to each first undirected edge, the voltage column vector corresponding to each first undirected edge is iteratively updated until the iteration stopping condition is met, so as to decode the original bit information corresponding to the error correction code to be decoded.

[0235] Optionally, the decoding unit 908 is also used for:

[0236] Based on the output current of the decoding subarray corresponding to each first undirected edge, the new confidence level of each first variable node in transmitting its own state value to each connected check node, and the probability of the new state value of each first variable node are updated.

[0237] Hard decision is made on the probability of the new state value of each first variable node to obtain the codeword vector;

[0238] Perform a modulo operation on the target parity check matrix and the codeword vector to obtain the result;

[0239] If the calculation result is not equal to 0, it is determined that the iteration stopping condition has not been met. Each first variable node passes its own state value to each connected verification node with a new confidence level as the current confidence level. Then, the process of constructing the voltage column vector corresponding to each first undirected edge based on each confidence level and each first undirected edge is returned until the latest calculation result is equal to 0.

[0240] If the latest calculation result is equal to 0, then the iteration stopping condition is met, and the original bit information corresponding to the error correction code to be decoded is determined based on the latest codeword vector.

[0241] Optionally, the decoding unit 908 is also used for:

[0242] When the error correction code to be decoded is an LDPC code or a Turbo code, determine the total number of characters K of the original bit information corresponding to the error correction code to be decoded, select the first K elements from the latest codeword vector, and use them as the original bit information corresponding to the error correction code to be decoded; where K is a positive integer.

[0243] When the error correction code to be decoded is the Polar code to be decoded, determine the total number of codewords N of the error correction code to be decoded, select the first N elements in the latest codeword vector, and use them as the original error correction code corresponding to the error correction code to be decoded. Decode the original error correction code corresponding to the error correction code to be decoded to obtain the original bit information corresponding to the error correction code to be decoded; where K is a positive integer.

[0244] The three-code unification decoding device based on the probability domain of the in-memory computing unit proposed in this embodiment can realize the unified decoding of LDPC codes, Polar codes and Turbo codes to be decoded, and can effectively reduce the power consumption of unified decoding of LDPC codes, Polar codes and Turbo codes to be decoded.

[0245] In this embodiment, the probability domain-based three-code decoding device based on in-memory computing is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0246] This invention also provides a computer device having the above-described features. Figure 9 The device shown is a probability domain-based three-code decoding device based on an in-memory computing unit.

[0247] Please see Figure 10 The present invention provides a schematic diagram of the structure of a computer device according to an optional embodiment. The computer device includes one or more processors 10, a memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are interconnected via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on an external input / output device (such as a display device coupled to the interface). In some optional embodiments, multiple processors and / or multiple buses can be used with multiple memories, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 10 Take a processor 10 as an example.

[0248] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0249] The memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.

[0250] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function. The data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, which can be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0251] Memory 20 may include volatile memory, such as random access memory. Memory may also include non-volatile memory, such as flash memory, hard disk, or solid-state drive. Memory 20 may also include combinations of the above types of memory.

[0252] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0253] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0254] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for three-code unification decoding based on the probability domain of an in-memory computing device, characterized in that, Applied to the decoding end, the method includes: The receiver sends multiple error correction codes to be decoded, including LDPC codes, Polar codes, and Turbo codes to be decoded. For any of the error correction codes to be decoded, a target parity-check matrix and a target probabilistic graphical model are created based on the error correction code. The initial probability of the state value of each variable node in the target probabilistic graphical model is determined based on the probability domain operation method. Based on each undirected edge in the target probabilistic graphical model and the target parity-check matrix, an initial decoding submatrix corresponding to each undirected edge is created. The number of rows in the initial decoding submatrix corresponding to each undirected edge created based on each error correction code to be decoded is not exactly the same. The initial decoding submatrix corresponding to each undirected edge created based on each of the error correction codes to be decoded is aligned at the bottom and concatenated horizontally to obtain the corresponding matrix containing null values. Fill each null value position in the null value matrix with 0 to construct a three-in-one decoding matrix including the LDPC decoding matrix, the Polar decoding matrix, and the Turbo decoding matrix; Based on the three-code-in-one decoding matrix, the node state is configured in the in-memory computing unit to obtain a three-code-in-one decoding array including an LDPC decoding array, a Polar decoding array, and a Turbo decoding array; Using the initial probability of the state value of each variable node and the three-code unified decoding array, each error correction code to be decoded is uniformly decoded to obtain the original bit information corresponding to each error correction code to be decoded.

2. The method according to claim 1, characterized in that, The error correction code to be decoded is obtained by digitally modulating the original error correction code at the encoding end, and the original error correction code is obtained by encoding the original bit information at the encoding end; the step of creating a target parity check matrix and a target probability graph model based on the error correction code to be decoded includes: An initial parity check matrix and a corresponding initial probability graphical model are created based on the error correction code to be decoded. The initial probability graphical model includes multiple initial variable nodes. When the error correction code to be decoded is a Turbo code to be decoded, the short loop structure in the initial parity check matrix and the initial probabilistic graphical model is eliminated to obtain the target parity check matrix and the target probabilistic graphical model. The target probabilistic graphical model includes each of the initial variable nodes and E extended variable nodes; where E is 0 or a positive integer. When the error correction code to be decoded is a Polar code to be decoded, the butterfly polarization relation corresponding to the error correction code to be decoded is tiled to generate an intermediate probability graphical model and an intermediate parity check matrix. The intermediate probability graphical model includes each of the initial variable nodes and F additional variable nodes. The intermediate probability graphical model and the intermediate parity check matrix are pruned and optimized to obtain the target probability graphical model. The target probability graphical model includes each of the initial variable nodes and Z additional variable nodes; where F and Z are positive integers, and F is greater than Z. When the error correction code to be decoded is an LDPC code to be decoded, the initial parity check matrix is ​​directly used as the target parity check matrix, and the initial probabilistic graphical model is used as the target probabilistic graphical model.

3. The method according to claim 2, characterized in that, The determination of the initial probability of the state value of each variable node in the target probabilistic graphical model based on probability domain arithmetic includes: Obtain the noise variance corresponding to the error correction code to be decoded; For any variable node in the target probabilistic graphical model, when the variable node is the initial variable node, according to the noise variance and probability domain operation method, the first initial probability and the second initial probability of the original error correction codeword corresponding to the variable node are 1 and 0 respectively, under the condition that the received codeword corresponding to the variable node is known, and the first initial probability and the second initial probability as a whole are taken as the initial probability of the state value of the variable node. When the variable node is the extended variable node or the added variable node, under the condition that the extended codeword corresponding to the variable node is known, the third initial probability and the fourth initial probability of the original error correction codeword corresponding to the variable node being 1 and 0 respectively are both determined to be 0.5, and the third initial probability and the fourth initial probability as a whole are used as the initial probability of the state value of the variable node.

4. The method according to claim 1, characterized in that, The number of rows in the initial decoding submatrix corresponding to each undirected edge created based on the error correction code to be decoded is not exactly the same; The step of aligning the bottom edges of the initial decoding submatrices corresponding to each undirected edge created based on each of the error-correcting codes to be decoded and concatenating them horizontally to construct a matrix containing null values ​​includes: For any of the error correction codes to be decoded, the initial decoding sub-matrices corresponding to each undirected edge created based on the error correction code to be decoded are aligned at the bottom and concatenated horizontally to obtain a null sub-matrice corresponding to the error correction code to be decoded; wherein, the null sub-matrice includes multiple null values ​​and the initial decoding sub-matrices corresponding to each undirected edge created based on the error correction code to be decoded. Each null-value submatrix is ​​bottom-aligned and horizontally concatenated to obtain the null-value matrix; wherein, the null-value matrix includes multiple null values ​​and an initial decoding submatrix corresponding to each undirected edge created according to each of the error correction codes to be decoded.

5. The method according to claim 4, characterized in that, The process of filling each null value position in the null-value matrix with 0 to construct a three-in-one decoding matrix including the LDPC decoding matrix, the Polar decoding matrix, and the Turbo decoding matrix includes: For any undirected edge in the null value matrix, determine the target column order of the initial decoding submatrix in the null value matrix, fill each null position in the target column order of the null value matrix with 0, and take each 0 filled in the target column order and each element in the initial decoding submatrix as a whole as the decoding submatrix corresponding to the undirected edge. For any of the error correction codes to be decoded, the decoding sub-matrix corresponding to each undirected edge in the target probabilistic graphical model created based on the error correction code to be decoded is used as the decoding matrix corresponding to the error correction code to be decoded; wherein, the decoding matrix corresponding to the error correction code to be decoded is an LDPC decoding matrix, a Polar decoding matrix, or a Turbo decoding matrix. The decoding matrix corresponding to each of the error-correcting codes to be decoded is taken as the three-code unified decoding matrix.

6. The method according to claim 5, characterized in that, The elements in the three-code unified decoding matrix are 0 or 1; when the in-memory computing unit is a memristor, the node state configuration in the in-memory computing unit based on the three-code unified decoding matrix yields a three-code unified decoding array including an LDPC decoding array, a Polar decoding array, and a Turbo decoding array, including: Obtain the memristor to be configured corresponding to the three-code unified decoding matrix, wherein the number of rows and columns of nodes in the memristor to be configured is the same as the number of rows and columns of elements in the three-code unified decoding matrix; Traverse the decoding submatrix corresponding to each undirected edge in the three-code unified decoding matrix; For any target element in the decoding submatrix corresponding to the traversed undirected edge, determine the first row order and first column order of the target element in the three-code-in-one decoding matrix. Based on the first row order and first column order, determine the corresponding target node in the memristor to be configured. The second row order and second column order of the target node in the memristor to be configured are equal to the first row order and first column order, respectively. When the target element is 0, set the resistance state of the target node to a high resistance state. When the target element is 1, set the resistance state of the target node to a low resistance state to obtain the decoding subarray corresponding to the undirected edge. The decoding subarray corresponding to the undirected edge is a subarray obtained by configuring the node resistance state in the memristor to be configured based on each target element in the decoding submatrix. For any of the error correction codes to be decoded, the decoding subarrays corresponding to each undirected edge in the target probabilistic graphical model created based on the error correction codes to be decoded are used as the decoding array corresponding to the error correction codes to be decoded; wherein, the decoding array is an LDPC decoding array, a Polar decoding array, or a Turbo decoding array. The decoding array corresponding to each of the error-correcting codes to be decoded is taken as the three-code-in-one decoding array.

7. The method according to claim 6, characterized in that, The method of using the initial probability of the state value of each variable node and the three-code unified decoding array to uniformly decode each error correction code to be decoded, and obtaining the original bit information corresponding to each error correction code to be decoded, includes: For any of the error correction codes to be decoded, the initial probability of the state value of each first variable node is used as the confidence level by which the first variable node transmits its own state value to each connected verification node. Based on each confidence level and each first undirected edge, a voltage column vector corresponding to each first undirected edge is constructed. Wherein, the first variable node is the variable node in the target probabilistic graphical model corresponding to the error correction code to be decoded, the first undirected edge is the undirected edge in the target probabilistic graphical model corresponding to the error correction code to be decoded, and the voltage column vector corresponding to the first undirected edge includes N voltage elements. For any of the first undirected edges, based on the N voltage elements in the voltage column vector corresponding to the first undirected edge, N voltage signals corresponding one-to-one with the N voltage elements are generated, and the N voltage signals are respectively input to the first N input terminals of the three-code-in-one decoding array from bottom to top, and the output current of the decoding subarray corresponding to the first undirected edge is read; where N is a positive integer; Based on the output current of the decoding subarray corresponding to each of the first undirected edges, the voltage column vector corresponding to each of the first undirected edges is iteratively updated until the iteration stopping condition is met, so as to decode the original bit information corresponding to the error correction code to be decoded.

8. The method according to claim 7, characterized in that, The step of iteratively updating the voltage column vector corresponding to each of the first undirected edges based on the output current of the decoding subarray corresponding to each first undirected edge until the iteration stopping condition is met, in order to decode the original bit information corresponding to the error correction code to be decoded, includes: Based on the output current of the decoding subarray corresponding to each first undirected edge, the new confidence level of each first variable node in transmitting its own state value to each of the connected verification nodes, and the probability of the new state value of each first variable node are updated. Hard decision is made on the probability of the new state value of each first variable node to obtain the codeword vector; Perform a modulo operation between the target parity-check matrix and the codeword vector to obtain the result. If the calculation result is not equal to 0, it is determined that the iteration stopping condition is not met. Each first variable node passes its own state value to each connected verification node with a new confidence level as the current confidence level. Then, the step of constructing the voltage column vector corresponding to each first undirected edge based on each confidence level and each first undirected edge is returned until the latest calculation result is equal to 0. If the latest calculation result is equal to 0, then the iteration stopping condition is satisfied, and the original bit information corresponding to the error correction code to be decoded is determined according to the latest codeword vector.

9. The method according to claim 8, characterized in that, The step of determining the original bit information corresponding to the error-correcting code to be decoded based on the latest codeword vector includes: When the error correction code to be decoded is an LDPC code or a Turbo code to be decoded, determine the total number of characters K of the original bit information corresponding to the error correction code to be decoded, select the first K elements from the latest codeword vector, and use them as the whole as the original bit information corresponding to the error correction code to be decoded; where K is a positive integer; When the error correction code to be decoded is a Polar code to be decoded, the total number of codewords N of the error correction code to be decoded is determined, the first N elements are selected from the latest codeword vector, and the whole is used as the original error correction code corresponding to the error correction code to be decoded. The original error correction code corresponding to the error correction code to be decoded is decoded to obtain the original bit information corresponding to the error correction code to be decoded; where K is a positive integer.

10. A three-code decoding device based on the probability domain of a memory computing unit, characterized in that, Applied to a decoding end, the device includes: The receiving unit is used to receive multiple error correction codes to be decoded sent by the encoding end, wherein the multiple error correction codes to be decoded include LDPC codes, Polar codes and Turbo codes to be decoded; The first creation unit is used to create a target verification matrix and a target probability graph model based on any of the error correction codes to be deciphered. The determining unit is used to determine the initial probability of the state value of each variable node in the target probabilistic graphical model based on the probability domain operation method. The second creation unit is used to create an initial decoding sub-matrix corresponding to each undirected edge based on each undirected edge in the target probabilistic graphical model and the target parity check matrix; wherein the number of matrix rows of the initial decoding sub-matrix corresponding to each undirected edge created based on each error correction code to be decoded is not exactly the same; The splicing unit is used to align the bottom end of the initial decoding submatrix corresponding to each undirected edge created according to each of the error correction codes to be decoded and splice them horizontally to obtain the corresponding matrix containing null values. Filling units are used to fill each null position in the null matrix with 0 to construct a three-in-one decoding matrix including the LDPC decoding matrix, the Polar decoding matrix, and the Turbo decoding matrix. The configuration unit is used to configure the node state in the in-memory computing unit according to the three-code-in-one decoding matrix to obtain a three-code-in-one decoding array including an LDPC decoding array, a Polar decoding array, and a Turbo decoding array. The decoding unit is used to perform unified decoding on each of the error correction codes to be decoded using the initial probability of the state value of each variable node and the three-code unified decoding array, so as to obtain the original bit information corresponding to each error correction code to be decoded.

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