Network topology configuration method and system and signal switch

Abstract

The invention provides a network topology configuration method and system and a signal switch, and relates to the technical field of communication. The method is applied to a master station and a plurality of slave stations which are connected based on a daisy chain physical topology, each slave station comprises a signal switch, and each signal switch comprises a plurality of pairs of wires and a switch array. The master station obtains topological information of a network, generates a tree topology according to the topological information, and sends switch configuration information to the plurality of slave stations. The switch configuration information is used for indicating the plurality of slave stations to configure a switch array, so that the master station and the plurality of slave stations form a tree topology. And the slave stations receive the switch configuration information sent by the master station and configure the switch arrays of the slave stations according to the switch configuration information, so that the slave stations are directly connected or in bypass connection with the upstream and downstream slave stations to form a tree topology. Thus, on the basis of the daisy chain physical topology, the connection mode of the master station and the plurality of slave stations is changed from the daisy chain topology to the tree topology, the data transmission hop count between the slave stations and the master station is greatly reduced, and the message transmission delay of large-scale networking is reduced.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a network topology configuration method, system and signal switch. Background Technology

[0002] In industrial motion control scenarios, frame aggregation is commonly used to aggregate messages from slave stations to master stations, thereby improving bandwidth utilization, resolving long message queuing times, and reducing message latency. However, while frame aggregation is suitable for daisy-chain networks or tree-structured networks where the actual signal routing remains daisy-chain, message transmission latency increases linearly with the number of hops in the daisy chain. This results in high latency in large-scale networks. Summary of the Invention

[0003] This application provides a network topology configuration method, system, and signal switch to solve the problem of high message transmission latency in daisy-chain networking. The technical solution is as follows:

[0004] Firstly, a network topology configuration method is provided, applied to a master station in a network. The master station and multiple slave stations are connected sequentially in a daisy-chain topology. At least one of the slave stations includes a signal switch, which comprises multiple pairs of wires and a switch array. The switch array is used to determine the connection method of the multiple pairs of wires. The method includes: First, the master station acquires the network topology information. Then, the master station generates a tree topology based on the topology information. In this tree topology, any slave station among the multiple slave stations is directly connected or bypassed to its upstream or downstream slave stations. Next, the master station sends switch configuration information to the multiple slave stations. The switch configuration information instructs the multiple slave stations to configure the switch array so that the master station and the multiple slave stations form a tree topology.

[0005] Based on the network topology configuration method described above, the master station uses switch configuration information to instruct the slave stations to configure the switch array of signal switches, controlling the direct or bypass connection between the slave stations and upstream and downstream slave stations. This changes the connection method between the master station and multiple slave stations from a daisy-chain topology to a tree topology, building upon the existing daisy-chain physical topology. In this way, while retaining the easily deployable daisy-chain IoT architecture, the number of data transmission hops between slave and master stations is significantly reduced, lowering message transmission latency in large-scale networks.

[0006] As one possible implementation, network topology information is carried by topology information messages. The master station receives topology information messages sent by multiple slave stations. These messages include network topology information, which includes the position and connection relationships of the master station and the multiple slave stations within the daisy-chain topology.

[0007] Optionally, topology information messages can be proactively reported from the slave station to the master station. For example, the slave station periodically sends topology information messages to the master station.

[0008] Optionally, topology information messages can be retrieved by the master station. For example, during network initialization or topology changes, the master station retrieves topology information messages from multiple slave stations.

[0009] As one possible implementation, after determining the initial tree topology based on the number of slave stations and fractal rules in the topology information, the master station removes branches from the initial tree topology that exceed the number of multiple pairs of wires in the signal switches, thus obtaining the final tree topology. The fractal rules are used to indicate the overall wiring structure of the tree topology. In this way, the master station determines the final tree topology based on the number of tree topology branches supported by the number of multiple pairs of wires in the signal switches, avoiding the situation where slave stations cannot achieve the master station's determination of the tree topology through the switch array configuration in the control signal switches.

[0010] As one possible implementation, the master station sends switch configuration information to the processors of multiple slave stations, and the processors of the slave stations send switch configuration information to the switch register.

[0011] As one possible implementation, the switch configuration information includes multiple slave switch configurations, with each slave switch configuration corresponding to a slave station.

[0012] Optionally, the switch configuration information includes a switch configuration identifier and multiple slave identifiers. The switch configuration identifier is used to indicate the switch configuration information. The slave identifier is used to indicate the slave corresponding to any slave switch configuration information in the slave switch configuration information.

[0013] Secondly, a network topology configuration method is provided, applied to slave stations in a network. A master station and multiple slave stations are connected sequentially in a daisy-chain topology. At least one slave station includes a signal switch, which comprises multiple pairs of wires and a switch array. The switch array is used to determine the connection method of the multiple pairs of wires. The method includes: first, the slave station receives switch configuration information sent by the master station; then, the slave station configures the switch array according to the switch configuration information, so that the master station and the multiple slave stations form a tree topology.

[0014] One possible implementation is for the slave station to send a topology information message to the master station. This topology information message includes network topology information, such as the position and connection relationships of the master station and multiple slave stations within the daisy-chain topology.

[0015] In one possible implementation, the slave station includes a processor and a switch register. The processor receives switch configuration information sent by the master station and sends the switch configuration information to the switch register.

[0016] As one possible implementation, the switch configuration information includes multiple slave switch configurations. The switch configuration information includes a switch configuration identifier and multiple slave identifiers. The switch configuration identifier is used to indicate the switch configuration information, and the slave identifier is used to indicate the slave corresponding to any slave switch configuration information among the multiple slave switch configuration information.

[0017] Optionally, the slave station configures the switch array according to the slave switch configuration information indicated in the switch configuration information.

[0018] Regarding the technical principles and beneficial effects of the second aspect, please refer to the relevant description of the first aspect mentioned above, which will not be repeated here.

[0019] Thirdly, a signal switch is provided, which is installed in a slave station of a network. A master station and multiple slave stations are connected sequentially in a daisy-chain topology. At least one of the slave stations includes a signal switch, which comprises multiple pairs of wires and a switch array. The switch array is used to determine the connection method of the multiple pairs of wires. At least one wire of the multiple pairs of wires of the signal switch and the switch array are used to connect to the processor of the slave station through at least one interface. The switch array and the multiple pairs of wires form a circuit that directly connects to any one of the at least one interface, or bypasses any one of the at least one interface through a bypass connection, so that any slave station in the network can be directly or bypassed to upstream or downstream slave stations, forming a tree topology.

[0020] In this way, by configuring the switch array, the signal switch can change the connection method between the slave station and the upstream and downstream stations, connecting them directly or by bypass, thereby transforming the daisy chain logic topology into a tree topology.

[0021] As one possible implementation, the switch array includes at least one single-pole double-throw switch.

[0022] Optionally, at least one interface has m interfaces connected to the switch array, and the number of pairs of wires is n. The switch array includes m-1 columns and n rows of single-pole double-throw switches. The moving end of the single-pole double-throw switch located in the second row and second column is connected to any interface in at least one interface. The stationary end of the single-pole double-throw switch located in the (m-1)th column and nth row is connected to the output line of the last pair of wires in the multiple pairs of wires. The moving end of the single-pole double-throw switch located in the first column is connected to the input line of any interface in at least one interface and any pair of wires in the multiple pairs of wires. The stationary end of the single-pole double-throw switch located in the (m-1)th column is connected to the output line of any pair of wires in the multiple pairs of wires. The moving end of the single-pole double-throw switch located in the i-th row and j-th column is connected to the stationary end of the single-pole double-throw switch located in the i-th row and j-1th column and the stationary end of the single-pole double-throw switch located in the (i+1)th row and j-1th column. Where m and n are positive integers, i is a positive integer less than n, and j is a positive integer less than m-1.

[0023] For example, at least one interface includes a first interface, a second interface, and a third interface; multiple pairs of lines include a first input line, a first output line, a second input line, a second output line, a third input line, a third output line, a fourth input line, and a fourth output line; the switch array includes a first single-pole double-throw (SPD) switch, a second SPD switch, a third SPD switch, a fourth SPD switch, a fifth SPD switch, and a sixth SPD switch. The first input line is connected to the processor via the first interface. The first moving terminal of the first SPD switch is connected to the processor via the second interface; the second moving terminal of the first SPD switch is connected to the stationary terminal of the second SPD switch; and the stationary terminal of the first SPD switch is connected to the first output line. The first moving terminal of the second SPD switch is connected to the processor via the third interface; the second moving terminal of the second SPD switch is connected to the second input line; and the stationary terminal of the second SPD switch is also connected to the first moving terminal of the third SPD switch. The second moving terminal of the third SPD switch is connected to the stationary terminal of the fourth SPD switch; and the stationary terminal of the third SPD switch is connected to the second output line. The first moving terminal of the fourth single-pole double-throw switch is connected to the second input line, the second moving terminal of the fourth single-pole double-throw switch is connected to the third input line, and the stationary terminal of the fourth single-pole double-throw switch is also connected to the first moving terminal of the fifth single-pole double-throw switch. The second moving terminal of the fifth single-pole double-throw switch is connected to the stationary terminal of the sixth single-pole double-throw switch, and the stationary terminal of the fifth single-pole double-throw switch is connected to the third output line. The first moving terminal of the sixth single-pole double-throw switch is connected to the third input line, the second moving terminal of the sixth single-pole double-throw switch is connected to the fourth input line, and the stationary terminal of the sixth single-pole double-throw switch is connected to the fourth output line.

[0024] As one possible implementation, the output lines in a multi-pair configuration include signal compensation circuitry.

[0025] Regarding the technical principles and beneficial effects of the third aspect, please refer to the relevant description of the application of signal switches to slave stations in the first aspect mentioned above, which will not be repeated here.

[0026] Fourthly, a circuit board is provided, including a processor and a signal switch as described in the second aspect above, wherein the processor is connected to at least one of a plurality of pairs of lines and a switch array via at least one interface.

[0027] Fifthly, a chip is provided, including the signal switch described in the second aspect above, wherein the signal switch is connected to the media access control (MAC) layer via at least one interface.

[0028] Sixthly, a network topology configuration device is provided. This network topology configuration includes a transceiver module and a processing module. The transceiver module is used to acquire network topology information. The processing module is used to determine a tree topology based on the topology information; in the tree topology, any one of the multiple slave stations is directly connected or bypassed to its upstream or downstream slave stations. The transceiver module is also used to send switch configuration information to the multiple slave stations; the switch configuration information is used to instruct the multiple slave stations to configure a switch array according to the switch configuration information, so that the master station and the multiple slave stations form a tree topology.

[0029] As one possible implementation, the transceiver module is specifically used to: acquire topology information messages sent by multiple slave stations; the topology information messages include network topology information, which includes the positions and connections of multiple master stations and slave stations in the daisy chain topology.

[0030] As one possible implementation, the processing module is specifically used to: determine the initial tree topology based on the number of multiple slave stations and fractal rules in the topology information; the fractal rules are used to indicate the overall connection structure of the tree topology; and remove branches in the initial tree topology that exceed the number of pairs of lines of the signal switches to obtain the final tree topology.

[0031] In one possible implementation, each of the multiple slave stations includes a processor and a switch register. Specifically, the transceiver module is used to: send switch configuration information to the processors of the multiple slave stations; and the processors send switch configuration information to the switch registers, which instruct the multiple slave stations to configure the switch array according to the switch configuration information, thus forming a tree topology between the master station and the multiple slave stations.

[0032] As one possible implementation, the switch configuration information includes multiple slave switch configuration information. The slave switch configuration information includes a switch configuration identifier and multiple slave identifiers. The switch configuration identifier is used to indicate the switch configuration information, and the slave identifier is used to indicate the slave corresponding to any one of the multiple slave switch configuration information.

[0033] Seventhly, a network topology configuration device is provided. This network topology configuration includes a transceiver module and a processing module. The transceiver module is used to receive switch configuration information sent by the master station. The processing module is used to configure a switch array according to the switch configuration information, enabling the master station and multiple slave stations to form a tree topology.

[0034] As one possible implementation, the transceiver module is also used to: send topology information messages to the master station; the topology information messages include network topology information, including the position and connection relationship of the master station and multiple slave stations in the daisy chain topology.

[0035] As one possible implementation, the slave station includes a processor and a switch register. The transceiver module is specifically used to: receive switch configuration information sent by the master station via the processor, and send switch configuration information to the switch register via the processor.

[0036] As one possible implementation, the switch configuration information includes multiple slave switch configurations. This configuration information includes a switch configuration identifier and multiple slave identifiers. The switch configuration identifier indicates the switch configuration information, and the slave identifier indicates the slave corresponding to any one of the multiple slave switch configurations. Specifically, the processing module configures the switch array according to the slave switch configuration information corresponding to its own slave identifier within the switch configuration information.

[0037] Regarding the technical principles and beneficial effects of aspects six and seven, please refer to the relevant description of the application of signal switches to slave stations in aspect one above, which will not be repeated here.

[0038] Eighthly, a network topology configuration system is provided, including a master station and multiple slave stations, wherein the master station and multiple slave stations are connected sequentially in a daisy-chain topology, and any one of the multiple slave stations includes the signal switch described in the third aspect above.

[0039] A ninth aspect provides a computer-readable storage medium storing at least one instruction, which is loaded and executed by a processor to implement the network topology configuration method described in any possible implementation of the first or second aspect above. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of a daisy chain topology;

[0041] Figure 2 A schematic diagram of a network architecture provided for this application;

[0042] Figure 3 A schematic diagram of a slave station structure is provided for this application;

[0043] Figure 4 A flowchart illustrating a network topology configuration method provided in this application;

[0044] Figure 5 A schematic diagram of a fractal rule provided for this application;

[0045] Figure 6 A schematic diagram of the connection rules for a tree topology provided in this application;

[0046] Figure 7 A schematic diagram of the wiring rules for a signal switch provided in this application;

[0047] Figure 8 This application provides a schematic diagram of the structure of an inter-board level signal switch;

[0048] Figure 9 This application provides a schematic diagram of the structure of a chip-level signal switch;

[0049] Figure 10 A schematic diagram of a network topology configuration device provided in this application;

[0050] Figure 11 A schematic diagram of another network topology configuration device provided in this application;

[0051] Figure 12 This is a schematic diagram of the structure of an electronic device provided in this application. Detailed Implementation

[0052] The terminology used in the embodiments section of this application is only for explaining specific embodiments of this application and is not intended to limit this application. For example, the network topology configuration method and signal switch provided in the embodiments of this application can be applied to scenarios in the communication field where the network has a daisy-chain topology. The following is a brief introduction to the technologies that may be involved in this application.

[0053] (1) Chrysanthemum chain

[0054] A daisy chain, also known as a daisy-chain topology, is a connection method in computer networks, also called a linear topology. For example... Figure 1 As shown, a daisy chain connects multiple devices (such as...) Figure 1 Devices 1-5 shown are connected in a linear order. Each device is connected to adjacent or upstream / downstream devices via a single link, forming a linear or ring structure. In a daisy-chain topology, data transmission from one endpoint to another requires passing through all the devices; that is, data passes through each device in the daisy chain sequentially during transmission.

[0055] (2) Tree topology

[0056] A tree topology is a local area network (LAN) topology similar to a bus topology. A tree network can contain branches, and each branch can contain multiple nodes. Tree topology is an extension of bus topology; the transmission medium is an open-ended branch cable. Like bus topology, in a tree topology, if one station sends data, all other stations can receive it.

[0057] (3) Ethernet control automation technology

[0058] Ethernet control automation technology (EtherCAT) is an open architecture fieldbus system based on Ethernet that can be applied to fields such as industrial automation, robotics, motion control, and measurement.

[0059] In an EtherCAT hardware network architecture, there is typically one master station and multiple slave stations. The master station can use a standard Ethernet controller, offering good compatibility; for example, any computer with a network interface card and any embedded device with Ethernet control can serve as an EtherCAT master. The master station is the central control unit in EtherCAT, responsible for coordinating the operation and communication of the entire network. Slave stations are the controlled devices or modules in EtherCAT, responsible for providing input / output functions and executing commands from the master station.

[0060] Unlike traditional Ethernet communication protocols, EtherCAT employs a special real-time Ethernet technology. By embedding control commands and data within data frames, it achieves real-time data processing and transmission, thereby reducing communication latency and enabling simultaneous communication and data transmission between multiple devices. As the aggregate frame passes through each device (including lower-level terminal devices), the slave station reads the data important to that device. Similarly, input data can be inserted into the message as it passes through the slave station. While the aggregate frame is being transmitted, the slave station identifies and processes the relevant commands. The last EtherCAT slave station in the network segment returns a fully processed message, which then serves as a response message from the first slave station back to the master station.

[0061] Currently, EtherCAT is only suitable for daisy chain networking in scenarios with low latency requirements, or tree networking but with the actual data transmission path being daisy chained. Therefore, the data transmission latency increases linearly with the number of hops in the data transmission, which cannot meet the low latency requirements in large-scale networking.

[0062] This application provides a network topology configuration method, particularly a method for configuring a tree topology in a daisy chain by controlling the signal switches of slave stations using switch configuration information. The method is applied to a master station in a network, which also includes multiple slave stations. The master station and the slave stations are connected sequentially in a daisy chain topology. Each slave station includes a signal switch, which comprises multiple pairs of wires and a switch array. The switch array is used to determine the connection method of the multiple pairs of wires. The method includes: the master station acquiring network topology information, determining a tree topology based on the topology information, and directly or indirectly connecting any slave station in the tree topology to its upstream or downstream slave stations. Then, the master station sends switch configuration information to the multiple slave stations, instructing them to configure the switch array according to the switch configuration information, thereby forming a tree topology between the master station and the multiple slave stations.

[0063] Based on the network configuration method described above, the master station uses switch configuration information to instruct the slave stations to configure the switch array of signal switches, controlling the direct or bypass connection between the slave stations and upstream and downstream slave stations. This changes the connection method between the master station and multiple slave stations from a daisy-chain topology to a tree topology, building upon the existing daisy-chain physical topology. In this way, while retaining the easily deployable daisy-chain IoT architecture, the number of data transmission hops between slave and master stations is significantly reduced, lowering message transmission latency in large-scale networks.

[0064] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0065] Figure 2 This is a schematic diagram of a network architecture provided in this application. Network architecture 200 may include a master station and multiple slave stations connected by a daisy-chain physical topology. Network architecture 200 includes master station 201, slave station 202, slave station 203, and slave station 204, and may also be referred to as a network.

[0066] For example, network architecture 200 could be a data transmission network for an industrial internet park. An industrial internet park is an industrial park that uses information and communication technologies to enable network communication between industrial infrastructure within the park, such as control equipment and business terminals.

[0067] Figure 2 This illustrates one connection method for the nodes in network architecture 200. Master station 201 is connected to slave station 202, slave station 202 is connected to slave station 203, and slave station 203 is connected to slave station 204. That is, master station 201, slave station 202, slave station 203, and slave station 204 are connected sequentially in a daisy chain topology.

[0068] The master station 201 can be implemented by a computer, a programmable logic controller (PLC), or a dedicated master station controller.

[0069] Master station 201 may also include a master station chip. The master station chip is an integrated circuit used to build master station functionality, providing the hardware and software support required for real-time communication and control. For example, the master station chip may be a central processing unit (CPU), microcontroller unit (MCU), etc., connected to the physical layer chip (PHY) via a Medium Independent Interface (MII). The MII interface is a standard Ethernet physical layer interface that isolates the Ethernet data link layer from the physical layer. The PHY connects to other devices, such as slave station 202, through this interface.

[0070] Slave station 202, slave station 203, and slave station 204 can be implemented by a computer, a programmable logic controller, or a dedicated slave station controller.

[0071] Taking slave station 202 as an example, slave station 202 can include a slave controller and a slave chip. The slave controller can be used to read and process data frames and transmit the data frames to the chip of the next transceiver port. Reading data frames mainly involves extracting the output command data sent to itself from the message and storing it in the internal storage area. This input data is then inserted from the internal storage area into the corresponding sub-message. Both data extraction and insertion are implemented by the data link layer hardware. The slave chip is an integrated circuit used to build slave functions, providing the hardware and software support required for real-time communication and control. For example, the slave chip is an MCU, used to read control data in the slave controller, implement device control functions (perform corresponding actions on input signals), and sample device feedback data (returning corresponding output results based on inputs), writing it to the slave controller for the master station to read.

[0072] In this embodiment, the slave controller and slave chip described above can be integrated into a single MCU.

[0073] Continuing with station 202 as an example, such as Figure 2 Slave station 202 may include MCU 2021 and signal switch 2022. MCU 2021 is connected to MCU signal switch 2022 through at least one interface. Signal switch 2022 includes multiple pairs of wires and switch array 2023. Switch array 2023 and multiple pairs of wires form a circuit that directly connects to any interface or bypasses any interface, so that slave station 202 is directly or indirectly connected to upstream or downstream slave stations or master stations (such as master station 201 or slave station 203).

[0074] It should be understood that Figure 2This is a simplified diagram for ease of understanding only. The network architecture 200 may also include other network devices and / or other terminal devices, and the connection relationships between nodes may also vary. Figure 2 This is not shown in the diagram. For example, network architecture 200 also includes one or more slave stations other than slave station 202, slave station 203, and slave station 204.

[0075] It should be noted that the solutions in the embodiments of this application can also be applied to other networks, such as other types of campus networks, data center networks, mobile bearer networks, etc., and the corresponding names can also be replaced by the names of the corresponding functions in other network architectures.

[0076] Please refer to Figure 3 , Figure 3 This application provides a schematic diagram of a slave station structure. Taking an interface including at least three PHYs and a signal switch 2022 including four pairs of wires as an example, the switch array 2023 is connected to the upstream master station or slave station (e.g., master station 201) through the upstream four wires of the four pairs of wires, and is connected to the downstream master station or slave station (e.g., slave station 203) through the downstream four wires of the four pairs of wires. The MCU 2021 is connected to the switch array 2023 through PHY1, PHY2, and PHY3 respectively.

[0077] As one possible implementation, a signal compensation module is also provided between the switch array 2023 and the upstream or downstream master or slave station lines.

[0078] As one possible implementation, the signal switch 2022 also includes a switch register 2024. The switch register 2024 is used to receive switch configuration information sent by the master station 201, so as to configure the switch array 2023 according to the switch configuration information, so that the master station and multiple slave stations form a tree topology.

[0079] As one possible implementation, the switch array 2023 includes at least one single-pole double-throw switch.

[0080] In this embodiment, the connection method of at least one single-pole double-throw switch in the switch array 2023 corresponds to the wiring rules. For the specific connection method of the switch array 2023, please refer to... Figure 7 The relevant content shown will not be repeated here.

[0081] Next, the network topology configuration method provided in the embodiments of this application will be described in detail with reference to the accompanying drawings. Here, we will refer to... Figure 2 Taking the network architecture 200 as an example, the specific steps of the network topology configuration method are explained.

[0082] Figure 4 This is a flowchart illustrating a network topology configuration method provided in this application. Please refer to it. Figure 4 The network topology configuration method may include the following steps 410-490.

[0083] Step 410: The main station 201 obtains the network topology information.

[0084] With master station 201, slave station 202, slave station 203 and slave station 204 connected in a daisy chain physical topology, master station 201 obtains the topology information of multiple slave stations.

[0085] As one possible implementation, master station 201, slave station 202, slave station 203 and slave station 204 form a logical aggregation chain through a pair of wires of signal switch 2022 and a pair of PHYs as inlet and outlet connections. Master station 201 obtains the topology information of multiple slave stations through the topology information message uploaded by slave station 202 in the aggregation chain.

[0086] Optionally, the topology information message can be an aggregate frame uploaded by slave station 202. The topology information message includes the topology information of network architecture 200, including the position and connection relationship of master station 201 and multiple slave stations in the daisy chain topology.

[0087] Step 420: The main station 201 determines the tree topology based on the topology information.

[0088] The master station 201 determines the tree topology based on the number of multiple slave stations and fractal rules in the topology information. In the tree topology, any slave station among the multiple slave stations is directly connected or bypassed to the upstream and downstream slave stations.

[0089] As one possible implementation, fractal rules are used to indicate the overall interconnection structure of the tree topology. The fractal rules can be flexibly adjusted based on the specific structure of the signal switch 2022. The fractal rules shown in this application embodiment are merely examples and do not limit the scope of the fractal rules.

[0090] For example, a binary tree fractal rule based on a signal switch 2022 including four pairs of lines and three PHYs is used. This fractal rule uses one PHY as an inlet to connect to the upstream slave station and uses two PHYs as outlets to realize binary tree branches. Each time the binary tree adds a hop, the existing topology is copied as two branches of the root node.

[0091] As one possible implementation, the master station 201 determines the initial tree topology based on the number of multiple slave stations and fractal rules in the topology information. Considering the number of line pairs contained in the signal switch 2022, the number of branches in the tree topology supported by the signal switch 2022 is limited. The master station 201 removes branches in the initial tree topology that exceed the number of line pairs of the signal switch 2022 to obtain the final tree topology.

[0092] For example, such as Figure 5 As shown, based on the binary tree fractal rules of the signal switches 2022 including four pairs of lines and three PHYs, nodes with a vertical length exceeding four pairs of lines need to be pruned. Here, a circle represents a node, i.e., a master or slave station, the line between every two circles represents the connection line between the master or slave station, and the dashed box represents the part that needs to be pruned.

[0093] Step 430: The master station 201 sends switch configuration information to multiple slave stations.

[0094] The master station 201 generates the switch configuration of the signal switches 2022 of multiple slave stations according to the tree topology, obtains the switch configuration information, and sends the switch configuration information to multiple slave stations.

[0095] As one possible implementation, the master station 201 calculates the switching configuration of the signal switches 2022 of each slave station based on the tree topology and the connection rules.

[0096] Optionally, the wiring rules are used to define the wiring method between multiple pairs of wires of the signal switch 2022 of each slave station and the PHY based on the overall wiring structure of the tree topology. The wiring rules can be flexibly adjusted based on the specific structure of the signal switch 2022. The wiring rules shown in the embodiments of this application are only an example and do not limit the wiring rules.

[0097] For example, the wiring rule is that the input line of the first pair of lines upstream of each slave station is always connected to the slave station's MCU input PHY1. Downstream, the MCU's output PHY2 and PHY3 are used first, connected to the output lines of the first and second pairs of lines in sequence, and so on. If the downstream PHY is not connected, it is connected to the bypass connection line upstream.

[0098] The following text combines Figure 7 The wiring rules for signal switch 2022 are explained in detail, and will not be repeated here.

[0099] As one possible implementation, the master station 201 sends switch configuration information to multiple slave stations in the form of aggregated frames.

[0100] Optionally, the switch configuration information may include multiple slave switch configuration information. The switch configuration information includes a switch configuration identifier and multiple slave identifiers, with a one-to-one correspondence between the slave identifiers and the slave switch configuration information. The switch configuration identifier is used to indicate the switch configuration information. The slave identifier is used to indicate the slave corresponding to any one of the multiple slave switch configuration information.

[0101] Step 440: The slave station 202 receives the switch configuration information sent by the master station 201.

[0102] Slave station 202 receives switch configuration information sent by master station 201 through a processor such as MCU 2021, extracts the slave identifier in the switch configuration information to indicate the slave switch configuration information of slave station 202 through MCU 2021, and sends the extracted slave switch configuration information to switch register 2024.

[0103] Step 450: Slave station 202 configures switch array 2024 according to switch configuration information.

[0104] Slave 202 configures switch array 2024 according to slave switch configuration information in switch register 2024.

[0105] Step 460: The slave station 203 receives the switch configuration information sent by the master station 201.

[0106] Step 470: Slave station 203 configures switch array 2024 according to switch configuration information.

[0107] Step 480: Slave station 204 receives switch configuration information sent by master station 201.

[0108] Step 490: Slave station 204 configures switch array 2024 according to switch configuration information.

[0109] As one possible implementation, the specific methods by which slave stations 203 and 204 receive switch configuration information and configure switch array 2024 are described in steps 440 and 450, and will not be repeated here. Each of the slave stations 202, 203, and 204 includes an independent signal switch 2022, and the switch array 2024 configured by each slave station is the switch array 2024 within its own signal switch 2022.

[0110] As one possible implementation, the switch configuration information received by slave station 203 and slave station 204 can be received from master station 201 or from upstream slave station, depending on whether the connection between slave station 203 and upstream master station 201 or upstream slave station is a bypass connection or a direct connection.

[0111] In this way, after slave stations 202, 203, and 204 configure their own switch arrays 2024 according to the switch configuration information, the master station 201, slave stations 202, 203, and 204 form a tree-like logical topology based on the daisy-chain physical topology. This significantly reduces the number of data transmission hops between slave stations and the master station while retaining the easy-to-deploy daisy-chain network architecture, thus reducing message transmission latency in large-scale networks.

[0112] The above text combined Figure 4 and Figure 5 The network topology configuration method provided in this application has been described. The following section will combine... Figure 6 and Figure 7 A detailed explanation of the wiring rules based on signal switch 2022 is provided.

[0113] Please refer to Figure 6 and Figure 7 , Figure 6 This application provides a schematic diagram of the connection rules for a tree topology. Figure 7 This is a schematic diagram of the wiring rules for a signal switch provided in this application.

[0114] like Figure 6 As shown, from station 1 to station 8 ( Figure 6 The connection relationships between the circles marked 1-8 are as follows: Station 1 is connected to Station 2, Station 2 is connected to Station 3, Station 3 is connected to Station 4, Station 4 is connected to Station 5, Station 5 is connected to Station 6, Station 3 is connected to Station 7, and Station 7 is connected to Station 8. Figure 6 Unmarked circles indicate parts that were removed during part-time work.

[0115] like Figure 7 As shown, the signal switch of any slave station from slave station 1 to slave station 8 includes four pairs of wires. Each slave station includes PHY1, PHY2, and PHY3. PHY1 is the input terminal of the MCU, and PHY2 and PHY3 are the output terminals of the MCU. PHY1 is located at... Figure 7 PHY2 is located on the left side of each slave station. Figure 7 PHY3 is located on the upper right side of each station. Figure 7 The lower right side of each slave station. Slave station 1's PHY2 is connected to slave station 2's PHY1 via the output line of the first pair of wires. Slave station 2's PHY2 is connected to slave station 3's PHY1 via the output line of the first pair of wires. Slave station 3's PHY2 is connected to slave station 4's PHY1 via the output line of the first pair of wires. Slave station 4's PHY2 is connected to slave station 5's PHY1 via the output line of the first pair of wires. Slave station 5's PHY2 is connected to slave station 6's PHY1 via the output line of the first pair of wires. Slave stations 1-8 form a bypass via the fourth pair of wires. This bypass bypasses the input terminals of the MCUs of slave stations 2-8 and any subsequent downstream slave station (…). Figure 7 (Not shown in the diagram) is connected. The PHY3 of slave station 2 is bypassed by the third pair of wires of slave stations 3-8, which bypasses the input terminals of the MCUs of slave stations 3-8 and connects to any subsequent downstream slave station (…). Figure 7 (Not shown in the diagram) is connected. PHY3 of slave station 3 is bypassed by the second pair of wires to the second pair of wires of slave stations 4-6, and this bypass connects to PHY1 of slave station 7, bypassing the input of the MCUs of slave stations 4-6. PHY2 of slave station 7 is connected to PHY1 of slave station 8 via the first pair of wires, and PHY3 of slave station 7 bypasses the input of the MCU of slave station 8 via the second pair of wires, connecting to any subsequent downstream slave station (…). Figure 7(Not shown in the diagram) Connections. Among them, the bypass connections in different slave stations are the same pair of lines. For example, the third pair of lines in slave station 2 is connected to the third pair of lines in slave stations 3, slave stations 4, etc., which will not be elaborated further here.

[0116] As can be seen, when the slave station includes three PHYs and four pairs of wires, the connection rules can be as follows:

[0117] For an upstream bypass path, if there are 0 downstream PHY outputs, the second pair of upstream wires is connected to the first pair of downstream wires. If there is 1 downstream PHY output, PHY2 is connected to the first pair of downstream wires, and the second pair of upstream wires is connected to the second pair of downstream wires. If there are 2 downstream PHY outputs, PHY2 is connected to the first pair of downstream wires, PHY3 is connected to the second pair of downstream wires, and the second pair of upstream wires is connected to the third pair of downstream wires.

[0118] For the two upstream bypasses, if there are 0 downstream PHY outputs, the second pair of upstream wires is connected to the first pair of downstream wires, and the third pair of upstream wires is connected to the second pair of downstream wires. If there is 1 downstream PHY output, PHY2 is connected to the first pair of downstream wires, the second pair of upstream wires is connected to the second pair of downstream wires, and the third pair of upstream wires is connected to the third pair of downstream wires. If there are 2 downstream PHY outputs, PHY2 is connected to the first pair of downstream wires, PHY3 is connected to the second pair of downstream wires, the second pair of upstream wires is connected to the third pair of downstream wires, and the third pair of upstream wires is connected to the fourth pair of downstream wires.

[0119] For the three upstream bypasses, if there are zero downstream PHY outputs, the second upstream pair of wires is connected to the first downstream pair of wires, the third upstream pair of wires is connected to the second downstream pair of wires, and the fourth upstream pair of wires is connected to the third downstream pair of wires. If there is one downstream PHY output, PHY2 is connected to the first downstream pair of wires, the second upstream pair of wires is connected to the second downstream pair of wires, the third upstream pair of wires is connected to the third downstream pair of wires, and the fourth upstream pair of wires is connected to the fourth downstream pair of wires.

[0120] Thus, different signal switches are available for different tree topology requirements. The signal switches can achieve bypass or direct connection between multiple slave stations through the configuration of the switch array, thereby forming a tree logical topology on the basis of the daisy chain physical topology. Moreover, the connection rules can be adjusted according to the specific structure of the signal switches, which has high flexibility.

[0121] The above text combined Figure 6 and Figure 7 The wiring rules are explained. These rules are determined based on how the switch array in the signal switch controls the connection relationship of multiple pairs of lines; that is, there is a correspondence between the wiring rules and the switch structure. The following section will combine... Figure 8 and Figure 9 The structure of the signal switch is described in detail.

[0122] Please refer to Figure 8 , Figure 8 This is a schematic diagram of the structure of an inter-board level signal switch provided in this application.

[0123] As one possible implementation, the number of interfaces connected to the switch array 2023 from at least one interface connected to the MCU2021 in the slave station is m, and the number of pairs of wires is n. The switch array includes m-1 columns and n rows of single-pole double-throw switches. The moving end of the single-pole double-throw switch located in the second row and second column is connected to any interface in at least one interface. The stationary end of the single-pole double-throw switch located in the m-1 column and n row is connected to the output line of the last pair of wires in the multiple pairs of wires. The moving end of the single-pole double-throw switch located in the first column is connected to the input line of any interface in at least one interface and any pair of wires in the multiple pairs of wires. The stationary end of the single-pole double-throw switch located in the m-1 column is connected to the output line of any pair of wires in the multiple pairs of wires. The moving end of the single-pole double-throw switch located in the i-th row and j-th column is connected to the stationary end of the single-pole double-throw switch located in the i-th row and j-1 column and the stationary end of the single-pole double-throw switch located in the i+1-th row and j-1 column, respectively. Where m and n are positive integers, i is a positive integer less than n, and j is a positive integer less than m-1.

[0124] For example, continuing with the example of multiple pairs of lines including four pairs of lines (first input line in1 and first output line out1, second input line in2 and second output line out2, third input line in3 and third output line out3, fourth input line in4 and fourth output line out4), and at least one interface including first interface PHY1, second interface PHY2, and third interface PHY3, refer to... Figure 8 An example of a switch array 2023 is provided. Figure 8 The solid black dot in the middle represents the moving end.

[0125] The switch array 2023 includes a first single-pole double-throw switch S1, a second single-pole double-throw switch S2, a third single-pole double-throw switch S3, a fourth single-pole double-throw switch S4, a fifth single-pole double-throw switch S5, and a sixth single-pole double-throw switch S6.

[0126] The first input line in1 is connected to the first interface PHY1, the first moving end of the first single-pole double-throw switch S1 is connected to the second interface PHY2, the second moving end of the first single-pole double-throw switch S1 is connected to the stationary end of the second single-pole double-throw switch S2, and different segments of the first single-pole double-throw switch S1 are connected to the first output line out1.

[0127] The first moving end of the second single-pole double-throw switch S2 is connected to the third interface PHY3, the second moving end of the second single-pole double-throw switch S2 is connected to the second input line in2, and the stationary end of the second single-pole double-throw switch S2 is also connected to the first moving end of the third single-pole double-throw switch S3.

[0128] The second moving end of the third single-pole double-throw switch S3 is connected to the stationary end of the fourth single-pole double-throw switch S4, and the stationary end of the third single-pole double-throw switch S3 is connected to the second output line out2.

[0129] The first moving end of the fourth single-pole double-throw switch S4 is connected to the second input line in2, the second moving end of the fourth single-pole double-throw switch S4 is connected to the third input line in3, and the stationary end of the fourth single-pole double-throw switch S4 is also connected to the first moving end of the fifth single-pole double-throw switch S5.

[0130] The second moving terminal of the fifth single-pole double-throw switch S5 is connected to the stationary terminal of the sixth single-pole double-throw switch S6, and the stationary terminal of the fifth single-pole double-throw switch S5 is connected to the third output line out3.

[0131] The first moving end of the sixth single-pole double-throw switch S6 is connected to the third input line in3, the second moving end of the sixth single-pole double-throw switch S6 is connected to the fourth input line in4, and the stationary end of the sixth single-pole double-throw switch S6 is connected to the fourth output line out4.

[0132] Optionally, a signal compensation circuit is further provided between the first output line out1, the second output line out2, the third output line out3, and the fourth output line out4 and the downstream slave station. For example, the signal compensation circuit includes two hybrid transformers (HYD) and a compensation circuit between the two hybrid transformers.

[0133] The connection positions of the moving ends of the first single-pole double-throw switch S1 to the sixth single-pole double-throw switch S6 are configured according to the switch configuration information, thereby enabling the topology of multiple slave stations to be changed, whether multiple pairs of wires in the slave station are connected to the MCU or bypassed.

[0134] In the embodiments provided in this application, the structure of the switch array 2023 described above is only an example. The structure of the switch array 2023 can be adjusted according to the specific structural requirements of the tree topology, and does not constitute a limitation on the structure of the switch array 2023. For example, the switch array of the signal switch is easy to expand. When adding a pair of lines, only one row of single-pole double-throw switches needs to be added accordingly; when adding a PHY, only one column of single-pole double-throw switches needs to be added accordingly.

[0135] Please refer to Figure 9 , Figure 9 This is a schematic diagram of a chip-level signal switch provided in this application.

[0136] As one possible implementation method, Figure 9 The chip-level signal switch shown is Figure 8 The only difference between the board-level signal switches shown is the interface connection method. The switch array 2023 of signal switch 2022 has no structural changes, and will not be described in detail here.

[0137] The slave MCU2021 connects to three PHYs via three MII interfaces. Each PHY includes a Physical Coding Sublayer (PCS) port and a Physical Medium Attachment (PMA) port. The PCS port connects to the MCU via the MII interface, and the PMA port connects to multiple pairs of wires on the signal switch 2022. For example, PHY1 ( Figure 9 (Not shown in the image) includes PCS1, PMA1, PHY2 ( Figure 9 (Not shown in the image) includes PCS2, PMA2, ​​PHY3 ( Figure 9 (Not shown in the image) Includes PCS3 and PMA3.

[0138] In particular, each pair of wires in the signal switch 2022 can be a single pair Ethernet (SPE).

[0139] Thus, the signal switch 2022 provided in this application can be applied at the board level or chip level, improving the diversity of application scenarios for the network topology configuration method based on the signal switch 2022.

[0140] To complement the network topology configuration method provided in the embodiments of this application, the embodiments of this application also provide a network topology configuration device 1000, which is used to execute the above-described network topology configuration method. For example... Figure 10 As shown, the network topology configuration device 1000 includes:

[0141] The transceiver module 1001 is used to obtain network topology information.

[0142] The processing module 1002 is used to determine the tree topology based on the topology information; any slave station among multiple slave stations in the tree topology is directly connected or bypassed to the upstream and downstream slave stations.

[0143] The transceiver module 1001 is also used to send switch configuration information to multiple slave stations; the switch configuration information is used to instruct multiple slave stations to configure the switch array according to the switch configuration information, so that the master station and multiple slave stations form a tree topology.

[0144] As one possible implementation, the transceiver module 1001 is specifically used to: acquire topology information messages sent by multiple slave stations; the topology information messages include network topology information, which includes the positions and connections of multiple master stations and slave stations in the daisy-chain topology.

[0145] As one possible implementation, the processing module 1002 is specifically used to: determine an initial tree topology based on the number of multiple slave stations and fractal rules in the topology information; the fractal rules are used to indicate the overall connection structure of the tree topology; and remove branches in the initial tree topology that exceed the number of pairs of lines of the signal switches to obtain the final tree topology.

[0146] In one possible implementation, each of the multiple slave stations includes a processor and a switch register. The transceiver module 1001 is specifically used to: send switch configuration information to the processors of the multiple slave stations; the processors are used to send switch configuration information to the switch registers, the switch configuration information instructing the multiple slave stations to configure the switch array according to the switch configuration information, so that the master station and the multiple slave stations form a tree topology.

[0147] As one possible implementation, the switch configuration information includes multiple slave switch configuration information. The slave switch configuration information includes a switch configuration identifier and multiple slave identifiers. The switch configuration identifier is used to indicate the switch configuration information, and the slave identifier is used to indicate the slave corresponding to any one of the multiple slave switch configuration information.

[0148] To complement the network topology configuration method provided in the embodiments of this application, the embodiments of this application also provide a network topology configuration device 1100, which is used to execute the above-described network topology configuration method. For example... Figure 11 As shown, the network topology configuration device 1100 includes:

[0149] The transceiver module 1101 is used to receive switch configuration information sent by the master station.

[0150] The processing module 1102 is used to configure the switch array according to the switch configuration information, so that the master station and multiple slave stations form a tree topology.

[0151] As one possible implementation, the transceiver module is also used to: send topology information messages to the master station; the topology information messages include network topology information, including the position and connection relationship of the master station and multiple slave stations in the daisy chain topology.

[0152] As one possible implementation, the slave station includes a processor and a switch register. The transceiver module 1101 is specifically used to: receive switch configuration information sent by the master station via the processor, and send switch configuration information to the switch register via the processor.

[0153] As one possible implementation, the switch configuration information includes multiple slave switch configurations. The switch configuration information includes a switch configuration identifier and multiple slave identifiers. The switch configuration identifier indicates the switch configuration information, and the slave identifier indicates the slave corresponding to any one of the multiple slave switch configurations. The processing module 1102 is specifically used to: configure the switch array according to the slave switch configuration information corresponding to its own slave identifier in the switch configuration information.

[0154] It should be understood that the above Figure 10 or Figure 11 The provided device, in implementing its functions, is only illustrated by the division of the above-described functional modules. In practical applications, the functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. Furthermore, the device and method embodiments provided in the above embodiments belong to the same concept, and their specific implementation processes are detailed in the method embodiments, and will not be repeated here.

[0155] Figure 12 This is a schematic diagram of the structure of an electronic device provided in this embodiment. Figure 12 As shown, the electronic device 1200 includes a processor 1210, a bus 1220, a memory 1230, a communication interface 1240, and a memory unit 1250 (also referred to as a main memory unit). The processor 1210, memory 1230, memory unit 1250, and communication interface 1240 are connected via the bus 1220.

[0156] It should be understood that in this embodiment, the processor 1210 may be a CPU, but it may also be other general-purpose processors, digital signal processors (DSPs), ASICs, FPGAs, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0157] The processor may also be a graphics processing unit (GPU), a neural network processing unit (NPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits used to control the execution of the program of the present application.

[0158] The communication interface 1240 is used to enable communication between the electronic device 1200 and external devices or components. In this embodiment, the electronic device 1200 is used to implement... Figure 2 When the system functions as a master station or slave station, the communication interface 1240 is used as a physical port for sending and receiving data.

[0159] Bus 1220 may include a pathway for transmitting information between the aforementioned components (such as processor 1210, memory unit 1250, and memory 1230). In addition to a data bus, bus 1220 may also include a power bus, a control bus, and a status signal bus, etc. However, for clarity, ... Figure 12 In this context, various buses are labeled as Bus 1220. Bus 1220 can be a Peripheral Component Interconnect Express (PCIe) bus, or an Extended Industry Standard Architecture (EISA) bus, a Unified Bus (Ubus or UB), a Compute Express Link (CXL) bus, a Cache Coherent Interconnect for Accelerators (CCIX) bus, etc. Bus 1220 can be categorized into address bus, data bus, and control bus.

[0160] As an example, electronic device 1200 may include multiple processors. A processor may be a multi-core (multi-CPU) processor. Here, a processor may refer to one or more devices, circuits, and / or computing units used to process data (e.g., computer program instructions).

[0161] It is worth noting that, Figure 12 Taking the electronic device 1200 as an example, which includes a processor 1210 and a memory 1230, the processor 1210 and the memory 1230 are used to indicate a type of device or equipment. In specific embodiments, the number of each type of device or equipment can be determined according to business needs.

[0162] Memory unit 1250 can correspond to the storage medium used to store switch configuration information in the above method embodiments. Memory unit 1250 can be volatile memory or non-volatile memory, or it can include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0163] The memory 1230 can correspond to the storage medium used to store computer instructions and other information in the above method embodiments, such as a disk, like a mechanical hard disk or a solid-state hard disk.

[0164] The aforementioned electronic device 1200 can be a general-purpose device or a special-purpose device. For example, electronic device 1200 can be an edge device (e.g., a box carrying a chip with processing capabilities). Alternatively, electronic device 1200 can also be a network device, a server, or other device with computing capabilities.

[0165] It should be understood that the electronic device 1200 according to this embodiment may correspond to the network topology configuration device 1000 or the network topology configuration device 1100 in this embodiment, and may correspond to the execution of the network topology configuration device 1200 according to this embodiment. Figure 4 The corresponding entities in the method, and the above and other operations and / or functions of each module in the network topology configuration device 1000 or network topology configuration device 1100, are respectively for the purpose of implementing Figure 4 For the sake of brevity, the corresponding process of the Chinese method will not be elaborated here.

[0166] The method steps in this embodiment can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory, flash memory, read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside in an ASIC. Alternatively, the ASIC can reside in an electronic device. Of course, the processor and storage medium can also exist as discrete components in an electronic device.

[0167] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of this application are performed entirely or partially. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user equipment, or other programmable device. The computer program or instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a digital video disc (DVD); or it can be a semiconductor medium, such as a solid-state drive (SSD). The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A network topology configuration method, characterized in that, A master station is applied in a network, which also includes multiple slave stations. The master station and the multiple slave stations are connected sequentially in a daisy-chain topology. Each slave station includes a signal switch, which comprises multiple pairs of wires and a switch array. The switch array is used to determine the connection method of the multiple pairs of wires. The method includes: Obtain the topology information of the network; A tree topology is determined based on the topology information; in the tree topology, any slave station among the plurality of slave stations is directly connected or bypassed to the upstream and downstream slave stations; Send switch configuration information to the plurality of slave stations; the switch configuration information is used to instruct the plurality of slave stations to configure the switch array according to the switch configuration information, so that the master station and the plurality of slave stations form the tree topology.

2. The method according to claim 1, characterized in that, The process of obtaining the network topology information includes: Obtain the topology information messages sent by the plurality of slave stations; the topology information messages include the topology information of the network, and the topology information includes the position and connection relationship of the master station and the plurality of slave stations in the daisy chain topology.

3. The method according to claim 1 or 2, characterized in that, Determining the tree topology based on the topology information includes: The initial tree topology is determined based on the number of slave stations and fractal rules in the topology information; the fractal rules are used to indicate the overall connection structure of the tree topology. Remove the number of branches in the initial tree topology that exceed the number of pairs of lines of the signal switches to obtain the final tree topology.

4. The method according to any one of claims 1-3, characterized in that, Each of the plurality of slave stations includes a processor and a switch register. Sending the switch configuration information to the plurality of slave stations includes: The processor sends the switch configuration information to the processor of the plurality of slave stations; the processor is used to send the switch configuration information to the switch register, the switch configuration information is used to instruct the plurality of slave stations to configure the switch array according to the switch configuration information, so that the master station and the plurality of slave stations form the tree topology.

5. The method according to claim 4, characterized in that, The switch configuration information includes multiple slave switch configuration information. The slave switch configuration information includes a switch configuration identifier and multiple slave identifiers. The switch configuration identifier is used to indicate the switch configuration information, and the slave identifier is used to indicate the slave corresponding to any slave switch configuration information among the multiple slave switch configuration information.

6. A network topology configuration method, characterized in that, A method for using slave stations in a network, the network including a master station and multiple slave stations connected sequentially in a daisy-chain topology, each of the multiple slave stations including a signal switch, the signal switch including multiple pairs of wires and a switch array, the switch array being used to determine the connection method of the multiple pairs of wires, the method including: Receive the switch configuration information sent by the master station; Configure the switch array according to the switch configuration information, so that the master station and the multiple slave stations form a tree topology.

7. The method according to claim 6, characterized in that, The method further includes: Send a topology information message to the master station; the topology information message includes the topology information of the network, including the position and connection relationship of the master station and the plurality of slave stations in the daisy-chain topology.

8. The method according to claim 6 or 7, characterized in that, The slave station includes a processor and a switch register. Receiving the switch configuration information sent by the master station includes: The processor receives the switch configuration information sent by the master station; The processor sends the switch configuration information to the switch register.

9. The method according to any one of claims 6-8, characterized in that, The switch configuration information includes multiple slave switch configurations. The switch configuration information includes a switch configuration identifier and multiple slave identifiers. The switch configuration identifier indicates the switch configuration information, and the slave identifier indicates the slave corresponding to any one of the multiple slave switch configurations. Configuring the switch array according to the switch configuration information includes: Configure the switch array according to the slave switch configuration information corresponding to the slave identifier that indicates itself in the switch configuration information.

10. A signal switch, characterized in that, The network is used to provide multiple slave stations in a network, which also includes a master station. The master station and the multiple slave stations are connected sequentially in a daisy-chain topology. Each of the multiple slave stations includes the signal switch, which includes multiple pairs of wires and a switch array. At least one of the multiple pairs of lines and the switch array are used to be connected to the processor via at least one interface; The switch array and the multiple pairs of lines form a circuit that is directly connected to any one of the at least one interfaces, or bypasses any one of the at least one interfaces through a bypass connection, so that any slave station among the multiple slave stations in the network is directly connected or bypassed to the upstream and downstream slave stations, forming a tree topology.

11. The signal switch according to claim 10, characterized in that, The switch array includes at least one single-pole double-throw switch.

12. The signal switch according to claim 11, characterized in that, The number of interfaces connected to the switch array in the at least one interface is m, the number of pairs of wires is n, the switch array includes m-1 columns and n rows of single-pole double-throw switches, the moving end of the single-pole double-throw switch located in the second row and second column is connected to any interface in the at least one interface, the stationary end of the single-pole double-throw switch located in the m-1 column and n row is connected to the output line of the last pair of wires in the multiple pairs of wires, and the moving end of the single-pole double-throw switch located in the first column is connected to any interface in the at least one interface. An interface is connected to the input line of any pair of lines in the multiple pairs of lines. The stationary terminal of the single-pole double-throw switch located in the (m-1)th column is connected to the output line of any pair of lines in the multiple pairs of lines. The moving terminal of the single-pole double-throw switch located in the i-th row and j-th column is connected to the stationary terminal of the single-pole double-throw switch located in the i-th row and j-1th column and the stationary terminal of the single-pole double-throw switch located in the (i+1)th row and j-1th column, respectively. Wherein, m and n are positive integers, i is a positive integer less than n, and j is a positive integer less than m-1.

13. The signal switch according to claim 12, characterized in that, The at least one interface includes a first interface, a second interface, and a third interface; the multiple pairs of lines include a first input line, a first output line, a second input line, a second output line, a third input line, a third output line, a fourth input line, and a fourth output line; the switch array includes a first single-pole double-throw switch, a second single-pole double-throw switch, a third single-pole double-throw switch, a fourth single-pole double-throw switch, a fifth single-pole double-throw switch, and a sixth single-pole double-throw switch. The first input line is connected to the processor through the first interface; The first moving terminal of the first single-pole double-throw switch is connected to the processor through the second interface; the second moving terminal of the first single-pole double-throw switch is connected to the stationary terminal of the second single-pole double-throw switch; the stationary terminal of the first single-pole double-throw switch is connected to the first output line. The first moving terminal of the second single-pole double-throw switch is connected to the processor through the third interface; the second moving terminal of the second single-pole double-throw switch is connected to the second input line; the stationary terminal of the second single-pole double-throw switch is also connected to the first moving terminal of the third single-pole double-throw switch. The second moving terminal of the third single-pole double-throw switch is connected to the stationary terminal of the fourth single-pole double-throw switch. The second output line is connected; the first moving terminal of the fourth single-pole double-throw switch is connected to the second input line, the second moving terminal of the fourth single-pole double-throw switch is connected to the third input line, and the stationary terminal of the fourth single-pole double-throw switch is also connected to the first moving terminal of the fifth single-pole double-throw switch; the second moving terminal of the fifth single-pole double-throw switch is connected to the stationary terminal of the sixth single-pole double-throw switch, and the stationary terminal of the fifth single-pole double-throw switch is connected to the third output line; the first moving terminal of the sixth single-pole double-throw switch is connected to the third input line, the second moving terminal of the sixth single-pole double-throw switch is connected to the fourth input line, and the stationary terminal of the sixth single-pole double-throw switch is connected to the fourth output line.

14. The signal switch according to any one of claims 10-13, characterized in that, The output lines of the multiple pairs of lines include signal compensation circuitry.

15. A circuit board, characterized in that, The system includes a processor and a signal switch as described in any one of claims 10-14, wherein the processor is connected to at least one of the multiple pairs of lines and the switch array via at least one interface.

16. A chip, characterized in that, Includes a signal switch as described in any one of claims 10-14, wherein the signal switch is connected to the media access control layer via at least one interface.

17. A network topology configuration system, characterized in that, It includes a master station and multiple slave stations, which are connected sequentially in a daisy-chain topology, and each of the multiple slave stations includes a signal switch as described in any one of claims 10-14.

18. A computer-readable storage medium, characterized in that, The storage medium stores at least one instruction, which is loaded and executed by a processor to implement the network topology configuration method as described in any one of claims 1-9.

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