Technological method applied to manufacturing of flash memory device
By forming a protective oxide layer on the front nitride layer during flash memory device fabrication and removing the back nitride layer first, the problem of morphological defects in the floating gate polysilicon layer is avoided, thus improving product reliability and yield.
Patent Information
- Application Number
- CN202511205629.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-26
- Publication Date
- 2025-12-12
AI Technical Summary
In the manufacturing process of flash memory devices, the wet etching process in the existing technology causes over-etching of the floating gate polysilicon layer, resulting in morphological defects, which affects the storage capacity and data retention of the storage electronics, and reduces product reliability and yield.
A protective oxide layer is formed on the front nitride layer. The back nitride layer is removed first. Then, a groove is formed by photolithography and etching. The front nitride layer is used as a hard mask for planarization to avoid over-etching of the floating gate polysilicon layer.
It improves the reliability and yield of flash memory devices, reduces morphological defects in the floating gate polysilicon layer, and enhances the storage and data retention capabilities of memory electronics.
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Figure CN121126783A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor devices and integrated circuits, and in particular to a process method applied in the manufacture of a flash memory device. BACKGROUND
[0002] The memory using non-volatile memory (NVM) technology is currently widely used in smart phones, tablet computers, digital cameras, universal serial bus flash disks (USB flash disks, referred to as "U disks") and other electronic products with storage functions. In the NVM memory, the flash memory has the characteristics of high transmission efficiency and low cost. Generally, a wafer for integrating flash memory has a storage array formed of flash memory cell devices and a peripheral circuit formed of logic devices.
[0003] In the related art, in the manufacture of a flash memory device, a front nitride layer is formed on a float gate (FG) polysilicon layer, a back nitride layer is formed on the back surface of a substrate, and after forming a recess for manufacturing a shallow trench isolation (STI) structure on the front surface of the substrate, an oxide layer is deposited on the front nitride layer to fill the recess, and a planarization process is performed using the front nitride layer as a hard mask. The front nitride layer is removed by a dry etching process and a wet etching process in sequence to form the STI structure.
[0004] However, in the above manufacturing process, in order to completely remove the front nitride layer and the back nitride layer, the amount of acid in the wet etching process is determined based on the thickness of the back nitride layer. For the front nitride layer, this etching method will cause a large amount of over etching (OE). Excessive acid will erode the float gate polysilicon layer, affecting the flatness of the polysilicon layer, and even forming FG pits defects, affecting the storage electron storage capacity of the float gate, and even the data retention capability, reducing the reliability and yield of the product. SUMMARY
[0005] The present application provides a process method applied in the manufacture of a flash memory device, which can solve the problem that the surface of the float gate polysilicon layer is prone to have topography defects in the manufacturing process of the flash memory device provided in the related art. The method comprises:
[0006] forming a protective oxide layer on a front nitride layer, the front nitride layer being formed on a floating gate polysilicon layer, the floating gate polysilicon layer being formed on a coupling oxide layer, the coupling oxide layer being formed on a front surface of a substrate, a back surface of the substrate having a back oxide layer formed thereon, the back oxide layer having a back nitride layer formed thereon;
[0007] etching to remove the back nitride layer;
[0008] forming a first recess and a second recess in the front nitride layer, the floating gate polysilicon layer, the coupling oxide layer and the substrate by a photolithography process, the protective oxide layer being removed in the process of forming the first recess and the second recess;
[0009] forming an insulating layer on the front nitride layer, the insulating layer filling the first recess and the second recess;
[0010] performing a planarization process with the front nitride layer as a hard mask to remove the insulating layer outside the first recess and the second recess;
[0011] performing etching to make a top of the insulating layer in the first recess lower than a top of the floating gate polysilicon layer, and to make a top of the insulating layer in the second recess lower than a top of the front nitride layer and higher than the top of the floating gate polysilicon layer;
[0012] etching to remove the front nitride layer.
[0013] In some embodiments, the etching to remove the back nitride layer comprises:
[0014] performing a first wet etching process to remove the back nitride layer.
[0015] In some embodiments, the performing etching to make a top of the insulating layer in the first recess lower than a top of the floating gate polysilicon layer, and to make a top of the insulating layer in the second recess lower than a top of the front nitride layer and higher than the top of the floating gate polysilicon layer comprises:
[0016] performing a second wet etching process to make a top of the insulating layer in the first recess and the second recess lower than a top of the front nitride layer;
[0017] performing a dry etching process to make a top of the insulating layer in the first recess lower than a top of the floating gate polysilicon layer, and to make a top of the insulating layer in the second recess lower than a top of the front nitride layer and higher than the top of the floating gate polysilicon layer.
[0018] In some embodiments, the etching to remove the front nitride layer comprises:
[0019] A third wet etching process is performed to remove the front nitride layer.
[0020] In some embodiments, the acid used in the first wet etching process and the third wet etching process comprises phosphoric acid.
[0021] In some embodiments, the protective oxide layer has a thickness of 30 angstroms to 150 angstroms.
[0022] In some embodiments, forming an insulating layer on the front nitride layer comprises:
[0023] Depositing a silicon dioxide layer on the protective oxide layer by an ALD process and a HARP CVD process in sequence forms the insulating layer.
[0024] The technical solution of the present application has at least the following advantages:
[0025] By forming a protective oxide layer on the front nitride layer after forming the front nitride layer above the floating gate oxide layer in the flash memory device manufacturing, the back nitride layer can be removed before the front nitride layer is removed, avoiding the problem that the amount of over-etching is large when the front nitride layer and the back nitride layer are removed at the same time, which causes the floating gate polysilicon layer to be eroded by too much acid and generate topography defects, thereby affecting the storage electron storage capacity of the floating gate and even the data retention capacity. In a certain extent, the reliability and yield of the product are improved. BRIEF DESCRIPTION OF DRAWINGS
[0026] In order to more clearly illustrate the technical solutions in the specific embodiments or prior art of the present application, the following will briefly introduce the drawings needed to be used in the specific embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.
[0027] Figure 1 is a flow chart of the process method applied in the flash memory device manufacturing provided by an exemplary embodiment of the present application;
[0028] Figures 2 to 7 is a manufacturing schematic diagram of the process method provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION
[0029] The technical solutions in the present application will be described in detail below with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.
[0030] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", "third" are only for descriptive purposes and cannot be understood as indicating or implying relative importance.
[0031] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication between two elements, it can be wireless connection, or it can be wired connection. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0032] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as there is no conflict.
[0033] Reference Figure 1 It shows the flow chart of the process method applied in the manufacture of flash memory device provided by an exemplary embodiment of the present application, as shown in Figure 1 The method comprises:
[0034] Step S1, forming a protective oxide layer on the front nitride layer, the front nitride layer is formed on the floating gate polysilicon layer, the floating gate polysilicon is formed on the coupling oxide layer, the coupling oxide layer is formed on the front surface of the substrate, the back surface of the substrate is formed with a back oxide layer, and the back surface of the substrate is formed with a back nitride layer.
[0035] Reference Figure 2 It shows the cross-sectional schematic diagram after forming the protective oxide layer on the front nitride layer. Exemplarily, as shown in Figure 2 The coupling oxide layer 221 is formed on the front surface of the substrate 210, the floating gate polysilicon layer 231 (which is used to manufacture the floating gate of the flash memory device) is formed on the coupling oxide layer 221, the front nitride layer 241 is formed on the floating gate polysilicon layer 231, the protective oxide layer 223 is formed on the front nitride layer 241, the back oxide layer 222 is formed on the back surface of the substrate 210, and the back nitride layer 242 is formed on the back oxide layer 222.
[0036] The coupling oxide layer 221 has a thickness of 50 angstroms. The thickness of the floating gate polysilicon layer 231 is 150 to 350 angstroms, the thickness of the front nitride layer 241 is 350 to 800 angstroms, and the thickness of the protective oxide layer 223 is 30 to 150 angstroms. The front nitride layer 241 and the back nitride layer 242 have the same thickness. The protective oxide layer 223 can be formed by depositing a silicon dioxide (SiO2) layer on the front nitride layer using a chemical vapor deposition (CVD) process.
[0037] Step S2: Etch to remove the nitride layer on the back side.
[0038] refer to Figure 3 This shows a schematic cross-sectional view after the back nitride layer has been removed. For example, as shown... Figure 3 As shown, a first wet etching process can be performed to remove the back nitride layer 242. The acid used in the first wet etching process includes phosphoric acid (P3O4), which protects the oxide layer 223 from being eroded by the phosphoric acid.
[0039] In step S3, a first groove and a second groove are formed in the front nitride layer, the floating gate polysilicon layer, the coupling oxide layer and the substrate by photolithography. During the formation of the first groove and the second groove, the protective oxide layer is removed.
[0040] refer to Figure 4 It shows a cross-sectional schematic diagram after the formation of the first and second grooves. For example, as shown... Figure 4 As shown, photoresist can be coated on the protective oxide layer 223. Figure 4 (Not shown in the image) The photoresist in the target area (the area corresponding to the first trench 301 and the second trench 302) is removed by exposure and development in sequence, followed by etching to a predetermined depth in the substrate 210. The first trench 301 and the second trench 302 are formed in the front nitride layer 241, the floating gate polysilicon layer 231, the coupling oxide layer 221, and the substrate 210. During the formation of the first trench 301 and the second trench 302, the protective oxide layer 223 is removed by the cleaning process after etching. The first trench 301 is used to form the STI structure of the flash memory cell, and the second trench 302 is used to form the STI structure of the logic device. Typically, the width of the STI structure of the logic device is larger than the width of the STI structure of the flash memory cell. Therefore, the width of the second trench 302 is larger than the width of the first trench 301.
[0041] Step S4: An insulating layer is formed on the front nitride layer, and the insulating layer fills the first groove and the second groove.
[0042] refer toFigure 5 which shows a cross-sectional schematic view after forming the insulating layer. As shown in Figure 5 the insulating layer 224 can be formed by sequentially depositing a silicon dioxide layer on the front nitride layer 241 through an atomic layer deposition (ALD) process and a high aspect ratio process chemical vapor deposition (HARP CVD) process.
[0043] Step S5, performing a planarization process with the front nitride layer as a hard mask to remove the insulating layer outside the first groove and the second groove.
[0044] Step S6, performing etching to make the top of the insulating layer in the first groove lower than the top of the floating gate polysilicon layer, and make the top of the insulating layer in the second groove lower than the top of the front nitride layer and higher than the top of the floating gate polysilicon layer.
[0045] Referring to Figure 6 which shows a cross-sectional schematic view after sequentially performing the planarization process and the etching. As shown in Figure 6 the planarization process can be performed through a chemical mechanical polishing (CMP) process until the front nitride layer 241 is exposed; a second wet etching process is performed to make the top of the insulating layer 224 in the first groove 301 and the second groove 302 lower than the top of the front nitride layer 241; a dry etching process is performed to make the top of the insulating layer 224 in the first groove 301 lower than the top of the floating gate polysilicon layer 231, and make the top of the insulating layer 224 in the second groove 302 lower than the top of the front nitride layer 241 and higher than the top of the floating gate polysilicon layer 231. After the CMP process and the dry etching process, the thickness of the front nitride layer 241 is 50% to 70% of the original thickness.
[0046] Step S7, etching to remove the front nitride layer.
[0047] Referring to Figure 7 which shows a cross-sectional schematic view after etching to remove the front nitride layer. As shown in Figure 7 a third wet etching process can be performed to remove the front nitride layer 241. The acid used in the third wet etching process includes phosphoric acid, and the amount of the phosphoric acid can be determined according to the thickness of the remaining front nitride layer 241.
[0048] In summary, in the embodiments of the present application, by forming a protective oxide layer on the front nitride layer after forming the front nitride layer above the floating gate oxide layer in the manufacturing of the flash memory device, the back nitride layer can be removed before the front nitride layer is removed, thereby avoiding the problem that the simultaneous removal of the front nitride layer and the back nitride layer is easy to cause a large over-etching amount (the thickness of the front nitride layer is reduced due to the erosion of the previous process when the front nitride layer and the back nitride layer are simultaneously removed), and the excessive acid erosion of the floating gate polysilicon layer causes the appearance defects of the floating gate polysilicon layer, and further affects the storage electron storage capacity of the floating gate, and even the data retention capacity, thereby improving the reliability and yield of the product to a certain extent.
[0049] Obviously, the above embodiments are only examples for clearly illustrating but not limiting the embodiments. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, all the embodiments are not required to be exhausted, and the obvious changes or variations derived therefrom are still within the protection scope of the present application.
Claims
1. A process method applied in the fabrication of flash memory devices, characterized in that, include: A protective oxide layer is formed on a front nitride layer, the front nitride layer is formed on a floating gate polysilicon layer, the floating gate polysilicon layer is formed on a coupling oxide layer, the coupling oxide layer is formed on the front surface of the substrate, a back oxide layer is formed on the back surface of the substrate, and a back nitride layer is formed on the back oxide layer. Etching removes the back nitride layer; A first groove and a second groove are formed in the front nitride layer, the floating gate polysilicon layer, the coupling oxide layer and the substrate by photolithography. During the formation of the first groove and the second groove, the protective oxide layer is removed. An insulating layer is formed on the front nitride layer, and the insulating layer fills the first groove and the second groove. The planarization process is performed using the front nitride layer as a hard mask to remove the insulating layer outside the first and second grooves; Etching is performed so that the top of the insulating layer in the first groove is lower than the top of the floating gate polysilicon layer, and the top of the insulating layer in the second groove is lower than the top of the front nitride layer and higher than the top of the floating gate polysilicon layer. The front nitride layer is removed by etching.
2. The method according to claim 1, characterized in that, The etching process removes the back nitride layer, including: A first wet etching process is performed to remove the back nitride layer.
3. The method according to claim 2, characterized in that, The etching process, which involves etching such that the top of the insulating layer in the first groove is lower than the top of the floating gate polysilicon layer, and the top of the insulating layer in the second groove is lower than the top of the front-side nitride layer but higher than the top of the floating gate polysilicon layer, includes: A second wet etching process is performed so that the top of the insulating layer in the first and second grooves is lower than the top of the front nitride layer. A dry etching process is performed so that the top of the insulating layer in the first groove is lower than the top of the floating gate polysilicon layer, and the top of the insulating layer in the second groove is lower than the top of the front nitride layer and higher than the top of the floating gate polysilicon layer.
4. The method according to claim 3, characterized in that, The etching process removes the front nitride layer, including: A third wet etching process is performed to remove the front nitride layer.
5. The method according to claim 4, characterized in that, The acid used in the first wet etching process and the third wet etching process includes phosphoric acid.
6. The method according to any one of claims 1 to 5, characterized in that, The thickness of the protective oxide layer is 30 to 150 angstroms.
7. The method according to claim 6, characterized in that, The formation of an insulating layer on the front nitride layer includes: The insulating layer is formed by depositing a silicon dioxide layer on the protective oxide layer sequentially using ALD and HARP CVD processes.