Memory device including conductive contacts and support structure

Abstract

The invention relates to a memory device including conductive contacts and a support structure. Some embodiments include devices and methods of forming the devices. One of the apparatuses includes a memory device including a first region including a first level of conductive material interleaved with a first level of dielectric material, and a first memory cell including pillars extending through the first level of conductive material and at least a portion of the first level of dielectric material; a first region comprising a conductive material of a first level, a second region comprising a conductive material of a second level interleaved with a dielectric material of the second level, and a second memory cell comprising pillars extending through the conductive material of the first level and at least a portion of the dielectric material of the first level; a third region comprising a dielectric structure separating the conductive material of the first level from the conductive material of the second level; and a conductive contact extending through at least a portion of the third region and contacting a conductive material of the conductive material of the first level.

Description

Technical Field

[0001] This application relates to a memory device, and more specifically, to a memory device comprising conductive contacts and a support structure. Background Technology

[0002] Some components in memory devices (such as flash memory devices) have relatively small structural dimensions (e.g., nanometer scale). At specific small dimensions of the memory device, parts of the memory device can suffer structural damage (e.g., collapse) during manufacturing. This collapse can negatively impact the yield, cost, performance, and reliability of the memory device. Summary of the Invention

[0003] In this example, a device is described. The device includes a first region, a second region, a third region, and conductive contacts. The first region includes a first-level conductive material interleaved with a first-level dielectric material and a first memory cell, the first memory cell including a pillar extending through at least a portion of the first-level conductive material and the first-level dielectric material. The second region includes a second-level conductive material interleaved with a second-level dielectric material and a second memory cell, the second memory cell including a pillar extending through at least a portion of the first-level conductive material and the first-level dielectric material. The third region includes a dielectric structure separating the first-level conductive material from the second-level conductive material. The conductive contacts extend through at least a portion of the third region and contact the conductive material in the first-level conductive material.

[0004] In this example, a device is described. The device includes a first-level conductive material, a second-level conductive material, a memory cell, and conductive contacts. The first-level conductive material is interleaved with a first-level dielectric material. The second-level conductive material is interleaved with a second-level dielectric material, and the second-level conductive material and the second-level dielectric material are positioned above the first-level conductive material and the first-level dielectric material. The memory cell includes a pillar associated with the memory cell, and the pillar extends through the first-level conductive material, the first-level dielectric material, the second-level conductive material, and the second-level dielectric material. The conductive contacts extend in a direction from the second-level conductive material to the first-level conductive material. The conductive contacts include a first conductive portion, a third conductive portion, and a second conductive portion between the first portion and the third portion, wherein the second conductive portion contacts one of the second-level conductive materials.

[0005] In one example, a method is described. The method includes: forming a first memory cell and a first control gate associated with the first memory cell; forming a second memory cell and a second control gate associated with the second memory cell; forming a dielectric structure between the first memory cell and the second memory cell; forming a first conductive contact passing through a first portion of the dielectric structure and contacting the first control gate in the first control gate; and forming a second conductive contact passing through a second portion of the dielectric structure and contacting the second control gate in the second control gate. Attached Figure Description

[0006] Figure 1 A block diagram illustrating a device in the form of a memory device according to some embodiments described herein.

[0007] Figure 2 This illustration shows a general schematic diagram of a portion of a memory device comprising a memory array having blocks (memory cell blocks) and sub-blocks in each block, according to some embodiments described herein.

[0008] Figure 3 Demonstrating some embodiments according to the description herein Figure 2 A detailed schematic diagram of the two blocks of the memory device.

[0009] Figure 4 Demonstrating some embodiments according to the description herein Figure 3 A top view of a portion of the structure of a memory device, including the areas of the memory array, conductive contact areas, and the structure between blocks of the memory device.

[0010] Figure 5 Demonstrating some embodiments according to the description herein Figure 4 A side view (e.g., cross-section) of a portion of a memory device, which includes material layers comprising the respective memory cells and control gates associated with the memory cells.

[0011] Figure 6 Demonstrating some embodiments according to the description herein Figure 4 A top view of the structure of a memory device, which includes the areas between blocks of the memory device and the conductive contacts within those areas.

[0012] Figure 7 The illustrations represent some embodiments described herein. Figure 6 A diagram showing the structure of a memory device, illustrating the relative positions of the memory device blocks and conductive contacts.

[0013] Figure 8 Demonstrating some embodiments according to the description herein Figure 7The change in the connection between the conductive contacts and the control gate of the memory device.

[0014] Figure 9A and Figure 9B Demonstrating some embodiments according to the description herein Figure 7 More details on the structure of the conductive contacts of the memory device.

[0015] Figures 10A to 27C Different views of elements during the process of forming a memory device are shown according to some embodiments described herein.

[0016] Figures 28 to 35 Different views of elements are shown during the replacement process of forming a memory device according to some embodiments described herein.

[0017] Figure 36A and Figure 36B This document illustrates a memory device comprising conductive contacts and a control gate located in a region outside a memory cell array region, according to some embodiments described herein.

[0018] Figures 37 to 47 Different views of elements are shown during the process of forming an alternative memory device according to some embodiments described herein. Detailed Implementation

[0019] The techniques described herein relate to memory devices comprising memory cells formed in layers (different physical layers) of a memory device. A layer comprises a conductive material of the corresponding layer. The conductive material forms portions of control gates (e.g., word lines) associated with the memory cells. The memory device also includes conductive contacts coupled to the respective control gates. The conductive contacts and control gates are portions of access lines (e.g., word lines) of the memory device. The memory device also includes support pillars (e.g., dielectric pillars) adjacent to the conductive contacts. In one example, the conductive contacts are positioned between blocks of the memory device. In another example, the support pillars are positioned adjacent to the conductive contacts. As described in more detail below, the structure and location of the conductive contacts allow for improvements in at least one of yield, cost, performance, and reliability associated with the memory device. Other improvements and benefits of the techniques described herein are referenced below. Figures 1 to 47 Further discussion.

[0020] Figure 1A block diagram illustrating a device in the form of a memory device 100 according to some embodiments described herein. The memory device 100 may include a memory array (or multiple memory arrays) 101 containing memory cells 102 arranged, for example, in blocks (memory cell blocks) BLK0 to BLKi. Each of the blocks BLK0 to BLKi may itself contain sub-blocks, such as sub-blocks SB0 to SBj. Sub-blocks are part of a block. In the physical structure of the memory device 100, the memory cells 102 may be arranged vertically (e.g., stacked one on top of the other) on a substrate (e.g., a semiconductor substrate) of the memory device 100.

[0021] like Figure 1 As shown, memory device 100 may include access lines (which may include word lines) 150 and data lines (which may include bit lines) 170. Access lines 150 may carry signals (e.g., word line signals) WL0 to WLm. Data lines 170 may carry signals (e.g., bit line signals) BL0 to BLn. Memory device 100 may use access lines 150 to selectively access memory cells 102 of blocks BLK0 to BLKi and use data lines 170 to selectively exchange information (e.g., data) with memory cells 102 of blocks BLK0 to BLKi. Data lines 170 may be shared between blocks BLK0 to BLKi.

[0022] Memory device 100 may include an address register 107 for receiving address information (e.g., address signals) ADDR on a line (e.g., address line) 103. Memory device 100 may include row access circuitry 108 and column access circuitry 109 capable of decoding the address information from address register 107. Based on the decoded address information, memory device 100 may determine which memory cells 102 of which sub-blocks of blocks BLK0 to BLKi will be accessed during memory operations. Memory device 100 may perform read operations to read (e.g., sense) information (e.g., previously stored information) from memory cells 102 of blocks BLK0 to BLKi or perform write operations to store (e.g., program) information in memory cells 102 of blocks BLK0 to BLKi. Memory device 100 may use data lines 170 associated with signals BL0 to BLn to provide information stored in memory cells 102 or to obtain information read (e.g., sensed) from memory cells 102. The memory device 100 can also perform an erase operation to erase information from some or all of the memory cells 102 from block BLK0 to BLKi.

[0023] Memory device 100 may include control unit 118, which may be configured to control memory operations of memory device 100 based on control signals on line 104. Examples of control signals on line 104 include one or more clock signals and other signals (e.g., chip enable signal CE#, write enable signal WE#) to indicate which operation (e.g., read, write, or erase operation) memory device 100 may perform. Other devices external to memory device 100 (e.g., memory controller or processor) may control the values ​​of the control signals on line 104. Specific values ​​of combinations of signals on line 104 may generate commands (e.g., read, write, or erase commands) that cause memory device 100 to perform corresponding memory operations (e.g., read, write, or erase operations).

[0024] Memory device 100 may include a sensing and buffering circuitry system 120, which may include components such as a sense amplifier and page buffer circuitry (e.g., a data latch). The sensing and buffering circuitry system 120 is responsive to signals BL_SLE0 to BL_SELn from column access circuitry system 109. The sensing and buffering circuitry system 120 may be configured to determine (e.g., by sensing) information values ​​read (e.g., during a read operation) from memory cells 102 in blocks BLK0 to BLKi and to provide these information values ​​to lines (e.g., global data lines) 175. The sensing and buffering circuitry system 120 may also be configured to use signals on line 175 to determine information values ​​stored (e.g., programmed) in memory cells 102 in blocks BLK0 to BLKi (e.g., during a write operation) based on signal values ​​(e.g., voltage values) on line 175 (e.g., during a write operation).

[0025] Memory device 100 may include an input / output (I / O) circuitry 117 for exchanging information between memory cells 102 in blocks BLK0 to BLKi and lines (e.g., I / O lines) 105. Signals DQ0 to DQN on line 105 may indicate information read from or stored in memory cells 102 in blocks BLK0 to BLKi. Line 105 may contain nodes within memory device 100 or pins (or solder balls) on a package of memory device 100 that may reside therein. Other devices external to memory device 100 (e.g., memory controllers or processors) may communicate with memory device 100 via lines 103, 104, and 105.

[0026] The memory device 100 may receive a supply voltage, including a supply voltage Vcc and a supply voltage Vss. The supply voltage Vss may operate at a ground potential (e.g., having a value of about 0 volts). The supply voltage Vcc may include an external voltage supplied to the memory device 100 from an external power source, such as a battery or an AC / DC converter circuit system.

[0027] Each of the memory cells 102 can be programmed to store information representing the value of up to one bit (e.g., a single bit) or the value of multiple bits (e.g., 2, 3, 4, or another number of bits). For example, each of the memory cells 102 can be programmed to store information representing the binary value "0" or "1" of a single bit. A single bit per cell is sometimes referred to as a single-level cell. In another instance, each of the memory cells 102 can be programmed to store information representing the value of multiple bits, such as one of the four possible values ​​"00", "01", "10", "11" for 2 bits, one of the eight possible values ​​"000", "001", "010", "011", "100", "101", "110", and "111" for 3 bits, or one of other values ​​of multiple bits (e.g., more than 3 bits per memory cell). Cells with the ability to store multiple bits are sometimes referred to as multi-level cells (or multi-state cells).

[0028] Memory device 100 may include a non-volatile memory device, and memory cell 102 may include a non-volatile memory cell, such that memory cell 102 can retain information stored thereon when power (e.g., voltage Vcc, Vss, or both) is disconnected from memory device 100. For example, memory device 100 may be a flash memory device, such as NAND flash (e.g., 3D NAND) or NOR flash memory device, or another type of memory device, such as a variable resistance memory device (e.g., phase-change memory device or resistive random access memory (RAM) device).

[0029] Those skilled in the art will recognize that the memory device 100 may include other components, some of which are not shown. Figure 1 To avoid obscuring the exemplary embodiments described herein, at least a portion of the memory device 100 may include elements referenced below. Figures 2 to 27C Any of the described memory devices has a similar or identical structure and performs similar or identical operations.

[0030] Figure 2 This illustration shows a general schematic diagram of a portion of a memory device 200 according to some embodiments described herein, comprising a memory array 201 having blocks (blocks of memory cells or blocks of memory cells) BLK0 to BLKi and sub-blocks SB0 to SBj within each block. The memory device 200 may correspond to... Figure 1 The memory device 100. For example, the memory array 201 may be formed Figure 1 Part of the memory array 101.

[0031] like Figure 2As shown, each sub-block (e.g., SB0 or ​​SBj) has its own string of memory cells that can be associated with (e.g., coupled) a corresponding selection circuit. Sub-blocks of a block of memory device 200 (e.g., blocks BLK0 to BLKi) may have the same number of memory cell strings and associated selection circuits. For example, sub-block SB0 of block BLK0 has memory cell strings 231a, 232a, and 233a and corresponding associated selection circuits (e.g., drain selection circuits) 241a, 242a, and 243a and corresponding selection circuits (e.g., source selection circuits) 241'a, 242'a, and 243'a. In another example, sub-block SBj of block BLK0 has memory cell strings 234a, 235a, and 236a and corresponding associated selection circuits (e.g., drain selection circuits) 244a, 245a, and 246a and corresponding selection circuits (e.g., source selection circuits) 244'a, 245'a, and 246'a.

[0032] Similarly, sub-block SB0 of block BLK1 has memory cell strings 231b, 232b, and 233b and corresponding associated selection circuits (e.g., drain selection circuits) 241b, 242b, and 243b and corresponding selection circuits (e.g., source selection circuits) 241'b, 242'b, and 243'b. Sub-block SBj of block BLK1 has memory cell strings 234b, 235b, and 236b and corresponding associated selection circuits (e.g., drain selection circuits) 244b, 245b, and 246b and corresponding selection circuits (e.g., source selection circuits) 244'b, 245'b, and 246'b.

[0033] Figure 2 An example of three memory cell strings and their associated circuitry in a sub-block (e.g., sub-block SB0) is shown. The number of memory cell strings and their associated selection circuitry in each sub-block from BLK0 to BLKi can vary. Each memory cell string in memory device 200 may contain memory cells connected in series ( Figure 3 and Figure 4 (details shown in the text) and pillars (e.g.) Figure 5 The pillar 550 in the middle, wherein the serially connected memory cells can be positioned (e.g., vertically positioned) along the corresponding portion of the pillar.

[0034] like Figure 2 As shown in the diagram, the memory device 200 may include signals BL0 to BL0 respectively. N Data cable 2700 to 270 N Data cable 2700 to 270 N Each of them can be structured into conductive lines that may contain conductive materials (such as conductive doped polysilicon, metals or other conductive materials).

[0035] The memory cell strings from block BLK0 to BLKi can share data lines 2700 to 270. N Information (in signal form) is read from or stored in a selected memory cell (e.g., a selected memory cell in block BLK0 or BLK1) of memory device 200. For example, memory cell strings 231a, 234a (belonging to block BLK0), 231b, and 234b (belonging to block BLK1) may share data line 2700. Memory cell strings 232a, 235a (belonging to block BLK0), 232b, and 235b (belonging to block BLK1) may share data line 2701. Memory cell strings 233a, 236a (belonging to block BLK0), 233b, and 236b (belonging to block BLK1) may share data line 2702.

[0036] Memory device 200 may include a source (e.g., source line, source plate, or source region) 290 that can carry a signal (e.g., a source line signal) SRC. Source 290 may be structured as a conductive line or conductive plate (e.g., a conductive region) of memory device 200. Source 290 may be a common source (e.g., a common source plate or common source region) for blocks BLK0 to BLKi. Alternatively, each of blocks BLK0 to BLKi may have its own source similar to source 290. Source 290 may be coupled to a ground connection of memory device 200.

[0037] Each of blocks BLK0 to BLKi may have its own control gate group for controlling access to memory cells in a string of memory cells of the corresponding block's sub-blocks. For example... Figure 2 As shown, memory device 200 may include control gates (e.g., word lines) 2200, 2210, 2220, and 2230 in block BLK0, which may be portions of conductive paths (e.g., access lines) 2560 of memory device 200. Memory device 200 may also include control gates (e.g., word lines) 2201, 2211, 2221, and 2231 in block BLK1, which may be portions of other conductive paths (e.g., access lines) 2561 of memory device 200. Conductive paths 2560 and 2561 may correspond to... Figure 1 A portion of the access line 150 of the memory device 100.

[0038] like Figure 2 As shown, control gates 2200, 2210, 2220, and 2230 are electrically decoupled from each other. Control gates 2201, 2211, 2221, and 2231 are electrically decoupled from each other. Control gates 2200, 2210, 2220, and 2230 are electrically decoupled from control gates 2201, 2211, 2221, and 2231. Therefore, blocks BLK0 to BLKi can be accessed individually (e.g., one at a time).

[0039] Figure 2 A memory device 200 is shown as an example, comprising four control gates in each of blocks BLK0 to BLKi. The number of control gates in blocks (e.g., blocks BLK0 to BLKi) of the memory device 200 may be different from four. For example, each of blocks BLK0 to BLKi may contain up to several hundred control gates (or more than several hundred control gates).

[0040] Each of control gates 2200, 2210, 2220, and 2230 may be part of a structure (e.g., a layer) of conductive material (e.g., a conductive material layer) located in a layer of memory device 200. Control gates 2200, 2210, 2220, and 2230 may carry corresponding signals (e.g., word line signals) WL00, WL10, WL20, and WL30. Memory device 200 may use signals WL00, WL10, WL20, and WL30 to selectively control access to memory cells of block BLK0 during operations (e.g., read, write, or erase operations).

[0041] Each of the control gates 2201, 2211, 2221, and 2231 may be part of a structure (e.g., a layer) of conductive material (e.g., a conductive material layer) located in a layer of the memory device 200. The control gates 2201, 2211, 2221, and 2231 may carry corresponding signals (e.g., word line signals) WL01, WL11, WL21, and WL31. The memory device 200 may use signals WL01, WL11, WL21, and WL31 to selectively control access to memory cells of block BLK1 during operations (e.g., read, write, or erase operations).

[0042] like Figure 2 As shown, in sub-block SB0 of block BLK0, memory device 200 may include a select line (e.g., drain select line) 2800 that can be shared by select circuits 241a, 242a, and 243a. In sub-block SBj of block BLK0, memory device 200 may include a select line (e.g., drain select line) 280 that can be shared by select circuits 244a, 245a, and 246a. j Block BLK0 may contain a select line (e.g., source select line) 284 that can be shared by select circuits 241'a, 242'a, 243'a, 244'a, 245'a and 246'a.

[0043] In sub-block SB0 of block BLK1, memory device 200 may include a select line (e.g., drain select line) 2800, which is electrically isolated from the select line 2800 of block BLK1. The select line 2800 of block BLK1 may be shared by select circuits 241b, 242b, and 243b. In sub-block SBj of block BLK1, memory device 200 may include a select line (e.g., drain select line) 280 that can be shared by select circuits 244b, 245b, and 246b. j BLK1 selects lines 2800 and 280. j With block BLK0, select lines 2800 and 280 j Electrically isolated. Block BLK1 may contain a select line (e.g., source select line) 284 that can be shared by select circuits 241'b, 242'b, 243'b, 244'b, 245'b, and 246'b.

[0044] Figure 2 The memory device 200 is shown to include a drain select line (e.g., select line 2800) shared by select circuits (e.g., select circuits 241a, 242a, or 243a) in a sub-block (e.g., sub-block SB0 of block BLK0). However, the memory device 200 may include multiple drain select lines shared by select circuits in the sub-block. Figure 2 The memory device 200 is shown to include a source select line (e.g., select line 284) shared by source select circuits (e.g., select circuits 241'a, 242'a, or 243'a) in a sub-block (e.g., sub-block SB0 of block BLK0). However, the memory device 200 may include multiple source select lines shared by source select circuits in the sub-block.

[0045] exist Figure 2 In the memory device 200, each of the drain selection circuits may include a drain selection gate between the corresponding data line and the corresponding memory cell string (e.g., Figure 3 (The transistor shown in the image). A drain-select gate (e.g., a transistor) can be controlled (e.g., turned on or off) by a signal on the corresponding drain-select line based on the voltage supplied to the signal.

[0046] exist Figure 2 In the memory device 200, each of the source selection circuits may include a source selection gate (e.g., a source selection gate coupled between the source 290 and the corresponding memory cell string) Figure 3 (The transistor shown in the image). A source-select gate (e.g., a transistor) can be controlled (e.g., turned on or off) by a signal on the corresponding source-select line based on the voltage supplied to the signal.

[0047] Figure 3 Demonstrating some embodiments according to those described herein, including Figure 2Detailed schematic diagram of blocks BLK0 and BLK1 in memory device 200. Figure 3 middle, Figure 3 The directions X, Y, and Z can be relative to the physical orientation (e.g., three-dimensional (3D) dimensions) of the structure of the memory device 200. For example, the Z direction can be perpendicular to the substrate of the memory device 200 (e.g., ...). Figure 5 The orientation of the substrate 599 shown in the diagram (e.g., the vertical direction relative to the substrate). The Z direction is perpendicular to the X and Y directions (e.g., the Z direction is perpendicular to the XY plane of the memory device 200).

[0048] For simplicity, Figure 3 Only marked in Figure 2 The memory device 200 includes some memory cell strings and some selection circuits. For example... Figure 3 As shown, each select line can carry an associated individual select signal. For example, in sub-block SB0 of block BLK0, select line (e.g., drain select line) 2800 can carry a signal (e.g., drain select gate signal) SGD00. In sub-block SBj of block BLK0, select line (e.g., drain select line) 280... j Signal that can be carried (e.g., drain select gate signal) SGD0 j The sub-blocks SB0 and SBj of block BLK0 can share the select line 284 of SGS0, which can carry signals (e.g., source select gate signals).

[0049] In sub-block SB0 of block BLK1, the select line (e.g., drain select line) 2800 can carry a signal (e.g., drain select gate signal) SGD00. In sub-block SBj of block BLK1, the select line (e.g., drain select line) 280... j Signal that can be carried (e.g., drain select gate signal) SGD0 j Sub-blocks SB0 and SBj of block BLK1 can share the select line 284 of SGS1, which can carry signals (e.g., source select gate signals).

[0050] For simplicity, similar or identical elements in the memory devices described herein are given the same reference numerals. For example, such as Figure 3 As shown in the diagram, for simplicity, similar drain select lines (and their associated signals) are given the same label. However, as... Figure 3 As shown, the drain select lines of memory device 200 (from the same block or different blocks) are electrically separated from each other and carry different signals (but the signals are given the same label).

[0051] like Figure 3As shown, memory device 200 may include: memory cells 210, 211, 212, and 213; a select gate (e.g., a drain select gate or a transistor) 260; and a select gate (e.g., a source select gate) 264, which may be relative to the structure of memory device 200 (in... Figure 4 (As shown in the image) The physical arrangement is on three dimensions (3D), such as the X, Y and Z directions (e.g., dimensions).

[0052] exist Figure 3 In the memory device 200, each of the memory cell strings (e.g., memory cell string 231a) may contain memory cells connected in series, including one of memory cells 210, one of memory cells 211, one of memory cells 212, and one of memory cells 213. Figure 3 Examples of four memory cells 210, 211, 212, and 213 in each memory cell string are shown. The number of memory cells in each memory cell string can vary. For example, each memory string can contain up to several hundred (or more) memory cells.

[0053] like Figure 3 As shown, each drain select circuit (e.g., select circuit 241a) may include one of select gates 260. Each source select circuit (e.g., select circuit 241'a) may include one of select gates 264.

[0054] Figure 3 Each selection gate 260 in the circuit can operate like a transistor. For example, the selection gate 260 of the selection circuit 241a can operate like a field-effect transistor (FET), such as a metal-oxide-semiconductor FET (MOSFET). An example of this MOSFET includes an n-channel MOS (NMOS) transistor.

[0055] Select lines (e.g., select line 2800 of sub-block SB0 of block BLK0) can carry signals (e.g., signal SGD00), but they do not operate like switches (e.g., transistors). Select gates (e.g., select gate 260 of select circuit 241a) can receive signals (e.g., signal SGD00) from the corresponding select lines (e.g., select line 2800 of sub-block SB0 of block BLK0) and can operate like switches (e.g., transistors).

[0056] In the physical structure of memory device 200, the select line (e.g., select line 2800 of sub-block SB0 of block BLK0) may be a structure (e.g., a layer) of conductive material (e.g., a conductive material layer (e.g., a wafer) or region) located in a single layer of memory device 200. The conductive material may include metals, doped polysilicon, or other conductive materials.

[0057] In the physical structure of the memory device 200, a selection gate (e.g., selection gate 260 of selection circuit 241a of sub-block SB0 of block BLK0) may include (or may be formed by): a portion of conductive material of the corresponding selection line (e.g., selection line 2800 of sub-block SB0 of block BLK0), a portion of channel material (e.g., polysilicon channel), and a portion of dielectric material between the portion of conductive material and the portion of channel material (e.g., similar to the gate oxide of a transistor [e.g., FET]).

[0058] Figure 3 An example is shown in which the memory device 200 includes a drain select gate (e.g., select gate 260) in each drain select circuit and a source select gate (e.g., select gate 264) in each source select circuit coupled to the memory cell string. However, the memory device 200 may include multiple drain select gates (e.g., multiple select gates 260 connected in series) in each drain select circuit, multiple source select gates (e.g., multiple select gates 264 connected in series) in each source select circuit, or both multiple drain select gates and multiple source select gates coupled to the memory cell string.

[0059] Figure 4 This illustration depicts blocks BLK0 and BLK1 and a dielectric structure 451 between the blocks, according to some embodiments described herein. Figure 2 and Figure 3 This is a top view of a portion of the structure of the memory device 200. For simplicity, some elements of the memory device 200 (and other memory devices described herein) may be omitted from specific views of the drawings to avoid obscuring the view or description of one or more elements depicted in that specific view. Furthermore, for simplicity, cross-sectional lines (e.g., section lines) are omitted from some or all elements shown in the drawings described herein. Some elements of the memory device 200 may be omitted from specific views of the drawings to avoid obscuring the view or description of one or more elements depicted in that specific view. Furthermore, the dimensions (e.g., physical structures) of the elements of the memory device 200 (and other memory devices) in the drawings described herein are not to scale. Moreover, the references above are not repeated. Figure 2 and Figure 3 Description of the same elements as the described memory device 200.

[0060] exist Figure 4 In this configuration, dielectric structure 451 can be formed to separate (physically separate) the blocks of memory device 200 from each other. Two adjacent blocks (e.g., blocks BLK0 and BLK1) can be separated from each other by one of the structures 451. Adjacent blocks can be positioned directly adjacent to each other.

[0061] Each dielectric structure 451 may have a length in the Y direction. Each dielectric structure 451 may comprise a dielectric material (e.g., silicon dioxide) or a combination of a dielectric material and an additional material (e.g., a non-conductive material). Each dielectric structure 451 may comprise a slit (not labeled) and a material (not labeled) formed in (e.g., filled in) the slit. The slit may comprise a trench (or may be a portion of) between adjacent blocks (e.g., blocks BLK0 and BLK1). The dielectric structure 451 may be referred to as a dielectric structure or a slit structure. The area of ​​the memory device 200 in which the structure 451 is located may be referred to as a slit region.

[0062] like Figure 4 The data cable is shown in the image, priced from 2700 to 270. N It can extend across blocks (e.g., blocks BL0 and BL1) in the X direction. Data lines 2700 to 270. N A pillar that can be positioned in the memory device 200 (e.g. Figure 5 Above and in electrical contact with the support column 550. Support column 550 is connected to data lines 2700 to 2700. N Connections between data lines (such as vertical connections in the Z direction) can be hidden under the data line and not displayed. Figure 4 In the middle. However, each pillar in the same sub-block of the block can be coupled to data lines 2700 to 270. N A single (e.g., unique) data line in the system.

[0063] like Figure 4 As shown, block BLK0 may include sub-blocks (e.g., four sub-blocks) SB0, SB1, SB2, and SB3, respectively associated with signals SGD00, SGD10, SGD20, and SGD30, and select lines (e.g., four drain select lines). The select lines may include corresponding conductive regions (e.g., conductive material) that are electrically separated from each other (in the X direction) and can be located on the same level (relative to the Z direction). The select lines associated with signals SGD00, SGD10, SGD20, and SGD30 can be located (relative to the Z direction) above the control gate of block BLK0 (below the select lines). Figure 4 As shown, each of the selected lines (associated with signals SGD00, SGD10, SGD20, and SGD30) can have a length in the Y direction. Figure 4 An example is shown in which each of the memory devices 200 may have four sub-blocks SB0, SB1, SB2, and SB3. However, the number of sub-blocks may be different from four.

[0064] Block BLK1 can have the same structure as block BLK0. For example... Figure 4 As shown in the diagram, block BLK1 may contain signals WL0 to WL M The associated control gate (which represents) Figure 3The control gates associated with signals WL01, WL11, WL21, and WL31, and signal SGS1 (also in Figure 3 The associated selection lines (e.g., source selection lines), sub-blocks SB0, SB1, SB2 and SB3, and selection lines (e.g., drain selection lines) SGD01, SGD11, SGD21 and SGD31 are shown in the diagram.

[0065] exist Figure 4 In block BLK0, signals WL0 to WL... M Associated control gate representation Figure 3 The control gates associated with signals WL00, WL10, WL20, and WL30. Figure 4 In block BLK0, signals WL0 to WL... M Associated control gate representation Figure 3 The control gates associated with signals WL01, WL11, WL21, and WL31. For example... Figure 4 As shown in the diagram, structure 451 between blocks BLK0 and BLK1 connects signals WL0 to WL in block BLK0. M The associated control gate and the signal WL0 to WL in block BLK1 are related. M The associated control gates are separated (physically and electrically).

[0066] Memory device 200 may include conductive contacts (e.g., word line contacts) 6650 and 6651 located between blocks BLK0 and BLK1 in the area containing dielectric structure 451. A detailed description of conductive contacts 6650 and 6651 is provided below. Figures 6 to 9B describe.

[0067] like Figure 4 As shown, conductive contact 6650 is associated (e.g., coupled) with the corresponding control gate of block BLK0. Conductive contact 6651 is associated (e.g., coupled) with the corresponding control gate of block BLK1.

[0068] Figure 4 A side view (e.g., cross-section) of the memory array (memory cell array) 201 of the memory device 200 at line 5 in the middle. Figure 5 It is displayed in the middle.

[0069] Figure 5 Demonstrating some embodiments according to the description herein Figure 4 A side view (e.g., cross-section) of a portion of the structure of the memory device 200, which includes a layer (material layer) 535 comprising a respective memory cell and a control gate associated with the memory cell (e.g., controlling the memory cell). Figure 5Other blocks of the memory device 200 are also partially shown (on the left and right sides of blocks BLK0 and BLK1).

[0070] like Figure 5 As shown, the memory device 200 may include a substrate 599 and different layers 501 to 512 of the memory device 200 in the Z direction above the substrate 599. Layers 501 to 512 are physical device layers of the memory device 200 above the substrate 599. The memory device 200 may include layers 521, 522, and 523. Each of layers 521, 522, and 523 may include a portion of the memory device 200 in a different physical layer (e.g., layers 501 to 512).

[0071] The memory device 200 may include a dielectric material 581 formed on at least a portion of the memory device 200. Figure 5 In the memory cell strings of the corresponding sub-blocks SB0, SB1, SB2, and SB3 of each of blocks BLK0 and BLK1 (e.g., Figure 3 The memory cells 210, 211, 212 and 213 of the memory cell string 231a can be formed on the substrate 599 and the source 290 (for example, vertically formed in the corresponding layers of layers 501 to 512 in the Z direction).

[0072] exist Figure 5 In this context, the selection lines indicated by the SGD signal (e.g., the four drain selection lines in the X direction) correspond to the corresponding selection lines (e.g., drain selection lines) in the corresponding blocks of BLK0 and BLK1. For example, in the sub-blocks SB0, SB1, SB2, and SB3 of block BLK0, the selection lines indicated by the SGD signal (e.g., the four drain selection lines) correspond to the... Figure 4 The diagram shows the corresponding selection lines associated with signals SGD00, SGD10, SGD20, and SGD30 in block BLK0. In another example, in sub-blocks SB0, SB1, SB2, and SB3 of block BLK1, the selection lines indicated by signal SGD (e.g., the four drain selection lines in the X direction) can correspond to... Figure 4 The corresponding selection lines associated with signals SGD01, SGD11, SGD21 and SGD31 of block BLK1 are shown in the figure.

[0073] like Figure 5 As shown, the select lines (e.g., four drain select lines) in the same block (e.g., block BLK0) may contain corresponding conductive regions (e.g., four conductive regions) that are electrically separated from each other and can be located on the same level (e.g., level 512) in the Z direction of the memory device 200 and located above the control gate of the corresponding block (in the Z direction).

[0074] The selection line (e.g., the source select line) indicated by the signal SGS (on layer 501) can correspond to the corresponding selection lines in blocks BLK0 and BLK1. For example, in block BLK0, the selection line indicated by the signal SGS can correspond to... Figure 4 The example shown is the selection line (e.g., the source select line) associated with signal SGS0 in block BLK0. In another example, in block BLK1, the selection line indicated by signal SGS may correspond to... Figure 4 The selection line (e.g., source selection line) associated with the signal SGS1 of block BLK1 is shown in the figure.

[0075] exist Figure 5 For simplicity, the control gates (e.g., four control gates) of blocks BLK0 and BLK1 are indicated by the same signals WL0, WL1, WL2, and WL3. For example, in block BLK0, the control gates indicated by signals WL0, WL1, WL2, and WL3 can correspond to the control gates indicated by signals WL0, WL1, WL2, and WL3 respectively. Figure 4 The block BLK0 is shown in the diagram, with signals WL00, WL10, WL20, and WL30 associated with their respective control gates. In another example, in... Figure 5 In block BLK1, the control gates indicated by signals WL0, WL1, WL2, and WL3 can correspond to respectively... Figure 4 The corresponding control gates associated with signals WL01, WL11, WL21 and WL31 of block BLK1 shown in the figure. Figure 5 The illustrated memory device 200 includes four control gates (associated with signals WL0, WL1, WL2, and WL3) as an example. However, the memory device 200 may include numerous control gates (e.g., associated with signals WL0 to WL3). M Associated control gates, such as Figure 7 It is displayed in the middle.

[0076] like Figure 5 As shown, the memory device 200 may include dielectric material (e.g., silicon dioxide) 531 positioned on layers 503, 505, 507, 509, and 511. The dielectric material 531 in the respective blocks is interleaved with conductive material 532. The conductive material 532 may form respective control gates (associated with signals WL0, WL1, WL2, and WL3) in the respective blocks. Figure 5As shown, dielectric material 531 can be positioned on a corresponding step of layers 501 to 512. Conductive material 532 can be positioned on a corresponding step of layers 501 to 512 (e.g., layers 502, 504, 506, 508, 510, and 512) that intersect with the layers of dielectric material 531. Examples of conductive material 532 (which forms the control gate) include a single conductive material (e.g., a single metal, such as tungsten) or a combination of different layers of conductive materials. For example, each of the control gates of blocks BLK0 and BLK1 can comprise (e.g., multiple layers) aluminum oxide, titanium nitride, and tungsten.

[0077] The layers of dielectric material 531 and conductive material 532 can form the layers 535 of the memory device 200. Each layer 535 may include layers of dielectric material 531 and layers of conductive material 532. For simplicity, Figure 5 Only some levels 535 are marked in the text. For example... Figure 5 As shown, the hierarchy 535 can be positioned vertically to each other and can contain memory cells 210, 211, 212 and 213 of corresponding hierarchy and control gates associated with the memory cells. Figure 5 Several levels (e.g., four levels 535) of the memory device 200 are shown as examples. However, the memory device 200 may contain up to hundreds (or more) levels.

[0078] like Figure 5 As shown, memory device 200 may include pillars (memory cell pillars) 550 in blocks BLK0 and BLK1. Each of the pillars 550 may be a portion of a corresponding memory cell string (e.g., memory cell string 231a). Each of the pillars 550 may have a length extending in the Z direction (e.g., vertically extending from substrate 599) between substrate 599 and data line 270, passing through at least a portion of each of layers 521, 522, and 523. Figure 5 As shown, the Z direction is also the direction in which the length of the pillar 550 extends from one level to another, and it is also the direction from the layer of dielectric material 531 to the layer of conductive material 532.

[0079] like Figure 5As shown, memory cells 210, 211, 212, and 213 of a corresponding memory cell string (e.g., memory cell string 231a) can be located in different layers (e.g., layers 504, 506, 508, and 510) of the memory device 200 in the Z direction. The control gate of each of blocks BLK0 and BLK1 (associated with signals WL0, WL1, WL2, and WL3) can be located on the same layer (e.g., layers 504, 506, 508, and 510) where memory cells 210, 211, 212, and 213 are located. Therefore, the control gates of memory cells 210, 211, 212, and 213 and blocks BLK0 and BLK1 can be located (e.g., vertically) in the Z direction along corresponding portions of pillar 550 (e.g., portions on layers 504, 506, 508, and 510).

[0080] The substrate 599 of the memory device 200 may comprise a single-crystal (also referred to as a monocrystalline) semiconductor material. For example, the substrate 599 may comprise single-crystal silicon (also referred to as monocrystalline silicon). The single-crystal semiconductor material of the substrate 599 may contain impurities, such that the substrate 599 may have a specific conductivity type (e.g., n-type or p-type).

[0081] like Figure 5 As shown, memory device 200 may include circuitry 595 located (e.g., formed in) substrate 599. At least a portion of circuitry 595 may be located in a portion of substrate 599 under (e.g., directly under) the memory cell strings of blocks BLK0 and BLK1. Circuitry 595 may include transistors (e.g., Tr1 and Tr2), which may be part of decoder circuitry, driver circuitry (e.g., word line drivers), buffers, sense amplifiers, charge pumps, and other circuitry of memory device 200.

[0082] exist Figure 5 In this process, the source electrode 290 may contain a conductive material (or several conductive materials, such as different materials of different layers) and may extend in the X direction. Figure 5 An example is shown in which the source 290 may be formed on a portion of the substrate 599 (e.g., by depositing a conductive material on the substrate 599). Alternatively, the source 290 may be formed in or on a portion of the substrate 599 (e.g., by doping a portion of the substrate 599).

[0083] The select lines of blocks BLK0 and BLK1 (associated with signals SGS and SGD) may have the same material (or materials) as the control gates of blocks BLK0 and BLK1 (associated with signals WL0, WL1, WL2, and WL3). Alternatively, the select gates associated with signals SGS, SGD, or both may have a different material (or materials) than the control gates.

[0084] Figure 6 Demonstrating some embodiments according to the description herein Figure 4 A top view of the structure of the memory device 200. (See attached image.) Figure 6 As shown in the diagram, pillar 550 (shown in a top view) is positioned within a region contained in memory array 201. Conductive contacts 6650 and 6651 may be positioned within a region containing dielectric structure 451 between blocks BLK0 and BLK1. Dielectric structure 451 may contain a material (e.g., dielectric material 451D) separating blocks BLK0 and BLK1. One or more materials of conductive contacts 6650 and 6651 may be used with... Figure 9A The conductive material 532 is similar to or the same.

[0085] Conductive contacts 6650 and 6651 can contact corresponding control gates associated with blocks BLK0 and BLK1 of the memory device 200, respectively. Figure 7 (As shown in the diagram) (forming an electrical connection with the corresponding control gate). Conductive contact 6650 enables signals (e.g., word line signals WL00, WL10, WL20, and WL30) through conductive contact 6650 to the corresponding control gate of block BLK0. Conductive contact 6651 enables signals (e.g., word line signals WL01, WL11, WL21, and WL31) through conductive contact 6651 to the corresponding control gate of block BLK1. Figure 7 , Figure 8 , Figure 9A and Figure 9B (More detailed description below) Different views of the memory device 200 including conductive contacts 665 are shown.

[0086] Figure 7 , Figure 8 , Figure 9A and Figure 9B Different views of a memory device 200 including conductive contacts 6650 and 6651 and associated control gates according to some embodiments described herein are shown. Figure 7 and Figure 8 The same view of the memory device 200 is shown, except that the connection between the conductive contacts and the control gate is different. For simplicity and to improve readability, Figure 7 and Figure 8 A simplified diagram showing the structure of the memory device 200 is displayed. Figure 7 and Figure 8 Some details Figure 9A and Figure 9B It is displayed in the middle. Figure 7 and Figure 8 The dielectric material 531 between the conductive material 532 is omitted. Figure 9AConductive material 532 and dielectric material 531 (which can form layers of memory device 200) are shown. Conductive material 532 can form corresponding control gates. In block BLK0, the control gates are associated with signals WL00, WL10, WL20, and WL30, such as... Figure 7 As shown in the diagram. In block BLK1, the control gate is associated with signals WL01, WL11, WL21, and WL31, as follows: Figure 7 Displayed in [the text]. For example... Figure 7 and Figure 8 As shown, the conductive contacts 6650 and 6651 of blocks BLK0 and BLK1 (which are adjacent blocks) can be located in the area containing the dielectric structure 451.

[0087] Figure 7 and Figure 8 Different example patterns of the connection between conductive contacts 6650 and 6651 associated with the control gate of memory device 200 are shown. For example, coupling to signals WL20 and WL21 (in Figure 7 The conductive contacts of the corresponding control gates associated with (in the middle) can be coupled to signals WL10 and WL11 (in Figure 7 The conductive contacts of the corresponding control gates associated with (in the middle) are swapped, so that the connection of the swapped pair becomes Figure 8 The connections shown are illustrated in the diagram. Memory device 200 can have different connection modes as long as different control gates are associated (coupled) with different conductive contacts. Therefore, two different control gates can be associated with two different conductive contacts. The two different control gates may not share conductive contacts (they may not have common conductive contacts).

[0088] Figure 9A A 3D view (three-dimensional view) of a memory device 200 is shown, comprising two conductive contacts 6650 and 6651 coupled to two different control gates associated with signals WLi0 and WLi1. Figure 9B exhibit Figure 9A A top view (e.g., cross-section) of a portion of the memory device 200. Figure 9A As shown, dielectric structure 451 may include a length in the Y direction, which is a direction perpendicular to the direction from conductive contact 6650 to conductive contact 6651 (e.g., the X direction).

[0089] like Figure 9B As shown, dielectric structure 451 may be included between conductive contacts 6650 and 6651 (e.g., directly between conductive contacts 6650 and 6651) and in contact with dielectric portion 451P of conductive contacts 6650 and 6651. Dielectric portion 451P includes sidewalls 451W. For simplicity, from Figure 9A The dielectric part 451P is omitted.

[0090] exist Figure 9A and Figure 9B In the diagram, signal WLi0 represents... Figure 7 One of the signals WL00, WL10, WL20, and WL30 in block BLK0. Signal WLi1 represents... Figure 7 One of the signals WL01, WL11, WL21, and WL31 in block BLK1. Conductive contacts 6650 and 6651 respectively represent Figure 7 The two conductive contacts are 6650 and 6651.

[0091] like Figure 9A and Figure 9B As shown, conductive contacts 6650 and 6651 are adjacent to each other in the X direction. Each of conductive contacts 6650 and 6651 includes a length in the Z direction. The layer 901i can be... Figure 7 or Figure 8 One of the following layers: 502, 504, 506, and 508. Layers 502, 504, 506, and 508 are related to... Figure 5 The hierarchical structure shown in the text is the same. For example... Figure 9A As shown, the control gates associated with signals WLi0 and WLi1 can be located on the same layer in a layer containing the corresponding conductive material 532. For example, the control gates associated with signals WLi0 and WLi1 can be located on the same layer 901i, where layer 901i can be... Figure 7 One of the layers 502, 504, 506, and 508. Since the control gates associated with signals WLi0 and WLi1 can be located on the same layer 901i, the conductive contacts associated with the control gates (e.g., conductive contacts 6650 and 6651) can have the same length (length in the Z direction).

[0092] like Figure 9A and Figure 9B As shown, conductive contacts 6650 and 6651 can be positioned on opposite sides (in the X direction) of dielectric portion 451P. Conductive contacts 6650 and 6651 may include corresponding sidewalls 665W0 and 665W1 (e.g., vertical sidewalls in the Z direction).

[0093] like Figure 9A and Figure 9B As shown, sidewall 665W0 can be recessed into conductive material 532 forming a control gate associated with signal WLi0. Sidewall 665W1 can be recessed into conductive material 532 forming a control gate associated with signal WLi1.

[0094] like Figure 9A and Figure 9BAs shown, each of the sidewalls 665W0 and 665W1 has a semi-circular or semi-elliptical shape (resembling the letter "C" from a top view). A conductive contact 6650 may be adjacent to and enclose a portion of the sidewall 451W of the dielectric portion 451P (e.g., formed on said portion). For example, in Figure 9B As shown, conductive contact 6650 may cover the left (in the X direction) portion of the sidewall 451W of dielectric portion 451P. In a similar but opposite manner, conductive contact 6651 may be adjacent to and cover another portion of the sidewall 451W of dielectric portion 451P (e.g., formed on said other portion). For example, in... Figure 9B As shown, conductive contact 6651 can wrap around the right side of the sidewall 451W of dielectric portion 451P (in the X direction).

[0095] like Figure 9A As shown, conductive contacts 6650 and 6651 can be positioned at edges 532E0 and 532E1 of the corresponding control gates associated with signals WLi0 and WLi1. Edges 532E0 and 532E1 are adjacent to each other in the X direction (e.g., directly opposite each other in the X direction). Edge 532E0 is the edge of the conductive material 532 (in block BLK0) forming the control gate associated with signal WLi0. Edge 532E1 is the edge of the conductive material 532 (in block BLK1) forming the control gate associated with signal WLi1. Other conductive contacts in blocks BLK0 and BLK1 have... Figure 9A and Figure 9B The conductive contacts 6650 and 6651 shown in the image have similar structures.

[0096] The described memory device 200 including conductive contacts 6650 and 6651 allows the memory device 200 to have a relatively small area (e.g., a small area) of conductive contacts (e.g., conductive contacts 6650 and 6651) associated with the control gate of the memory device 200. This can lead to cost reduction. Furthermore, the memory device 200 including conductive contacts 6650 and 6651 can mitigate or prevent damage (e.g., layer collapse, layer bending, or both) to portions of the memory device 200 (e.g., at the locations of conductive contacts 6650 and 6651) during processing. This can improve yield and cost. Moreover, the absence of layer collapse and layer bending allows the memory device 200 to maintain proper electrical connections between the circuit elements of the memory device 200 (e.g., less susceptible to electrical short circuits between circuit elements). This can lead to improvements in at least one of the performance and reliability of the memory device 200.

[0097] refer to Figures 2 to 9B The above description describes the structure of the memory device 200. Some or all of the structures of the memory device 200 may be used with reference to the following. Figures 10A to 27CThe process described is formed by the related processes.

[0098] Figures 10A to 27C Different views of elements during the process of forming memory device 1000 according to some embodiments described herein are shown. Figure 10A exhibit Figure 10B A side view (e.g., cross-section) of a portion of the memory device 1000 at line 10A in the YZ direction. Figure 10B This is a top view (in the XY direction) of a portion of the memory device 1000.

[0099] and Figure 10A and Figure 10B The associated process may include forming dielectric material (dielectric material layer) 1031 and dielectric material (dielectric material layer) 1032 on substrate 1099. Dielectric material 1031 may comprise silicon dioxide. Dielectric material 1032 may comprise silicon nitride. Dielectric materials 1031 and 1032 may be formed sequentially on substrate 1099 in an alternating manner, such that dielectric material 1031 and dielectric material 1032 are interleaved.

[0100] like Figure 10A As shown, dielectric materials 1031 and 1032 can form a layer (material layer) 1035. Layers 1035 are positioned vertically relative to each other in the Z direction. Each layer 1035 can contain dielectric materials 1031 and 1032 of a corresponding level. For example... Figure 10A As shown in the diagram, layer 1035 may be contained within layer 521' of the memory device. In this document ( Figures 10A to 47 In the description, levels 521', 522', and 523' can correspond to Figure 5 Levels 521, 522, and 523.

[0101] Figure 11A and Figure 11B The memory device 1000 is shown after openings (e.g., holes) 1150 and 1151 have been formed. Opening 1151 may be formed in region 1151' between blocks BLK0 and BLK1. In subsequent processes of forming the memory device 1000, conductive contacts (like...) Figure 7 , Figure 8 and Figure 9A The conductive contacts 6650 and 6651 of the memory device 200 may be formed in region 1151'.

[0102] like Figure 11BAs shown, opening 1150 can be formed in the corresponding area of ​​the memory device 1000 containing blocks BLK0 and BLK1. In subsequent processes of forming the memory device 1000, portions of the memory cell string of the memory device 1000 can be formed at the locations of the corresponding openings 1150. For simplicity, Figure 11B A small number of openings 1150 are shown. In reality, numerous openings 1150 can be formed.

[0103] The openings 1150 and 1151 may include a portion of the dielectric material 1031 and 1032 at the locations where the openings 1150 and 1151 have been removed (e.g., etched). Figure 11B In the middle, zone 1151' and dielectric structure 451 ( Figure 4 and Figure 6 The memory device 200 is similar to the area where the memory is located.

[0104] Figure 12A and Figure 12B A memory device 1000 is shown after a material (or materials) 1233 is formed (e.g., filled) in openings 1150 and 1151. In subsequent processes of forming the memory device 1000, the material 1233 may be removed from openings 1150 and 1151 (e.g., removed at different times). Therefore, the material 1233 may be referred to as a sacrificial material. Examples of the material 1233 may include carbon or other materials. The forming material 1233 may include a material (e.g., carbon) formed in openings 1150 and 1151. A chemical mechanical polishing (CMP) process may be performed after the material 1233 is formed.

[0105] Figure 13A and Figure 13B The memory device 1000 is shown after additional dielectric material 1031 and dielectric material 1032 (additional layers) of layer 522' are formed on layer 521'. The formation of layer 522' can be similar to the formation of layer 521' described above. Therefore, for simplicity, some processes (process steps) are not shown. For example, compared with the formation... Figure 13A The process associated with layer 522' may include forming openings in dielectric materials 1031 and 1032 of layer 522', and then forming material (e.g., sacrificial) 1333 in the openings. Figure 13A ).

[0106] Figure 14A , Figure 14B and Figure 14C The memory device 1000 is shown after additional dielectric material 1031 and dielectric material 1032 (additional layers) of layer 523' are formed on layer 522'. Figure 14A and Figure 14C exhibit Figure 14BSide view of memory device 1000 at lines 14A and 14C.

[0107] form Figure 14A Layer 523' in the middle can be similar to the layer 521' formed above. Therefore, for simplicity, some processes (process steps) are not shown. For example, compared with the formation Figure 14A The process associated with layer 523' may include forming openings in dielectric materials 1031 and 1032 of layer 523', and then forming material (e.g., sacrificial) 1433 in the openings. Figure 14A ).and Figure 14A and Figure 14B The associated process may include forming material 1431 on layer 523'.

[0108] Each of pillars 1422 and 1422A may contain materials 1233, 1333, and 1433 in the corresponding layers 521', 522', and 523'. Pillar 1422 may be formed in region 1151 of layers 521', 522', and 523'. Pillar 1422A may be formed in regions (memory array regions) of blocks BLK0 and BLK1 of layers 521', 522', and 523'.

[0109] like Figure 14A , Figure 14B and Figure 14C As shown, supports 1422 and 1422A can be formed in the same manner and have the same outline (e.g., the same shape). However, supports 1422 and 1422A can be formed for different purposes, as described below.

[0110] In subsequent processes associated with the formation of memory device 1000, materials 1233, 1333, and 1433 in pillar 1422 can be removed. Figure 21A (in the middle), which serves as the conductive contact of the memory device 1000.

[0111] In subsequent processes associated with the portion forming the memory cells of the memory device 1000 (see below) Figure 20A describe), Figure 14C Materials 1233, 1333 and 1433 in the pillar 1422A can be removed to form memory cells and associated with the pillars (memory cell pillars) of blocks BLK0 and BLK1 of the memory device 1000.

[0112] In Figures 15A to 19A and Figure 19BIn the associated processes, when the process is performed at region 1151', material (e.g., support pillar 1422A) in the regions (e.g., memory array regions) of blocks BLK0 and BLK1 is covered (e.g., masked). Therefore, when the process is performed at region 1151', the material (e.g., sacrificial material) 1233, 1333, and 1433 formed in the regions of blocks BLK0 and BLK1 can be retained (not removed). Figure 20A and Figure 20B During the association process, the regions (memory array regions) of blocks BLK0 and BLK1 can be uncovered (e.g., exposed). After uncovering, memory cells and associated struts (memory cell struts) can be formed in the regions of blocks BLK0 and BLK1.

[0113] Figure 15A and Figure 15B The memory device 1000 is shown after a contact opening (e.g., a hole) 1565 has been formed. The contact opening 1565 may be formed in a region 1151' between blocks BLK0 and BLK1. Forming the contact opening 1565 may include removing a portion of the dielectric material 1031 and 1032 from the region 1151' at the location of the contact opening 1565. In subsequent processes of forming the memory device 1000, conductive contacts (e.g., like...) Figure 7 , Figure 8 and Figure 9A Conductive contacts 6650 and 6651 in the middle) and structure (e.g. Figure 20A The dielectric contact structure 2065 is formed at the location of the contact opening 1565.

[0114] Figure 16A and Figure 16B A memory device 1000 is shown after spacers 1664, 1665, and 1666 are formed. Spacers 1664, 1665, and 1666 comprise a dielectric material. For example, spacers 1664, 1665, and 1666 may comprise silicon dioxide, silicon nitride, and silicon dioxide, respectively. (For ease of viewing) Figure 16A and Figure 16B Spacers 1664, 1665, and 1666 (and other figures described herein) are not drawn with section lines (diagonal lines). Furthermore, the labels for spacers 1664 and 1666 are sometimes omitted from the figures to avoid overcrowding of elements in the figures.

[0115] Figure 17A and Figure 17B The image shows a memory device 1000 after a portion of the material directly beneath the contact opening 1565 has been removed to form a cut 1751 beneath the corresponding contact opening 1565. For simplicity, Figure 17AOnly two cuts 1751 are marked. Cut 1751 is an open space (e.g., a hole). Cut 1751 may be formed to expose the deepest opening (e.g., opening 1151X in layer 521') of the filling sacrificial material (e.g., material 1233).

[0116] Figure 18A and Figure 18B The memory device 1000 is shown after material 1233 and 1333 (sacrificial material) at a portion of layer 521' and a portion of layer 522' has been removed (e.g., excavated) through cut 1751. Figure 18A As shown in the image, open space 1851 is formed at the locations where materials 1233 and 1333 are removed.

[0117] Figure 19A and Figure 19B Display removal Figure 18A The memory device 1000 is positioned after the exposed dielectric material 1032 (e.g., silicon nitride at layer 1035) at the open space 1851. An etching process can be used to remove the dielectric material 1032. Figure 19A As shown, an open space 1951 is formed below the corresponding contact opening 1565. The open space 1951 includes an open space 1851 and a removed dielectric material 1032. Figure 18A The space occupied in the middle.

[0118] Figure 20A and Figure 20B A memory device 1000 is shown after the dielectric contact structure 2065 has been formed. The formation of the dielectric contact structure 2065 includes... Figure 19A A dielectric material (e.g., silicon dioxide) 2065D is formed (e.g., filled) in the open opening 1951 and contact opening 1565. A CMP process can be performed after the material 2065D is formed. Dielectric material 2031 may also be formed.

[0119] Figure 20C After display materials 1233, 1333 and 1433 were removed from the position of support 1422A Figure 20B Side view of memory device 1000 at line 20C (e.g., with) Figure 14C (Same cross-section).

[0120] Figure 20D The memory cell (unlabeled) and associated pillar 550' are formed in the opening 1442A. Figure 20C After the position of ) Figure 20C The memory device 1000. Figure 20B and Figure 20D The memory cells and associated pillars 550' of the memory device 1000 are respectively connected with Figure 5The memory cells 210, 211, 212 and pillar 550 of the memory device 200 are similar.

[0121] Formation and Figure 20D The process of forming the associated memory cell and associated pillar 550' may include elements forming a charge storage structure and channel (e.g., pillar channel) that may contain the memory cell. After the memory cell and pillar 550' are formed, they may be covered (e.g., shielded) when additional processes are performed at region 1151 and pillar 1422, as described below.

[0122] Figure 21A and Figure 21B Display opening 2151 is formed on support column 1422 (in) Figure 14A and 14B and Figure 20B The memory device 1000 is located after the position marked in the middle. Forming the opening 2151 may include patterning and removing material 1233, 1333, and 1433 from the corresponding supports 1422. Figure 21A and Figure 21B The associated process may also include forming dielectric structures (like...) Figure 4 The dielectric structure 451 in the middle is used to separate the word lines of block BLK0 from the neighboring block (not shown) (electrical separation) and to separate the word lines of block BLK1 from the neighboring block (not shown) (electrical separation).

[0123] Figure 22A and Figure 22B The memory device 1000 is shown after the dielectric material (e.g., silicon dioxide) 1031 at region 1151 has been removed. Figure 22A As shown, a spacer (e.g., a silicon nitride spacer) 1665 is exposed at a corresponding structure (e.g., a dielectric contact structure) 2065.

[0124] Figure 23A and Figure 23B Showing the removal of spacer 1665 (in) Figure 22A The memory device 1000 is marked with a middle label. Figure 23B In the middle, opening 2365 (which has an oval shape) is before the spacer is removed. Figure 22A The position of spacer 1665 in the middle.

[0125] Figure 23A and Figure 23C The dielectric material (e.g., silicon nitride) 1032 at the regions (memory array regions) of blocks BLK0 and BLK1 is shown from... Figure 23C The memory device 1000 after being removed (e.g., dug out) from position 1032'. Figure 23C Position 1032' in the dielectric material 1032 is Figure 23CThe gaps (blank spaces) previously occupied by dielectric material 1032 (as shown in Figure 14) are removed. In subsequent processes ( Figure 24C In the memory device 1000, conductive material may be formed at position 1032' to form a corresponding control gate.

[0126] Figure 23D exhibit Figure 23B A side view (e.g., cross-section) at line 23D, which includes one of the dielectric contact structures 2065 in region 1151' and portions of blocks BLK0 and BLK1 of the memory device 1000. Figure 23D In this context, level 1035' is one of the levels in the corresponding blocks BLK0 and BLK1. For example... Figure 23D As shown, opening 2365 can engage with a gap (empty space) at position 1032' within the hierarchy 1035' of the corresponding blocks BLK0 and BLK1 (forming a continuous access path). The corresponding blocks BLK0 and BLK1 at hierarchy 1035' coupled to opening 2365 can be positioned in the same hierarchy in the Z direction. In subsequent processes ( Figure 24C In ), conductive materials (e.g. Figure 24C The conductive material 2465 can be formed concurrently in the opening 2365 and the position 1032'. As described below, the conductive material in the position 1032' ( Figure 24C The conductive material 2465 in the middle forms the control gates of blocks BLK0 and BLK1. Opening 2365 ( Figure 23D Conductive materials in ) Figure 24C The same conductive material 2465) is formed with the corresponding control gate (which is also made of Figure 24C The conductive material 2465 in the conductive material forms the conductive contacts of blocks BLK0 and BLK1, which are associated (contacts). Therefore, the formation of conductive contacts and the formation of control gates can occur concurrently (e.g., in situ).

[0127] Figure 24A , Figure 24B and Figure 24C A conductive material (or several conductive materials) 2465 is formed at position 1032' (in Figure 23D (marked in the middle) and opening 2365 (in Figure 23D The memory device 1000 (marked in the middle). Conductive material 2465 can be used with... Figure 9A The conductive material 532 is similar to or the same as the conductive material 532. For example, the conductive material 2465 may comprise a single material (e.g., a metal) or a combination of conductive materials (e.g., a metal and other conductive materials) (e.g., different layers). For example, material 2465 may comprise tungsten or a combination of tungsten and other conductive materials (e.g., titanium nitride or other conductive materials).

[0128] As mentioned above, position 1032' (in Figure 23D The conductive material 2465 (marked in the middle) forms the control gates of blocks BLK0 and BLK1. Opening 2365 (in...) Figure 23D The conductive material 2465 (marked in the middle) forms conductive contacts associated with the corresponding control gates of blocks BLK0 and BLK1.

[0129] like Figure 24A and Figure 24B As shown, conductive material 2465 can form conductive structures 2465C adjacent to corresponding spacers 1664 and 1666. From a top view, each conductive structure 2465C has a circular or elliptical shape, resembling a ring. Each conductive structure 2465C can be adjacent to and surround (e.g., completely enclose) the sidewall 1666W of the corresponding spacer 1666 of the corresponding dielectric contact structure 2065. Figure 24B ).like Figure 24B As shown, sidewall 1666W is the outer sidewall of spacer 1666, opposite to the inner sidewall (not labeled) of spacer 1666. For simplicity, Figure 24B Only the sidewalls 1666W of the two spacers 1666 are marked.

[0130] In the subsequent process ( Figure 25A , Figure 25B , Figure 25C and Figure 25D In this structure, each conductive structure 2465C can be divided into two parts (a pair of conductive contacts). The two parts (divided parts) form two conductive contacts associated with two corresponding control gates of different blocks (one control gate in block BLK0 and the other control gate in block BLK1).

[0131] Figure 25A , Figure 25B , Figure 25C and Figure 25D A memory device 1000 is shown after conductive contacts 665'0 and 665'1 are formed in corresponding blocks BLK0 and BLK1. Figure 25A exhibit Figure 25B A side view (e.g., cross-section) at line 25A, which includes a dielectric contact structure 2065 and a portion of conductive material 2465 associated with the control gate of block BLK1. Figure 25C exhibit Figure 25B A side view (e.g., cross-section) at line 25C, which includes a dielectric contact structure 2065 and a portion of conductive material 2465 associated with the control gate of block BLK0. Figure 25D exhibit Figure 25BA side view (e.g., cross-section) at line 25D, which includes dielectric contact structure 2065, conductive material 2465 associated with the control gates of blocks BLK0 and BLK1, and pillars (memory cell pillars) 550' of the corresponding blocks BLK0 and BLK1.

[0132] Figure 25A Examples of some control gates of block BLK1 associated with signals WL01, WL11, WL21, WL31, WL41, and WL51 are shown. Figure 25D In this context, signals WL1 and WLi1 are associated with the control gate of block BLK1. Signals WL1 and WLi1 can correspond to... Figure 25A Some of the signals WL01, WL11, WL21, WL31, WL41 and WL51 in the signal. Figure 25D The signal WLi1 in the middle can represent Figure 25A One of the signals WL01, WL11, WL21, WL31, WL41 and WL51.

[0133] Figure 25C Examples of some control gates of block BLK0 associated with signals WL00, WL10, WL20, WL30, WL40, and WL50 are shown. Figure 25D In this context, signals WL0 and WLi0 are associated with the control gate of block BLK0. Signals WL0 and WLi0 can correspond to... Figure 25C Some of the signals WL00, WL10, WL20, WL30, WL40 and WL50. Figure 25D The signal WLi0 in the middle can represent Figure 25C One of the signals WL00, WL10, WL20, WL30, WL40 and WL50.

[0134] exist Figure 25D In this context, the control gates associated with signals WLi0 and WLi1 can be represented (or similar to or identical to) respectively associated with the memory device 200 in... Figure 9A The control gates associated with signals WLi0 and WLi1 in the signal.

[0135] exist Figure 25A , Figure 25B , Figure 25C and Figure 25D In this process, the formation of conductive contacts 665'0 and 665'1 may include removal (e.g., etching). Figure 24B The conductive structure 2465C in the conductive material 2465 is a portion thereof. For example... Figure 25B As shown in the top view, portions of the left and right sides (in the Y direction) of the corresponding conductive structure 2465C can be removed to divide each conductive structure 2465C into two remaining portions. One remaining portion (e.g.) Figure 25B The bottom portion of the block (BLK0) forms a conductive contact 665'0 associated with the control gate of the BLK0 block. The remaining portion (e.g.) Figure 25B The top portion of the block forms a conductive contact 665'1 associated with the control gate of block BLK1. Figure 25A , Figure 25B , Figure 25C and Figure 25D The conductive contacts 665'0 and 665'1 in the middle can be connected with Figure 7 , Figure 8 and Figure 9A The conductive contacts 665'0 and 665'1 of the memory device 200 are similar or identical.

[0136] like Figure 25B As shown in the diagram, from a top view, each conductive contact 665' has a semi-circular or semi-elliptical shape (like the letter "C"). Each conductive contact 665' may be adjacent to and partially enclose the corresponding dielectric contact structure 2065 (e.g., may enclose a portion of the outer wall 1666W of the spacer 1666 of the corresponding dielectric contact structure 2065). Figure 25A and Figure 25C In this context, the control gate of block BLK0 associated with signals WL00, WL10, WL20, WL30, WL40, and WL50 can be located at the same level as the control gate of block BLK1 associated with signals WL01, WL11, WL21, WL31, WL41, and WL51, respectively. Figure 5 (Similar to the layers 502, 504, 506, 508, 510, and 512 in the model). Therefore, the conductive contacts 665'0 and 665'1 associated with the control gates located on the same layer (e.g., the control gates associated with signals WL00 and WL01) can have the same length (in the Z direction).

[0137] Figure 26A and Figure 26B A memory device 1000 is shown after a dielectric structure 2651 is formed in region 1151'. Forming the dielectric structure 2651 may include forming (e.g., filling) a dielectric material (or several dielectric materials) 2651D in region 1151'. The dielectric structure 2651 separates blocks BLK0 and BLK1 from each other (physical separation). Therefore, the control gate of block BLK0 (e.g., with...) Figure 25C The control gates associated with signals WL00, WL10, WL20, WL30, WL40, and WL50 in the dielectric structure 2651 are connected to the control gate of block BLK1 (e.g., with the control gate of block BLK1) via the material 2651D of dielectric structure 2651. Figure 25A The control gates associated with signals WL01, WL11, WL21, WL31, WL41 and WL51 are separated (physically and electrically).

[0138] Figure 27A , Figure 27B and Figure 27C The illustration shows a memory device 1000 after conductive connections 27420 and 27421 are formed on corresponding conductive contacts 665'0 and 665'1 (e.g., formed on corresponding conductive contacts 665'0 and 665'1). In subsequent processes (not described), conductive lines (e.g., conductive routes) of the memory device 1000 may be formed to connect conductive connections 27420 and 27421 to other components of the memory device 1000 (e.g., word line drivers).

[0139] The above reference Figures 12A to 27C The process of forming memory device 1000 described herein may include other processes for forming a complete memory device (e.g., memory device 1000). Such processes are omitted from the above description to avoid obscuring the subject matter described herein. The improvements and benefits of memory device 1000 are similar to or the same as those of memory device 200 described above.

[0140] Figures 28 to 35 Different views of elements during the process of forming memory device 2800 according to some embodiments described herein are shown. Some of the processes and materials used in forming memory device 2800 are similar to or the same as those used in forming memory device 1000. Therefore, for simplicity, detailed descriptions of similar or identical processes and materials are not repeated. Furthermore, for simplicity, cross-sectional lines (e.g., section lines) are shown from... Figures 28 to 35 Some or all of the elements shown are omitted.

[0141] Figure 28 A memory device 2800 is shown after pillars 2851 are formed in the dielectric materials 1031 and 1032 of layer 521'. Pillars 2851 may include (e.g., may be filled with) and Figure 12A The same sacrificial material as material 1233 in the text.

[0142] Figure 29 The memory device 2800 is shown after additional dielectric material 1031 and dielectric material 1032 (additional layers) of layer 522' are formed on layer 521'. Figure 29 The associated process also includes forming an opening 2951 in layer 522'.

[0143] Figure 30 A memory device 2800 is shown after openings 3065 are formed in dielectric materials 1031 and 1032 in layers 521' and 522'.

[0144] Figure 31 Display pillars 3151 and 3165 through Figure 29 Opening 2951 and Figure 30 Sacrificial material is formed in the opening 3065 to form the subsequent memory device 2800.

[0145] Figure 32 The memory device 2800 is shown after additional dielectric material 1031 and dielectric material 1032 (additional layers) of layer 523' are formed on layer 522'. Figure 32 The associated process also includes forming a strut 3251 in layer 523'. Forming the strut 3251 may include forming an opening in layer 523' and forming (e.g., filling) the opening in layer 523' with a sacrificial material.

[0146] Figure 33 The memory device 2800 is shown after additional dielectric material 1031 and dielectric material 1032 (additional layers) of layer 524' are formed on layer 523'. Figure 33 The associated process also includes forming a strut 3351 in layer 524'. Forming the strut 3351 may include forming an opening in layer 524' and forming (e.g., filling) the opening in layer 524' with a sacrificial material.

[0147] Figure 34 A memory device 2800 is shown after contact openings 3465 are formed in dielectric materials 1031 and 1032 in layers 523' and 524'.

[0148] Figure 35 Display removal (e.g., digging out). Figure 35 The support column 3165 under the contact opening 3565 (in Figure 34 In the display, Figure 31 The memory device 2800 is the material following the marked material. (e.g., [the material is] marked in the middle.) Figure 35 As shown, contact opening 3565 is formed through layers 522', 523', and 524' and at least partially through layer 521'. Contact opening 3565 and Figure 15A The contact opening is similar to 1565.

[0149] In execution and Figure 35 Following the associated processes, the process of forming memory device 2800 may include additional processes for forming the complete memory device. For example, the process of forming memory device 2800 may continue with and Figure 16A and 16B arrive Figure 27A , Figure 27B and Figure 27C Related processes and similar processes in Figure 35 A conductive contact is formed at the contact opening 3565 of the memory device 2800. The conductive contact of the memory device 2800 can interact with... Figures 25B to 27B The conductive contacts 665'0 and 665'1 of the memory device 1000 are similar. For simplicity, the description of the additional processes for forming the conductive contacts of the memory device 2800 is omitted. The improvements and benefits of the memory device 2800 are similar to or the same as those of the improvements and benefits of the memory device 200 described above.

[0150] Figure 36A and Figure 36B A top view and a side view of a memory device 3600 including conductive contacts 4765' according to some embodiments described herein are shown. Figure 36B exhibit Figure 36A A side view (e.g., cross-section) of block BLK0 of memory device 3600 at line 36B. Memory device 3600 may contain elements similar to or the same as those in memory devices 200, 1000, and 2800. Therefore, for simplicity, descriptions of similar or identical elements are not repeated.

[0151] exist Figure 36A and Figure 36B In the middle, the pillar (memory cell pillar) 550” can be connected to the memory device 200 ( Figure 6 ) pillar 550, memory device 1000 ( Figure 22B ) memory cell pillar 500' or memory device 3700 ( Figure 44 The memory cell pillar 500” is similar. Figure 36A As shown, the memory device 3600 may include blocks BLK0 and BLK1, a dielectric structure 451' including material (e.g., dielectric material) 451D' between blocks BLK0 and BLK1, and a connection between signals BL0 and BL1. N The associated data line is 270'0 to 270' N Blocks BLK0 and BLK1 and dielectric structure 451' are respectively connected to... Figure 6 The memory device 1000 has BLK0 and BLK1 and dielectric structure 451 similar to those.

[0152] like Figure 36A and Figure 36B As shown, the memory device 3600 may include regions 3601 and 3602. Region 3601 may be referred to as the memory array region where the pillar (memory cell pillar) 550” is located. Region 3602 may be referred to as the contact region where the conductive contact 4765' is located. The conductive contact 4765' may include conductive material 4765M'. The conductive contact 4765' and the conductive material 4765M' can respectively connect to… Figure 47 The conductive contacts 4765 and conductive material 4765M' of the memory device 3700 are similar. Therefore, the conductive contacts 4765' of the memory device 3600 can be formed by... Figures 37 to 47(As described below) A similar process is used to form the conductive contact 4765 in the associated memory device 3700. Figure 36A In this context, block BLK0 may contain control gates associated with signals WL00 to WLm0. BLK1 may contain control gates associated with signals WL01 to WLm1. For example... Figure 36A As shown, the conductive contact 4765' in block BLK0 can be associated with the corresponding control gate (signals WL00 to WLm0).

[0153] Figure 36A and Figure 36B Also shown is a support pillar (e.g., a dielectric pillar) 4344' for the memory device 3600. The support pillar 4344' may comprise a dielectric material (e.g., silicon dioxide) 4344D'. The support pillar 4344' may be formed to provide structural support for the memory device 3600 at region 3602. The support pillar 4344' may be coupled with… Figures 43B to 47 The support pillar 4344 of the memory device 3700 is similar. Therefore, the support pillar 4344' of the memory device 3600 can be formed by [the support pillar 4344' in relation to the memory device 3600]. Figures 37 to 47 (Described below) A process similar to that used to form the support pillar 4344 in the associated memory device 3700 is formed.

[0154] Figure 36B The control gate (associated signals WL00, WL10, WL20, WL30, WL40 and WL50) associated with the conductive contact 4765' and the pillar 550 (for simplicity, only one pillar 550 is shown). Figure 36B Signals WL00, WL10, WL20, WL30, WL40, and WL50 are Figure 36A Some of the signals from WL00 to WLm0. For example... Figure 36B As shown, the control gate can be positioned on the corresponding level 535' (only two levels 535' are marked). Figure 36B The control gate and memory device 3700 in Figure 47 The control gates associated with signals WL0 to WL5 are similar. For simplicity, Figure 36B Other control gates (unlabeled) in the corresponding levels of the memory device 3600 shown in the figure are not drawn with cross-sectional lines (e.g., profile lines).

[0155] Figure 36B An example configuration is shown of a conductive contact 4765' coupled to an associated control gate of memory device 3600. However, memory device 3600 can have different configurations as long as different control gates are associated (coupled) to different conductive contacts. This means that two different control gates are associated with two different conductive contacts (and do not share conductive contacts).

[0156] like Figure 36B As shown, each of the conductive contacts 4765' may include a portion 3611, a portion 3612 positioned in the Z direction above the portion, and a portion 3613 positioned in the Z direction above the portion 3612. At least one (e.g., two or more) of the conductive contacts 4765' includes a portion comprising at least one conductive post (e.g., conductive posts 4765_P1' and 4765_P2'). For example, as... Figure 36B As shown, the conductive contact 4765 associated with the control gate associated with signal WL40 may include a portion 3611, which includes conductive pillars 4765_P1' and 4765_P2'. The conductive pillars 4765_P1' and 4765_P2' of portion 3611 are parts of the corresponding conductive contact 4765' and have the same conductive material 4765M' as other portions (e.g., portions 3612 and 3613) as conductive contacts 4765'.

[0157] like Figure 36B As shown, each of the conductive contacts 4765' may contain a conductive strip 4665S'. For simplicity, Figure 36B Only two conductive bands, 4665S', are marked in the middle. Conductive band 4665S' and... Figure 46 The conductive strip of the memory device 3700 is similar to or the same as that of 4665S. For example... Figure 36B As shown, in the conductive contact 4765 associated with the control gate associated with the signal WL40, the conductive strip 4665S' may be a portion of portion 3612 (e.g., may be located at portion 3612) and contacts the control gate associated with the signal WL40. Therefore, as Figure 36B As shown, conductive contact 4765' associated with the control gate associated with signal WL40 can contact the control gate associated with signal WL40 at portion 3612 between portion 3611 and portion 3613.

[0158] Figure 36B The portion 3611 showing the corresponding conductive contact 4765' includes two conductive pillars 4765_P1' and 4765_P2' as an example. However, in an alternative structure of the memory device 3600, the number of pillars (like conductive pillars 4765_P1' and 4765_P2') may vary.

[0159] In another alternative configuration of the memory device 3600, portion 3611 may have the same as Figure 36B The structure shown is different (e.g., different from the support structure). For example, part 3611 may contain a piece of material (e.g., conductive or non-conductive material) and does not have the same support structure as supports 4765_P1' and 4765_P2'.

[0160] exist Figure 36B In the present invention, portions 3611, 3612, and 3613 are examples of having the same conductive material (e.g., conductive material 4765M'). However, in an alternative configuration of the memory device 3600, portion 3611 may be a dielectric portion, such that portion 3611 may contain a material different from the conductive material 4765M (e.g., a non-conductive material (e.g., a dielectric material)). For example, portion 3611 may contain a dielectric pillar (or several dielectric pillars).

[0161] The conductive contact 4765' and the support pillar 4344' provide structural support for portions of the memory device 3600 to prevent damage to the memory device 3600 during the formation of the memory device 3600. For example, region 3602 of the memory device 3600 ( Figure 36B The layer 535' in the memory device 3600 is susceptible to collapse (e.g., layer collapse), bending (e.g., layer bending), or both during the formation of the memory device 3600. The conductive contacts 4765' and support pillars 4344' provide structural support to prevent such collapse or bending. The memory device 3600 also has other improvements and benefits similar to those of the memory devices 200 and 1000 described above.

[0162] refer to Figures 36A to 36B The above description describes the structure of memory device 3600. Some or all of the structures of memory device 200 may be used with reference to the following. Figures 10A to 27C and Figures 37 to 47 The process described is formed by the related processes.

[0163] Figures 37 to 47 Different views of the components during alternative processes for forming memory device 3700 according to some embodiments described herein are shown. Some of the processes and materials used in forming memory device 3700 are similar to or the same as those used in forming memory device 1000. Therefore, for simplicity, detailed descriptions of similar or identical processes and materials are not repeated. Furthermore, for simplicity, cross-sectional lines (e.g., section lines) are drawn from Figure 27 to... Figure 47 Some or all of the elements shown are omitted.

[0164] Figure 37 The memory device 3700 is shown after some of its components are assembled. Figure 37 The components of the memory device 3700 in the memory and Figure 16AThe components of the memory device 1000 shown are similar. For example, the contact opening (e.g., hole) 1565' is similar to the contact opening 1565 in FIG. 15. The spacers 1664 and 1665 are similar to or the same as the spacers 1664 and 1665 in FIG. 16. The support 1422' is similar to... Figure 14A Similar to pillar 1422. Therefore, with Figures 10A to 16A Related processes can be used to form Figure 37 The memory device 3700 in the middle.

[0165] Figure 37 The image shows a memory device 3700 with spacers (dielectric spacers) 3767 and 3768 formed in addition to spacers 1664 and 1665. Spacer 3767 may be made of silicon dioxide or may protect the spacer from subsequent processes (e.g., in...). Figure 44 Other materials are removed (e.g., excavated) to form the spacer. Example material of spacer 3767 comprises polycrystalline silicon.

[0166] Figure 38 The image shows a memory device 3700 after a portion of the material directly beneath the contact opening 1565' has been removed to form cutouts 1751 (only two are marked) beneath the corresponding contact opening 1565'. The cutouts (e.g., open spaces) 1751 may be formed to expose the filled material. Figure 12A The deepest opening of the sacrificial material 1233 (e.g., opening 1151X).

[0167] Figure 39 The memory device 3700 is shown after the open space 1951 has been formed. Forming the open space 1951 may include removing (digging out) material at the open space 1951 to expose dielectric material 1032 (e.g., silicon nitride of layer 1035) at the open space 1951. The material removed from the open space 1951 may be used with dielectric material 1032 (e.g., silicon nitride of layer 1035) at the open space 1951. Figure 12A and Figure 13A The sacrificial materials 1233 and 1333 formed in this process are similar. Figure 39 In addition, the dielectric material 1032 at the open space 1951 (which is exposed) can also be removed (e.g., etched).

[0168] Figure 40 Demonstrating the dielectric material (silicon dioxide) 4021 formed in Figure 39 The memory device 3700 is located in the corresponding open space 1951 at the position of the removed dielectric material 1032.

[0169] Figure 41 The memory device 3700 demonstrates a memory material 4165S formed in the corresponding contact opening 1565' after the material (e.g., carbon or polycrystalline silicon) 4165S is formed. The material 4165S will be used in subsequent processes (in...) Figure 45The sacrificial material removed (in the middle). The material (e.g., silicon dioxide) 4121 can also be formed on other materials, such as... Figure 41 It is displayed in the middle.

[0170] Figure 42 The memory device 3700 is shown after the memory cell (unlabeled) and associated pillar 550” are formed. The position of the pillar 550” can be... Figure 36A and Figure 36B The position of the pillar 550 at region 3601 of the memory device 3600 is similar.

[0171] Figure 43A Display opening 4344H is formed on pillar 1422 (in) Figure 38 The memory device 3700 is located after the position marked in the middle. Forming the opening 4344H may include patterning and removing material from the corresponding support 1422. As from the corresponding support ( Figure 37 The material to be removed may be similar to materials 1233, 1333 and 1433 in Figure 14.

[0172] Figure 43B The support column 4344 is formed in the opening 4344H (in Figure 43A The memory device 3700 is located after the position marked in the middle. A support pillar 4344 may be formed (e.g., filled) with a material (e.g., silicon dioxide) 4344D within an opening 4344H. The support pillar 4344 may be formed in the area of ​​the memory device 3700 where the conductive contact 4765 is located (e.g., with...). Figure 36B The same as area 3602 in the middle provides structural support for memory device 3700.

[0173] Figure 44 A memory device 3700 is shown after a conductive material (or several conductive materials) 4432 has been formed in a layer 1035. Forming the conductive material 4432 may involve removing (e.g., digging out) a dielectric material (e.g., silicon nitride) 1032 from the layer 1035. The conductive material 4432 may then be formed in the location of the removed dielectric material 1032. The conductive material 4432 may be coupled with… Figure 9A The conductive material 532 is similar to or the same as that of the memory device 3700. The conductive material 4432 in the corresponding layer 1035 may form the corresponding control gate of the memory device 3700, for example, in relation to the memory device 3700. Figure 47 The control gates associated with signals WL0, WL1, WL2, WL3, WL4 and WL5 in the signal.

[0174] Figure 45 Display material (sacrificial material) 4165S (in Figure 41The memory device 3700 is formed after the material 4165S is removed from the contact opening 1565'. Patterning and etching processes can be used to remove the material 4165S from the contact opening 1565'. Figure 45 The associated process can expose spacer 3768 at the corresponding contact opening 1565'.

[0175] Figure 46 The image shows a memory device 3700 after spacers 3767 and 3768 have been removed from contact opening 1565'. Patterning and etching processes can be used to remove spacers 3767 and 3768. Figure 46 As shown in the diagram, the memory device 3700 may include components that can be formed Figure 44 The conductive strip 4665S, formed by conductive material 4432, is used during the process of controlling the gate of the memory device 3700. For example, with Figure 44 In level 1035 of the middle Figure 44 The conductive material 4432 replaces the dielectric material 1032, and the spacer 1665 (in) Figure 37 A portion of the marked area is also removed and replaced with conductive material 4432. The conductive strip 4665S may be a corresponding conductive contact 4765 formed in the corresponding contact opening 1565'. Figure 47 () part.

[0176] Figure 47 The conductive contact 4765 is formed in the contact opening 1565' (in Figure 46 The memory device 3700 is located after the position marked in the middle. The conductive contact 4765 may be formed (e.g., filled) with a conductive material (e.g., a metal or a combination of different conductive materials) 4765M in the contact opening 1565'.

[0177] like Figure 47 As shown, conductive contact 4765 can contact the corresponding control gate (associated with signals WL0, WL1, WL2, WL3, WL4, and WL5). For simplicity, Figure 47 A portion of a memory device 3700 is shown, comprising six control gates (associated with six signals WL0 to WL5). The memory device 3700 may include numerous control gates. The control gates associated with signals WL0 to WL5 may represent signals respectively associated with… Figure 36B The control gates associated with signals WL00, WL10, WL20, WL30, WL40 and WL50 of the memory device 3600.

[0178] Figure 47 An example structure of conductive contact 4765 is shown. However, conductive contact 4765 may have the same... Figure 36BThe conductive contacts 4765' of the memory device 3600 have similar structures and materials to portions 3611, 3612, and 3613 (e.g., variations).

[0179] The above reference Figures 37 to 47 The process for forming memory device 3700 described herein may include other processes for forming the complete memory device. Such processes are omitted from the above description to avoid obscuring the subject matter described herein. The improvements and benefits of memory device 3700 are similar to or the same as those of memory device 200 described above.

[0180] The description of the apparatus (e.g., memory devices 100, 200, 1000, 2800, 3600, and 3700) and methods (e.g., methods of forming memory devices 1000 and 2600) is intended to provide a general understanding of the structure of the various embodiments and is not intended to provide a complete description of all elements and features of an apparatus that can use the structures described herein. As used herein, "apparatus" refers to, for example, a device (e.g., any of memory devices 100, 200, 1000, 2800, 3600, and 3700) or a system (e.g., a computer, mobile phone, or other electronic system) that includes, for example, any of memory devices 100, 200, 1000, 2800, 3600, and 3700.

[0181] The above reference Figures 1 to 47 Any of the components described can be implemented in many ways, including via software simulation. Thus, devices such as the memory devices 100, 200, 1000, 2800, 3600, and 3700 described above, or portions of each of these memory devices, can all be characterized herein as “a number of modules” (or “a module”). Such a module may, as needed and / or according to specific embodiments of the various embodiments, include hardware circuitry, single-processor and / or multi-processor circuitry, memory circuitry, software program modules and objects, and / or firmware, and combinations thereof. For example, such a module may be included in a system operation simulation package, such as a software electrical signal simulation package, a power usage and range simulation package, a capacitor-inductor simulation package, a power / heat dissipation simulation package, a signal transmit-receive simulation package, and / or a combination of software and hardware for operating or simulating the operation of the various potential embodiments.

[0182] Memory devices 100, 200, 1000, 2800, 3600, and 3700 may be included in devices (e.g., electronic circuit systems), such as high-speed computers, communication and signal processing circuit systems, single-processor or multi-processor modules, single-embedded or multi-embedded processors, multi-core processors, message exchange switches, and dedicated modules containing multi-layer, multi-chip modules. Such devices may be further included as sub-components within various other devices (e.g., electronic systems), such as televisions, mobile phones, personal computers (e.g., laptops, desktops, handhelds, tablets, etc.), workstations, radios, video players, audio players (e.g., MP3 (Moving Image Experts Group, Audio Layer 3) players), vehicles, medical devices (e.g., heart monitors, blood pressure monitors, etc.), set-top boxes, and others.

[0183] The above reference Figures 1 to 47 The described embodiments include an apparatus and a method of forming the apparatus. One of the apparatuses includes a memory device comprising: a first region comprising a first-level conductive material interleaved with a first-level dielectric material and a first memory cell, the first memory cell comprising a pillar extending through at least a portion of the first-level conductive material and the first-level dielectric material; a second region comprising a second-level conductive material interleaved with a second-level dielectric material and a second memory cell, the second memory cell comprising a pillar extending through at least a portion of the first-level conductive material and the first-level dielectric material; a third region comprising a dielectric structure separating the first-level conductive material from the second-level conductive material; and a conductive contact extending through at least a portion of the third region and contacting the conductive material in the first-level conductive material. Other embodiments including additional apparatus and methods are described.

[0184] In the detailed description and claims, the term "on" (one "on the other") used with respect to two or more elements (e.g., materials) means that there is at least some contact between the elements (e.g., between materials). The term "on top of" means that the elements (e.g., materials) are close together, but may have one or more additional intervening elements (e.g., materials) that make contact possible but not required. Neither "on" nor "on top of" implies any directionality as used herein unless stated otherwise.

[0185] In the detailed embodiments and claims, the terms "first," "second," and "third," etc., are used only as labels and are not intended to impose numerical requirements on their objects.

[0186] In the detailed description and claims, a list of items combined with the term "at least one of..." can mean any combination of the listed items. For example, if items A and B are listed, then the phrase "at least one of A and B" means only A, only B, or A and B. In another example, if items A, B, and C are listed, then the phrase "at least one of A, B, and C" means only A, only B, only C, A and B (excluding C), A and C (excluding B), B and C (excluding A), or all of A, B, and C. Item A may contain a single element or multiple elements. Item B may contain a single element or multiple elements. Item C may contain a single element or multiple elements.

[0187] In the detailed description and claims, a list of items combined with the term "...one of..." can mean only one of the listed items. For example, if items A and B are listed, then the phrase "one of A and B" means only A (excluding B) or only B (excluding A). In another example, if items A, B, and C are listed, then the phrase "one of A, B, and C" means only A, only B, or only C. Item A may contain a single element or multiple elements. Item B may contain a single element or multiple elements. Item C may contain a single element or multiple elements.

[0188] The foregoing description and drawings illustrate some embodiments of the subject matter of the invention to enable those skilled in the art to practice the embodiments of the subject matter of the invention. Other embodiments may incorporate structural, logical, electrical, process, and other variations. Examples are merely representative of possible variations. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Many other embodiments will become apparent to those skilled in the art upon reading and understanding the foregoing description.

Claims

1. An apparatus comprising: A first region includes a first-level conductive material interleaved with a first-level dielectric material, and a first memory cell, the first memory cell including a pillar extending through at least a portion of the first-level conductive material and the first-level dielectric material. The second region includes a second-level conductive material interleaved with the dielectric material of the second level, and a second memory cell, the second memory cell including a pillar extending through at least a portion of the conductive material of the first level and the dielectric material of the first level. The third region includes a dielectric structure that separates the conductive material of the first layer from the conductive material of the second layer. and A conductive contact that extends through at least a portion of the third region and contacts the conductive material in the first layer of conductive material.

2. The device of claim 1, wherein the dielectric structure comprises a dielectric portion, the dielectric portion includes a sidewall, and the conductive contact wraps around a portion of the sidewall of the dielectric portion.

3. The device of claim 1, further comprising an additional conductive contact extending through at least a portion of the third region and contacting the conductive material in the second layer of conductive material.

4. The device according to claim 3, wherein: The dielectric structure includes a dielectric portion, and the dielectric portion includes sidewalls; The conductive contact is adjacent to a first portion of the sidewall of the dielectric portion; and The additional conductive contact is adjacent to a second portion of the sidewall of the dielectric portion.

5. The device of claim 3, wherein the dielectric structure includes a length in a direction perpendicular to the direction from the conductive contact to the additional conductive contact.

6. The device of claim 3, wherein the conductive contact and the additional conductive contact have the same length.

7. The device according to claim 3, wherein the conductive material in the first layer and the conductive material in the second layer are positioned on the same layer of the device.

8. The device of claim 1, wherein the first layer of conductive material forms a first control gate associated with the first memory cell, and the second layer of conductive material forms a second control gate associated with the second memory cell.

9. The device of claim 1, wherein the device includes a memory device comprising a first memory cell block and a second memory cell block, wherein the first memory cell is included in the first memory cell block and the second memory cell is included in the second memory cell block.

10. An apparatus comprising: The first layer of conductive material is interleaved with the first layer of dielectric material; The second-level conductive material is interleaved with the second-level dielectric material, and the second-level conductive material and the second-level dielectric material are positioned on top of the first-level conductive material and the first-level dielectric material. A memory cell comprising a pillar associated with the memory cell, the pillar extending through a first-level conductive material, a first-level dielectric material, a second-level conductive material, and a second-level dielectric material. and A conductive contact extending in a direction from the conductive material of the second layer to the conductive material of the first layer, the conductive contact comprising a first conductive portion, a third conductive portion and a second conductive portion between the first portion and the third portion, wherein the second conductive portion contacts one of the conductive materials of the second layer.

11. The device of claim 10, wherein the first conductive portion comprises a conductive post.

12. The device of claim 11, wherein the first conductive portion includes additional conductive struts.

13. The device of claim 10, further comprising an additional conductive contact extending in the direction from the conductive material of the second layer to the conductive material of the first layer, the additional conductive contact comprising a fourth conductive portion, a sixth conductive portion and a fifth conductive portion between the fourth portion and the sixth portion, wherein the fifth conductive portion contacts one of the conductive materials of the second layer.

14. The device of claim 13, wherein the fourth conductive portion of the additional conductive contact comprises at least one conductive post.

15. The device of claim 10, further comprising a dielectric pillar adjacent to the conductive contact and extending through the first-layer conductive material, the first-layer dielectric material, the second-layer conductive material, and the second-layer dielectric material.

16. The device of claim 15, further comprising an additional dielectric pillar, wherein the dielectric pillar is located between the additional dielectric pillar and the conductive contact.

17. The device of claim 10, wherein the first layer of conductive material forms a first control gate associated with the memory cell, and the second layer of conductive material forms a second control gate associated with the memory cell.

18. A method comprising: Forming a first memory cell and a first control gate associated with the first memory cell; Forming a second memory cell and a second control gate associated with the second memory cell; A dielectric structure is formed between the first memory cell and the second memory cell; A first conductive contact is formed that passes through a first portion of the dielectric structure and contacts the first control gate in the first control gate; and A second conductive contact is formed that passes through the second portion of the dielectric structure and contacts the second control gate in the second control gate.

19. The method of claim 18, wherein forming the first conductive contact comprises: Conductive material is formed at a first position and a second position, wherein a first portion of the conductive material forms the first conductive contact, and a second portion of the conductive material forms the first control gate.

20. The method of claim 18, wherein forming the first conductive contact and the second conductive contact comprises: A conductive material is formed in the opening; and A portion of the conductive material is removed to obtain a first remaining portion and a second remaining portion of the conductive material, wherein the first remaining portion of the conductive material forms the first conductive contact, and the second remaining portion of the conductive material forms the second conductive contact.

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